View detail for AT91SAM9M10-G45-EK User Guide

AT91SAM9M10-G45-EK
....................................................................................................................
User Guide
6495B–ATARM–21-Apr-10
Section 1
Introduction .................................................................................................................1-1
1.1
Scope ................................................................................................................................. 1-1
1.2
Applicable Documents ....................................................................................................... 1-2
Section 2
Kit Contents ................................................................................................................2-1
2.1
Deliverables ....................................................................................................................... 2-1
2.2
Evaluation Board Specifications......................................................................................... 2-2
2.3
Electrostatic Warning ......................................................................................................... 2-2
Section 3
Power up.....................................................................................................................3-1
3.1
Power Up the Board........................................................................................................... 3-1
3.2
Battery................................................................................................................................ 3-1
3.3
DevStart ............................................................................................................................. 3-1
3.4
Recovery Procedure .......................................................................................................... 3-2
3.5
Sample Code and Technical Support ................................................................................ 3-2
Section 4
Board Description .......................................................................................................4-1
4.1
4.2
Equipment on the Board .................................................................................................... 4-1
4.1.1
Interfaces ............................................................................................................. 4-1
4.1.2
Board Interface Connection ................................................................................. 4-2
4.1.3
Push Button Switches .......................................................................................... 4-2
4.1.4
Display LCD and LEDs ........................................................................................ 4-3
Hardware Layout and Configuration .................................................................................. 4-3
4.2.1
Processor............................................................................................................. 4-3
4.2.2
Clock Circuitry...................................................................................................... 4-4
4.2.3
Reset Circuitry ..................................................................................................... 4-4
4.2.4
Memory ................................................................................................................ 4-4
4.2.5
Power Supplies .................................................................................................... 4-7
4.2.6
Debug Interface ................................................................................................. 4-10
4.2.7
Audio Stereo Interface ....................................................................................... 4-15
4.2.8
TV-Out Extension .............................................................................................. 4-17
4.2.9
Software Controlled LEDs ................................................................................. 4-18
4.2.10 Serial Peripheral Interface Controller (SPI) ....................................................... 4-19
4.2.11 Two Wire Interface (TWI)................................................................................... 4-19
4.2.12 SD/MMC Interface ............................................................................................. 4-19
4.2.13 TFT LCD with Touch Panel ............................................................................... 4-20
4.2.14 Push Buttons ..................................................................................................... 4-22
AT91SAM9M10-G45-EK User Guide
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6495B–ATARM–21-Apr-10
4.2.15 Expansion Slot ................................................................................................... 4-22
Section 5
Configuration ..............................................................................................................5-1
5.1
JTAG/ICE Configuration..................................................................................................... 5-1
5.2
ETHERNET Configuration ................................................................................................. 5-1
5.3
Jumpers Configuration ....................................................................................................... 5-2
5.4
Miscellaneous Configuration Items .................................................................................... 5-3
5.5
PIO Configuration............................................................................................................... 5-3
5.5.1
Peripheral Signals Multiplexing on I/O Lines ....................................................... 5-3
5.5.2
Multiplexing on PIO Controller A (PIOA).............................................................. 5-3
5.5.3
Multiplexing on PIO Controller B (PIOB).............................................................. 5-5
5.5.4
Multiplexing on PIO Controller C (PIOC) ............................................................. 5-6
5.5.5
Multiplexing on PIO Controller D (PIOD) ............................................................. 5-7
5.5.6
Multiplexing on PIO Controller E (PIOE).............................................................. 5-8
Section 6
Connectors .................................................................................................................6-1
6.1
Power Supply ..................................................................................................................... 6-1
6.2
RS232 Connector with RTS/CTS Handshake Support ...................................................... 6-1
6.3
DBGU................................................................................................................................. 6-2
6.4
Ethernet.............................................................................................................................. 6-3
6.5
USB Host ........................................................................................................................... 6-3
6.6
USB Host/Device ............................................................................................................... 6-4
6.7
JTAG Debugging Connector .............................................................................................. 6-4
6.8
SD/MMC- MCI0.................................................................................................................. 6-6
6.9
SD/MMC- MCI1.................................................................................................................. 6-7
6.10 AC97 .................................................................................................................................. 6-8
6.11 Image Sensor - ISI ............................................................................................................. 6-9
6.12 Video ................................................................................................................................ 6-10
6.13 Display Devices................................................................................................................ 6-10
6.13.1 TFT LCD ............................................................................................................ 6-10
6.14 LCD Extension ................................................................................................................. 6-11
Section 7
Schematics .................................................................................................................7-1
7.1
Schematics......................................................................................................................... 7-1
Section 8
Revision History..........................................................................................................8-1
8.1
Revision History ................................................................................................................. 8-1
1-ii
6495B–ATARM–21-Apr-10
AT91SAM9M10-G45-EK User Guide
Section 1
Introduction
1.1
Scope
This User Guide introduces the AT91SAM9M10(G45) Evaluation Kit and describes its development and
debugging capabilities.
Figure 1-1.
Board Photo
The Atmel® SAM9M10-G45-EK is a fully-featured evaluation platform for the Atmel AT91SAM9M10 or
AT91SAM9G45 microcontroller. The kit is equipped with an AT91SAM9M10 chip, which is a superset of
the AT91SAM9G45, and therefore allows evaluating that reference as well. The evaluation kit allows
users to extensively evaluate, prototype and create application-specific designs.
The SAM9M10-G45-EK includes many hardware peripherals such as:
„
Two high speed USB hosts and one high speed device port
„
An Ethernet 10/100 interface
„
Two high speed multimedia card interfaces
AT91SAM9M10-G45-EK User Guide
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6495B–ATARM–21-Apr-10
Introduction
„
An LCD TFT display (480*272 RGB) with resistive touch panel
„
A composite video output
„
A camera interface
„
Several communication peripherals such as:
– Universal Synchronous/Asynchronous Receiver Transmitter (USART)
– Two-Wire Interface (TWI)
The external memory block is made of 3 memory types:
1.2
„
DDR2-SDRAM
„
NAND Flash
„
NOR Flash (not populated by default)
Applicable Documents
Table 1-1. Applicable Documents
Reference
Title
Comments
Atmel Literature n° 6438
SAM9G45 Preliminary
This document describes the SAM9G45, which is part of the
Atmel's Smart ARM® Microcontrollers.
It is available from
http://www.atmel.com/dyn/resources/prod_documents/doc6438.pdf
Atmel Literature n° 6355
SAM9M10 Preliminary
This document describes the SAM9M10, which is part of the
Atmel's Smart ARM® Microcontrollers
http://www.atmel.com/dyn/resources/prod_documents/doc6355.pdf
1-2
6495B–ATARM–21-Apr-10
AT91SAM9M10-G45-EK User Guide
Section 2
Kit Contents
2.1
Deliverables
The Atmel SAM9M10-G45-EK toolkit includes:
„
Board
– The SAM9M10-G45-EK board
„
Power supply
– Universal input AC/DC power supply with US, Europe and UK plug adapters
– One 3V Lithium Battery type CR1225
„
Cables
– One micro A/B-type USB cable
– One serial RS232 cable
– One RJ45 crossed cable
„
A Welcome Letter
Figure 2-1.
Unpacked SAM9M10-G45-EK
Unpack and inspect this kit carefully. Contact your local Atmel distributor, should you have issues concerning the contents of the kit.
AT91SAM9M10-G45-EK User Guide
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6495B–ATARM–21-Apr-10
Kit Contents
2.2
Evaluation Board Specifications
Table 2-1. SAM9M10-G45-EK Specifications
2.3
Characteristics
Specifications
Clock speed
400 MHz PCK, 133 MHz MCK
Ports
Ethernet, USB, RS232, DBGU, JTAG
Board supply voltage
5 VDC from connector
Temperature
- operating
- storage
-10° to +50° C
Relative humidity
0 to 90% (non condensing)
Dimensions
180 mm x 140 mm
RoHS status
Compliant
-40° to +85° C
Electrostatic Warning
The SAM9M10-G45-EK evaluation board is shipped in a protective anti-static package. The board must
not be subjected to high electrostatic potentials. We strongly recommend using a grounding strap or similar ESD protective device when handling the board in hostile ESD environments (offices with synthetic
carpet, for example...). Avoid touching the component pins or any other metallic element on the board.
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6495B–ATARM–21-Apr-10
AT91SAM9M10-G45-EK User Guide
Section 3
Power up
3.1
Power Up the Board
Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right
power plug adapter corresponding to that of your country, and insert it in the power supply.
Connect the power supply DC connector to the board and plug the power supply to an AC power plug.
The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the
screen and enjoy the demo.
3.2
Battery
The SAM9M10-G45-EK ships with a 3V coin battery.
This battery is not required for the board to start up.
The coin battery is provided for user convenience in case the user would like to exercise the date and
time backup function of the SAM9M10 series devices when the board is switched off.
3.3
DevStart
The on-board NAND Flash contains a “SAM9M10-G45-EK DevStart”.
It is stored in the “SAM9M10-G45-EK DevStart” folder on the USB Flash disk available when the
SAM9M10-G45-EK is connected to a host computer.
Click the file “welcome.html” in this folder to launch SAM9M10-G45-EK DevStart.
SAM9M10-G45-EK DevStart guides you through installation processes of IAR™ EWARM, Keil MDK and
GNU toolkits. Then, it gives you step-by-step instructions on how to rebuild a single example project and
how to program it into the SAM9M10-G45-EK. Optionally, if you have a SAM-ICE™, instructions are also
given about how to debug the code.
We recommend that you backup the “SAM9M10-G45-EK DevStart” folder on your computer
before launching it.
AT91SAM9M10-G45-EK User Guide
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6495B–ATARM–21-Apr-10
Power up
3.4
Recovery Procedure
The DevStart ends by giving step-by-step instructions on how to recover the SAM9M10-G45-EK to the
state as it was when shipped by Atmel.
Follow the instructions if you deleted the contents of the NAND Flash and want to recover from this
situation.
3.5
Sample Code and Technical Support
After boot up, you can run some sample code or your own application on the development kit. You can
download
sample
code
and
get
Technical
support
from
http://www.atmel.com/dyn/products/tech_support.asp?Faq=y&family_id=689%20.
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6495B–ATARM–21-Apr-10
AT91SAM9M10-G45-EK User Guide
Section 4
Board Description
4.1
Equipment on the Board
Figure 4-1.
Board Architecture
Main Memory
Multimedia cards
LCD TFT
Data
Flash
PARALLEL
FLASH
NPCS0
4 bits
interface
SD/MMC
Micro
MCI1
MCI1
EBI1 / 1.8v
EBI1 / 1.8v
Touch
Touch
Screen
Screen
Joystick
& P.B
Line Out
SPI0
SPI0
Led
Composite
video
CD
NCS0
NCS3
NCS1
8 bits
interface
SD/MMC
Codec
MCI0
MCI0
Multimedia Cards Interface
Multimédia Cards Interface
External Memory
External Memory
AC97
AC97
LCD Interface
LCD Interface
PWM
PWM
AT91SAM9M10
System Controller
System Controller
Image Sensor
Image
Sensor
Interface
Interface
TWI
TWI
ETHERNET
ETHERNET
10/100
MAC
10/100 MAC
USB
USB
USART
USART
Host A
Host A
Serial
Eeprom
Power /
Shdn
Host B
Device
Host B
Device
PIO
PIO
DEBUG
DEBUG
DBGU
JTAG/ICE
RS232
oooooooo
oooooooo
PHY RMII
oooooooo
oooooooo
VCC 5V
4.1.1
User I/O
Line In
NAND
FLASH
EBI0
EBI0
Audio
LCD TFT
LCD
TFT
480*272
480*272
DDR2
SDRAM
DDR2
SDRAM
Vidéo
ISI
oooooooo
oooooooo
Ethernet RMII/MII
RS232
USB Hub
High / Full
USB
Hub / Device
DBGU
JTAG/ICE
PIO
Interfaces
The board is equipped with an AT91SAM9M10-CU embedded microprocessor (324-ball TFBGA package) together with the following interfaces or peripherals:
„
DDR2/LPDDR memory interface is connected to 128 MB DDR2-SDRAM memory
„
External Bus Interface (EBI) is connected to three kinds of memory devices (DDR2-SDRAM, NAND
Flash and NOR Flash (not populated))
AT91SAM9M10-G45-EK User Guide
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6495B–ATARM–21-Apr-10
Board Description
4.1.2
4.1.3
„
One TWI serial memory
„
One USB Host/Device multiplexed port interface
„
One USB Host port interface
„
One RS232 serial communication port
„
One DBGU serial communication port
„
One JTAG/ICE debug interface
„
One Ethernet 100-base TX with three status LEDs
„
One AC97 Audio CODEC with headphone line out, line in and mono/stereo microphone inputs
„
One TV interface (composite video output)
„
One 4.3" TFT LCD Module with touch screen and back light
„
One ISI connector (camera interface)
„
One power red LED and two general-purpose green LEDs
„
Two user input push buttons
„
One joystick with 4-direction control and selector
„
One wakeup input push button
„
One reset input push button
„
One SD/SDIO/MMC plus card slot (4/8 bit interface)
„
One SD/SDIO/MMC card slot (4-bit interface)
„
One Lithium Coin Cell Battery Retainer for 12 mm cell size (memory backup usage)
Board Interface Connection
„
Ethernet using RJ45 connector (J15)
„
USB Host, support USB host using a type A connector (J12)
„
USB Host/Device, support USB host/device using a type micro AB connector (J14)
„
UART1 (RX, TX, RTS, CTS) connected to a 9-way male D-type RS232 connector (J11)
„
DBGU (RX and TX only) connected to a 9-way male D-type RS232 connector (J10)
„
JTAG, 20 pin IDC connector (J13)
„
SD/MMCplus connector (J5)
„
SD/MMC connector (J6)
„
Headphone (J7), line-in (J8) and microphone headset (J9)
„
Speaker output (JP15)
„
Image sensor connector (J17)
„
TFT LCD display, with TouchScreen and backligth (J24)
„
Test points; various test points are located throughout the board
„
Main power supply (J2)
Push Button Switches
„
Reset, board reset (BP1)
„
Wake up, push button to bring processor out of low power mode (BP2)
„
Right and left click, user push button switches (BP4 and BP5)
„
Joystick (BP3)
4-2
6495B–ATARM–21-Apr-10
AT91SAM9M10-G45-EK User Guide
Board Description
Display LCD and LEDs
Display, 480xRGBx272 pixels LCD module display connected to the PIO port E (LCD1)
„
One surface-mounted power red LED, user interface (D3)
„
Two surface-mounted green LEDs, user interface (D1 and D2)
„
Three surface-mounted LEDs indicate Ethernet status (D4, D5, D6)
Board Layout Commented
2
Y7
J15
TP1
C12
C9
C180
C181
C182
C27
C23
JP16
C6
BP2
WAKEUP
JP12
L5
JP7
2
VDDBU
BAT
J3
3V
J17
D1
BACKUP
BATTERY
D2
C31
R27
MN20
R183
R181
L20 TP6
R185
BP1
NRST
3V3
30
Y2
MN1
CR1225
R203
Q1
MN13
NPCS0
R21
R204
C37
R29
BP4
RIGHT
BP5
L17
C198
TP2
LCD EXTENSION
SD/MMC
SELECT
J6
SD/MMC 0
SLOT
SD/MMC+
2
202
40
1
191
39
J18
«RIGHT»
USER BUTTON
«LEFT»
USER BUTTON
LEFT
BP3
RESET
BUTTON
1
C64
1
VDDIOM1
R112
R105
R104
7
CR1
ETHERNET
L4
R22
RR19
R114
R109
R116
R117
R12 R39 R101C179
R106C177
R120
C186
JP11
1
JP4
R197
R198
Y6
8
29
JP6
C185 R115
RR36
R191
R192
R193
R194
R195
R196
1
USER
JOYSTICK
3
J1
2
MN4
R110
L2
E2PROM
C201
JP13
MN12
C206
VIDEO J20
4
J1
ISI
L3
C187
1 Y5 2
RR45
WAKE-UP
BUTTON
MN2
C176
C178
JP1 JP2 JP3
C203
C205 L22
VIDEO
OUTPUT
VDDUTMII
VDDUTMIC
VDDCORE
VDDPLLUTMI
RR9
RR25
RR11
R75
C128 C129
R71 R72
C126 C127
R69 R70
MN8
MN9
R99
R100
JP8
C47
C38
RR13
RR17
C199
HEAD PHONE J7
Y1
MN11
R73
R85
HEADPHONES
HEADER
MN5
C48
Y3
C133
C143
L11
R37
C66
R20R5
R44
R42
VDDIOM0
R40
JP5
TP5
JP15
C183
BMS
MN10
R74
C141
JP14
JP17
JP18
1
J9
MIC IN
D5
D6
RR47
4 Y4 3
NCS0
R78
C137
MICROPHONE
INPUT
JP2/P2/JD3
VDDIOPn
C170
C168
R46
L9
NANDCS
C149 R80
C148 R79
L8
L12
C156 R84
C155 R83
L10
ICE
RR21
MN14
JP9
JP10
MN7
MN6
J2
D4
J13
Q2
MN17
RR23
C59
LINE
INPUT
C146
C147
C139
TP4
LINE IN J8
RS232
MN16
MN15
J11
D3
HOST
/DEV
HOST
1
J12 4
J10
POWER
ETHERNET
5VCC POWER
J14
DBGU
JTAG
R48
RS232
USB
DBGU
HOST
HOST DEVICE
USB
USB
C41
Figure 4-2.
„
USB
4.1.4
TP3
J5
J23
SD/MMC 1
SLOT
1
LCD DISPLAY AREA
LCD EXTENSION
CONNECORS
ISI/CAMERA
CONNECTOR
The major components of the SAM9M10-G45-EK board are shown in Figure 4-1.
4.2
Hardware Layout and Configuration
4.2.1
Processor
The board features the Atmel SAM9M10-CU 324-ball TFBGA package. This chip runs at a nominal frequency of 400 MHz for the core and 133 MHz for the system bus.
For more information, refer to the latest SAM9M10 datasheet available from http://www.atmel.com/
AT91SAM9M10-G45-EK User Guide
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6495B–ATARM–21-Apr-10
Board Description
4.2.2
Clock Circuitry
The SAM9M10-G45-EK includes six clock sources:
„
Two are alternatives for the SAM9M10 main clock,
„
One crystal and one crystal oscillator are used for the Ethernet MII/RMII chip,
„
One crystal is used for the AC97 codec chip,
„
One crystal or one crystal oscillator is used for the TV encoder.
Table 4-1. Main Components Associated with the Clock Systems
Quantity
4.2.3
Description
Component assignment
1
Crystal for Internal Clock, 12 MHz
Y1
1
Crystal for RTC Clock, 32.768 kHz
Y2
1
Oscillator for Ethernet Clock RMII, 50 MHz
Y4
1
Crystal for Ethernet Clock MII, 25 MHz (not populated)
Y5
1
Crystal for AC97 Codec Clock, 24.576 MHz
Y3
1
Crystal for TV Encoder Clock, 13 MHz, or
Oscillator for TV Encoder, 13 MHz (not populated)
Y7
Y6
Reset Circuitry
The reset sources are:
„
Power on reset
„
Push button reset
„
JTAG reset from an in-circuit emulator interface.
4.2.4
Memory
4.2.4.1
External Memories
The SAM9M10 features a DDR2/LPDDR memory interface and an External Bus Interface (EBI) to permit
interfacing to a wide range of external memories and to almost any kind of parallel peripheral.
The SAM9M10-G45-EK board is equipped with DDR2/LPDDR devices featuring 128 MB of DDR2SDRAM memory (16Meg*8*4).
The External Bus Interface (EBI) is connected to three kinds of memory devices:
„
One Parallel Flash (not populated by default)
„
Two DDR2-SDRAM
„
One NAND Flash (2Gb, 8 bit bus)
The chip selects NCS0, NCS1 and NCS3 are used for NOR Flash, DDR2-SDRAM and NAND Flash
memories, respectively. Furthermore, a dedicated jumper can disconnect each of the two NCS0 and
NCS3 signals, making them available for other functions.
4-4
6495B–ATARM–21-Apr-10
AT91SAM9M10-G45-EK User Guide
AT91SAM9M10-G45-EK User Guide
DDR_W E
DDR_CAS
DDR_RAS
DDR_CS
DDR_CLK
DDR_NCLK
DDR_CKE
DDR_BA0
DDR_BA1
G7
F7
F3
CS
CAS
RAS
NW E
G1
L3
L7
E8
F8
G8
CK
NCK
F2
F9
G2
G3
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
CKE
BA0
BA1
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
RFU1
RFU2
RFU3
WE
CAS
RAS
CS
CK
CK
CKE
ODT
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
MN6
DQS
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VDD
VDD
VDD
VDD
RDQS/DM
RDQS/NU
DDR2 SDRAM
E1
E7
A7
B2
B8
D2
D8
A3
E3
J1
K9
E2
A9
C1
C3
C7
C9
DDR_VREF
1V8
C67
C69
C71
C73
100n
100n
100n
100n
100n
C87
100n
100n
C75
C77
C79
C81
C83
C85
100n
100n
100n
100n
1V8
DDR_DQM0
A1
E9
H9
L1
DDR_DQS0
B3
A2
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
B7
A8
C8
C2
D7
D3
D1
D9
B1
B9
L5
10uH
NW E
CAS
RAS
CS
CK
NCK
CKE
BA0
BA1
R50
1R
C90
4.7u
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
G1
L3
L7
F3
G7
F7
G8
E8
F8
F2
F9
G2
G3
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
C91
100n
C89
100n
RFU1
RFU2
RFU3
WE
CAS
RAS
CS
CK
CK
CKE
ODT
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
MN7
R52
1.5k
R51
1.5k
DQS
DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DDR_VREF
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VDD
VDD
VDD
VDD
RDQS/DM
RDQS/NU
DDR2 SDRAM
E7
A7
B2
B8
D2
D8
A3
E3
J1
K9
E2
A9
C1
C3
C7
C9
E1
C68
C70
C72
C74
C76
C78
C80
C82
C84
C86
DDR_VREF
DDR_VREF
1V8
C88
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
DDR_DQM1
A1
E9
H9
L1
DDR_DQS1
B3
A2
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
B7
A8
C8
C2
D7
D3
D1
D9
B1
B9
Figure 4-3.
DDR_A[0..13]
DDR_D[0..15]
Board Description
EBI0 - DDR2
6495B–ATARM–21-Apr-10
4-5
EBI1_FLASH_D[0..15]
EBI1_DDR_D[0..15]
6495B–ATARM–21-Apr-10
4-6
F3
W E_EBI1
G1
L3
L7
G7
F7
CAS_EBI1
RAS_EBI1
G8
CS_EBI1
(NCS1)
F2
E8
F8
CLK_EBI1
NCLK_EBI1
F9
G2
G3
CKE_EBI1
BA0_EBI1
BA1_EBI1
H8
EBI1_DDR_A2
H3
EBI1_DDR_A3
H7
EBI1_DDR_A4
J2
EBI1_DDR_A5
J8
EBI1_DDR_A6
J3
EBI1_DDR_A7
J7
EBI1_DDR_A8
K2
EBI1_DDR_A9
K8
EBI1_DDR_A10
K3
EBI1_DDR_A11
EBI1_DDR_A12 (SDA10) H2
K7
EBI1_DDR_A13
L2
EBI1_DDR_A14
L8
EBI1_DDR_A15
MN8
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VDD
VDD
VDD
VDD
E7
A7
B2
B8
D2
D8
A3
E3
J1
K9
E2
A9
C1
C3
C7
C9
E1
PC8
VREF1
1V8
C90
C92
C94
C96
C98
(RDY/BSY)
(NCS3)
(NANDCLE)
(NANDALE)
C101
100nF
100nF
100nF
100nF
100nF
JP10
100nF
100nF
100nF
100nF
100nF
C88 100nF
C80
C82
C84
C86
DQM0_EBI1
A1
E9
H9
L1
DQS0_EBI1
B7
A8
EBI1_DDR_D0
EBI1_DDR_D1
EBI1_DDR_D2
EBI1_DDR_D3
EBI1_DDR_D4
EBI1_DDR_D5
EBI1_DDR_D6
EBI1_DDR_D7
B3
A2
C8
C2
D7
D3
D1
D9
B1
B9
PC5
PC4
EBI1_NANDOE
EBI1_NANDW E
PC14
EBI1_NAND_FSH_D[0..15]
RFU1
RFU2
RFU3
WE
CAS
RAS
CS
CK
CK
CKE
ODT
BA0
BA1
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H64M8CF-3 DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
1V8
1V8
IMPORTANT note about system booting:
The bootROM allows booting from the block 0 of a NandFlash connected
on CS3. However, the bootROM does not feature ECC (Error Checking and
Correction) on NandFlash.
Most of the NandFlash vendors do not guarantee anymore that block 0
is error free. Therefore we advise the bootstrap program to be located
into another device supported by the bootrom (DataFlash, Serial Flash,
SDCARD or EEPROM) and implement NandFlash access with ECC.
W E_EBI1
CAS_EBI1
RAS_EBI1
CS_EBI1
CLK_EBI1
NCLK_EBI1
CKE_EBI1
BA0_EBI1
BA1_EBI1
EBI1_DDR_A[2..15]
R41
R46
R44
R45
R42
R43
CKE_EBI1
R47
DNP
470K
470K
0R
1K
0R
0R
W E_EBI1
CAS_EBI1
RAS_EBI1
CS_EBI1
CLK_EBI1
NCLK_EBI1
C3
A1
A2
A9
A10
B1
B9
B10
D6
D7
D8
E3
E4
E5
E6
E7
E8
F3
F4
F5
F6
F8
G3
G8
L1
L2
G5
C8
WP
D5
C4
D4
C7
C6
RB
RE
WE
CE
G1
L3
L7
F3
G7
F7
G8
E8
F8
F2
F9
G2
G3
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
(SDA10) H2
K7
L2
L8
BA0_EBI1
BA1_EBI1
EBI1_DDR_A2
EBI1_DDR_A3
EBI1_DDR_A4
EBI1_DDR_A5
EBI1_DDR_A6
EBI1_DDR_A7
EBI1_DDR_A8
EBI1_DDR_A9
EBI1_DDR_A10
EBI1_DDR_A11
EBI1_DDR_A12
EBI1_DDR_A13
EBI1_DDR_A14
EBI1_DDR_A15
MN9
VCC
VCC
VCC
VCC
N.C34
N.C35
N.C36
N.C37
N.C38
N.C39
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
N.C26
N.C27
N.C28
N.C29
N.C30
N.C31
N.C32
N.C33
VSS
VSS
VSS
VSS
VFBGA-63
MT29F2G08ABDHC:D
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
N.C15
N.C16
N.C17
N.C18
N.C19
N.C20
N.C21
N.C22
N.C23
N.C24
N.C25
LOCK
WP
R/B
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VREF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VDD
VDD
VDD
VDD
VSSDL
CLE
ALE NAND FLASH
RE MT29F2G08ABD
WE
CE
MN11
RFU1
RFU2
RFU3
WE
CAS
RAS
CS
CK
CK
CKE
ODT
BA0
BA1
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2 MT47H64M8CF-3 DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
C5
F7
K3
K8
D3
G4
H8
J6
L9
L10
M1
M2
M9
M10
H4
J4
K4
K5
K6
J7
K7
J8
H3
J3
H5
J5
H6
G6
H7
G7
E7
A7
B2
B8
D2
D8
A3
E3
J1
K9
E2
A9
C1
C3
C7
C9
E1
A1
E9
H9
L1
C102
100nF
1V8
100nF
100nF
100nF
100nF
C91
C93
C95
C97
C99
C103
C104
C105
C106
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
100nF
C89 100nF
C81
C83
C85
C87
EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D1
EBI1_NAND_FSH_D2
EBI1_NAND_FSH_D3
EBI1_NAND_FSH_D4
EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D6
EBI1_NAND_FSH_D7
EBI1_NAND_FSH_D8
EBI1_NAND_FSH_D9
EBI1_NAND_FSH_D10
EBI1_NAND_FSH_D11
EBI1_NAND_FSH_D12
EBI1_NAND_FSH_D13
EBI1_NAND_FSH_D14
EBI1_NAND_FSH_D15
VREF1
1V8
DQS1_EBI1
DQM1_EBI1
B3
A2
EBI1_DDR_D8
EBI1_DDR_D9
EBI1_DDR_D10
EBI1_DDR_D11
EBI1_DDR_D12
EBI1_DDR_D13
EBI1_DDR_D14
EBI1_DDR_D15
B7
A8
C8
C2
D7
D3
D1
D9
B1
B9
R39 100K
Optional 16bits DATA BUS
With AT29F2G16ABD Micron
DDR_VREF
EBI1_NCS0
EBI1_NRD/CFOE
1V8
EBI1_NW E/NW R0/CFW E
VREF1
JP9
1V8
EBI1_FLASH_A1
EBI1_FLASH_A2
EBI1_FLASH_A3
EBI1_FLASH_A4
EBI1_FLASH_A5
EBI1_FLASH_A6
EBI1_FLASH_A7
EBI1_FLASH_A8
EBI1_FLASH_A9
EBI1_FLASH_A10
EBI1_FLASH_A11
EBI1_FLASH_A12
EBI1_FLASH_A13
EBI1_FLASH_A14
EBI1_FLASH_A15
EBI1_FLASH_A16
EBI1_FLASH_A17
EBI1_FLASH_A18
EBI1_FLASH_A19
EBI1_FLASH_A20
EBI1_FLASH_A21
DNP
VPP
CE
OE
RESET
WE
1V8
CBGA
GND
GND
VCC
I/00
A0
I/O1
A1
FLASH
I/O2
A2
I/O3
A3
AT49SV322DT
I/O4
A4
A5
I/O5
A6
I/O6
A7
I/O7
A8
I/O8
A9
I/O9
A10
I/O10
A11
I/O11
A12
I/O12
A13
I/O13
A14
I/O14
A15
I/O15
A16
A17
A18
RDY/ BUSY
A19
A20
NC1
NC
MN10
R40 470K
B3
F1
G1
B4
A4
E1
D1
C1
A1
B1
D2
C2
A2
B5
A5
C5
D5
B6
A6
C6
D6
E6
B2
C3
D4
D3
H1
H6
G4
C4
F6
A3
E2
H2
E3
H3
H4
E4
H5
E5
F2
G2
F3
G3
F4
G5
F5
G6
1V8
C100
100nF
EBI1_FLASH_D0
EBI1_FLASH_D1
EBI1_FLASH_D2
EBI1_FLASH_D3
EBI1_FLASH_D4
EBI1_FLASH_D5
EBI1_FLASH_D6
EBI1_FLASH_D7
EBI1_FLASH_D8
EBI1_FLASH_D9
EBI1_FLASH_D10
EBI1_FLASH_D11
EBI1_FLASH_D12
EBI1_FLASH_D13
EBI1_FLASH_D14
EBI1_FLASH_D15
Figure 4-4.
EBI1_FLASH_A[1..21]
Board Description
EBI1 - DDR2 + Flash
AT91SAM9M10-G45-EK User Guide
Board Description
4.2.5
Power Supplies
The SAM9M10 Board contains four regulated power supplies:
„
3.3 VDC Supply
„
1.8 VDC Supply
„
1.0 VDC Core Supply
„
1.0 VDC Core UTMI Supply, PLL
The outputs of these regulated power supplies1 are distributed as necessary to each part of the circuit
board.
„
The 3.3 VDC Supply is generated by an adjustable LDO. It accepts VIN 5 VCC power and outputs a
regulated +3.3 V to most other circuits on the board.
„
The 1.8 VDC Supply (VDDIOM0, VDDIOM1) is generated by an adjustable LDO. It is powered by VIN
5 VCC power and outputs a regulated +1.8V.
„
The 1.0 VDC Core Supply (VDDCORE) is generated by an adjustable LDO. It is powered by the
output of the 3.3 VDC Supply.
„
The 1.0 VDC Core Supply (VDDUTMIC, VDDPLLUTMI and VDDPLLA) is generated by an adjustable
LDO RT9186A series. It is powered by the output of the 3.3 VDC Supply.
Note:
1. Corresponding test points (TP1 to TP4, GND) are used with jumpers (JP1.1 to JP7) to
permit probing of these voltages.
AT91SAM9M10-G45-EK User Guide
4-7
6495B–ATARM–21-Apr-10
Board Description
Figure 4-5.
Power Supply
3V3
J1-1
1
L1
2
VDDUTMII
10uH
VDDANA
R1
1R
C1
100n
C2
4.7u
L2
10uH
VDDOSC
R5
1R
C8
100n
C14
4.7u
JP1
1
3
JP2
VDDIOP0
2
1
3
JP3
VDDIOP1
2
1
3
2
VDDIOP2
VDDISI
J1-2
3
1V_VDDUTMIC
4
VDDUTMIC
8
VDDPLLUTMI
C15
2.2u
R10
100k
3V3
J1-4
L3
10uH
7
R13
1
2
3
4
VIN
VIN
PGOOD
EN
EP
MN3
RT9186A
VOUT
VOUT
ADJ
GND
8
7
6
5
1V_VDDUTMIC
R14
12k
C18
100n
C19
C20
4.7u
10n
9
100k
C25
1u
R12
1R
C21
10u
C22
1u
L4
10uH
VDDPLLA
R19
47k
R20
1R
C28
100n
C29
4.7u
1V
J1-3
5
6
VDDCORE
1V8
JP5
1
3
JP6
2
VDDIOM0
3
VDDIOM1
2
1
J3
3V3
JP7
C30
100n
3
2
1
VDDBU
4-8
6495B–ATARM–21-Apr-10
AT91SAM9M10-G45-EK User Guide
Board Description
Figure 4-6.
Management Power Block
3V3
5V
R3
100k
5V
MN2
RT9018A
J2
1
3
2
C4
33u
1
2
3
4
CR1
5V
+
PGOOD
EN
VIN
VDD
EP
REGULATED
5V ONLY
C10
1u
C9
10u
10n
47k
8
7
6
5
R7
15k
9
DC POWER JACK
GND
ADJ
VOUT
NC
C3
R4
C11
1u
3V3
C12
10u
5V
PWR_EN
R9
100k
1V8
5
FORCE
POWER
ON
2
JP4
5V
R11
100k
MN4
RT9018A
SIP2
1 C17
2
1
2
3
4
3
15p
R17
10k
R16
10k
PGOOD
EN
VIN
VDD
EP
1
4
C24
1u
C23
10u
GND
ADJ
VOUT
NC
C16
10n
R15
15k
8
7
6
5
R18
12k
9
Q1
6
Si1563EDH
1V8
C26
1u
C27
10u
SHDN
1V
R2
100k
3V3
1V
R199
1
2
3
4
VIN
VIN
PGOOD
EN
EP
MN1
RT9186A
VOUT
VOUT
ADJ
GND
8
7
6
5
R6
12k
C5
10n
100k
C7
9
C13
1u
AT91SAM9M10-G45-EK User Guide
C6
10u
1u
R8
47k
4-9
6495B–ATARM–21-Apr-10
Board Description
4.2.6
Debug Interface
4.2.6.1
JTAG/ICE
Software debug is accessed by a standard 20-pin JTAG connection. This allows connection to a standard USB-to-JTAG in-circuit emulator.
Figure 4-7.
JTAG Interface
5
6
7
8
3V3
3V3
3V3
RR43
100k
4
3
2
1
J13
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
R93
DNP
R91
0R
R92
0R
0R
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
R94
0R
DNP
HTST-110-01-SM-D
ICE INTERFACE
4.2.6.2
DBGU Com Port
This UART is connected to the DB-9 male socket through an RS-232 Transceiver (TXD and RXD only).
Figure 4-8.
DBGU Com Port
3V3
C158
MN15
100n 16
SERIAL DEBUG PORT
15
C157
100n 2
J10
C165
100n 6
C1+
1
C1C2+
3
4
C2-
5
C159
100n
3V3
GND
V+
V-
14
T
7
T
C163
100n
R87
100k
11
R88
100k
PB13
10
13
R
12
8
R
9
PB12
10
11
1
6
2
7
3
8
4
9
5
VCC
R90
0R
ADM3202ARNZ
4-10
6495B–ATARM–21-Apr-10
AT91SAM9M10-G45-EK User Guide
Board Description
4.2.6.3
User Serial Com Port
The USART1 is used as a user serial communication port. This USART1 is buffered with an RS-232
Transceiver (TXD, RXD and handshake CTS/RTS control) and connected to the DB-9 male socket. Software must assign the appropriate PIO pins (PB5 = RXD1, PB4 = TXD1, PD16 = RTS1, PD17 = CTS1) to
enable the UART1 function.
User Serial Com Port
3V3
MN16
1
3V3
C1+
C160
100n
3
4
R89
100k
R86
100k
C1C2+
VCC
16
GND
15
RS232 COM PORT
C161
100n
V+
2
C162
100n
V-
6
C166
100n
J11
C164
100n
5
C2-
PB4
11
PD16
10
PB5
12
R
13
9
R
8
14
T
7
10
T
1
6
2
7
3
8
4
9
5
PD17
11
Figure 4-9.
ADM3202ARNZ
Refer to the SAM9M10 datasheet for more information about the SAM9M10 USARTs.
4.2.6.4
USB Port
The SAM9M10-G45-EK features USB communication ports:
„
Two Host Ports: Full speed OHCI and High speed EHCI
„
One Device Port: High speed.
USB Host Port0 is directly connected to the first UTMI transceiver. The second Host Port (Port1) is multiplexed with the USB Device High speed and connected to the second UTMI port.
„
One USB high/full speed type standard A connector
„
One USB interface Host/Device Micro AB connector
Refer to the SAM9M10 datasheet for detailed programming information.
AT91SAM9M10-G45-EK User Guide
4-11
6495B–ATARM–21-Apr-10
Board Description
Figure 4-10. USB Port
J12
G3505-4NBT1S1W
USB HOST INTERFACE
1
2
HDMA
4
3
HDPA
USB-A
C167
100n
5
6
5V
L13
MN17
1
2
220ohm at 100MHz
+ C168
33u
L14
2
1
(ENA)
PD1
IN
FLGA
2
(FLGA)
PD2
GNG
FLGB
3
(FLGB)
PD4
ENB
4
(ENB)
PD3
OUTA
7
6
C169
100n
1
ENA
8
5
220ohm at 100MHz
OUTB
AIC1526-0GS
+ C170
33u
3V3
R95
C171
10p
47k
(VBUS)
PB19
R96
68k
R97
47k
J14
SHIELD
7
VBUS
DM
DP
ID
GND
1
2
3
4
5
6
(IDUSB)
HDMB
HDPB
PD28
USB HOST/DEVICE INTERFACE
G3515-09010101-00
C172
100n
4.2.6.5
Ethernet 10/100 (EMAC) Port
The port is compatible with IEEE® Standard 802.3.
The SAM9M10-G45-EK is equipped with a Davicom DM9161AEP 10/100 Mbps Fast Ethernet Physical
Layer TX/FX Single Chip Transceiver. It contains the entire physical layer functions of 100BASE-TX as
defined by IEEE 802.3u, including the Physical Coding Sublayer (PCS), Physical Medium attachment
(PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder
(ENC/DEC), and Twisted Pair Media Access Unit (TPMAU).
The Ethernet interface integrates an RJ45 connector with an embedded transformer, and three status
LEDs.
The Ethernet interface provides two selectable modes, MII or RMII (Reduced MII), for 100Base-TX or
10Base-TX. The MII and RMII interfaces are capable of both 10Mb/s and 100Mb/s data rates as
described in the IEEE 802.3u standard. The signals used by MII and RMII interfaces are described in the
table below.
4-12
6495B–ATARM–21-Apr-10
AT91SAM9M10-G45-EK User Guide
Board Description
Table 4-2. Pin Mapping for Normal MII and Reduced MII
Pin Name
Normal MII Mode
SAM9M10
Reduced MII Mode
DM9161
SAM9M10
DM9161
ETX0-ETX1
ETX[0:1] transmit data
TXD [0:1]
ETX[0:1]
TXD [0:1]
ETX2-ETX3
ETX[2:3] transmit data
TXD [2:3]
NC
NC
ETXEN
ETXEN: transmit enable
TXEN
ETXEN: transmit enable
TXEN
ETXER
ETXER: transmit error
TXER/TXD[4]
NC
NC
ETXCK/REFCK
ETXCK: transmit clock
TXCLK
REFCK: reference clock
REF_CLK
ERX0-ERX1
ERX[0:1]: receive data
RXD [0:1]
ERX[0:1]: receive data
RXD [0:1]
ERX2-ERX3
ERX[2:3]: receive data
RXD [2:3]
NC
NC
ERXER
ERXER: receive error
RXER/RXD[4]/
RPTR/NODE
ERXER: receive error
RPTR/NODE
ERXDV
ERXDV: receive valid data
RXDV
ECRSDV: carrier sense /
data valid
CRS DV
ERXCK
ERXCK: receive clock
RXCLK
NC
NC
ECOL
ECOL: collision detect
COL
NC
NC
ECRS
ECRS: carrier sense /
data valid
CRS (PHYAD[2:4]
NC
NC
EMDC
EMDC: management data clock
MDC
EMDC: management data
clock
MDC
EMDIO
EMDIO: management data
input / output
MDIO
EMDIO: management data
input / output
MDIO
NRST
NRST: microcontroller reset
RESET# XT1
(25 MHz)
NRST: microcontroller reset
RESET# XT1
(REF_CLK 50MHz)
AT91SAM9M10-G45-EK User Guide
4-13
6495B–ATARM–21-Apr-10
PA18
PA19
PD5
PA30
PA29
PA27
PA16
PA28
PA15
PA9
PA8
PA13
PA12
PA7
PA6
PA11
PA10
PA14
0R DNP
R109
R110
R112
R114
(RX_CLK)
(RX_DV)
(TX_ER)
(RX_ER)
(COL)
(CRS)
(MDC)
(MDIO)
(MDINTR)
0R DNP
0R DNP
R104
R105
(RXD3)
(RXD2)
(RXD1)
(RXD0)
NRST
0R DNP
0R DNP
0R DNP
0R DNP
0R DNP
R108
R103
RR46
10k
RR45
10k
RR44
10k
3V3
8
7
6
5
1
2
3
4
(TXD3)
(TXD2)
(TXD1)
(TXD0)
(TX_EN)
8
7
6
5
1
2
3
4
(TX_CLK)
8
7
6
5
1
2
3
4
PA17
VDD 4
50MHz
2 VSS
OUT 3
Y4
1 OE
10k
JP16
3V3
R120
R122
0R
100n
100n
C186
100n
C185
1.5k
C184
R115
0R
3V3
R106
40
10
15
33
44
23
30
41
39
24
25
32
36
35
16
38
34
37
26
27
28
29
17
18
19
20
21
0R DNP 22
42
DNP
R100
0R
C173
100n
R101
R99
0R
3V3
2
1
C174
22p
DNP
1
3V3
RX-
RX+
TX-
TX+
XT1
C175
22p
DNP
0R
GND_ETH
N.C
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
BGRESG
AGND
AGND
AGND
AVDDT
AVDDR
AVDDR
25MHz
DNP
Y5
3
DM9161AEP
C187
10u
10V
R123
RESET
PW RDW N
DGND
DGND
DGND
DVDD
DVDD
DVDD
DISMDIX
MDC
MDIO
MDINTR
COL/RMII
CRS/PHYAD4
TX_ER/TXD4
RX_ER/RXD4/RPTR
RX_CLK/10BTSER
RX_DV/TESTMODE
RXD3/PHYAD3
RXD2/PHYAD2
RXD1/PHYAD1
RXD0/PHYAD0
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
REF_CLK/XT2
MN18
0R
2
4
4-14
C177
C179
45
48
31
11
12
13
14
47
5
6
46
100n
R117
6.8k
0R
100n
100n
R116
AVDDT
C182
9
2
1
4
3
8
7
43
2
3V3
2200R
L15
C180
10u
10V
1
8
7
6
5
6495B–ATARM–21-Apr-10
1
2
3
4
R98
RR47
10k
2 D6
2 D5
2 D4
GND_ETH
C181
10u
10V
AVDDT
1 Green
1 Green
1 Yellow
R121
R119
R118
C183
100n
R113
49.9R
C178
100n
470R
470R
470R
3V3
8
J15
1nF
J00-0061NL
7 NC
6 RD-
5 CT
3 RD+
2 TD-
4 CT
1 TD+
75
15
75
16
75
75
RX-
RX+
TX-
TX+
8
7
5
4
6
3
2
1
LINK&ACT
SPEED 100
FULL DUPLEX
RJ45 ETHERNET CONNECTOR
GND_ETH
GND_ETH
R107
49.9R
AVDDT
GND_ETH
R111
49.9R
R102
49.9R
C176
100n
Board Description
Figure 4-11. Ethernet Port
For more information about the Ethernet controller device, refer to the Davicom DM9161 controller manufacturer's datasheet.
AT91SAM9M10-G45-EK User Guide
Board Description
4.2.7
Audio Stereo Interface
The SAM9M10-G45-EK includes a WM9711L AC97 CODEC for digital sound input and output. This
interface includes audio jacks for MIC input (J9), line audio input (J8), headphone line output (J7) and a
2-point speaker output connector (JP15).
It is compliant with AC97 Component Specification V2.2.
AT91SAM9M10-G45-EK User Guide
4-15
6495B–ATARM–21-Apr-10
Board Description
Figure 4-12. Audio Stereo Interface
HEADPHONE
LINE-OUT
0R
C126
R70
0R
C127
+
R69
100u/6.3V
1
2
+
L6
220ohm at 100MHz
100u/6.3V
1
2
2
5
J7
JP17 DNP
2
1
JP18 DNP
2
1
100n 100n
Y3
4
2
24.576MHz
22p
C134 C135
10u
10V 100n
C136
100n
1
C137
1
PD7
PD9
PD6
R78
AGND_AC97
1
2
3
4
5
6
7
8
9
10
11
12
49.9R
(AC97RX)
(AC97FS)
DBVDD
XTLIN
XTLOUT
DGND1
SDATAOUT
BITCLK
DGND2
SDATAIN
DCVDD
SYNC
RESET
CREF
WM9711L
R76
0R
JP15
DNP
ROUT2
LOUT2
SPKGND
MONOOUT
CAP2
COMP3
COMP2
COMP1
MICBIAS
VREF
AGND
AVDD1
36
35
34
33
32
31
30
29
28
27
26
25
C138
100n
AVDD2
NC1
NC2
NC3
NC4
AGND1
PCBEEP
PHONE
MIC1
MIC2
LINE_IN_L
LINE_IN_R
PD8
NRST
(AC97TX)
(AC97CK)
2
DNP
49
48
47
46
45
44
43
42
41
40
39
38
37
22p
JP14
AGND_AC97
AGND_AC97
MN14
4
3
AGND_AC97
THERMAL
GPIO5/SPDIF
GPIO4
GPIO3
GPIO2/IRQ
GPIO1
HPVDD
AGND2
HP_OUT_R
HP_GND
HP_OUT_L
SPKVDD
OUT3
C133
0R
C132
10u
10V
100k
3V3
3
PE31
R75
C129
470p
C128
470p
1
R74
R72
47k
STEREO_3.5mm
C130 C131
3V3
(EXT_CLK)
R71
47k
C139
100n
C140
10u
10V
C141
100n
R77
0R
C142
10u
10V
C143
100n
C144
10u
10V
8 Ohm SPEAKER
OUTPUT
2
JP17/JP18 are used
as testpoints
DNP
L7
220ohm at 100MHz
10k AVDD_AC97
R73
1
13
14
15
16
17
18
19
20
21
22
23
24
AGND_AC97
AVDD_AC97
L8
220ohm at 100MHz
C145
100n
AGND_AC97
C146
1u
R79
8.2K
1
C147
1u
R80
8.2K
1
AGND_AC97
LINE-IN
2
2
5
L9
J8
2
1
220ohm at 100MHz
R81
8.2K
R82
8.2K
C148
470p
3
C149
470p
4
STEREO_3.5mm
R83
680R
3V3
L11 AVDD_AC97
10uH
C150
1u
C153
100n
R85
C154
10u
10V
0R
AGND_AC97
MONO / STEREO
MICROPHONE INPUT
L10
220ohm at 100MHz
2
1
2
5
J9
C151
1u
C152
10u
10V
R84
680R
1
2
1
L12
220ohm at 100MHz
C155
470p
C156
470p
3
4
STEREO_3.5mm
AGND_AC97
AGND_AC97
For more information about the AC97 codec device, refer to the Wolfson WM9711L controller manufacturer's datasheet.
4-16
6495B–ATARM–21-Apr-10
AT91SAM9M10-G45-EK User Guide
Board Description
4.2.8
TV-Out Extension
The Chrontel™ CH7024 chip provides an interface between the SAM9M10 LCD Controller and a TV set
by converting LCD signals to TV signals.
The CH7024 is a TV encoder device which encodes the video signals and generates synchronization
signals for NTSC and PAL standards. Supported TV output formats are NTSC-M, NTSC-J, NTSC-433,
PAL-B/D/G/A/I, PAL-M, PAL-N and PAL-60. The CH7024 provides video output support for CVBS or Svideo.
Figure 4-13. TV-Out Extension Port
PE[0..30]
L17
2200R
1
MN20
TV_VSYNC
TV_HSYNC
TV_XCLK
PE6
VDDIO
DVDD
DGND
18
AVDD_PLL
32
AGND_PLL
31
AVDD
33
AGND
36
AVDD_DAC
25
AGND_DAC
29
ISET
30
CVBS
28
V
H
XCLK
DE
VDD 4
23
RESET
24
NC
34
Y6
1 OE
C199
10u
10V
1
L19
2200R
2
1
L20
2200R
2
1
L21
2200R
2
C200
100n
C202
100n
3V3
C201
10u
10V
C203
100n
C204
33p
RCA JACK
J20
L22
1%
3
1.8uH
27
C/CVBS
26
P-OUT
37
Composite
Video
Output
3V3
R183 75R
XO
3V3
SPD
SPC
2
R182
75R
C205
100p
C206
D8
100p 1
2
BAT54SLT1G
35
NRST
Y
21
22
1V8
C198
10u
10V
R181 75R
(TWDO)
(TWCK0)
10k DNP
1
C197
100n
R178 1.2k
4.7k
4.7k
R184
L18
2200R
38
16
C196
100n
XI/FIN
PA20
PA21
R179
R180
39
40
41
20
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
TP6
13MHz
2 VSS
OUT 3
R185
0R
DNP
R186
0R
DNP
2
3V3
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
19
2
CH7024B
1
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE15
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
3V3
3
(B7)
(B6)
(B5)
(B4)
(B3)
(B2)
(B1)
(B0)
(G7)
(G6)
(G5)
(G4)
(G3)
(G2)
(G1)
(G0)
(R7)
(R6)
(R5)
(R4)
(R3)
(R2)
(R1)
(R0)
(LCDDEN)
(LCDDOTCK)
(HSYNC)
(VSYNC)
(LCDCC)
(LCDMOD)
(LCDPWR)
Y7
4
PE30
PE29
PE28
PE27
PE26
PE25
PE24
PE23
PE22
PE21
PE20
PE19
PE18
PE17
PE16
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
13MHz
1
C207
100n
DNP
AT91SAM9M10-G45-EK User Guide
C208
10p
3
C209
10p
4-17
6495B–ATARM–21-Apr-10
Board Description
4.2.9
Software Controlled LEDs
Three users LED are provided for general use. The LEDs are connected to PIO port lines, allowing their
control through either GPIO or PWM control.
„
LEDs D1 to D3 are software controlled by PIO pins.
„
LEDs D4 to D6 indicate Ethernet traffic and link status. These are automatically managed by on-chip
microcontroller hardware. See Section 7.1 ”Schematics” .
Table 4-3. Discrete LEDs
LED
Description
Comment
D1
Green LED
User software controlled
D2
Green LED
User software controlled
D3
Red LED
User software controlled
D4
Yellow LED
Indicates transmission or reception via Ethernet
D5
Green LED
Indicates speed 100
D6
Green LED
Is lit when a good link test has been detected
Figure 4-14. Software Controlled LEDs
USER INTERFACE
3V3
Green
D1
1
3V3
2
R21
470R
PD0
2
R22
470R
PD31
D2
1
Green
R25
470R
1
PB15
PB16
D3
Red
R26
100k
2
BP3
PB14
PB18
3
Q2
IRLML2402
1
4-18
6495B–ATARM–21-Apr-10
4 UP
5 RIGHT
6 DOWN
JOYSTICK
PB17
PD30
C32
C33
C34
10n
10n
10n
2
POWER LED
LEFT
PUSH
1
2
3
R28
100R
C35
10n
C36
10n
PB[14..18]
AT91SAM9M10-G45-EK User Guide
Board Description
4.2.10
Serial Peripheral Interface Controller (SPI)
The SAM9M10 provides two high-speed Serial Peripheral Interface (SPI) controllers. One port is used to
interface with the on-board serial DataFlash®.
Figure 4-15. SPI
3V3
(test points)
DNP
JP11
PB0
PB1
PB2
PB3
R67
470k
3
1
2
(SPI0_MISO)
(SPI0_MOSI)
(SPI0_SPCK)
(SPI0_NPCS0)
3V3
MN13
1
2
8
1
2
4
SO
SI
SCK
CS
3
RESET
JP12
SIP2
NRST
VCC
6
GND
7
WP
5
C124
100n
SERIAL DATAFLASH
4.2.11
R68
0R
DNP
Two Wire Interface (TWI)
The SAM9M10 has a full speed (400 kHz) master/slave I2C Serial Controller. The controller is fully compatible with the industry standard I2C and SMBus Interfaces. This port is used to interface with the onboard Serial EEPROM, ISI and TV encoder interface.
Figure 4-16. TWI
3V3
R66
10k
MN12
3V3
C125
6
5
SCL
SDA
8
VCC
JP13
100n
4 GND
SIP2
A0
A1
A3
1
2
3
1
(TW CK0)
(TW DO)
2
PA21
PA20
WP
7
SERIAL EEPROM
4.2.12
SD/MMC Interface
The SAM9M10-G45-EK has two high-speed 8-bit multimedia interfaces MMC/MMCPlus v4.1. The first
interface is used as an 8-bit interface (MCI1), connected to a CE-ATA connector footprint and an 8-bit
SD/MMC card slot. The second interface is used as a 4-bit interface (MCI0), connected to a 4-bit
SD/MMC card slot.
The users must provide their own compatible cards for use with these connectors.
Please note that the power is connected to VCC, which is 3.3 volts.
AT91SAM9M10-G45-EK User Guide
4-19
6495B–ATARM–21-Apr-10
Board Description
Figure 4-17. SD/MMC0
3V3
8
7
6
5
R191R192R193R194R195R196R197R198
RR36
10k
1
2
3
4
68k 68k 68k 68k 68k 68k 68k 68k
(MCI1_W P)
(MCI1_CD)
PD29
PD11
PA[22..31]
RR39
J5
PA24
PA23
(MCI1_DA1)
(MCI1_DA0)
PA31
(MCI1_CK)
1
2
3
4
PA22
PA26
PA25
(MCI1_CDA)
(MCI1_DA3)
(MCI1_DA2)
1 RR41 8 27R
7
2
6
3
5
4
PA27
PA28
PA29
PA30
(MCI1_DA4)
(MCI1_DA5)
(MCI1_DA6)
(MCI1_DA7)
1
2
3
4
8
7
6 27R
5
RR42
16
15
14
8
7
6
5
4
3
2
1
9
3V3
13
12
11
10
C123
100n
27R
8
7
6
5
SD/MMCPlus CARD INTERFACE - MCI1
Figure 4-18. SD/MMC1
3V3
R187R188R189R190
R64
10k
R65
10k
68k 68k 68k 68k
(MCI0_CD)
PD10
PA[0..5]
PA3
PA2
(MCI0_DA1)
(MCI0_DA0)
PA0
(MCI0_CK)
PA1
PA5
PA4
(MCI0_CDA)
(MCI0_DA3)
(MCI0_DA2)
RR38 27R
8
1
7
2
6
3
5
4
1
2
3
4
8
7
6
5
RR40
27R
J6
3V3
12
11
10
8
7
C122 100n 6
5
4
3
2
1
9
SD/MMC CARD INTERFACE - MCI0
4.2.13
TFT LCD with Touch Panel
The SAM9M10 features an LCD controller. A 4.3" 480x272 Portrait Mode LCD provides the SAM9M10G45-EK with a low power LCD display, back light unit and a touch panel, similar to that used on commercial PDAs.
The TFT LCD component is a truly model number TFT1N4633.
Graphics and text can be displayed on the dot matrix panel with up to 16 million colors by supplying 24bit data signals (8bitxRGB by default) or 16-bit data signals (5+6+5bitxRGB in option). This allows the
user to develop graphical user interfaces for a wide variety of end applications.
Warning: never connect/disconnect the LCD display from the board while the power supply is on. Doing
so may damage both units and is not covered by warranty.
The back light voltage is generated from a CP2122ST boost converter. It is powered directly by the VIN
5 VCC power (the control for the back light voltages is separated from the main board voltages due to
the specific voltage requirements of the LCD panel).
4-20
6495B–ATARM–21-Apr-10
AT91SAM9M10-G45-EK User Guide
Board Description
Figure 4-19. TFT LCD
(pinxx = display pin number )
3V3
J24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Z7
LG PHILIPS
4.3" 480x272
TFT LCD DISPLAY
Conductors
on
TOP SIDE
PIN 45
PIN 1
LB043W Q1
pin45
pin44
pin43
pin42
pin41
pin40
pin39
pin38
pin37
pin36
pin35
pin34
pin33
pin32
pin31
pin30
pin29
pin28
pin27
pin26
pin25
pin24
pin23
pin22
pin21
pin20
pin19
pin18
pin17
pin16
pin15
pin14
pin13
pin12
pin11
pin10
pin9
pin8
pin7
pin6
pin5
pin4
pin3
pin2
pin1
VLED+
VLEDYpLCD
XpLCD
YmLCD
XmLCD
R180
10K
(LCDDEN)
PE6
(LCDPW R)
PE0
LCDDOTCK
PE[0..30]
R50 27R
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
RR48A
RR48B
RR48C
RR48D
RR49A
RR49B
RR49C
RR49D
RR50A
RR50B
RR50C
RR50D
RR51A
RR51B
RR51C
RR51D
RR52A
RR52B
RR52C
RR52D
RR53A
RR53B
RR53C
RR53D
BLUE7
BLUE6
BLUE5
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
GREEN7
GREEN6
GREEN5
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
RED7
RED6
RED5
RED4
RED3
RED2
RED1
RED0
C188
100nF
C189
10uF
10V
R136
4.7K
R179
R178
R177
0R
0R
0R
PE25
PE24
PE23
R176
R175
0R
0R
PE16
PE15
R174
R173
R172
0R
0R
0R
PE9
PE8
PE7
R48 is placed near processor
LCDDOTCK
3V3
R48 33R
PE30
PE29
PE28
PE27
PE26
PE25
PE24
PE23
PE22
PE21
PE20
PE19
PE18
PE17
PE16
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
(B7)
(B6)
(B5)
(B4)
(B3)
(B2)
(B1)
(B0)
(G7)
(G6)
(G5)
(G4)
(G3)
(G2)
(G1)
(G0)
(R7)
(R6)
(R5)
(R4)
(R3)
(R2)
(R1)
(R0)
(LCDDEN)
(LCDDOTCK)
(LCDCC)
(LCDPW R)
XF2M45151A
D12
STPS0540Z
VLED+
BLUE7
R171
R170
DNP
0R
PE24
PE30
BLUE6
R169
R168
DNP
0R
PE23
PE29
BLUE5
R167
R166
DNP
0R
PE22
PE28
BLUE4
R165
R164
DNP
0R
PE21
PE27
BLUE3
R163
R162
DNP
0R
PE20
PE26
GREEN7
R161
R160
DNP
0R
PE18
PE22
GREEN6
R159
R158
DNP
0R
PE17
PE21
GREEN5
R157
R156
DNP
0R
PE16
PE20
GREEN4
R155
R154
DNP
0R
PE15
PE19
GREEN3
R153
R152
DNP
0R
PE14
PE18
GREEN2
R151
R150
DNP
0R
PE13
PE17
RED7
R149
R148
DNP
0R
PE12
PE14
RED6
R147
R146
DNP
0R
PE11
PE13
RED5
R145
R144
DNP
0R
PE10
PE12
RED4
R184
R183
DNP
0R
PE9
PE11
RED3
R182
R181
DNP
0R
PE8
PE10
5V
L23
22uH
4
SW
CTRL
3
FB
THP
1
R123
10R
C208
DNP
MN25 TPS61161DRVT
6
VIN
COMP
7
VLED-
C201
2.2uF
GND
C202
1uF
5
PE2
(LCDCC)
2
C203
220nF
YpLCD
XmLCD
YmLCD
XpLCD
C209
DNP
R130
0R
R132
R133
0R
R137
10K
20mA MAX 9 LEDs Back Light
AT91SAM9M10-G45-EK User Guide
C210
DNP
0R
R131
C211
DNP
0R
(AD2Yp)
(AD1Xm)
(AD3Ym)
(AD0Xp)
PD22
PD21
PD23
PD20
4-21
6495B–ATARM–21-Apr-10
Board Description
4.2.14
Push Buttons
The SAM9M10-G45-EK is equipped with two system push buttons, two user push buttons and one joystick. The push buttons consist of momentary push button switches mounted directly to the board. When
any switch is depressed, a low (zero) appears at the associated input pin.
„
System push buttons:
– Reset, perform system reset
– Wakeup, perform system wake up
„
User push button:
– Right click
– Left click
„
Joystick:
– One touch, 5-way switching,
– Normally open momentary contacts,
– Push down to select in any position.
Figure 4-20.
Push Buttons
3V3
VDDBU
R23
100k
BP1
NRST
NRST
BP2
WAKE UP
RIGHT CLICK
R24
1k
WAKE UP
BP4
PB7
C31
R27
100R
10n
BP5
LEFT CLICK
4.2.15
PB6
C37
R29
10n
100R
Expansion Slot
„
GPIO1 & GPIO2, LCD signals (PIO E) are routed to the connectors extension J23
„
All I/Os of the SAM9M10 Image Sensor Interface are routed to connectors J17
„
Touch screen signals and analog I/O are connected to J18
This allows the developer to extend the features of the board by adding external hardware components
or boards.
4-22
6495B–ATARM–21-Apr-10
AT91SAM9M10-G45-EK User Guide
Board Description
Figure 4-21. Expansion Slot
CONNECTOR EXTENSION FOR LARGE LCD
J23
PE8
PE10
PE12
PE14
PE16
PE18
PE20
PE22
PE24
PE26
PE28
PE30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
LCDHSYNC
LCDDOTCK
PE6
PE0
(GPIO1)
PD14
3V3
DNP
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PE7
PE9
PE11
PE13
PE15
PE17
PE19
PE21
PE23
PE25
PE27
PE29
LCDVSYNC
PE2
PE1
(GPIO2)
PD15
HDR_2x20_SMT
J18
PD21
PD23
PD25
PD27
PD19
(AD1Xm)
(AD3Ym)
R175
0R
DNP
3V3
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
(AD0Xp)
(AD2Yp)
R176
PD20
PD22
PD24
PD26
PD18
0R
DNP
5V
3V3
HDR_2x10_SMT
DNP
IMAGE SENSOR CONNECTOR
3V3
C210
100n
C211
10u
10V
C212
100n
(CTRL2)
PA20
PB31
PB29
PB30
PB28
PB20
PB22
PB24
PB26
PB8
PB10
PD13
J17
VDDISI
PD12
(CTRL1)
PA21
PB21
PB23
PB25
PB27
PB9
PB11
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
HDR_2x15_SMT
AT91SAM9M10-G45-EK User Guide
4-23
6495B–ATARM–21-Apr-10
Section 5
Configuration
5.1
JTAG/ICE Configuration
Table 5-1. JTAG/ICE Configuration
Designation
5.2
Default Setting
Feature
R91
Not populated
Disables the ICE NTRST input
R92
Soldered
Enables the ICE RTCK return. R94 must be opened
R93
Soldered
Enables the ICE NRST input
R94
Not populated
Disables TCK <-> RTCK local loop
ETHERNET Configuration
RMII is the factory default mode.
To evaluate the MII mode, the user has to unsolder R99 and solder R100, R103 to R105, R108 to R110,
R112, R114, C174, C175, Y5.
AT91SAM9M10-G45-EK User Guide
5-1
6495B–ATARM–21-Apr-10
Configuration
5.3
Jumpers Configuration
Two types of jumpers are used on the SAM9M10-G45-EK board:
„
2-pin jumpers with two possible settings:
– Fitted: the circuit is closed
– Not fitted: the circuit is open
„
3-pin jumpers with two possible positions, for which settings are presented in the following tables.
Table 5-2. Jumpers Configuration
Default
Setting
Designation
J1
(combined
jumper array)
JP1
JP2
Closed
J1-1
1-2
VDDUTMII
3V3
Closed
J1-2
3-4
VDDUTIMC
1V
Closed
J1-3
5-6
VDDCORE
1V
Closed
J1-4
7-8
VDDPLLUTMI
1V
1-2
VDDIOP0
3V3
1-2
JP1
2-3
External power to VDDIOP0
1-2
VDDIOP1
2-3
External power to VDDIOP1
1-2
VDDIOP2
2-3
External power to VDDIOP2
1-2
JP3
1-2
JP4
Opened
JP5
1-2
JP6
1-2
JP7
Feature
1-2
3V3 nominal
3V3
JP2
3V3 nominal
3V3
JP3
3V3 nominal
Forces power on.
To use the software shutdown control, JP4 must be opened.
3V battery backup must be present and JP7 jumper set in position 1-2
1-2
VDDIOM0
1V8
2-3
External power to VDDIOM0
1-2
VDDIOM1
2-3
External power to VDDIOM1
1-2
VDDBU
Lithium 3V Battery
2-3
VDDBU
3.3V from regulator
JP5
1V8 nominal
1V8
JP6
1V8 nominal
JP7
JP8
Opened
BMS Enables Boot on the internal ROM; closed selects the boot from the external device connected
to NCS0
JP9
Closed
Enables chip select access, Boot on the NCS0 (MN10 Flash)
JP10
Closed
Enables chip select access, Boot on the NCS3 (MN11 NAND Flash)
JP11
Test point
JP12
Closed
Enables chip select access, Boot on the SPIO_NPCS0 (Serial DataFlash MN13)
JP13
Opened
Set address A0 low (MN12 Serial EEPROM), enable Boot access.
JP14
JP11.1: SO
JP14.1 = Line_Out
JP15
JP11.2: SI
JP11.3: SCK
JP14.3 = AGND
Used to connect a Loudspeaker
JP16
Closed
JP17-JP18
Test points
5-2
6495B–ATARM–21-Apr-10
DISMDIX (MN18)
Give access to the four GPIOs of WM9711L
AT91SAM9M10-G45-EK User Guide
Configuration
5.4
Miscellaneous Configuration Items
N.P = not populated
P = populated
Table 5-3. Miscellaneous Configuration
Designation
Default
Setting
R34
N.P
R35
P
Connect TSADVREF to VDDANA (may be used for specific filtering)
R36
P
Connect GNDANA to GND (may be used for specific filtering)
R38
P
Force TST pin to GND (chip is set in non-test mode = normal operation mode)
R63
N.P
Write protect NAND Flash (mount a 0-ohm resistor to write-protect the NAND
Flash device)
R68
N.P
Write protect serial DataFlash (mount a 0-ohm resistor to write-protect the serial
Flash device)
R75
N.P
External clock Audio AC97 (mount a 0-ohm resistor to connect it)
R91,R92
R93,R94
JTAGSEL
ICE interface reset and clocking schemes (see Section 5.1 ”JTAG/ICE
Configuration” )
R100, R103
to R105,
R108 to
R110, R112,
R114, C174,
C175, Y5
Y6, R184,
R186
Feature
Ethernet interface, MII mode (see Section 5.2 ”ETHERNET Configuration” )
N.P
External 13 MHz oscillator (option) for the on-board video composite encoder
TP1
GND Test point
TP2
GND Test point
TP3
GND Test point
TP4
GND Test point
5.5
PIO Configuration
5.5.1
Peripheral Signals Multiplexing on I/O Lines
The AT91SAM9M10 product features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be
assigned to one of two peripheral functions, A or B. The multiplexing tables in the following paragraphs
define how the I/O lines of peripherals A and B are multiplexed on the PIO Controllers.
5.5.2
Multiplexing on PIO Controller A (PIOA)
"R.Select" = connection selectable via an on-board resistor (default not populated)
AT91SAM9M10-G45-EK User Guide
5-3
6495B–ATARM–21-Apr-10
Configuration
Table 5-4. PIO Multiplexing Port A
I/O
Peripheral A
PA0
MCI0_CK
TCLK3
MMCI0 Clock
VDDIOP0
PA1
MCI0_CDA
TIOA3
MMCI0 Command
VDDIOP0
PA2
MCI0_DA0
TIOB3
MMCI0 Data0
VDDIOP0
PA3
MCI0_DA1
TCKL4
MMCI0 Data1
VDDIOP0
PA4
MCI0_DA2
TIOA4
MMCI0 Data2
VDDIOP0
PA5
MCI0_DA3
TIOB4
MMCI0 Data3
VDDIOP0
PA6
MCI0_DA4
ETX2
Ethernet MII
VDDIOP0
PA7
MCI0_DA5
ETX3
Ethernet MII
VDDIOP0
PA8
MCI0_DA6
ERX2
Ethernet MII
VDDIOP0
PA9
MCI0_DA7
ERX3
Ethernet MII
VDDIOP0
PA10
ETX0
Ethernet RMII Transmit data 0
VDDIOP0
PA11
ETX1
Ethernet RMII Transmit data 1
VDDIOP0
PA12
ERX0
Ethernet RMII Receive data 0
VDDIOP0
PA13
ERX1
Ethernet RMII Receive data 1
VDDIOP0
PA14
ETXEN
Ethernet RMII Transmit enable
VDDIOP0
PA15
ERXDV
Ethernet RMII Receive data valid
VDDIOP0
PA16
ERXER
Ethernet RMII Receive Error
VDDIOP0
PA17
ETXCK
Ethernet RMII Transmit Clock
VDDIOP0
PA18
EMDC
Ethernet RMII Manag.Data Clock
VDDIOP0
PA19
EMDIO
Ethernet RMII Manag.Data In/Out
VDDIOP0
PA20
TWD0
Two Wire Interface Data
VDDIOP0
PA21
TWCK0
Two Wire Interface Clock
VDDIOP0
PA22
MCI1_CDA
SCK3
MMCI1 Command
VDDIOP0
PA23
MCI1_DA0
RTS3
MMCI1 Data0
VDDIOP0
PA24
MCI1_DA1
CTS3
MMCI1 Data1
VDDIOP0
PA25
MCI1_DA2
PWM3
MMCI1 Data2
VDDIOP0
PA26
MCI1_DA3
TIOB2
MMCI1 Data3
VDDIOP0
PA27
MCI1_DA4
ETXER
R.Select
MMCI1 Data4
Ethernet MII
VDDIOP0
PA28
MCI1_DA5
ERXCK
R.Select
MMCI1 Data5
Ethernet MII
VDDIOP0
PA29
MCI1_DA6
ECRS
R.Select
MMCI1 Data6
Ethernet MII
VDDIOP0
PA30
MCI1_DA7
ECOL
R.Select
MMCI1 Data7
Ethernet MII
VDDIOP0
PA31
MCI1_CK
PCK0
5-4
6495B–ATARM–21-Apr-10
Peripheral B
Function and Comments
MMCI1_clock
Power
VDDIOP0
AT91SAM9M10-G45-EK User Guide
Configuration
5.5.3
Multiplexing on PIO Controller B (PIOB)
Table 5-5. PIO Multiplexing Port B
I/O
Peripheral A
Peripheral B
PB0
SPI0_MISO
SPI Slave Out Serial DataFlash
VDDIOP0
PB1
SPI0_MOSI
SPI Slave In Serial DataFlash
VDDIOP0
PB2
SPI0_SPCK
SPI Serial Clock Serial DataFlash
VDDIOP0
PB3
SPI0_NPCS0
SPI Chip Select Serial DataFlash
VDDIOP0
PB4
TXD1
USART1 Transmit Data
VDDIOP0
PB5
RXD1
USART1 Receive Data
VDDIOP0
PB6
TXD2
User Push Button Right click
VDDIOP0
PB7
RXD2
User Push Button Left click
VDDIOP0
PB8
TXD3
ISI_D8
Image Sensor Data 8
VDDIOP2
PB9
RXD3
ISI_D9
Image Sensor Data 9
VDDIOP2
PB10
TWD1
ISI_D10
Image Sensor Data 10
VDDIOP2
PB11
TWCK1
ISI_D11
Image Sensor Data 11
VDDIOP2
PB12
DRXD
DBGU Receive Data
VDDIOP0
PB13
DTXD
DBGU Transmit Data
VDDIOP0
PB14
SPI1_MISO
Joystick Left
VDDIOP0
PB15
SPI1_MOSI
CTS0
Joystick Right
VDDIOP0
PB16
SPI1_SPCK
SCK0
Joystick Up
VDDIOP0
PB17
SPI1_NPCS0
RTS0
Joystick Down
VDDIOP0
PB18
RXD0
SPI0_NPCS1
Joystick Push
VDDIOP0
PB19
TXD0
SPI0_NPCS2
UsbVbus
VDDIOP0
PB20
ISI_D0
Image Sensor Data 0
VDDIOP2
PB21
ISI_D1
Image Sensor Data 1
VDDIOP2
PB22
ISI_D2
Image Sensor Data 2
VDDIOP2
PB23
ISI_D3
Image Sensor Data 3
VDDIOP2
PB24
ISI_D4
Image Sensor Data 4
VDDIOP2
PB25
ISI_D5
Image Sensor Data 5
VDDIOP2
PB26
ISI_D6
Image Sensor Data 6
VDDIOP2
PB27
ISI_D7
Image Sensor Data 7
VDDIOP2
PB28
ISI_PCK
Image Sensor Data Clock
VDDIOP2
PB29
ISI_VSYNC
Image Sensor Vertical Synchro
VDDIOP2
PB30
ISI_HSYNC
Image Sensor Horizontal Synchro
VDDIOP2
PB31
ISI_MCK
Image Sensor Reference Clock
VDDIOP2
PCK1
AT91SAM9M10-G45-EK User Guide
Function and Comments
Power
5-5
6495B–ATARM–21-Apr-10
Configuration
5.5.4
Multiplexing on PIO Controller C (PIOC)
Table 5-6. PIO Multiplexing Port C
I/O
Peripheral A
Peripheral B
Function and Comments
Power
PC0
DQM2
VDDIOM1
PC1
DQM3
VDDIOM1
PC2
A19
Add19 NAND Flash
VDDIOM1
PC3
A20
Add20 NAND Flash
VDDIOM1
PC4
A21/NANDALE
ALE NAND Flash
VDDIOM1
PC5
A22/NANDCLE
CLE NAND Flash
VDDIOM1
PC6
A23
VDDIOM1
PC7
A24
VDDIOM1
PC8
CFCE1
PC9
CFCE2
RTS2
VDDIOM1
PC10
NCS4/CFCS0
TCLK2
VDDIOM1
PC11
NCS5/CFCS1
CTS2
VDDIOM1
PC12
A25/CFRNW
VDDIOM1
PC13
NCS2
VDDIOM1
PC14
NCS3/NANDCS
PC15
NWAIT
VDDIOM1
PC16
D16
VDDIOM1
PC17
D17
VDDIOM1
PC18
D18
VDDIOM1
PC19
D19
VDDIOM1
PC20
D20
VDDIOM1
PC21
D21
VDDIOM1
PC22
D22
VDDIOM1
PC23
D23
VDDIOM1
PC24
D24
VDDIOM1
PC25
D25
VDDIOM1
PC26
D26
VDDIOM1
PC27
D27
VDDIOM1
PC28
D28
VDDIOM1
PC29
D29
VDDIOM1
PC30
D30
VDDIOM1
PC31
D31
VDDIOM1
5-6
6495B–ATARM–21-Apr-10
Ready/Busy NAND Flash
Chip select NAND Flash
VDDIOM1
VDDIOM1
AT91SAM9M10-G45-EK User Guide
Configuration
5.5.5
Multiplexing on PIO Controller D (PIOD)
Table 5-7. PIO Multiplexing Port D
I/O
Peripheral A
Peripheral B
PD0
TK0
PWM3
PD1
Function and Comments
Power
Command LED2
VDDIOP0
TF0
Output ENA USB Host
VDDIOP0
PD2
TD0
Input FLGA USB Host
VDDIOP0
PD3
RD0
Output ENB USB Host
VDDIOP0
PD4
RK0
Input FLGB USB Host
VDDIOP0
PD5
RF0
Int. Ethernet 10/100 MDINTR
VDDIOP0
PD6
AC97RX
AC97 Receive Signal
VDDIOP0
PD7
AC97TX
TIOA5
AC97 Transmit Signal
VDDIOP0
PD8
AC97FS
TIOB5
AC97 Frame Sync Signal
VDDIOP0
PD9
AC97CK
TCLK5
AC97 Clock Signal
VDDIOP0
PD10
TD1
Card Detect MMCI0 MCI0_CD
VDDIOP0
PD11
RD1
Card Detect MMCI1 MCI1_CD
VDDIOP0
PD12
TK1
CTRL1 Image Sensor Interface
VDDIOP0
PD13
RK1
CTRL2 Image Sensor Interface
VDDIOP0
PD14
TF1
GPIO1 Large LCD (connector)
VDDIOP0
PD15
RF1
GPIO2 Large LCD (connector)
VDDIOP0
PD16
RTS1
USART1 Request to Send
VDDIOP0
PD17
CTS1
USART1 Clear To Send
VDDIOP0
PD18
SPI1_NPCS2
IRQ
VDDIOP0
PD19
SPI1_NPCS3
FIQ
VDDIOP0
PD20
TIOA0
TSAD0
Touch screen X_Right
VDDANA
PD21
TIOA1
TSAD1
Touch screen X_Left
VDDANA
PD22
TIOA2
TSAD2
Touch screen Y_Up
VDDANA
PD23
TCLK0
TSAD3
Touch screen Y_Down
VDDANA
PD24
SPI0_NPCS1
PWM0
GPAD4
General purpose A/D4
VDDANA
PD25
SPI0_NPCS2
PWM1
GPAD5
General purpose A/D5
VDDANA
PD26
PCK0
PWM2
GPAD6
General purpose A/D6
VDDIOP0
PD27
PCK1
SPI0_NPCS3
GPAD7
General purpose A/D7
VDDIOP0
PD28
TSADTRG
SPI1_NPCS1
USB Plug-ID IDUSB
VDDIOP0
PD29
TCLK1
SCK1
MCI1_WP
VDDIOP0
PD30
TIOB0
SCK2
Command Power Led
VDDIOP0
PD31
TIOB1
PWM1
Command LED1
VDDIOP0
PCK0
AT91SAM9M10-G45-EK User Guide
5-7
6495B–ATARM–21-Apr-10
Configuration
5.5.6
Multiplexing on PIO Controller E (PIOE)
Table 5-8. PIO Multiplexing Port E
I/O
Peripheral A
PE0
LCDPWR
PE1
Peripheral B
Power
LCD Panel Pow.Enab.Ctrl
VDDIOP1
LCDMOD
LCD Modulation Signal
VDDIOP1
PE2
LCDCC
LCD Contrast Control
VDDIOP1
PE3
LCDVSYNC
LCD Vertical Synch.
VDDIOP1
PE4
LCDHSYNC
LCD Horizontal Synch.
VDDIOP1
PE5
LCDDOTCK
LCD Dot Clock
VDDIOP1
PE6
LCDDEN
LCD Data Enable
VDDIOP1
PE7
LCDD0
LCDD2
LCD-Red0
VDDIOP1
PE8
LCDD1
LCDD3
LCD-Red1
VDDIOP1
PE9
LCDD2
LCDD4
LCD-Red2
VDDIOP1
PE10
LCDD3
LCDD5
LCD-Red3
VDDIOP1
PE11
LCDD4
LCDD6
LCD-Red4
VDDIOP1
PE12
LCDD5
LCDD7
LCD-Red5
VDDIOP1
PE13
LCDD6
LCDD10
LCD-Red6
VDDIOP1
PE14
LCDD7
LCDD11
LCD-Red7
VDDIOP1
PE15
LCDD8
LCDD12
LCD-Green0
VDDIOP1
PE16
LCDD9
LCDD13
LCD-Green1
VDDIOP1
PE17
LCDD10
LCDD14
LCD-Green2
VDDIOP1
PE18
LCDD11
LCDD15
LCD-Green3
VDDIOP1
PE19
LCDD12
LCDD18
LCD-Green4
VDDIOP1
PE20
LCDD13
LCDD19
LCD-Green5
VDDIOP1
PE21
LCDD14
LCDD20
LCD-Green6
VDDIOP1
PE22
LCDD15
LCDD21
LCD-Green7
VDDIOP1
PE23
LCDD16
LCDD22
LCD-Blue0
VDDIOP1
PE24
LCDD17
LCDD23
LCD-Blue1
VDDIOP1
PE25
LCDD18
LCD-Blue2
VDDIOP1
PE26
LCDD19
LCD-Blue3
VDDIOP1
PE27
LCDD20
LCD-Blue4
VDDIOP1
PE28
LCDD21
LCD-Blue5
VDDIOP1
PE29
LCDD22
LCD-Blue6
VDDIOP1
PE30
LCDD23
LCD-Blue7
VDDIOP1
PE31
PWM2
AC97 External Clock
VDDIOP1
5-8
6495B–ATARM–21-Apr-10
PCK0
Function and Comments
PCK1
AT91SAM9M10-G45-EK User Guide
Section 6
Connectors
6.1
Power Supply
The SAM9M10-G45-EK evaluation board can be powered from a DC 5V power supply via the external
power supply jack (J2) shown in Figure 6-1. The positive pole must be on J2 center pin.
Figure 6-1.
Power Supply Connector J2
Table 6-1. Power Supply Connector J2 Signal Description
6.2
Pin
Mnemonic
Signal description
1
Center
+5 VCC
2
Gnd
RS232 Connector with RTS/CTS Handshake Support
Connector J11 is the COM1 connector.
Figure 6-2.
RS232 COM1 Connector J11
AT91SAM9M10-G45-EK User Guide
6-1
6495B–ATARM–21-Apr-10
Connectors
Table 6-2. Serial COM1 Connector J11 Signal Descriptions
Pin
1, 4, 6, 9
6.3
Mnemonic
Signal description
NC
NO CONNECTION
2
TXD TRANSMITTED DATA
RS232 serial data output signal
3
RXD RECEIVED DATA
RS232 serial data input signal
5
GND
GROUND
7
RTS READY TO SEND
Active-positive RS232 input signal
8
CTS CLEAR TO SEND
Active-positive RS232 output signal
DBGU
Connector J10 is the DBGU connector.
Figure 6-3.
RS232 DBGU Connector J10
Table 6-3. RS232 DBGU Connector J10 Signal Descriptions
Pin
1, 4, 6, 7, 8, 9
6-2
6495B–ATARM–21-Apr-10
Mnemonic
Signal description
NC
NO CONNECTION
2
TXD TRANSMITTED DATA
RS232 serial data output signal
3
RXD RECEIVED DATA
RS232 serial data input signal
5
GND
GROUND
AT91SAM9M10-G45-EK User Guide
Connectors
6.4
Ethernet
Connector J15 is the RJ-45 Ethernet Connector.
Figure 6-4.
Ethernet RJ45 Connector J15
Table 6-4. Ethernet RJ45 Connector J15 Signal Descriptions
Pin
6.5
Mnemonic
Pin
Mnemonic
1
TxData+ DIFFERENTIAL OUTPUT PLUS
2
Txdata- DIFFERENTIAL OUTPUT MINUS
3
RxData+ DIFFERENTIAL INPUT PLUS
4
Shield
5
Shield
6
RxData- DIFFERENTIAL INPUT MINUS
7
Shield
8
Shield
USB Host
Connector J12 is the USB Host connector.
Figure 6-5.
USB Host type A connector J12
Table 6-5. USB Host Type A Connector J12 Signal Descriptions
Pin
Mnemonic
Signal description
1
Vbus
5v power
2
DM
Data minus
3
DP
Data plus
4
Gnd
Ground
5
Shield
Shield
AT91SAM9M10-G45-EK User Guide
6-3
6495B–ATARM–21-Apr-10
Connectors
6.6
USB Host/Device
Connector J14 is the USB Host/Device connector.
Figure 6-6.
USB Host/Device Micro AB connector J14
Table 6-6. USB Host/Device MicroAB Connector J14 Signal Descriptions
Pin
6.7
Mnemonic
Signal description
1
Vbus
5v power
2
DM
Data minus
3
DP
Data plus
4
ID
On the Go Identification
5
Gnd
Ground
JTAG Debugging Connector
Connector J13 is the JTAG/ICE connector.
A SAM-ICE connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm
male) that mates with IDC sockets mounted on a ribbon cable.
Figure 6-7.
6-4
6495B–ATARM–21-Apr-10
JTAG/ICE Connector J13
AT91SAM9M10-G45-EK User Guide
Connectors
Table 6-7. JTAG/ICE Connector J13 Signal Descriptions
Pin
Mnemonic
Description
1
VTref. 3.3V power
This is the target reference voltage. It is used to check if the target
has power, to create the logic-level reference for the input
comparators, and to control the output logic levels to the target. It is
normally fed from VDD on the target board and must not have a
series resistor.
2
Vsupply. 3.3V power
This pin is not connected in SAM-ICE. It is reserved for compatibility
with other equipment. Connect to VDD or leave open in target
system.
3
nTRST TARGET RESET - Active-low output
signal that resets the target
JTAG Reset. Output from SAM-ICE to the Reset signal on the target
JTAG port. Typically connected to nTRST on the target CPU. This pin
is normally pulled HIGH on the target to avoid unintentional resets
when there is no connection.
4
GND
Common ground
5
TDI TEST DATA INPUT - Serial data output line,
sampled on the rising edge of the TCK signal.
JTAG data input of target CPU. It is recommended that this pin is
pulled to a defined state on the target board. Typically connected to
TDI on target CPU.
6
GND
Common ground
7
TMS TEST MODE SELECT
JTAG mode set input of target CPU. This pin should be pulled up on
the target. Typically connected to TMS on target CPU. Output signal
that sequences the target's JTAG state machine, sampled on the
rising edge of the TCK signal.
8
GND
Common ground
9
TCK TEST CLOCK - Output timing signal, for
synchronizing test logic and control register
access.
JTAG clock signal to target CPU. It is recommended that this pin is
pulled to a defined state on the target board. Typically connected to
TCK on target CPU.
10
GND
Common ground
11
RTCK - Input Return test clock signal from the
target.
Some targets must synchronize the JTAG inputs to internal clocks. To
assist in meeting this requirement, a returned and retimed TCK can
be used to dynamically control the TCK rate. SAM-ICE supports
adaptive clocking which waits for TCK changes to be echoed
correctly before making further changes. Connect to RTCK if
available, otherwise to GND
12
GND
Common ground
13
TDO JTAG TEST DATA OUTPUT - Serial data
input from the target.
JTAG data output from target CPU. Typically connected to TDO on
target CPU.
14
GND
Common ground
15
nSRST RESET
Active-low reset signal. Target CPU reset signal
16
GND
Common ground
17
RFU
This pin is not connected in SAM-ICE.
18
GND
Common ground
19
RFU
This pin is not connected in SAM-ICE
20
GND
Common ground
AT91SAM9M10-G45-EK User Guide
6-5
6495B–ATARM–21-Apr-10
Connectors
6.8
SD/MMC- MCI0
Connector J6 is the SD/MMC connector.
Figure 6-8.
SD/MMC0 Connector J6
Table 6-8. SD/MMC0 Connector J6 Signal Descriptions
6-6
6495B–ATARM–21-Apr-10
Pin
Mnemonic
Pin
Mnemonic
1
RSV/DAT3
2
CDA
3
GND
4
VCC
5
CLK
6
GND
7
DAT0
8
DAT1
9
DAT2
10
Card Detect
11
GND
12
AT91SAM9M10-G45-EK User Guide
Connectors
6.9
SD/MMC- MCI1
Connector J5 is the SD/MMC connector.
Figure 6-9.
SD/MMC1 Connector J5
Table 6-9. SD/MMC1 Connector J5 Signal Descriptions
Pin
Mnemonic
Pin
Mnemonic
1
RSV/DAT3
2
CMD
3
GND
4
VCC
5
CLK
6
7
DAT0
8
DAT1
9
DAT2
10
DAT3
11
DAT4
12
DAT5
13
DAT6
14
DAT7
AT91SAM9M10-G45-EK User Guide
6-7
6495B–ATARM–21-Apr-10
Connectors
6.10
AC97
„
Connector J7 is the Headphone connector.
„
Connector J8 is the Line In connector.
„
Connector J9 is the Microphone Input.
„
Connector JP15 is the Speaker Output connector
Figure 6-10. Audio Connector J7, J8, J9
Table 6-10. J7, J8, J9 Signal Description
Pin
Mnemonic
1
Signal
2
Signal
3
Gnd
Table 6-11. Speaker JP15 Signal Descriptions
6-8
6495B–ATARM–21-Apr-10
Pin
Mnemonic
1
Speaker bridge output A
2
Speaker bridge output B
AT91SAM9M10-G45-EK User Guide
Connectors
6.11
Image Sensor - ISI
Connector J17 is the ISI connector.
Figure 6-11. ISI Connector J17
Table 6-12. ISI Connector J17 Signal Descriptions
Pin
Mnemonic
Pin
Mnemonic
1
VCC 3v3
2
Gnd
3
VCC 3v3
4
Gnd
5
Ctrl1
6
Ctrl2
7
SCL
8
SDA
9
Gnd
10
ISI_MCK
11
Gnd
12
ISI_VSYNC
13
Gnd
14
ISI_HSYNC
15
Gnd
16
ISI_PCK
17
Gnd
18
ISI_Data0
19
ISI_Data1
20
ISI_Data2
21
ISI_Data3
22
ISI_Data4
23
ISI_Data5
24
ISI_Data6
25
ISI_Data7
26
ISI_Data8
27
ISI_Data9
28
ISI_Data10
29
ISI_Data11
30
Gnd
AT91SAM9M10-G45-EK User Guide
6-9
6495B–ATARM–21-Apr-10
Connectors
6.12
Video
Connector J20 is the Video connector
Figure 6-12. Video Connector J20
Table 6-13. Video Connector J20 Signal Description
Pin
Mnemonic
Signal description
1
Center
Composite video signal output
6.13
Display Devices
6.13.1
TFT LCD
Connector J24 is the TFT-LCD connector.
Figure 6-13. TFT LCD Connector J24
Table 6-14. TFT LCD Connector J24 Signal Descriptions
6-10
6495B–ATARM–21-Apr-10
Pin
Mnemonic
Pin
Mnemonic
1
VLED-
2
VLED+
3
GND
4
VDD 3V3
5
R0
6
R1
7
R2
8
R3
9
R4
10
R5
AT91SAM9M10-G45-EK User Guide
Connectors
Table 6-14. TFT LCD Connector J24 Signal Descriptions
6.14
Pin
Mnemonic
Pin
Mnemonic
11
R6
12
R7
13
G0
14
G1
15
G2
16
G3
17
G4
18
G5
19
G6
20
G7
21
B0
14
B1
23
B2
16
B3
25
B4
18
B5
27
B6
20
B7
29
GND
30
DCLK
31
DISPON
32
HSYNC
33
VSYNC
34
LCDEN
35
NO CONNECT
36
GND
37
X2
38
Y1
39
X1
40
Y2
LCD Extension
Connectors J23 and J18 are for an optional LCD extension (not populated).
Table 6-15. Connector J23 Signal Description for an LCD Extension
Pin
Mnemonic
Pin
Mnemonic
1
PE8
RED Data Signal
2
PE7
RED Data Signal (LSB)
3
PE10
RED Data Signal
4
PE9
RED Data Signal
5
PE12
RED Data Signal
6
PE11
RED Data Signal
7
PE14
RED Data Signal (MSB)
8
PE13
RED Data Signal
9
PE16
GREEN Data Signal
10
PE15
GREEN Data Signal (LSB
11
PE18
GREEN Data Signal
12
PE17
GREEN Data Signal
13
PE20
GREEN Data Signal
14
PE19
GREEN Data Signal
15
PE22
GREEN Data Signal (MSB)
16
PE21
GREEN Data Signal
17
PE24
BLUE Data Signal
18
PE23
BLUE Data Signal (LSB)
19
PE26
BLUE Data Signal
20
PE25
BLUE Data Signal
21
PE28
BLUE Data Signal
22
PE27
BLUE Data Signal
23
PE30
BLUE Data Signal (MSB)
24
PE29
BLUE Data Signal
25
PE4
LCDHSYNC
26
PE3
LCDVSYNC
27
PE5
LCDDOTCK
28
GND
(0V)
29
GND
(0V)
30
NC
AT91SAM9M10-G45-EK User Guide
6-11
6495B–ATARM–21-Apr-10
Connectors
Table 6-15. Connector J23 Signal Description for an LCD Extension
Pin
Mnemonic
Pin
Mnemonic
31
PE6
LCDDEN
32
PE2
LCDCC
33
PE0
DISPON
34
PE1
LCDMOD
35
PD14
GPIO1
36
PD15
GPIO2
37
GND
(0V)
38
GND
(0V)
39
VCC
+3V3 power source
40
NC
Table 6-16. Connector J18 Signal Description for an LCD Extension
Pin
6-12
6495B–ATARM–21-Apr-10
Mnemonic
Pin
Mnemonic
1
XM
AD1XM
2
XP
AD0XP
3
YM
AD3YM
4
YP
AD2YP
5
GND
(0V)
6
GND
(0V)
7
PD25
PD25
8
PD24
PD24
9
PD27
PD27
10
PD26
PD26
11
PD19
PD19
12
PD18
PD18
13
GND
(0V)
14
GND
(0V)
15
GND
(0V)
16
17
GND
(0V)
18
GND
(0V)
19
VCC
+3V3 power source
20
VCC
+3V3 power source
+5V
AT91SAM9M10-G45-EK User Guide
Section 7
Schematics
7.1
Schematics
This section contains the following schematics:
„
Top Level view, block architecture of the design
„
Power Supply
„
SAM Processor
„
Bus impedance adaptor
„
Main memory
„
EBI memory
„
MCI & TWI
„
Audio AC97
„
Serial interfaces
„
Ethernet
„
LCD
„
Video interfaces and LCD extension
AT91SAM9M10-G45-EK User Guide
7-1
6495B–ATARM–21-Apr-10
7
6
4
3
2
1
3V3
POWER SUPPLY
1V8
POWER
USER
INTERFACE
D
5
EBI0
EBI0 DDR2 INTERFACE
1V
DDR2
128MB
5V
8
EBI0 DDR2 INTERFACE
PIO
D
Sheet 2
EBI1 DDR2 INTERFACE
HOST
EBI1 DATA INTERFACE
ICE
INTERFACE
PIO A,...E
ATMEL
ARM9 Processor
SAM9M10 (LFBGA324)
10/100 FAST
ETHERNET
RJ 45
EBI1 NANDFLASH INTERFACE
EBI1 BUS INTERFACE
Sheet 9
C
EBI1 FLASH INTERFACE
EBI1 ADDRESS INTERFACE
FLASH
HOST
DEVICE
NAND
FLASH
PIO
Sheet 6
Sheet 4
PIO
CARD
READER
PIO A,...E
LCD INTERFACE
CARD
READER
4.3"
480x272
TFT
RCA
B
MIC
PIO
Sheet 3
IN
ISI
SERIAL
EEPROM
AUDIO
B
CAMERA
INTERFACE
SERIAL
DATA
FLASH
OUT
HE 14
TOUCH SCREEN
MMC SD
SDIO
HE 14
Sheet 10
PIO
CONNECTOR
C
MMC SD
SDIO
COM1
DDR2
128MB
RES.ARRAYS
EBI0_EBI1 ADAPTER
EBI1
RS232
USB
HE 10
Sheet 5
DBGU
Sheet 8
TV
INTERFACE
Sheet 7
Sheet 11 12
NOTE
"DNP" means the component is not populated by default
A
PIOA
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
USAGE
MCI0_CK
MCI0_CDA
MCI0_DA0
MCI0_DA1
(MCI0_DA2)
(MCI0_DA3)
TXD2
TXD3
RXD2
RXD3
TXD0
TXD1
RXD0
RXD1
TX_EN
RX_DV
PIOA
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
USAGE
RX_ER
TX_CLK
MDC
MDIO
TWDO
TWCK0
MCI1_CDA
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
MCI1_DA4/TX_ER
MCI1_DA5/RX_CLK
MCI1_DA6/CRS
MCI1_DA7/COL
MCI1_CK
PIOB
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
USAGE
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
TXD1
RXD1
BP5_LEFT
BP4_RIGHT
ISI_D8
ISI_D9
ISI_D10
ISI_D11
DRXD
DTXD
BP3_LEFT
BP3_RIGHT
PIOB
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
USAGE
BP3_UP
BP3_DOWN
BP3_PUSH
VBUS
ISI_D0
ISI_D1
ISI_D2
ISI_D3
ISI_D4
ISI_D5
ISI_D6
ISI_D7
ISI_PCK
ISI_VSYNC
ISI_HSYNC
ISI_MCK
PIOC
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
USAGE
NOT USED
NOT USED
A19
A20
NANDALE/A21
NANDCLE
NOT USED
NOT USED
RDY/BSY
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NCS3
NOT USED
PIO
PIOC
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
MUXING
USAGE
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
PIOD
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
USAGE
USER LED D6
ENA
FLGA
ENB
FLGB
MDINTR
AC97RX
AC97TX
AC97FS
AC97CK
MCI0_CD
(MCI1_CD)
CTRL1
CTRL2
GPIO1
GPIO2
PIOD
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
USAGE
RTS1
CTS1
J18 12
J18 11
AD0Xp
AD1Xm
AD2Yp
AD3Ym
J18_8
J18_7
J18_10
J18_9
IDUSB
(MCI1_WP)
POWER_LED
USER LED D7
PIOE
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
USAGE
LCDPWR
LCDMOD
LCDCC
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDEN
R0
R1
R2
R3
R4
R5
R6
R7
G0
PIOE
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE31
USAGE
G1
G2
G3
G4
G5
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
EXT_CLK
A
A2
A
AT91SAM9M10-G45-EK
TOP LEVEL
REV
SCALE
MODIF.
PP
Derek
DES.
08-apr-10
05-Feb-10
DATE
1/1
REV.
A2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
PP
VER.
1
11-FEB-10
DATE
SHEET
1
12
8
7
6
5
4
3
2
1
3V3
J1-1
1
1V
C4
33u
CR1
5V
+
DC POWER JACK
C9
10u
PGOOD
EN
VIN
VDD
C10
1u
GND
ADJ
VOUT
NC
8
7
6
5
C3
10n
R4
47k
1
2
3
4
R199
3V3
MN1
RT9186A
VIN
VIN
PGOOD
EN
100k
EP
1
2
3
4
MN2
RT9018A
VOUT
VOUT
ADJ
GND
8
7
6
5
L2
C5
10n
R6
12k
R7
15k
C11
1u
C13
1u
C12
10u
10uH
C7
1u
R8
47k
C8
100n
C14
4.7u
JP1
1
3
2
JP2
1
VOUT =
0.8V x (Rtop + Rbottom)/Rbottom
VDDIOP0 {3}
3
2
JP3
VDDIOP1 {3}
3
VDDIOP2 {3,12}
2
1
VDDISI
5V
PWR_EN
R10
100k
1V8
4
1 C17
2
1
2
3
4
3
15p
R16
10k
R11
100k
R17
10k
C23
10u
MN4
RT9018A
PGOOD
EN
VIN
VDD
C24
1u
GND
ADJ
VOUT
NC
8
7
6
5
C16
10n
R15
15k
R13
1V8
100k
1
2
3
4
L3
MN3
RT9186A
VIN
VIN
PGOOD
EN
VOUT
VOUT
ADJ
GND
8
7
6
5
4
VDDUTMIC
{3}
R18
12k
{3} SHDN
C26
1u
C25
1u
C
7
10uH
R12
1R
1V_VDDUTMIC
R14
12k
C19
10n
C22
1u
C21
10u
R19
47k
L4
J1-4
8
VDDPLLUTMI
{3}
C18
100n
C20
4.7u
9
2
5V
SIP2
EP
JP4
FORCE
POWER
ON
3V3
VOUT =
0.8V x (Rtop + Rbottom)/Rbottom
1
5
9
Q1
6
Si1563EDH
J1-2
{3,12}
C15
2.2u
EP
C
3
1V_VDDUTMIC
R9
100k
D
VDDOSC {3}
R5
1R
C6
10u
{3}
C1
100n
C2
4.7u
1V
9
1
3
2
R3
100k
5V
EP
J2
5V
9
REGULATED
5V ONLY
VDDUTMII
VDDANA {3}
R1
1R
3V3
VOUT =
0.8V x (Rtop + Rbottom)/Rbottom
2
10uH
R2
100k
3V3
D
L1
10uH
VDDPLLA {3}
R20
1R
C27
10u
C28
100n
C29
4.7u
VOUT =
0.8V x (Rtop + Rbottom)/Rbottom
1V
B
5
1V8
3V3
1
D2
470R
PD0 {3}
2
R22
470R
PD31 {3}
R25
VDDBU
1
2
1
LEFT
PUSH
PD30 {3}
RIGHT CLICK
Z2
WAKE UP {3}
BP4
Z4
C36
10n
LEFT CLICK
{3} PB[14..18]
Z5
3V3
JP7
Bumpon
1
Z6
C30
100n
Bumpon Bumpon Bumpon
3
VDDBU {3}
PB7 {3}
C31
10n
C35
10n
R28
100R
VDDIOM1 {3}
J3
Z3
Bumpon
R27
A
GND TEST POINT
100R
BP5
TP1
C32
C33
C34
10n
10n
10n
POWER LED
4 UP
5 RIGHT
6 DOWN
JoyStick
PB17
2
1
2
3
VDDIOM0 {3}
3
ADHESIVE FEET
NRST {3,7,8,9,10,12}
WAKE UP
A
R24
1k
BP2
BP3
PB14
PB18
R23
100k
BP1
R26
100k
3
1
NRST
PB15
PB16
D3
Red
3
JP6
3V3
Green
470R
Q2
IRLML2402
R21
TP2
TP3
TP4
PB6 {3}
C37
R29
10n
100R
A2
A
AT91SAM9M10-G45-EK
POW ER SUPPLY
REV
SCALE
MODIF.
PP
Derek
DES.
08-apr-10
05-Feb-10
DATE
1/1
7
6
5
4
3
2
PP
VER.
REV.
A2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
{3}
JP5
1
2
VDDCORE
2
1
Green
D1
2
3V3
B
6
2
USER INTERFACE
J1-3
1
11-FEB-10
DATE
SHEET
2
12
{4} EBI0_CKE
{4} EBI0_CLK
{4} EBI0_NCLK
{4} EBI0_CS
{4} EBI0_CAS
{4} EBI0_RAS
{4} EBI0_WE
{5,6} DDR_VREF
{4} EBI0_DQM0
{4} EBI0_DQM1
{4} EBI0_DQS0
{4} EBI0_DQS1
G17
G16
J16
J18
H18
H14
H17
J17
H15
A16
G14
H16
G18
G15
EBI0_DDR_BA0
EBI0_DDR_BA1
EBI0_DDR_CKE
EBI0_DDR_CLK
EBI0_DDR_NCLK
EBI0_DDR_CS
EBI0_DDR_CAS
EBI0_DDR_RAS
EBI0_DDR_W E
EBI1_DQM0
EBI1_DQM1
EBI1_DQS0
EBI1_DQS1
EBI1_RAS
EBI1_CAS
EBI1_SDW E
EBI1_SDA10
EBI1_SDCKE
EBI1_NCS0
EBI1_NCS1/SDCS
EBI0_DDR_DQM0
EBI0_DDR_DQM1
EBI1_NRD/CFOE
EBI1_NW E/NW R0/CFW E
EBI1_NBS1/NW R1/CFIOR
EBI1_NBS3/NW R3/CFIOW
EBI0_DDR_DQS0
EBI0_DDR_DQS1
EBI1_A0
EBI1_A1
EBI1_A2
EBI1_A3
EBI1_A4
EBI1_A5
EBI1_A6
EBI1_A7
EBI1_A8
EBI1_A9
EBI1_A10
EBI1_A11
EBI1_A12
EBI1_A13
EBI1_A14
EBI1_A15
EBI1_A16
EBI1_A17
EBI1_A18
EBI1_NANDOE
EBI1_NANDW E
EBI1_D[0..15]
{4}
EBI1_A[1..18]
{4}
MN5D
R7
T7
L8
V6
M8
V7
N8
U7
P8
R8
U8
T8
V8
L9
U9
M9
N9
V9
R9
T9
D2
E1
F1
G2
F2
G1
H1
H2
P9
L10
T10
L11
PD0/TK0/PW M3
PD1/TF0
PD2/TD0
PD3/RD0
PD4/RK0
PD5/RF0
PD6/AC97RX
PD7/AC97TX/TIOA5
PD8/AC97FS/TIOB5
PD9/97CK/TCLK5
PD10/TD1
PD11/RD1
PD12/TK1/PCK0
PD13/RK1
PD14/TF1
PD15/RF1
PD16/RTS1
PD17/CTS1
PD18/SPI1_NPCS2/IRQ
PD19/SPI0_NPCS3/FIQ
PD20/TIOA0
PD21/TIOA1
PD22/TIOA2
PD23/TCLK0
PD24/SPI0_NPCS1/PW M0
PD25/SPI0_NPCS2/PW M1
PD26/PCK0/PW M2
PD27/PCK1/SPI0_NPCS3
PD28/TSADTRG/SPI1_NPCS1
PD29/TCLK1/SCK1
PD30/TIOB0/SCK2
PD31/TIOB1/PW M1
PD[0..31]
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
{2,7,8,9,10,11,12}
PE0/LCDPW R/PCK0
PE1/LCDMOD
PE2/LCDCC
PE3/LCDVSYNC
PE4/LCDHSYNC
PE5/LCDDOTCK
PE6/LCDDEN
PE7/LCDD0/LCDD2
PE8/LCDD1/LCDD3
PE9/LCDD2/LCDD4
PE10/LCDD3/LCDD5
PE11/LCDD4/LCDD6
PE12/LCDD5/LCDD7
PE13/LCDD6/LCDD10
PE14/LCDD7/LCDD11
PE15/LCDD8/LCDD12
PE16/LCDD9/LCDD13
PE17/LCDD10/LCDD14
PE18/LCDD11/LCDD15
PE19/LCDD12/LCDD18
PE20/LCDD13/LCDD19
PE21/LCDD14/LCDD20
PE22/LCDD15/LCDD21
PE23/LCDD16/LCDD22
PE24/LCDD17/LCDD23
PE25/LCDD18
PE26/LCDD19
PE27/LCDD20
PE28/LCDD21
PE29/LCDD22
PE30/LCDD23
PE31/PW M2/PCK1
D
C
VDDBU {2}
R30
R31
39R
39R
R33
R32
TP5
EBI1_A0
22p
C50
C53
C57
EBI1_RAS {4}
EBI1_CAS {4}
EBI1_SDWE {4}
EBI1_SDA10 {4}
EBI1_SDCKE {4}
{9}
{9}
{9}
{9}
{9}
{9}
{2,7,8,9,10,12}
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
EBI1_SDCK {4}
EBI1_NSDCK {4}
EBI1_NCS0 {6}
EBI1_NCS1/SDCS
U11
U12
C44
100n
C46
A12
C11
F12
B9
B12
V15
V16
U15
U16
{2} VDDOSC
{4}
{4}
{4}
{4}
39R
39R
{9} HDPB
{9} HDMB
TP pad
T18
R18
T17
R17
{9} HDPA
{9} HDMA
EBI1_DQM0
EBI1_DQM1
EBI1_DQS0
EBI1_DQS1
A10
F10
PC14
{6} PC14
B11
D11
A11
E11
A13
A14
EBI1_SDCK
EBI1_NSDCK
EBI0_DDR_VREF
F13
F14
F18
F15
E14
F17
F16
E17
E15
E16
D18
D17
C18
B18
A18
B17
C10
B10
C17
PC8
{6} PC8
MN5C
PC0/DQM2
PC1/DQM3
PC2/A19
PC3/A20
PC4/A21/NANDALE
PC5/A22/NANDCLE
PC6/A23
PC7/A24
PC8/CFCE1
PC9/CFCE2/RTS2
PC10/NCS4/CFCS0/TCLK2
PC11/NCS5/CFCS1/CTS2
PC12/A25/CFRNW
PC13/NCS2
PC14/NCS3/NANDCS
PC15/NW AIT
PC16/D16
PC17/D17
PC18/D18
PC19/D19
PC20/D20
PC21/D21
PC22/D22
PC23/D23
PC24/D24
PC25/D25
PC26/D26
PC27/D27
PC28/D28
PC29/D29
PC30/D30
PC31/D31
V12
2
Y1
4
22p
12MHz
V11
C1
15p
15p
Y2
32.768KHz
VDDBU
R34
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
{2} SHDN
DNP
0R
D1
E4
N10
R10
P10
U10
R11
V10
M10
F3
MN5H
HFSDPA
HFSDMA
VDDBU
GNDBU
HHSDPA
HHSDMA
VDDPLLUTMI
VDDUTMIC
DFSDP/HFSDPB
DFSDM/HFSDMB
EBI1_NRD/CFOE {6}
EBI1_NWE/NWR0/CFWE
D10
E10
EBI1_NANDOE {6}
EBI1_NANDWE {6}
VDDUTMII
DHSDP/HHSDPB
DHSDM/HHSDMB
VDDIOP0
VDDIOP0
VDDOSC
GNDOSC
VDDIOP1
XIN
VDDIOP2
VDDCORE
VDDCORE
VDDCORE
VDDCORE
XOUT
XIN32
VDDIOM0
VDDIOM0
VDDIOM0
VDDIOM0
XOUT32
VDDIOM1
VDDIOM1
VDDIOM1
VDDIOM1
JTAGSEL
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
SHDN
{4}
F11
C9
D9
A9
GNDUTMI
VDDPLLA
TSADVREF
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDIOM
GNDIOM
GNDIOM
GNDIOM
GNDIOM
GNDIOM
GNDIOM
GNDIOP
GNDIOP
{4} EBI0_BA0
{4} EBI0_BA1
EBI1_NBS0/A0
EBI1_NBS2/NW R2/A1
EBI1_A2
EBI1_A3
EBI1_A4
EBI1_A5
EBI1_A6
EBI1_A7
EBI1_A8
EBI1_A9
EBI1_A10
EBI1_A11
EBI1_A12
EBI1_A13
EBI1_A14
EBI1_A15
EBI1_BA0/A16
EBI1_BA1/A17
EBI1_A18
EBI0_DDR_A0
EBI0_DDR_A1
EBI0_DDR_A2
EBI0_DDR_A3
EBI0_DDR_A4
EBI0_DDR_A5
EBI0_DDR_A6
EBI0_DDR_A7
EBI0_DDR_A8
EBI0_DDR_A9
EBI0_DDR_A10
EBI0_DDR_A11
EBI0_DDR_A12
EBI0_DDR_A13
EBI1_D0
EBI1_D1
EBI1_D2
EBI1_D3
EBI1_D4
EBI1_D5
EBI1_D6
EBI1_D7
EBI1_D8
EBI1_D9
EBI1_D10
EBI1_D11
EBI1_D12
EBI1_D13
EBI1_D14
EBI1_D15
PC2
PC3
PC4
PC5
A8
E9
B8
C8
F9
A7
D8
A6
E8
C7
B6
B7
A5
D7
F8
C6
E7
B5
D6
F7
A4
C5
B4
E6
D5
A3
C4
A1
A2
B2
B3
B1
TST
B
EBI0_DDR_D0
EBI0_DDR_D1
EBI0_DDR_D2
EBI0_DDR_D3
EBI0_DDR_D4
EBI0_DDR_D5
EBI0_DDR_D6
EBI0_DDR_D7
EBI0_DDR_D8
EBI0_DDR_D9
EBI0_DDR_D10
EBI0_DDR_D11
EBI0_DDR_D12
EBI0_DDR_D13
EBI0_DDR_D14
EBI0_DDR_D15
A17
D15
C15
B16
B15
D14
C14
A15
B14
D13
C13
E13
B13
E12
D12
C12
{4,6} PC[2..5]
MN5E
G4
F4
G5
F5
G7
H5
G3
H6
G6
H7
H8
G8
J5
H4
J3
J4
J2
J6
J7
J1
J8
K1
K4
K2
K5
K6
K3
K7
K8
L3
L2
L4
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE31
VDDANA
GNDANA
D4
D3
C40
100n
V13
U18
VDDPLLUTMI
C38 100n
C39 100n
VDDUTMIC
U17
VDDUTMII
V17
{2}
{2}
C41 100n
K9
K10
C42 100n
C43 100n
H3
C45 100n
V14
C47 100n
E18
G12
G13
H11
C48 100n
C49 100n
C51 100n
C52 100n
K13
L12
L13
M14
C54
C55
C56
C58
100n
100n
100n
100n
D16
F6
G10
G11
C59
C60
C61
C62
100n
100n
100n
100n
P11
C63 100n
VDDIOP0 {2}
VDDIOP1 {2}
VDDIOP2 {2,12}
VDDCORE
{2}
VDDIOM0 {2}
B
VDDIOM1 {2}
VDDPLLA {2}
R35
E2
0R
E3
C2
{2}
C64
C65
100n
100n
VDDANA {2}
G9
H9
J9
J10
C16
H12
H13
J12
J13
K11
K12
H10
J11
M17
L14
M18
L15
L16
L18
L17
K14
K15
K16
K18
K17
J14
J15
{4} EBI0_A[0..13]
EBI1_D0
EBI1_D1
EBI1_D2
EBI1_D3
EBI1_D4
EBI1_D5
EBI1_D6
EBI1_D7
EBI1_D8
EBI1_D9
EBI1_D10
EBI1_D11
EBI1_D12
EBI1_D13
EBI1_D14
EBI1_D15
1
{8,11,12} PE[0..31]
VBG
C
MN5F
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
2
E5
EBI0_A0
EBI0_A1
EBI0_A2
EBI0_A3
EBI0_A4
EBI0_A5
EBI0_A6
EBI0_A7
EBI0_A8
EBI0_A9
EBI0_A10
EBI0_A11
EBI0_A12
EBI0_A13
MN5G
T4
V2
V3
U4
R5
V4
T5
U5
T12
N11
U13
M11
P6
R6
M7
V5
T6
U6
N7
P7
P12
T15
R12
T16
N12
M12
U14
M13
N13
R13
T13
P13
PB0/SPI0_MISO
PB1/SPI0_MOSI
PB2/SPI0_SPCK
PB3/SPI0_NPCS0
PB4/TXD1
PB5/RXD1
PB6/TXD2
PB7/RXD2
PB8/TXD3/ISI_D8
PB9/RXD3/ISI_D9
PB10/TW D1/ISI_D10
PB11/TW CK1/ISI_D11
PB12/DRXD
PB13/DTXD
PB14/SPI1_MISO
PB15/SPI1_MOSI/CTS0
PB16/SPI1_SPCK/SCK0
PB17/SPI1_NPCS0/RTS0
PB18/RXD0/SPI0_NPCS1
PB19/TXD0/SPI0_NPCS2
PB20/ISI_D0
PB21/ISI_D1
PB22/ISI_D2
PB23/ISI_D3
PB24/ISI_D4
PB25/ISI_D5
PB26/ISI_D6
PB27/ISI_D7
PB28/ISI_D8
PB29/ISI_VSYNC
PB30/ISI_HSYNC
PB31/ISI_MCK/PCK1
BMS
R16
R15
T14
P15
P16
P17
R14
P14
N15
N16
P18
N17
N18
N14
M15
M16
{4} EBI0_D[0..15]
MN5B
V18
EBI0_D0
EBI0_D1
EBI0_D2
EBI0_D3
EBI0_D4
EBI0_D5
EBI0_D6
EBI0_D7
EBI0_D8
EBI0_D9
EBI0_D10
EBI0_D11
EBI0_D12
EBI0_D13
EBI0_D14
EBI0_D15
MN5A
PA0/MCI0_CK/TCLK3
PA1/MCI0_CDA/TIOA3
PA2/MCI0_DA0/TIOB3
PA3/MCI0_DA1/TCKL4
PA4/MCI0_DA2/TIOA4
PA5/MCI0_DA3/TIOB4
PA6/MCI0_DA4/ETX2
PA7/MCI0_DA5/ETX3
PA8/MCI0_DA6/ERX2
PA9/MCI0_DA7/ERX3
PA10/ETX0
PA11/ETX1
PA12/ERX0
PA13/ERX1
PA14/ETXEN
PA15/ERXDV
PA16/ERXER
PA17/ETXCK
PA18/EMDC
PA19/EMDIO
PA20/TW D0
PA21/TW CK0
PA22/MCI1_CDA/SCK3
PA23/MCI1_DA0/RTS3
PA24/MCI1_DA1/CTS3
PA25/MCI1_DA2/PW M3
PA26/MCI1_DA3/TIOB2
PA27/MCI1_DA4/ETXER
PA28/MCI1_DA5/ERXCK
PA29/MCI1_DA6/ECRS
PA30/MCI1_DA7/ECOL
PA31/MCI1_CK/PCK0
3
WKUP
L1
M1
L5
N1
L6
M2
M3
M4
L7
N2
M5
P1
N3
P2
M6
N4
N5
N6
R1
P3
R2
P4
T1
P5
R3
T2
T3
U1
U3
U2
R4
V1
4
{2,7,9,12}
C3
D
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
5
PB[0..31]
T11
{7,10,12} PA[0..31]
6
3
7
1
8
{6}
R36
0R
{2} WAKE UP
3V3
C66
R37 R38
10p
A
A
6.8k 10k
R39
4.7k
1
SUP1 DNP
A2
A
JP8
2
SG-BGA-CA89405MF
BOOT MODE SELECT
Opened = Internal ROM BOOT
Closed = NCS0
SIP2
AT91SAM9M10-G45-EK
AT91SAM9M10 chip
REV
SCALE
MODIF.
PP
Derek
DES.
08-apr-10
05-Feb-10
DATE
1/1
REV.
A2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
PP
VER.
1
11-FEB-10
DATE
SHEET
3
12
8
7
6
5
4
EBI Bus Impedance Adaptor
EBI1_D0
4 RR1D 5
3
2
EBI1_DDR_D[0..15]
EBI1_DDR_D0
{3} EBI1_D[0..15]
DDR_D[0..15]
{3} EBI0_D[0..15]
D
EBI0
EBI0_D0
2 RR4B 7
DDR_D0
EBI0_D1
4 RR2D 5
DDR_D1
EBI0_D2
2 RR2B 7
DDR_D2
EBI0_D3
1 RR4A 8
DDR_D3
EBI0_D4
3 RR4C 6
DDR_D4
EBI0_D5
4 RR4D 5
DDR_D5
EBI0_D6
1 RR2A 8
DDR_D6
EBI0_D7
3 RR2C 6
DDR_D7
EBI0_D8
2 RR6B 7
DDR_D8
EBI0_D9
4 RR8D 5
DDR_D9
EBI0_D10
4 RR6D 5
DDR_D10
EBI0_D11
2 RR8B 7
DDR_D11
1 RR8A 8
DDR_D12
EBI0_D13
3 RR6C 6
DDR_D13
EBI0_D14
1 RR6A 8
DDR_D14
EBI0_D15
3 RR8C 6
DDR_D15
EBI0_D12
C
EBI0_A0
1 RR10A 8
DDR_A0
EBI0_A1
2 RR10B 7
DDR_A1
EBI0_A2
3 RR10C 6
DDR_A2
EBI0_A3
3 RR12C 6
DDR_A3
EBI0_A4
4 RR10D 5
DDR_A4
EBI0_A5
2 RR12B 7
DDR_A5
EBI0_A6
1 RR12A 8
DDR_A6
EBI0_A7
4 RR14D 5
DDR_A7
EBI0_A8
3 RR14C 6
DDR_A8
EBI0_A9
2 RR14B 7
DDR_A9
EBI0_A10
4 RR12D 5
DDR_A10
EBI0_A11
1 RR14A 8
DDR_A11
EBI0_A12
2 RR16B 7
DDR_A12
EBI0_A13
1 RR16A 8
DDR_A13
EBI1_D1
EBI1_D2
EBI1_D3
EBI1_D4
EBI1_D5
EBI1_D6
EBI1_D7
{5}
EBI1_D8
EBI1_D9
EBI1_D10
EBI1_D11
EBI1_D12
EBI1_D13
EBI1_D14
EBI1_D15
4 RR26D 5
{3} EBI0_CKE
{3} EBI0_CLK
{3} EBI0_NCLK
{3} EBI0_BA0
{3} EBI0_BA1
{3} EBI0_W E
{3} EBI0_CS
{3} EBI0_RAS
{3} EBI0_CAS
A
{3} EBI0_DQM0
{3} EBI0_DQM1
{3} EBI0_DQS0
{3} EBI0_DQS1
R40
27R
DDR_CKE {5}
{3} EBI1_SDCKE
R42
27R
DDR_CLK {5}
{3} EBI1_SDCK
R44
27R
DDR_NCLK
{3} EBI1_NSDCK
{5}
EBI1_D1
1 RR1A 8
EBI1_DDR_D1
EBI1_D2
2 RR1B 7
EBI1_DDR_D2
EBI1_D3
3 RR1C 6
EBI1_D4
2 RR3B 7
EBI1_DDR_D4
EBI1_D5
1 RR3A 8
EBI1_DDR_D5
EBI1_D6
4 RR3D 5
EBI1_DDR_D6
EBI1_D7
3 RR3C 6
EBI1_DDR_D7
EBI1_D8
3 RR5C 6
EBI1_DDR_D8
EBI1_D9
1 RR7A 8
EBI1_DDR_D9
EBI1_D10
2 RR5B 7
EBI1_DDR_D10
{5}
3 RR26C 6
B
{6}
EBI1_NAND_FSH_D[0..15]
EBI1_D0
DDR_A[0..13]
{3} EBI0_A[0..13]
1
1 RR9A 8
EBI1_FLASH_D0
2 RR9B 7
EBI1_NAND_FSH_D0
1 RR11A 8
EBI1_FLASH_D1
2 RR11B 7
EBI1_NAND_FSH_D1
4 RR11D 5
EBI1_FLASH_D2
3 RR11C 6
EBI1_NAND_FSH_D2
3 RR9C 6
EBI1_FLASH_D3
4 RR9D 5
EBI1_NAND_FSH_D3
1 RR13A 8
EBI1_FLASH_D4
2 RR13B 7
EBI1_NAND_FSH_D4
3 RR13C 6
EBI1_FLASH_D5
4 RR13D 5
EBI1_NAND_FSH_D5
1 RR17A 8
EBI1_FLASH_D6
2 RR17B 7
EBI1_NAND_FSH_D6
3 RR17C 6
EBI1_FLASH_D7
4 RR17D 5
EBI1_NAND_FSH_D7
4 RR19D 5
EBI1_FLASH_D8
3 RR19C 6
EBI1_NAND_FSH_D8
2 RR21B 7
EBI1_FLASH_D9
1 RR21A 8
EBI1_NAND_FSH_D9
3 RR25C 6
EBI1_FLASH_D10
4 RR25D 5
EBI1_NAND_FSH_D10
2 RR23B 7
EBI1_DDR_D3
EBI1_D11
4 RR7D 5
EBI1_DDR_D11
EBI1_D12
1 RR5A 8
EBI1_DDR_D12
EBI1_D13
3 RR7C 6
EBI1_D14
2 RR7B 7
EBI1_D15
4 RR5D 5
EBI1_A1
EBI1_A2
EBI1_A3
EBI1_A4
EBI1_DDR_D13
EBI1_A5
EBI1_DDR_D14
EBI1_A6
EBI1_DDR_D15
EBI1_A7
EBI1_NAND_FSH_D11
1 RR25A 8
EBI1_FLASH_D12
2 RR25B 7
EBI1_NAND_FSH_D12
3 RR23C 6
EBI1_FLASH_D13
4 RR23D 5
EBI1_NAND_FSH_D13
4 RR21D 5
EBI1_FLASH_D14
3 RR21C 6
EBI1_NAND_FSH_D14
2 RR19B 7
EBI1_FLASH_D15
1 RR19A 8
EBI1_NAND_FSH_D15
EBI1_A8
EBI1_A9
EBI1_A10
EBI1_A11
EBI1_FLASH_D[0..15]
R41
27R
CKE_EBI1 {6}
R43
27R
CLK_EBI1 {6}
R45
27R
NCLK_EBI1 {6}
DDR_BA0 {5}
EBI1_A16
1 RR31A 8
BA0_EBI1 {6}
1 RR26A 8
DDR_BA1 {5}
EBI1_A17
3 RR31C 6
BA1_EBI1 {6}
3 RR16C 6
DDR_W E {5}
2 RR33B 7
CS_EBI1 {6}
2 RR26B 7
DDR_CS {5}
{3} EBI1_SDW E
1 RR33A 8
W E_EBI1 {6}
3 RR29C 6
DDR_RAS {5}
{3} EBI1_RAS
2 RR15B 7
RAS_EBI1 {6}
{3} PC2
4 RR29D 5
DDR_CAS {5}
{3} EBI1_CAS
3 RR33C 6
CAS_EBI1 {6}
{3} PC3
1 RR29A 8
DDR_DQM0 {5}
{3} EBI1_DQM0
4 RR33D 5
DQM0_EBI1 {6}
2 RR29B 7
DDR_DQM1 {5}
{3} EBI1_DQM1
1 RR32A 8
DQM1_EBI1 {6}
R46
27R
DDR_DQS0 {5}
{3} EBI1_DQS0
R48
27R
DDR_DQS1 {5}
{3} EBI1_DQS1
{3} EBI1_SDA10
{3} EBI1_A[1..18]
R47
27R
DQS0_EBI1 {6}
R49
27R
DQS1_EBI1 {6}
EBI1_FLASH_A1
4 RR18D 5
EBI1_DDR_A2
1 RR18A 8
EBI1_FLASH_A2
2 RR28B 7
EBI1_DDR_A3
3 RR28C 6
EBI1_FLASH_A3
4 RR30D 5
EBI1_DDR_A4
1 RR15A 8
EBI1_FLASH_A4
2 RR18B 7
EBI1_DDR_A5
3 RR18C 6
EBI1_FLASH_A5
2 RR20B 7
EBI1_DDR_A6
1 RR20A 8
EBI1_FLASH_A6
1 RR22A 8
EBI1_DDR_A7
2 RR22B 7
EBI1_FLASH_A7
1 RR30A 8
EBI1_DDR_A8
4 RR28D 5
EBI1_FLASH_A8
4 RR24D 5
EBI1_DDR_A9
1 RR28A 8
EBI1_FLASH_A9
3 RR20C 6
EBI1_DDR_A10
4 RR20D 5
EBI1_FLASH_A10
1 RR27A 8
EBI1_DDR_A11
EBI1_A12
4 RR22D 5
EBI1_FLASH_A12
EBI1_A13
4 RR27D 5
EBI1_DDR_A13
3 RR27C 6
EBI1_FLASH_A13
3 RR15C 6
EBI1_DDR_A14
2 RR24B 7
EBI1_FLASH_A14
4 RR15D 5
EBI1_DDR_A15
3 RR24C 6
EBI1_FLASH_A15
EBI1_A16
2 RR31B 7
EBI1_FLASH_A16
EBI1_A17
4 RR31D 5
EBI1_FLASH_A17
EBI1_A18
1 RR24A 8
EBI1_FLASH_A18
2 RR32B 7
EBI1_FLASH_A19
(A20)
3 RR32C 6
EBI1_FLASH_A20
4 RR32D 5
AT91SAM9M10-G45-EK
RES.ARRAYS-EBI0_EBI1
EBI1_DDR_A[2..15]
C
B
A
REV
MODIF.
SCALE
PP
Derek
DES.
08-apr-10
05-Feb-10
DATE
1/1
7
6
5
4
3
2
PP
VER.
REV.
A2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
{6}
EBI1_FLASH_A21
A2
A
SDA10
D
EBI1_DDR_A12 (SDA10)
(A19)
(A21)
{3,6} PC4
EBI1
EBI1_FLASH_A11
3 RR22C 6
EBI1_A15
4 RR16D 5
{3} EBI1_NCS1/SDCS
3 RR30C 6
SDA10
EBI1_A14
{6}
2 RR30B 7
2 RR27B 7
{6}
EBI1_FLASH_A[1..21]
EBI1_FLASH_A1
EBI1_FLASH_A2
EBI1_FLASH_A3
EBI1_FLASH_A4
EBI1_FLASH_A5
EBI1_FLASH_A6
EBI1_FLASH_A7
EBI1_FLASH_A8
EBI1_FLASH_A9
EBI1_FLASH_A10
EBI1_FLASH_A11
EBI1_FLASH_A12
EBI1_FLASH_A13
EBI1_FLASH_A14
EBI1_FLASH_A15
EBI1_FLASH_A16
EBI1_FLASH_A17
EBI1_FLASH_A18
EBI1_FLASH_A19
EBI1_FLASH_A20
EBI1_FLASH_A21
EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D1
EBI1_NAND_FSH_D2
EBI1_NAND_FSH_D3
EBI1_NAND_FSH_D4
EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D6
EBI1_NAND_FSH_D7
EBI1_NAND_FSH_D8
EBI1_NAND_FSH_D9
EBI1_NAND_FSH_D10
EBI1_NAND_FSH_D11
EBI1_NAND_FSH_D12
EBI1_NAND_FSH_D13
EBI1_NAND_FSH_D14
EBI1_NAND_FSH_D15
EBI1_FLASH_D11
1 RR23A 8
{6}
1
11-FEB-10
DATE
SHEET
4
12
8
D
7
6
5
4
3
2
1
{4} DDR_D[0..15]
D
{4} DDR_A[0..13]
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
C
{4} DDR_BA0
{4} DDR_BA1
BA0
BA1
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
MN6
MN7
MT47H64M8CF-3 -F
MT47H64M8CF-3 -F
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
G2
G3
BA0
BA1
F9
{4} DDR_CKE
{4} DDR_CLK
{4} DDR_NCLK
{4} DDR_CS
{4} DDR_CAS
{4} DDR_RAS
{4} DDR_W E
CKE
F2
CK
NCK
E8
F8
CS
G8
CAS
RAS
G7
F7
NW E
F3
ODT
VDDL
CKE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CK
CK
CS
VREF
CAS
RAS
VSS
VSS
VSS
VSS
WE
G1
L3
L7
B
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
RFU1
RFU2
RFU3
VSSDL
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
B7
A8
B3
A2
DDR_DQS0 {4}
DDR_DQM0 {4}
1V8
A1
E9
H9
L1
C67
C69
C71
C73
100n
100n
100n
100n
E1
C75
100n
A9
C1
C3
C7
C9
C77
C79
C81
C83
C85
100n
100n
100n
100n
100n
E2
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
G2
G3
BA0
BA1
F9
DDR_VREF
A3
E3
J1
K9
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
H2
K7
L2
L8
C87
100n
CKE
F2
CK
NCK
E8
F8
CS
G8
CAS
RAS
G7
F7
NW E
F3
A7
B2
B8
D2
D8
G1
L3
L7
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
BA0
BA1
ODT
CKE
CK
CK
CS
VDD
VDD
VDD
VDD
VDDL
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
CAS
RAS
VSS
VSS
VSS
VSS
WE
RFU1
RFU2
RFU3
E7
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
B7
A8
B3
A2
DDR_DQS1 {4}
C
DDR_DQM1 {4}
1V8
A1
E9
H9
L1
C68
C70
C72
C74
100n
100n
100n
100n
E1
C76
100n
A9
C1
C3
C7
C9
C78
C80
C82
C84
C86
100n
100n
100n
100n
100n
E2
A3
E3
J1
K9
DDR_VREF
C88
100n
A7
B2
B8
D2
D8
B
E7
1V8
L5
10uH
R50
1R
C89
100n
R51
1.5k
C90
4.7u
DDR_VREF
C91
100n
DDR_VREF
{3,6}
R52
1.5k
A
A
A2
A
AT91SAM9M10-G45-EK
EBI0_DDR2
REV
MODIF.
SCALE
PP
Derek
DES.
08-apr-10
05-Feb-10
DATE
1/1
REV.
A2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
PP
VER.
1
11-FEB-10
DATE
SHEET
5
12
8
7
6
5
4
3
2
1
{4} EBI1_FLASH_D[0..15]
{4} EBI1_FLASH_A[1..21]
{4} EBI1_DDR_D[0..15]
{4} EBI1_DDR_A[2..15]
H8
EBI1_DDR_A2
H3
EBI1_DDR_A3
H7
EBI1_DDR_A4
J2
EBI1_DDR_A5
J8
EBI1_DDR_A6
J3
EBI1_DDR_A7
J7
EBI1_DDR_A8
K2
EBI1_DDR_A9
K8
EBI1_DDR_A10
K3
EBI1_DDR_A11
EBI1_DDR_A12 (SDA10) H2
K7
EBI1_DDR_A13
L2
EBI1_DDR_A14
L8
EBI1_DDR_A15
D
{4} BA0_EBI1
{4} BA1_EBI1
G2
G3
BA0_EBI1
BA1_EBI1
F9
{4} CKE_EBI1
{4} CLK_EBI1
{4} NCLK_EBI1
C
{4} CAS_EBI1
{4} RAS_EBI1
{4} W E_EBI1
E8
F8
CLK_EBI1
NCLK_EBI1
CS_EBI1
{4} CS_EBI1
F2
CKE_EBI1
(NCS1)
G8
CAS_EBI1
RAS_EBI1
G7
F7
W E_EBI1
F3
G1
L3
L7
MN8
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
BA0
BA1
VDD
VDD
VDD
VDD
ODT
VDDL
CKE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CK
CK
CS
VREF
CAS
RAS
VSS
VSS
VSS
VSS
WE
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
RFU1
RFU2
RFU3
VSSDL
C8
C2
D7
D3
D1
D9
B1
B9
EBI1_DDR_D0
EBI1_DDR_D1
EBI1_DDR_D2
EBI1_DDR_D3
EBI1_DDR_D4
EBI1_DDR_D5
EBI1_DDR_D6
EBI1_DDR_D7
B7
A8
B3
A2
A1
E9
H9
L1
DQS0_EBI1 {4}
DQM0_EBI1 {4}
1V8
C92
C94
C96
C98
100n
100n
100n
100n
E1
C100
100n
A9
C1
C3
C7
C9
C102
C104
C106
C108
C111
100n
100n
100n
100n
100n
E2
VREF1
A3
E3
J1
K9
EBI1_DDR_A2
EBI1_DDR_A3
EBI1_DDR_A4
EBI1_DDR_A5
EBI1_DDR_A6
EBI1_DDR_A7
EBI1_DDR_A8
EBI1_DDR_A9
EBI1_DDR_A10
EBI1_DDR_A11
EBI1_DDR_A12
EBI1_DDR_A13
EBI1_DDR_A14
EBI1_DDR_A15
H8
H3
H7
J2
J8
J3
J7
K2
K8
K3
(SDA10) H2
K7
L2
L8
G2
G3
BA0_EBI1
BA1_EBI1
F9
F2
CKE_EBI1
C116
100n
CLK_EBI1
NCLK_EBI1
E8
F8
CS_EBI1
G8
CAS_EBI1
RAS_EBI1
G7
F7
W E_EBI1
F3
A7
B2
B8
D2
D8
G1
L3
L7
MN9
A0
DQ0
DDR2 SDRAM
A1
DQ1
A2
DQ2
A3
DQ3
A4
DQ4
A5
DQ5
A6
DQ6
A7
DQ7
A8
A9
DQS
A10
DQS
A11
A12
RDQS/DM
A13
RDQS/NU
BA0
BA1
VDD
VDD
VDD
VDD
ODT
VDDL
CKE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
CK
CK
CS
VREF
CAS
RAS
VSS
VSS
VSS
VSS
WE
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
RFU1
RFU2
RFU3
E7
VSSDL
MT47H64M8CF-3 -F
C8
C2
D7
D3
D1
D9
B1
B9
EBI1_DDR_D8
EBI1_DDR_D9
EBI1_DDR_D10
EBI1_DDR_D11
EBI1_DDR_D12
EBI1_DDR_D13
EBI1_DDR_D14
EBI1_DDR_D15
B7
A8
B3
A2
DQS1_EBI1 {4}
DQM1_EBI1 {4}
1V8
A1
E9
H9
L1
C93
C95
C97
C99
E1
C101 100n
A9
C1
C3
C7
C9
E2
EBI1_FLASH_A1
EBI1_FLASH_A2
EBI1_FLASH_A3
EBI1_FLASH_A4
EBI1_FLASH_A5
EBI1_FLASH_A6
EBI1_FLASH_A7
EBI1_FLASH_A8
EBI1_FLASH_A9
EBI1_FLASH_A10
EBI1_FLASH_A11
EBI1_FLASH_A12
EBI1_FLASH_A13
EBI1_FLASH_A14
EBI1_FLASH_A15
EBI1_FLASH_A16
EBI1_FLASH_A17
EBI1_FLASH_A18
EBI1_FLASH_A19
EBI1_FLASH_A20
EBI1_FLASH_A21
100n
100n
100n
100n
C103 100n
C105 100n
C107 100n
C109 100n
C112 100n
1V8
VREF1
A3
E3
J1
K9
C117
100n
R200
0R
B4
R53
R54
R55
100k
0R
100k
B5
C4
D6
1V8
JP9
{3} EBI1_NCS0
MN10 DNP
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
NC/A21
1
2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
WAIT
NC
F7
E6
E5
G5
E4
G3
E3
G1
G7
F6
F5
F4
D5
F3
F2
E2
D
D7
1V8
RESET
LATCH
WP
VDD
VDD
VDDQ
VDDQ
CE
OE
WE
A5
EBI1_FLASH_D0
EBI1_FLASH_D1
EBI1_FLASH_D2
EBI1_FLASH_D3
EBI1_FLASH_D4
EBI1_FLASH_D5
EBI1_FLASH_D6
EBI1_FLASH_D7
EBI1_FLASH_D8
EBI1_FLASH_D9
EBI1_FLASH_D10
EBI1_FLASH_D11
EBI1_FLASH_D12
EBI1_FLASH_D13
EBI1_FLASH_D14
EBI1_FLASH_D15
D3
CLK
E7
F8
C5
{3} EBI1_NRD/CFOE
{3} EBI1_NW E/NW R0/CFW E
A7
B2
B8
D2
D8
E8
D8
C8
B8
A8
B7
A7
C7
A2
B2
C2
A1
B1
C1
D2
D1
D4
B6
A6
C6
B3
C3
VSS
VSS
VSSQ
VSSQ
VPP
A4
G4
E1
G6
C110
C113
C114
C115
100n
100n
100n
100n
A3
F1
G2
G8
C
M58W R032KT_VFBGA56
R56
470k
E7
{3,5} DDR_VREF
VREF1
MT47H64M8CF-3 -F
{4} EBI1_NAND_FSH_D[0..15]
{3} PC5
{3,4} PC4
{3} EBI1_NANDOE
{3} EBI1_NANDW E
{3} PC14
B
{3} PC8
(NANDCLE)
(NANDALE)
(NCS3)
(RDY/BSY)
1
JP10
SIP2
2
1V8
1V8
R57
R58
0R
0R
R59
R60
R61
R62
470k
0R
1k
470k
RE
WE
CE
D5
C4
D4
C7
C6
RB
C8
WP
C3
G5
R63
0R
DNP
IMPORTANT note about system booting:
The bootROM allows booting from the block 0 of a NandFlash connected
on CS3. However, the bootROM does not feature ECC (Error Checking and
Correction) on NandFlash.
Most of the NandFlash vendors do not guarantee anymore that block 0
is error free. Therefore we advise the bootstrap program to be located
into another device supported by the bootrom (DataFlash, Serial Flash,
SDCARD or EEPROM) and implement NandFlash access with ECC.
A
A1
A2
A9
A10
B1
B9
B10
D6
D7
D8
E3
E4
E5
E6
E7
E8
F3
F4
F5
F6
F8
G3
G8
L1
L2
MN11
CLE
ALE
RE
WE
CE
R/B
WP
LOCK
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
N.C15
N.C16
N.C17
N.C18
N.C19
N.C20
N.C21
N.C22
N.C23
N.C24
N.C25
NAND FLASH
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
N.C26
N.C27
N.C28
N.C29
N.C30
N.C31
N.C32
N.C33
N.C34
N.C35
N.C36
N.C37
N.C38
N.C39
H4
J4
K4
K5
K6
J7
K7
J8
H3
J3
H5
J5
H6
G6
H7
G7
EBI1_NAND_FSH_D0
EBI1_NAND_FSH_D1
EBI1_NAND_FSH_D2
EBI1_NAND_FSH_D3
EBI1_NAND_FSH_D4
EBI1_NAND_FSH_D5
EBI1_NAND_FSH_D6
EBI1_NAND_FSH_D7
EBI1_NAND_FSH_D8
EBI1_NAND_FSH_D9
EBI1_NAND_FSH_D10
EBI1_NAND_FSH_D11
EBI1_NAND_FSH_D12
EBI1_NAND_FSH_D13
EBI1_NAND_FSH_D14
EBI1_NAND_FSH_D15
B
L9
L10
M1
M2
M9
M10
1V8
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
D3
G4
H8
J6
C118
C119
C120
C121
100n
100n
100n
100n
C5
F7
K3
K8
A
MT29F2G08ABDHC:D
A2
A
AT91SAM9M10-G45-EK
EBI1_MEMORY
REV
MODIF.
SCALE
PP
Derek
DES.
08-apr-10
05-Feb-10
DATE
1/1
REV.
A2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
PP
VER.
1
11-FEB-10
DATE
SHEET
6
12
8
7
6
5
4
3
2
1
3V3
3V3
R187R188R189R190
R64
10k
D
R65
10k
R191R192R193R194R195R196R197R198
8
7
6
5
D
68k 68k 68k 68k
RR36
10k
1
2
3
4
68k 68k 68k 68k 68k 68k 68k 68k
RR38 27R
1
8
2
7
3
6
4
5
PA3
PA2
(MCI0_DA1)
(MCI0_DA0)
PA0
(MCI0_CK)
PA1
PA5
PA4
(MCI0_CDA)
(MCI0_DA3)
(MCI0_DA2)
1
2
3
4
8
7
6
5
RR40
27R
3V3
8
7
C122 100n 6
5
4
3
2
1
9
J6
(MCI1_W P)
(MCI1_CD)
{3} PD29
{3} PD11
{3,10} PA[22..31]
(MCI0_CD)
{3} PD10
{3} PA[0..5]
12
11
10
RR39
PA24
PA23
(MCI1_DA1)
(MCI1_DA0)
PA31
(MCI1_CK)
1
2
3
4
PA22
PA26
PA25
(MCI1_CDA)
(MCI1_DA3)
(MCI1_DA2)
1 RR41 8 27R
2
7
3
6
4
5
PA27
PA28
PA29
PA30
(MCI1_DA4)
(MCI1_DA5)
(MCI1_DA6)
(MCI1_DA7)
1
2
3
4
FPS009-3202-BL
8
7
6 27R
5
RR42
8
7
6
5
8
7
6
5
4
3
2
1
9
3V3
C123
100n
27R
16
15
14
J5
13
12
11
10
7SDMM-B0-2211
C
C
SD/MMCPlus CARD INTERFACE - MCI1
SD/MMC CARD INTERFACE - MCI0
3V3
3V3
Test point
DNP
JP11
1
3V3
C125
8
100n
4
SCL
SDA
VCC
GND
A0
A1
A3
WP
1
2
3
1
MN12
JP13
2
{3,12} PA21
{3,12} PA20
6
5
(TW CK0)
(TW DO)
7
{3}
{3}
{3}
{3}
SIP2
PB0
PB1
PB2
PB3
{2,3,8,9,10,12}
(SPI0_MISO)
(SPI0_MOSI)
(SPI0_SPCK)
(SPI0_NPCS0)
R67
470k
3
2
R66
10k
B
1
2
JP12
SIP2
NRST
8
1
2
4
3
3V3
B
MN13
SO
SI
SCK
CS
RESET
VCC
GND
WP
6
C124
100n
7
5
AT45DB321D-SU
SERIAL DATAFLASH
AT24C512BN
SERIAL EEPROM
R68
0R
DNP
A
A
A2
A
AT91SAM9M10-G45-EK
MCI & TW I
REV
MODIF.
SCALE
PP
Derek
DES.
08-apr-10
05-Feb-10
DATE
1/1
REV.
A2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
PP
VER.
1
11-FEB-10
DATE
SHEET
7
12
8
7
6
5
4
3
2
1
2
JP18 DNP
1
3V3
22p
C137
22p
C
{3} PD7
{3} PD9
{3} PD6
100k
AGND_AC97
MN14
Y3
4
24.576MHz
(AC97TX)
(AC97CK)
C131
100n
C134
10u
10V
R78
C135
100n
1
2
3
4
5
6
7
8
9
10
11
12
49.9R
(AC97RX)
(AC97FS)
DBVDD
XTLIN
XTLOUT
DGND1
SDATAOUT
BITCLK
DGND2
SDATAIN
DCVDD
SYNC
RESET
CREF
J7
C128
470p
C129
470p
3
D
4
AGND_AC97
1
2
DNP
AGND_AC97
ROUT2
LOUT2
SPKGND
MONOOUT
CAP2
COMP3
COMP2
COMP1
MICBIAS
VREF
AGND
AVDD1
WM9711L
HEADPHONE
LINE-OUT
1
L7
220ohm at 100MHz
R72
47k
5
JP14
AGND_AC97
C136
100n
2
C132
10u
10V
R76
0R
R77
0R
JP15
DNP
36
35
34
33
32
31
30
29
28
27
26
25
8 Ohm SPEAKER
OUTPUT
C
C138
100n
AVDD2
NC1
NC2
NC3
NC4
AGND1
PCBEEP
PHONE
MIC1
MIC2
LINE_IN_L
LINE_IN_R
{3} PD8
{2,3,7,9,10,12} NRST
1
2
C130
100n
3V3
0R
1
2
STEREO_3.5mm
49
48
47
46
45
44
43
42
41
40
39
38
37
C133
DNP
100u/6.3V
R71
47k
THERMAL
GPIO5/SPDIF
GPIO4
GPIO3
GPIO2/IRQ
GPIO1
HPVDD
AGND2
HP_OUT_R
HP_GND
HP_OUT_L
SPKVDD
OUT3
R75
(EXT_CLK)
3
{3} PE31
R74
C127
2
AVDD_AC97
JP17 DNP
2
1
JP17/JP18 are used
as Testpoint
0R
1
1
10k
R70
100u/6.3V
2
R73
C126
+
D
0R
+
L6
220ohm at 100MHz
R69
C139
100n
C140
10u
10V
C141
100n
C142
10u
10V
C143
100n
C144
10u
10V
13
14
15
16
17
18
19
20
21
22
23
24
AGND_AC97
AVDD_AC97
L8
220ohm at 100MHz
C145
100n
C146
1u
AGND_AC97
AGND_AC97
R79
C147
1u
R80
B
R81
8.2K
R83
680R
3V3
C152
10u
10V
L11
10uH
AVDD_AC97
C153
100n
R85
0R
C154
10u
10V
R84
680R
1
8.2K
1
8.2K
2
L9
2
2
5
LINE-IN
J8
1
220ohm at 100MHz
R82
8.2K
B
C148
470p
3
C149
470p
4
STEREO_3.5mm
AGND_AC97
C150
1u
1
C151
1u
1
L10
220ohm at 100MHz
2
2
2
L12
220ohm at 100MHz
5
J9
1
C155
470p
C156
470p
MONO / STEREO
MICROPHONE INPUT
3
4
STEREO_3.5mm
AGND_AC97
AGND_AC97
A
A
A2
A
AT91SAM9M10-G45-EK
AUDIO AC97
REV
SCALE
MODIF.
PP
Derek
DES.
08-apr-10
05-Feb-10
DATE
1/1
REV.
A2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
PP
VER.
1
11-FEB-10
DATE
SHEET
8
12
7
3V3
C158
SERIAL DEBUG PORT
1
6
2
7
3
8
4
9
5
D
100n 16
MN15
VCC
15
C157
J10
6
C165
GND
100n 2
C1C2+
V+
100n 6
V-
C2-
14
7
1
3
4
4
C160
100n
C163
100n
R87
100k
5
R89
100k
R88
100k
PB13 {3}
R86
100k
C164
100n
PB12 {3}
3
4
5
V+
C2-
V-
RS232 COM PORT
C161
100n
15
GND
2
C162
100n
6
C166
100n
7
T
J11
1
6
2
7
3
8
4
9
5
14
T
12
D
13
10
R
10
{3} PB5
16
VCC
C1C2+
10
1
3V3
MN16
C1+
11
{3} PB4
{3} PD16
12
R
2
1
3V3
10
T
3
3V3
C159
100n
11
T
13
11
C1+
5
8
9
R
R90
0R
9
{3} PD17
ADM3202ARNZ
11
8
8
R
ADM3202ARNZ
C
C
J12
G3505-4NBT1S1W
C167
100n
USB HOST INTERFACE
1
2
HDMA {3}
4
3
HDPA {3}
6
5
6
7
8
5
3V3
2
4
6
8
10
12
14
16
18
20
5V
L13
1
2
8
220ohm at 100MHz
+ C168
33u
B
1
7
C169
100n
L14
6
2
5
220ohm at 100MHz
+ C170
33u
MN17
OUTA
IN
ENA
FLGA
GNG
FLGB
OUTB
ENB
1
(ENA)
PD1 {3}
2
(FLGA)
PD2 {3}
3
(FLGB)
PD4 {3}
4
(ENB)
PD3 {3}
J13
RR43
100k
3V3
4
3
2
1
3V3
1
3
5
7
9
11
13
15
17
19
R91
R92
R93
HTST-110-01-SM-D
DNP
0R
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
0R
0R
NTRST {3}
TDI {3}
TMS {3}
TCK {3}
RTCK {3}
TDO {3}
NRST {2,3,7,8,10,12}
R94
0R
DNP
B
ICE INTERFACE
AIC1526-0GS
3V3
R95
C171
10p
J14
SHD
7
VBUS
DM
DP
ID
GND
(VBUS)
PB19 {3}
R96
68k
R97
47k
1
2
3
4
5
(IDUSB)
6
HDMB {3}
HDPB {3}
PD28 {3,11}
USB HOST/DEVICE INTERFACE
G3515-09010101-00
A
47k
C172
100n
A
A2
A
AT91SAM9M10-G45-EK
SERIAL INTERFACES
REV
SCALE
MODIF.
PP
Derek
DES.
08-apr-10
05-Feb-10
DATE
1/1
REV.
A2
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
6
5
4
3
2
PP
VER.
1
11-FEB-10
DATE
SHEET
9
12
8
7
6
5
4
3
2
1
3V3
D
VDD 4
C173
100n
{3} PA17
C
{3}
{3}
{3}
{3}
{3}
PA7
PA6
PA11
PA10
PA14
{3}
{3}
{3}
{3}
PA9
PA8
PA13
PA12
{3,7} PA28
{3} PA15
{3,7} PA27
{3} PA16
{3,7} PA30
{3,7} PA29
42
R101
0R
R106
17
18
19
20
21
0R DNP 22
(TXD3)
(TXD2)
(TXD1)
(TXD0)
(TX_EN)
R108
R103
0R DNP
0R DNP
(RXD3)
(RXD2)
(RXD1)
(RXD0)
R104
R105
0R DNP
0R DNP
26
27
28
29
(RX_CLK)
(RX_DV)
R109
0R DNP
34
37
(TX_ER)
(RX_ER)
R110
0R DNP
16
38
(COL)
(CRS)
R112
R114
0R DNP
0R DNP
3V3
(MDC)
(MDIO)
(MDINTR)
R115
36
35
1.5k
24
25
32
39
2
{3} PA18
{3} PA19
{3}
PD5
(TX_CLK)
4
R99
0R
3V3
1
8
7
6
5
8
7
6
5
8
7
6
5
JP16
RR44
10k
RR45
10k
1
2
3
4
1
2
3
4
1
2
3
4
3V3
C184
100n
41
C185
100n
30
C186
100n
23
15
33
44
RR46
10k
R120
10
0R
B
{2,3,7,8,9,12}
C174
22p
DNP
1
0R
40
NRST
C175
22p
DNP
Y5
3
REF_CLK/XT2
XT1
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
TX+
43
R102
49.9R
TX-
7
1 TD+
RX+
TX+
1
8
2 TD-
TX-
2
3
3 RD+
RX+
3
C
5 CT
RX-
TX_ER/TXD4
RX_ER/RXD4/RPTR
4
1
COL/RMII
CRS/PHYAD4
AVDDR
AVDDR
DM9161AEP
AVDDT
DISMDIX
AGND
AGND
AGND
DVDD
BGRESG
1
C177
100n
2
C179
100n
AVDDT
9
C182
47
RESET
N.C
C181
10u
10V
R113
49.9R
C178
100n
RR47
10k
48
31
11
12
13
14
GND_ETH
75
75
7 NC
75
1nF
4
8
75
7
8
J00-0061NL
GND_ETH
RJ45 ETHERNET CONNECTOR
3V3
2 D4
1 Yellow
2 D5
1 Green
1 Green
2 D6
45
6
5
C183
100n
GND_ETH
R117
6.8k
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
R111
49.9R
3V3
0R
RX-
AVDDT
2
C180
10u
10V
100n
R116
6 RD-
L15
2200R
5
6
46
DVDD
PW RDW N
J15
AVDDT
RX_CLK/10BTSER
RX_DV/TESTMODE
DGND
DGND
DGND
R107
49.9R
4 CT
RXD3/PHYAD3
RXD2/PHYAD2
RXD1/PHYAD1
RXD0/PHYAD0
DVDD
GND_ETH
25MHz
DNP
MN18
MDC
MDIO
MDINTR
C176
100n
16
DNP
R100
15
50MHz
2 VSS
OUT 3
8
7
6
5
Y4
1 OE
1
2
3
4
D
10k
2
R98
R118
R119
R121
470R
FULL DUPLEX
470R
SPEED 100
470R
LINK&ACT
B
3V3
R122
0R
C187
10u
10V
R123
0R
GND_ETH
A
A
A2
A
AT91SAM9M10-G45-EK
RMII_MII ETHERNET
REV
SCALE
MODIF.
PP
Derek
DES.
08-apr-10
05-Feb-10
DATE
1/1
REV.
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
8
7
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5
4
3
2
PP
VER.
1
11-FEB-10
DATE
SHEET
A2 10
12
8
7
6
5
4
3
2
1
J24
M1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D
TRULY
4.3" 480x272
TFT LCD DISPLAY
Conductors
on
TOP SIDE
PIN 40
PIN 1
TFT1N4633-E
C
LCD1
Y_UP
X_LEFT
Y_LOW
X_RIGHT
DE
VSYNC
HSYNC
DISP
PCLK
LCDDEN
LCDVSYNC
LCDHSYNC
(LCDDEN)
PE6
LCDVSYNC
LCDHSYNC
LCDDOTCK
LCDDOTCK
B7
B6
B5
B4
B3
B2
B1
B0
G7
G6
G5
G4
G3
G2
G1
G0
R7
R6
R5
R4
R3
R2
R1
R0
LCDD23
LCDD22
LCDD21
LCDD20
LCDD19
LCDD18
LCDD17
LCDD16
LCDD15
LCDD14
LCDD13
LCDD12
LCDD11
LCDD10
LCDD9
LCDD8
LCDD7
LCDD6
LCDD5
LCDD4
LCDD3
LCDD2
LCDD1
LCDD0
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
27R
RR48
27R
RR49
27R
RR50
27R
RR51
27R
RR52
27R
RR53
BLUE7
BLUE6
BLUE5
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
GREEN7
GREEN6
GREEN5
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
RED7
RED6
RED5
RED4
RED3
RED2
RED1
RED0
D
R125
27R (LCDPW R)
PE0
R126
4.7k
R127
R128
R129
0R
0R
0R
PE25
PE24
PE23
R130
R131
0R
0R
PE16
PE15
R132
R133
R134
0R
0R
0R
PE9
PE8
PE7
PE[0..30] {3,12}
3V3
VLED+
VLED-
C189
10u
C188
100n
LCDDOTCK
LCDHSYNC
LCDVSYNC
{12} LCDDOTCK
{12} LCDHSYNC
{12} LCDVSYNC
54104-4031
LCM_fix
1
2
3
4
RR54A
RR54B
RR54C
RR54D
R201
R202
R203
R204
8
7
6
5
10R
10R
10R
10R
PE30
PE29
PE28
PE27
PE26
PE25
PE24
PE23
PE22
PE21
PE20
PE19
PE18
PE17
PE16
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
(B7)
(B6)
(B5)
(B4)
(B3)
(B2)
(B1)
(B0)
(G7)
(G6)
(G5)
(G4)
(G3)
(G2)
(G1)
(G0)
(R7)
(R6)
(R5)
(R4)
(R3)
(R2)
(R1)
(R0)
(LCDDEN)
(LCDDOTCK)
(LCDHSYNC)
(LCDVSYNC)
(LCDCC)
C
(LCDPW R)
{12} TV_XCLK
{12} TV_HSYNC
{12} TV_VSYNC
BLUE7
R136
R137
0R DNP
0R
PE24
PE30
BLUE6
R138
R139
0R DNP
0R
PE23
PE29
BLUE5
R140
R141
0R DNP
0R
PE22
PE28
BLUE4
R142
R143
0R DNP
0R
PE21
PE27
BLUE3
R144
R145
0R DNP
0R
PE20
PE26
GREEN7
R146
R147
0R DNP
0R
PE18
PE22
GREEN6
R148
R149
0R DNP
0R
PE17
PE21
GREEN5
R151
R152
0R DNP
0R
PE16
PE20
GREEN4
R155
R157
0R DNP
0R
PE15
PE19
GREEN3
R159
R160
0R DNP
0R
PE14
PE18
GREEN2
R161
R163
0R DNP
0R
PE13
PE17
RED7
R165
R166
0R DNP
0R
PE12
PE14
RED6
R167
R168
0R DNP
0R
PE11
PE13
RED5
R169
R170
0R DNP
0R
PE10
PE12
RED4
R171
R172
0R DNP
0R
PE9
PE11
RED3
R173
R174
0R DNP
0R
PE8
PE10
B
5V
L16
22uH
D7
RB160M-60
C190
10u
5
BL_SHDN#
{3,12} PE2
4
MN19
VIN
SHDN#
VLED+
C191
2.2u
1
2
3
SW
GND
FB
CP2122ST
300mV
R162
10k
2 x 4 LEDs Back Light
LCDHSYNC
X_LEFT
X_RIGHT
Y_UP
Y_LOW
PE4 R150
R153
R154
R156
R158
0R DNP
TSADTRG
PD28 {3,9}
0R
0R
0R
0R
AD3Ym
AD2Yp
AD1Xm
AD0Xp
PD23
PD22
PD21
PD20
C192 C193 C194
VLED-
10n
R164
10R
DNP
10n
DNP
{3,12}
{3,12}
{3,12}
{3,12}
R205
220K
10n
DNP
2*15mA, 12.6+/-0.6V MAX
A
B
A
A2
A
AT91SAM9M10-G45-EK
DISPLAY
REV
MODIF.
SCALE
PP
Derek
DES.
08-apr-10
05-Feb-10
DATE
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REV.
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12
8
7
6
5
4
3
2
1
CONNECTOR EXTENSION FOR LARGE LCD
{3,11} PE[0..30]
1
{2,3,7,8,9,10}
PE6
21
22
23
NRST
24
3V3
AVDD
AGND
AVDD_DAC
AGND_DAC
V
H
XCLK
DE
ISET
CVBS
10k DNP
Y6
1 OE
VDD 4
Y
SPD
SPC
C/CVBS
RESET
NC
34
R184
2 VSS
B
AGND_PLL
4.7k
4.7k
(TW DO)
(TW CK0)
13MHz
DGND
AVDD_PLL
XO
{3,7} PA20
{3,7} PA21
R179
R180
39
40
41
20
OUT 3
R186
DNP
C207
100n
DNP
DNP
R185
0R
0R
1
C208
10p
38
16
1
C196
100n
P-OUT
35
3V3
TV_VSYNC
TV_HSYNC
TV_XCLK
VDDIO
DVDD
XI/FIN
{11}
{11}
{11}
CH7024B
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
C197
100n
18
32
33
25
27
26
L20
2200R
2
1
L21
2200R
2
C204
33p
3V3
{3} PD25
{3} PD27
{3} PD19
C201
10u
10V
(AD1Xm)
(AD3Ym)
R175
0R
DNP
3V3
LCDVSYNC
PE2
PE1
(GPIO2)
{11}
PD15 {3}
1
3
5
7
9
11
13
15
17
19
J18
2
4
6
8
10
12
14
16
18
20
(AD0Xp)
(AD2Yp)
R176
DNP
PD20 {3,11}
PD22 {3,11}
PD24 {3}
PD26 {3}
PD18 {3}
0R
5V
C
3V3
HDR_2x10_SMT
DNP
L22
1.8uH
R181 75R
R183 75R
D
HDR_2x20_SMT
L19
2200R
2
1
1%
28
3V3
PE7
PE9
PE11
PE13
PE15
PE17
PE19
PE21
PE23
PE25
PE27
PE29
3V3
R178 1.2k
30
PE6
PE0
(GPIO1)
{3} PD14
{3,11} PD21
{3,11} PD23
C203
100n
29
2
C199
10u
10V
1
C202
100n
36
{11} LCDHSYNC
{11} LCDDOTCK
1V8
C198
10u
10V
C200
100n
31
L18
2200R
3V3
2
DNP
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
R182
75R
C205
100p
J20
3
C206
D8
100p 1
2
RCA JACk
1
C
42
43
44
45
46
47
48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
19
L17
2200R
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
PE8
PE10
PE12
PE14
PE16
PE18
PE20
PE22
PE24
PE26
PE28
PE30
3
MN20
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE15
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
2
D
J23
(B7)
(B6)
(B5)
(B4)
(B3)
(B2)
(B1)
(B0)
(G7)
(G6)
(G5)
(G4)
(G3)
(G2)
(G1)
(G0)
(R7)
(R6)
(R5)
(R4)
(R3)
(R2)
(R1)
(R0)
(LCDDEN)
(LCDDOTCK)
(HSYNC)
(VSYNC)
(LCDCC)
(LCDMOD)
(LCDPW R)
BAT54SLT1G
37
Composite Video Output
TP6
IMAGE SENSOR CONNECTOR
3V3
Y7
B
3
4
PE30
PE29
PE28
PE27
PE26
PE25
PE24
PE23
PE22
PE21
PE20
PE19
PE18
PE17
PE16
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
13MHz
C209
10p
C210
100n
C212
100n
(CTRL2)
PA20
PB31
PB29
PB30
PB28
PB20
PB22
PB24
PB26
PB8
PB10
PD13 {3}
J17
{3} PB[8..11]
PB8
PB9
PB10
PB11
(ISI_D8)
(ISI_D09)
(ISI_D10)
(ISI_D11)
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
(ISI_D0)
(ISI_D1)
(ISI_D2)
(ISI_D3)
(ISI_D4)
(ISI_D5)
(ISI_D6)
(ISI_D7)
(ISI_PCK)
(ISI_VSYNC)
(ISI_HSYNC)
(ISI_MCK)
{2,3} VDDISI
{3} PD12
(CTRL1)
PA21
{3} PB[20..31]
A
C211
10u
10V
PB21
PB23
PB25
PB27
PB9
PB11
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
HDR_2x15_SMT
A
A2
A
AT91SAM9M10-G45-EK
REV
MODIF.
SCALE
PP
Derek
DES.
08-apr-10
05-Feb-10
DATE
1/1
REV.
LCD & ISI & VIDEO INTERFACE
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
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12
Section 8
Revision History
8.1
Revision History
Table 8-1.
Document
6495B
6495A
Comments
Change Request
Ref.
Main edits:
- Most Figures updated
- Hyperlinks to PDFs updated
- ‘Serial Synchronous Controller (SSC)’ removed
- ‘JTAG’ added
- ‘RJ45 crossed cable’ added
- Dimensions updated
- Most configuration tables (with LEDs, pins and connectors) updated
- ‘LG/Philips’ reference removed
6990
New Figure 4-4, ” EBI1 - DDR2 + Flash” and new Schematics in Section 7.1
”Schematics”
7169
First issue.
AT91SAM9M10-G45-EK User Guide
8-1
6495B–ATARM–21-Apr-10
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6495B–ATARM–21-Apr-10