SAM9N12/CN11-EK .................................................................................................................... User Guide 11186A–ATARM–29-Nov-12 Section 1 Introduction .................................................................................................................1-1 1.1 SAM9N12/CN11 Evaluation Kit.......................................................................................... 1-1 1.2 User Guide Content ........................................................................................................... 1-1 1.3 References and Applicable Documents ............................................................................. 1-1 Section 2 Kit Contents ................................................................................................................2-1 2.1 Deliverables ....................................................................................................................... 2-1 2.2 Evaluation Board Specifications......................................................................................... 2-2 2.3 Electrostatic Warning ......................................................................................................... 2-2 Section 3 Power Up ....................................................................................................................3-1 3.1 Power up the Board ........................................................................................................... 3-1 3.2 Battery................................................................................................................................ 3-1 3.3 Sample Code and Technical Support ............................................................................... 3-1 3.4 Recovery Procedure .......................................................................................................... 3-1 Section 4 Evaluation Kit Hardware .............................................................................................4-1 4.1 Board Overview.................................................................................................................. 4-1 4.2 Equipment List ................................................................................................................... 4-2 4.3 4.2.1 Features List ........................................................................................................ 4-2 4.2.2 Interface Connection............................................................................................ 4-3 4.2.3 Configuration Items.............................................................................................. 4-3 Function Blocks.................................................................................................................. 4-5 4.3.1 Processor............................................................................................................. 4-5 4.3.2 Clock Distribution ................................................................................................. 4-5 4.3.3 Reset and Wake-up Circuitry ............................................................................... 4-6 4.3.4 Power Supplies .................................................................................................... 4-6 4.3.5 Power Rails.......................................................................................................... 4-7 4.3.6 Battery Backup .................................................................................................... 4-8 4.3.7 Memory ................................................................................................................ 4-9 4.3.8 UART DBGU...................................................................................................... 4-10 4.3.9 JTAG Interface................................................................................................... 4-10 4.3.10 Serial Peripheral Interface (SPI) Controller ....................................................... 4-11 4.3.11 Two Wire Interface (TWI)................................................................................... 4-11 4.3.12 USB Ports .......................................................................................................... 4-12 4.3.13 1-Wire EEPROM................................................................................................ 4-13 4.3.14 ETH on EBI ........................................................................................................ 4-13 SAM9N12/CN11-EK User Guide 1-1 11186A–ATARM–29-Nov-12 4.3.15 Audio.................................................................................................................. 4-14 4.3.16 SD Card ............................................................................................................. 4-15 4.3.17 ZigBee Interface ................................................................................................ 4-15 4.3.18 Analog Interface ................................................................................................ 4-16 4.3.19 LED Indicators ................................................................................................... 4-16 4.3.20 Push Buttons ..................................................................................................... 4-17 4.3.21 Expansion Ports................................................................................................. 4-18 4.3.22 4.4 PIO Usage ........................................................................................................ 4-19 Connectors....................................................................................................................... 4-23 4.4.1 Power Supply..................................................................................................... 4-23 4.4.2 JTAG/ICE Connector ......................................................................................... 4-23 4.4.3 DBGU ................................................................................................................ 4-24 4.4.4 USB MicroB ....................................................................................................... 4-25 4.4.5 USB Type A port ................................................................................................ 4-25 4.4.6 SD Card MCI ..................................................................................................... 4-26 4.4.7 Ethernet RJ45 Socket ........................................................................................ 4-27 4.4.8 Zigbee Socket J12 ............................................................................................. 4-27 4.4.9 LCD Socket........................................................................................................ 4-28 4.4.10 IO Expansion Port ............................................................................................. 4-30 Section 5 EK Schematics ...........................................................................................................5-1 5.1 SAM9N12-EK Schematics ................................................................................................. 5-1 5.2 SAM9CN11-EK Schematics............................................................................................... 5-2 Section 6 Display Module Hardware...........................................................................................6-1 6.1 Board Overview.................................................................................................................. 6-1 6.2 Equipment List ................................................................................................................... 6-1 6.3 Function Blocks.................................................................................................................. 6-2 6.3.1 3.3V Regulator ..................................................................................................... 6-2 6.3.2 TFT LCD with Touch Panel ................................................................................. 6-2 6.3.3 Back Light ............................................................................................................ 6-3 6.3.4 QTouch ................................................................................................................ 6-4 6.3.5 1-Wire .................................................................................................................. 6-4 Section 7 DM Schematics...........................................................................................................7-1 7.1 DM Board Schematics ....................................................................................................... 7-1 Section 8 Revision History..........................................................................................................8-1 1-2 11186A–ATARM–29-Nov-12 SAM9N12/CN11-EK User Guide 8.1 Revision History ................................................................................................................. 8-1 SAM9N12/CN11-EK User Guide 1-3 11186A–ATARM–29-Nov-12 Section 1 Introduction 1.1 SAM9N12/CN11 Evaluation Kit This User Guide introduces the SAM9N12 and SAM9CN11 Evaluation Kits and describes their development and debugging capabilities running on SAM9N12 and SAM9CN11 devices. The Atmel ® SAM9N12/CN11 Evaluation Kit is a fully-featured evaluation platform for the Atmel SAM9N12 and SAM9CN11 microcontrollers. The evaluation kit allows users to extensively evaluate, prototype and create application-specific designs. SAM9N12/CN11 Evaluation Kit consists of two boards: 1.2 The Evaluation Kit (EK) board The Display Module (DM) board User Guide Content This guide gives details on how the SAM9N12/CN11-EK has been designed. It is made up of 8 sections: 1.3 Section 1 Introduction (including references, applicable documents) Section 2 Kit Contents Section 3 Power Up Section 4 Evaluation Kit Hardware Section 5 EK Schematics Section 6 Display Module Hardware Section 7 DM Schematics Section 8 Revision History References and Applicable Documents The documents listed below should be referred for more information on the SAM9CN11-EK. Table 1-1. References and Applicable Documents Title Comment SAM9N12/CN11 Datasheet www.atmel.com SAM9N12/CN11-EK User Guide 1-1 11186A–ATARM–29-Nov-12 Section 2 Kit Contents 2.1 Deliverables The Atmel SAM9N12/CN11 Evaluation Kit contains the following items: Board – One SAM9N12/CN11-EK board – One SAM9N12/CN11-DM board Power supply – Universal input AC/DC power supply with US, Europe and UK plug adapters – One 3V lithium battery type CR1225 Cables – One serial RS232 cable – One micro A/B-type USB cable – One RJ45 crossed cable A Welcome letter Figure 2-1. SAM9N12/CN11-EK User Guide Unpacked SAM9N12/CN11-EK 2-1 11186A–ATARM–29-Nov-12 Unpack and inspect the kit carefully. Contact your local Atmel distributor, should you have issues concerning the contents of the kit. 2.2 Evaluation Board Specifications Table 2-1. SAM9N12/CN11 Evaluation Kit Specifications Characteristics 2.3 Specifications Clock speed 400 MHz PCK, 133 MHz MCK Ports Ethernet, USB, RS232, JTAG, Audio, SD card Board supply voltage 5V DC from connector, or 5V DC from Micro USB receptacle Temperature - operating - storage -10°C to + 50°C -40°C to + 85°C Relative humidity 0 to 90% (non condensing) Dimensions - SAM9N12/CN11-EK - SAM9N12/CN11-DM 135 mm x 100 mm 135 mm x 70 mm RoHS status Compliant Electrostatic Warning The SAM9N12/CN11 Evaluation Kit is shipped in a protective anti-static package. The board system must not be subjected to high electrostatic potentials. We strongly recommend using a grounding strap or similar ESD protective device when handling the board in hostile ESD environments (offices with synthetic carpet, for example). Avoid touching the component pins or any other metallic element on the board. 2-2 11186A–ATARM–29-Nov-12 SAM9N12/CN11-EK User Guide Section 3 Power Up 3.1 Power up the Board Unpack the board, taking care to avoid electrostatic discharge. Unpack the power supply, select the right power plug adapter corresponding to that of your country, and insert it in the power supply. Connect the power supply DC connector to the board and plug the power supply to an AC power plug. The board LCD should light up and display a graphic demo program. Then, click or touch icons displayed on the screen and enjoy the demo. 3.2 Battery The SAM9N12/CN11-EK ships with a 3V coin battery. This battery is not required for the board to start up. The coin battery is provided for user convenience in case the user would like to exercise the date and time backup function of the SAM9N12/CN11 devices when the board is switched off. 3.3 Sample Code and Technical Support After boot-up, designers can run sample code or their own application on the development kit. Users can download sample code and get technical support from the Atmel web site: http://www.atmel.com/. 3.4 Recovery Procedure All boards of Evaluation Kit have passed strict test procedures before shipment. The demo software boots from SPI DataFlash® and stores the binary image in the NAND Flash. If the contents of either of the Flash have been deleted, follow the instructions below to recover it to the state as it was when shipped by Atmel. Under the web page of SAM9N12/CN11-EK, find the test package of AT91SAM9N12/CN11EK_test_xx_public.zip (xx is the version number), which is the file for Flash content burning. A step-bystep instruction is available in name of SAM9N12/CN11_EK_Test_Software on how to recover the contents and how to make test for each section of the boards. SAM9N12/CN11-EK User Guide 3-1 11186A–ATARM–29-Nov-12 Section 43 Evaluation Kit Hardware 4.1 Board Overview This section introduces the Atmel SAM9N12/CN11 Evaluation Kit design. It introduces system-level concepts, such as power distribution, memory, and interface assignments. The SAM9N12/CN11-EK board is built around on the integration of an ARM®926-based microcontroller (BGA 217 package) with on-board SDRAM, NAND-Flash and a set of popular peripherals. It is designed to provide a high performance processor evaluation solution with high flexibility for various kinds of applications. Figure 4-1. SAM9N12 Board Architecture SAM9N12/CN11-EK User Guide 4-1 11186A–ATARM–29-Nov-12 Figure 4-2. SAM9CN11 Board Architecture 4.2 Equipment List 4.2.1 Features List Here is the list of the EK board components: SAM9N12/CN11 microcontroller BGA – 16 MHz crystal – 32.768 kHz crystal Memory – 1 Gbit DDR2 memory – 2 Gbits NAND Flash memory with chip selection control switch – Optional NOR Flash – 32 Mbits SPI serial DataFlash with chip selection control switch – 512 Kbits serial EEPROM – 1 Kbit 1-Wire EEPROM 4-2 11186A–ATARM–29-Nov-12 SAM9N12/CN11-EK User Guide – SD/MMC interface Communication – One Ethernet Physical Transceiver Layer with RJ45 connector – UART DBGU port with level shifter IC – JTAG/ICE port – USB Host and Device – ZigBee® Add-on Display Module – TFT LCD module with touch screen – QTouch® elements for user QTouch: K1 to K4 4.2.2 Audio CODEC with input stereo headphone and microphone On-board power regulation and backup battery Two user LEDs and one power LED System buttons: NRST, WKUP, OE_CS One user button Interface Connection The SAM9N12/CN11-EK board includes hardware interfaces such as: 4.2.3 DC power supply (J1) Backup battery (Bt1) USB host, type A connector (J2) USB device, micro B connector (J3) One Ethernet 10/100 interface through an ETH controller (J16) DBGU (RX and TX only) connected to a 9-way male RS232 connector (J11) JTAG, 20 pin IDC connector (J4) SD connector (J8) Headphone (J13), line-in (J15), on board mic-phone (mic1) DM board connection for QTouch and TFT LCD display with touch screen and backlight (J9, J10) ZigBee connector (J12) Three IO expansion ports (J5, J6, J7) Test points (various test points are located throughout the board) Configuration Items Power selection switch (SW1) Push button - NAND/DataFlash OS_CS (PB1) Push button - NRST, board reset (PB2) Push button - Wake-up (PB3) Push button - PB_USER (PB4) SAM9N12/CN11-EK User Guide 4-3 11186A–ATARM–29-Nov-12 Figure 4-3. SAM9N12-EK Board Layout 4-4 11186A–ATARM–29-Nov-12 SAM9N12/CN11-EK User Guide Figure 4-4. SAM9CN11-EK Board Layout 4.3 Function Blocks 4.3.1 Processor The EK board is equipped with a SAM9N12/CN11 device in BGA217 package. The processor runs at a nominal frequency of 400 MHz for the core and 133 MHz for the system bus. 4.3.2 Clock Distribution The SAM9N12/CN11-EK board includes three clock systems. Two of the clock systems are alternatives for the SAM9N12/CN11 main clock and one clock system is an oscillator used for the Ethernet controller chip. SAM9N12/CN11-EK User Guide 4-5 11186A–ATARM–29-Nov-12 Table 4-1 lists the main components associated with these clock systems. Table 4-1. Main Components Associated with the Clock Systems 4.3.3 QTY Description Component assignment 1 Crystal for Internal Clock, 16 MHz Y1 1 Crystal for RTC Clock, 32.768 kHz Y2 1 Crystal for Ethernet Clock, 25 MHz Y3 Reset and Wake-up Circuitry The reset sources for the EK board are: Power-on reset Push-button reset (PB2) JTAG reset from an in-circuit emulator (JTAG interface is equipped on EK board) To disable any bootable content in NAND Flash or DataFlash, please refer to “Push Buttons” . 4.3.4 Power Supplies The SAM9N12/CN11-EK board evaluation and development platform embeds all the necessary power rails required for the SAM9N12/CN11 processor and peripherals. The SAM9N12/CN11-EK board can be supplied by either a USB connection via J3 or a 5V DC block through input J1 (refer to usb schematic). A manual power supply selection (SW1) between the USB supply and the 5V power supply is provided to select the main power line. Figure 4-5. 4-6 11186A–ATARM–29-Nov-12 Power Input SAM9N12/CN11-EK User Guide Connector J1 is provided for use with a DC adapter. It is a 2.5 mm male power jack. Table 4-2 below lists the DC adapter connector pinouts. Table 4-2. Power Input Configuration 4.3.5 PIN INPUT 1 (Center) Positive 2 No connection 3 (Outside) Ground Power Rails The SAM9N12/CN11-EK Board contains three regulated power supplies: 3.3V DC supply 1.8V DC supply 1.0V DC core supply The outputs of these regulated power supplies are distributed as necessary to the circuits on boards. The USB supplies and the 5V input DC block are further regulated to 3.3V. The main 3.3V regulator is based on a RICHTEK RT9018A low dropout regulator providing a fixed output of 3.3V. Its output is used for: VDDIOP0 VDDIOP1 VDDANA VDDOSC VDDUSB VDDFUSE When the 3.3V supply is present, power LED D10 is lit. Test points TP2 to TP5 are used to perform testing. 3.3V Supply TP1 +5V + C1 10uF 3 4 C2 1uF 5 2 +3V3 VIN VDD VOUT 6 R1 100K NC EN PGOOD ADJ 1 C3 100nF R2 47K + C4 10uF C5 1uF VDDIOP0 220ohm at 100MHz 2 L2 1 7 1 TP3 VDDIOP1 220ohm at 100MHz 2 L3 R3 15K SAM9N12/CN11-EK User Guide L1 TP2 1 8 9 PWR_EN MN1 R T9018A GND GND Figure 4-6. TP4 VDDANA 220ohm at 100MHz 2 TP5 4-7 11186A–ATARM–29-Nov-12 The 1.8V DC core supply is based on an LDO LP38692MP IC. It is powered by the 5V DC supply. Its output is used for VDDIOM and VDDNF. Test point TP6 is used to perform testing. Figure 4-7. 1.8V Supply +5V 4 VIN 3 VOUT L4 TP6 +1V8 1 VDDIOM 220ohm at 100MHz 2 TP7 PWR_EN 1 GND L5 VEN C9 10uF 2 NC VDDNF 220ohm at 100MHz 1 2 TP8 5 C8 4. 7uF MN2 LP38692MP-1.8 The 1.0V DC core supply is based on an LDO ADP1715AR. It is powered by the output of the 3.3V CC supply. Its output is used for VDDCORE and VDDPLL. Test point TP10 is used to perform testing. Figure 4-8. 1V Supply TP10 2 C147 22pF EN OUT IN C143 10nf ADP1715 ADJ 4.3.6 +1V 3 R10 12K 1% C11 10uF C144 100nF 4 R13 47K 1% 5 6 7 8 C10 10uF ADP1715ARMZ GND GND GND GND 1 +3V3 MN3 Battery Backup VDDBU pin is powered from the 3.3V rail and a backup battery BT1 via a dual Schottky diode D1. Test point TP13 and jumper JP2 are used to perform testing. Figure 4-9. Backup Battery VDDBU D1 BAT54C 1 J P2 +3V3 BT1 3 TP13 2 C16 100nF C18 2.2uF Note: 4-8 11186A–ATARM–29-Nov-12 Test points (TPn) are provided for easy access to each of the regulated power lines. SAM9N12/CN11-EK User Guide 4.3.7 Memory 4.3.7.1 DDR2 SDRAM The SAM9N12/CN11 processor uses DDR2 SDRAM as the system memory. The DDR2 interface uses 1.8V power. The DDR2 chips and SAM9N12/CN11 processor are connected directly. The interface is 1.8V provided by an on-board voltage regulator. VREF, which is half the interface voltage, or 0.9V, is provided by a simple voltage divider of 1.8V. 4.3.7.2 One 1 Gbit DDR2-SDRAM memory (Micron MT47H64M16HR 8Meg*16*8), 16 bits data interface connected to D[0-15]. NAND FLASH The SAM9N12/CN11-EK has native support for NAND Flash memory and implements an 8-bit NAND Flash with 2 Gbits in size. 4.3.7.3 One 2 Gbits NAND Flash (Micro MT29F2G08ABDHC), 16 bits data interface connected to D[0-15]. NOR FLASH The SAM9N12/CN11-EK provides an optional 128 Mbits of Flash memory using a chip-select signal. The Flash memory is used with the 16-bit port size. One reserved position for 128 Mbits NOR Flash (Numonyx JS28F128P30TF75A). Figure 4-10. External memory FLASH_D[0. .15] FLASH_A[ 1.. 23] MN13 DDR2_A[ 2.. 18] DDR2_A2 DDR2_A3 DDR2_A4 DDR2_A5 DDR2_A6 DDR2_A7 DDR2_A8 DDR2_A9 DDR2_A10 DDR2_A11 DDR2_A12 DDR2_A13 DDR2_A14 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 DDR2_A16 DDR2_A17 DDR2_A18 DDR2_A15 L2 L3 L1 K9 K2 DDR2_SDCKE J8 K8 DDR2_SDCK DDR2_NSDCK L8 DDR2_NCS1 L7 K7 DDR2_CAS DDR2_RAS K3 DDR2_SDWE B7 A8 DDR2_DQS1 F7 E8 DDR2_DQS0 B3 F3 DDR2_DQM1 DDR2_DQM0 DDR2_A15 A2 E2 R3 R7 R8 MN12 A0 DQ0 A1 DDR2 SDRAM DQ1 A2 MT47H64M16HR DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 A12 DQ12 DQ13 BA0 DQ14 BA1 DQ15 BA2 ODT VDD VDD VDD VDD VDD CKE CK CK VDDL VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ CS CAS RAS WE UDQS UDQS VREF LDQS LDQS VSS VSS VSS VSS VSS UDM LDM RFU1 RFU2 RFU3 RFU4 RFU5 +1V8 VSS Q VSS Q VSS Q VSS Q VSS Q VSS Q VSS Q VSS Q VSS Q VSS Q VSSDL G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 DDR2_D0 DDR2_D1 DDR2_D2 DDR2_D3 DDR2_D4 DDR2_D5 DDR2_D6 DDR2_D7 DDR2_D8 DDR2_D9 DDR2_D10 DDR2_D11 DDR2_D12 DDR2_D13 DDR2_D14 DDR2_D15 +1V8 A1 E1 J9 M9 R1 C61 C62 C63 C64 C65 J1 J2 A3 E3 J3 N1 P9 C67 C70 C71 C72 C73 C74 C75 C76 C77 C78 C86 100nF C88 100nF J P9 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF R72 100K R73 470K 45 DNP 44 15 30 32 14 43 R166 DNP CLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 34 36 39 41 47 49 51 53 35 37 40 42 48 50 52 54 FLASH_D0 FLASH_D1 FLASH_D2 FLASH_D3 FLASH_D4 FLASH_D5 FLASH_D6 FLASH_D7 FLASH_D8 FLASH_D9 FLASH_D10 FLASH_D11 FLASH_D12 FLASH_D13 FLASH_D14 FLASH_D15 56 WAI T ADV # RFU1 RFU2 NC 46 26 27 13 RST# WP# +1V 8 VCC VCCQ CE# OE# WE# VSS VSS VSS 33 38 C68 100nF 12 28 31 C69 100nF VPP J S28F128P30TF75A NOR FLASH (DNP) NAND_F SH_D[0.. 7] C79 100nF NANDCLE NANDA LE NANDOE NANDWE A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7 PD6 NANDR_B VDDNF R74 470K VDDNF R75 R76 470K 470K CE D5 C4 D4 C7 C6 RB C8 WP OE_Nandf lash 1 2 NANDCS 3 MN15 NL17SZ126 OE +1V8 5 V CC IN 4 OUT GND +1V 8 R156 10K OE_Nandf lash 1 2 D11 BA T54C 3 4 PB1 1 2 C82 100nF R77 DNP MN14 CLE ALE NAND FLASH RE WE MT29F2G08ABD CE R/ B C3 WP G5 3 R81 1.5K 1% 100K R165 OE_Dataf lash TP17 Tes t Poi nt R71 NCS0 NRD NWRE R54 10K R80 1.5K 1% 0R NOR_NRST VDDI OP0 DDR_VREF C87 4.7uF 100nF 100nF 100nF 100nF 100nF R70 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 DDR_VREF L12 10uH/150mA 150mA R79 1R +1V8 C66 100nF A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 DDR2 SDRAM C84 4.7uF 29 25 24 23 22 21 20 19 8 7 6 5 4 3 2 1 55 18 17 16 11 10 9 F LASH_A1 F LASH_A2 F LASH_A3 F LASH_A4 F LASH_A5 F LASH_A6 F LASH_A7 F LASH_A8 F LASH_A9 F LASH_A10 F LASH_A11 F LASH_A12 F LASH_A13 F LASH_A14 F LASH_A15 F LASH_A16 F LASH_A17 F LASH_A18 F LASH_A19 F LASH_A20 F LASH_A21 F LASH_A22 F LASH_A23 DDR2_D[ 0. .15] A1 A2 A9 A10 B1 B9 B10 D6 D7 D8 E3 E4 E5 E6 E7 E8 F3 F4 F5 F6 F8 G3 G8 L1 L2 LOCK N. C1 N. C2 N. C3 N. C4 N. C5 N. C6 N. C7 N. C8 N. C9 N. C10 N. C11 N. C12 N. C13 N. C14 N. C15 N. C16 N. C17 N. C18 N. C19 N. C20 N. C21 N. C22 N. C23 N. C24 N. C25 I/ O0 I/ O1 I/ O2 I/ O3 I/ O4 I/ O5 I/ O6 I/ O7 N.C26 N.C27 N.C28 N.C29 N.C30 N.C31 N.C32 N.C33 N.C34 N.C35 N.C36 N.C37 N.C38 N.C39 VCC VCC VCC VCC VSS VSS VSS VSS H4 J4 K4 K5 K6 J7 K7 J8 H3 J3 H5 J5 H6 G6 H7 G7 NAND_FSH_D0 NAND_FSH_D1 NAND_FSH_D2 NAND_FSH_D3 NAND_FSH_D4 NAND_FSH_D5 NAND_FSH_D6 NAND_FSH_D7 L9 L10 M1 M2 M9 M10 D3 G4 H8 J6 VDDNF C80 100nF C81 100nF C83 100nF C85 100nF C5 F7 K3 K8 VFBGA-63 MT29F 2G08ABDHC: D NAND FLASH SAM9N12/CN11-EK User Guide 4-9 11186A–ATARM–29-Nov-12 A 3-state buffer is in serial with NAND flash’s CE signal, with PB1 to give a manually disable manner for NAND boot. 4.3.8 UART DBGU The Universal Asynchronous Receiver Transmitter features a two-pin UART that can be used for communication and trace purposes and offers an ideal medium for in-situ programming solutions. This two-pin UART (TXD and RXD only) is buffered through an RS232 transceiver MN16 and brought to the DB9 male connector J11. Figure 4-11. UART MN 16 MAX3232CSE VDD IOP0 C92 100nF R 135 100K PA10 PA9 (D TXD) (D RXD) R136 100K 2 6 C1+ V+ C1- V- C2+ 3 C 91 100nF 4 C 93 100nF J 11 C 94 100nF 15 11 12 10 9 GND T1IN R1OUT T2IN R2OUT C2T1OU T R 1IN T2OU T R 2IN UART 4.3.9 1 5 14 13 7 8 1 6 2 7 3 8 4 9 5 11 C90 100nF VD DIOP0 VCC 10 16 JTAG Interface The SAM9N12/CN11-EK board includes a JTAG interface port (J4), to provide debug level access to the processor. The JTAG port is a 20-pin male connector. This port provides the required interface for in-circuit emulators such as ARM’s Multi-ICE. Figure 4-12. JTAG 4-10 11186A–ATARM–29-Nov-12 SAM9N12/CN11-EK User Guide 4.3.10 Serial Peripheral Interface (SPI) Controller The SAM9N12/CN11 serial processor provides two high-speed Serial Peripheral Interface (SPI) controllers. One port is used to interface with the on-board serial DataFlash. A 3-state buffer is in serial with DataFlash CS signal, with PB1 to give a manually disable manner for DataFlash boot. Figure 4-13. SPI DataFlash 1 OE_Dataf lash PA14 2 3 MN8 NL17SZ126 OE VCC IN OUT VDDIOP0 5 4 C58 100nF GND VDDIOP0 R55 470K PA12 PA11 PA13 (SPI0_MOSI ) R56 (SPI0_MI S0) R57 (SPI0_SPCK) R58 0R 0R 0R 5 2 6 1 (SPI0_NPCS0) MN9 AT25DF321A SI SO SCK VCC WP HOLD CS GND 4.3.11 8 VDDIOP0 3 7 C59 100nF 4 Two Wire Interface (TWI) The SAM9N12/CN11 processor has two full speed (400 kHz) master/slave I2C serial controllers. The controllers are fully compatible with the industry standard I2C interfaces. On the EK board, TWI0 port is used to interface with serial EEPROM, QTouch device and audio CODEC interface. SAM9N12/CN11 processor supports TWI EEPROM boot at the device address of 0x50. On board, the EEPROM device address is 0x51. Customer needs to dismount R61 and mount R62 as 10 kohms, if EEPROM boot is needed. Figure 4-14. EEPROM VDDIOP0 VDDIOP0 R59 4.7K PA31 PA30 R60 4.7K (TW CKO) (TW DO) VDDIOP0 C60 100nF SAM9N12/CN11-EK User Guide VDDIOP0 MN10 AT24C512C-SSHD-T 6 1 A0 2 5 SCL SDA A1 3 A3 8 VCC 4 GND WP R61 10K R62 DNP 7 4-11 11186A–ATARM–29-Nov-12 4.3.12 USB Ports The SAM9N12/CN11-EK features two full speed (OHCI) USB ports: Host full speed, type A USB receptacle, J2 Device full speed, micro B USB receptacle, J3 SAM9N12/CN11-EK features USB power function from device port J3. SW1 functions as switch between USB supply and DC input jack J1. The USB host ports are equipped with 500 mA power switch for bus-powered applications. Figure 4-15. USB Port L6 +5V_LCD 1 TP12 220ohm at 100MHz 2 +5V 8 MN6 OUTA 7 + C15 33uF C17 100nF L7 6 220ohm at 100MHz 1 2 TP14 5 ENA IN FLGA GNG FLGB OUTB ENB SP2526A-2 1 R16 0R 2 R17 0R PC31 3 R18 0R PB8 4 R19 0R PB7 J2 USB-AF-4 1 + C20 33uF C25 100nF 4 5 U SB _A 2 R20 27R 6 3 R21 27R 2 2 D2 TVS 1 D3 TVS 1 USB_+5V RV1 R22 V5.5MLA0603 7 8 9 6 C31 100nF 47K C32 10pF PB16 R23 68K J3 SHD USB Micro B + C37 10uF VBUS DM DP ID GND 1 2 3 4 5 R24 R25 2 R26 47K 1 RV2 2 D4 TVS 2 D5 TVS 1 27R 27R D6 TVS 1 +3V3 V5. 5MLA0603 4-12 11186A–ATARM–29-Nov-12 SAM9N12/CN11-EK User Guide 4.3.13 1-Wire EEPROM The SAM9N12/CN11 Evaluation Kit uses 1-Wire device as “soft label” to store the information such as chip type, manufacture’s name, production date, etc. Figure 4-16. 1-Wire VDDIOP0 R64 1.5K 2 0R 3 4 5 6 NC1 NC2 NC3 NC4 IO 1 R65 GND PA4 MN11 DS2431P+ 4.3.14 ETH on EBI The SAM9N12/CN11 Evaluation Kit uses EBI-based 8-bit EMAC controller KSZ8851 to implement a 10/100 Ethernet access. The board integrates an RJ45 connector with embedded transformer, and two status LEDs. For more information about the Ethernet controller device, refer to the Micrel KSZ8851 manufacturer's datasheet. Figure 4-17. Ethernet L22 +1 V8 1 C1 26 10 uF C12 7 100 nF C 128 1 00n F C1 29 10 0nF A1V8 220 ohm at 100 MHz 2 C1 30 10 0nF C 131 1 00n F C13 2 4.7 uF G ND_ ET H GND_ ETH L23 A3V3 1 C 133 1 00n F A1V8 220 ohm a t 100 MHz 2 +3 V3 C13 4 10u F +1 V8 R1 80 DN P R18 1 47K R 182 4 7K 11 A1 12 6 5 4 PD1 9 NW RE NR D PD2 1 TXP1 TX + 1 19 4 CT 20 2 TD- TX - 2 16 3 RD+ RX + 3 17 5 CT RX - 6 TXM1 RXP1 RXM1 6 RDR 176 R 177 R17 8 R17 9 +1 V8 49 .9R 1% EEC S EESK EED_ IO 4 9.9 R 1 % 4 9.9 R 1 % +1V8 ISET 75 75 4 7 8 +3V3 9 P1LED0 P1LED1 22 R18 5 1nF 8 GND _ETH GND_ ETH 2 1 75 5 GND_ ETH R1 97 4 .7K P1 LED0 P1 LED1 75 7 NC C1 37 10 0nF C13 6 100 nF R19 6 1K C SN W RN R DN I NTR N C13 5 10u F 49. 9R 1% R183 DNP 15 10 9 C MD 3 22R VD D_A3. 3 VDD _IO VDD_ IO VD D_I O VD D_A1. 8 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD1 0 SD1 1 SD1 2 SD1 3 SD1 4 SD1 5 VDD_ D1. 8 48 47 45 44 43 42 41 40 39 36 35 34 33 32 31 30 VD D_CO 1.8 ETH_ D0 ETH_ D1 ETH_ D2 ETH_ D3 ETH_ D4 ETH_ D5 ETH_ D6 ETH_ D7 ETH_ D8 ETH_ D9 ETH_ D10 ETH_ D11 ETH_ D12 ETH_ D13 ETH_ D14 ETH_ D15 KSZ8 851-1 6MLL P1L ED0 3 .01 K 1% P1L ED1 R1 84 470 R R1 86 470 R 10 12 11 PME 13 14 R 187 J16 J00 -00 61 1 TD+ MN19 + 1V8 PD2 0 A3V3 21 14 8 29 ET H_D [0. .15 ] 27 38 46 G ND_ ET H GND_ ETH 24 X1 A 3 AGN D AGND R1 88 4. 7K Y3 R ST N 13 18 NR ST 2 C13 8 100 nF 23 7 26 28 37 M N20 SN 74LVC 1G07 1 5 N.C .VCC +1V8 DG ND DGN D DGND DG ND + 3V3 1 C13 9 22p F 2 25M Hz +1V8 C14 0 22p F + C1 41 10 uF R18 9 0R 4 GND 4 3 25 X2 Y R19 0 0R G ND_ ET H GN D_ETH NOR _NRST SAM9N12/CN11-EK User Guide 4-13 11186A–ATARM–29-Nov-12 4.3.15 Audio The SAM9N12/CN11-EK includes a WM8904 audio CODEC for digital sound input and output. This interface includes features and audio jacks for: Line In (J13) Headphone output (J15) Microphone on board The SAM9N12/CN11 programmable clock output PCK0 is used to generate the WM8904 master clock (MCLK). The bit clock is shared; it can be the SSC Transmitter Clock (TK) or the Receiver Clock (RK). The default setting on SAM9N12/CN11-EK is TK and RK shorted together through R159/R160. Please note that trying different ADC/DAC rates would mean different RK/TK rates; this default setting can be modified. The 0-ohm resistors R159 to R163 have been implemented to offer a disconnection possibility (freeing these dedicated PIO lines for other custom usages). Figure 4-18. Audio CODEC L14 A UD_1V8 AV DD1V8 1 C99 100nF C101 100nF 220ohm at 100MHz 2 A UD_1V8 + C100 10uF R192 0R R193 0R 2 3 AGND_AUDI O J13 4 +3V3 C106 10uF C107 100nF C108 4. 7uF C102 100nF C103 100nF R154 20R R155 20R R152 3.9K R153 3.9K C104 220pF C105 220pF 1 5 HE ADP HONE AGND_AUDI O 22R PA 24 PA 28 PA 25 PA 29 PA 26 PA 27 (TK) (RK ) (TF) (RF ) (TD) (RD) R159 R160 R161 R162 0R 0R 0R 0R R163 0R 2 3 28 29 30 32 31 SCLK SDA 21 23 AVDD R158 AGND_AUDI O VM I DC (P CK0) DCVDD (TWCK 0) (TWD0) PB 10 DBV DD PA 31 PA 30 6 4 A GND_AUDI O MN17 13 HP OUTL HP OUTR HP OUTFB MCLK 15 14 BCLK /GP IO4 16 LRCLK DACDA T ADCDA T LINE OUTL LI NE OUTR 1 18 MIC1 17 GPI O1/ IRQ LINE OUTFB AV DD1V8 1 2 AGND_A UDIO WM8904 7 CPV DD 8 C113 2. 2uF CPCA C114 2. 2uF L19 1 220ohm at 100MHz 2 +3V 3 M ICB I AS R168 2. 2K C117 100nF C118 4. 7uF 20 I N2L IN2R 26 24 5 A GND_AUDI O AGND CPGND 19 MI CVDD 22 9 C142 1uF AVDD CPV OUTP CPV OUTN GND_P ADDLE C116 2. 2uF 27 25 CPCB DGND C115 2. 2uF 11 12 33 10 AGND_AUDI O I N1L/ DMICDA T1 I N1R/ DMICDA T2 R191 0R A GND_A UDI O AGND_A UDIO AGND_A UDIO C120 1uF +1V8 L15 10uH/ 150m A C119 4. 7uF C121 1uF AGND_AUDI O AUD_1V8 R194 0R R195 0R 2 3 R157 J15 1R C109 4. 7uF R173 DNP R174 DNP 4 C124 220pF C125 220pF 1 5 LI NE IN A GND_AUDI O 4-14 11186A–ATARM–29-Nov-12 SAM9N12/CN11-EK User Guide 4.3.16 SD Card The SAM9N12/CN11 has a high-speed Multimedia Card Interface (MCI). It is used as a 4-bit interface connected to an SD card slot. Figure 4-19. SD Card VDDIOP0 JP10 R82 10K PA7 R83 10K R84 68K R85 68K R86 68K R87 68K R88 68K J8 SD-P09KC-M1 Up-Touch Connector nCD 11 1 RR26A 2 RR26B 8 7 PA17 (MCI_CK) R106 PA16 PA20 (MCI_CDA) (MCI_DA3) R110 3 RR26C 27R 6 8 7 6 5 4 3 2 1 PA19 (MCI_DA2) 4 RR26D 5 9 PA18 PA15 (MCI_DA1) (MCI_DA0) UP-TOUCH 10 (MCI card detect) C89 100nF 27R Shell1 Shell2 WP 12 13 DAT1(RSV) DAT0(DO) VSS2 CLK(SCLK) VDD VSS1 CMD(DI) CD/DAT3(CS) DAT2(RSV) SD CARD SD CARD 4.3.17 ZigBee Interface The EK board has a 10-pin male connector for the Atmel RZ600 ZigBee module. DNP 0-ohm resistors have been implemented in series with the PIO lines that are used elsewhere in the design. Thereby, it enables their individual disconnection, should a conflict occur in user application. Figure 4-20. ZigBee PA5 PA3 PA8 PA21 R142 ZB_RSTN R144 ZB_IRQ1 (SPI1_NPCS0)R146 (SPI1_MISO) R148 0R 0R 0R 0R 1 3 5 7 9 J12 2 4 6 8 10 R143 R145 R147 R149 0R 0R 0R 0R C95 18pF ZB_IRQ0 ZB_SLPTR (SPI1_MOSI) (SPI1_SPCK) C96 2.2nF PA2 PA6 PA22 PA23 L13 1 220ohm at 100MHz 2 +3V3 C97 2.2uF ZIGBEE SAM9N12/CN11-EK User Guide 4-15 11186A–ATARM–29-Nov-12 4.3.18 Analog Interface The 3.0V voltage reference is based on an LM4040 (Precision Micropower Shunt Voltage Reference). This ADVREF level can be set as 3.0V or 3.3V via the jumper JP3. Figure 4-21. Analog Reference A 10 kohm potentiometer (VR1) is connected to AD6 port PB17 to implement an easy access to ADC programming and debugging (or to implement an analog user control such as display brightness, volume, etc). Figure 4-22. Potentiometer 4.3.19 LED Indicators There are three LEDs for general purpose on the SAM9N12/CN11-EK board: D8 blue and D9 green LEDs are user defined and controlled by the GPIO. D10 red LED is a power LED indicating that the 3.3V rail is enabled. It can also be controlled by the GPIO (by default, the GPIO is disabled and an on-board pull-up to 3.3V lights the LED). Figure 4-23. LED VDDANA PB4 PB5 R66 470R D8 Blue R67 470R D9 Green D10 Red R68 100K PB6 1 2 3 R69 470R Q2 IRLML2502 4-16 11186A–ATARM–29-Nov-12 SAM9N12/CN11-EK User Guide 4.3.20 Push Buttons SAM9N12/CN11-EK has three mechanical push buttons for system application (PB1 to PB3) and one for free use (PB4). 4.3.20.1 PB1 Output Enable Chip Select Access to the RomBoot: 1. Press simultaneously the PBs OE-CS and NRST 2. Release the PB NRST 3. Then release PB OE-CS The program boots to the ROM code whatever the contents of the NAND Flash or serial DataFlash. Please refer to SAM9N12/CN11 datasheet boot strategy for details. Figure 4-24. PB1 4.3.20.2 PB2 NRST The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components, or be asserted low externally to reset the microcontroller. It will reset the core and the peripherals except for the backup region. Figure 4-25. Push Button NRST WAKE UP PB_USER SAM9N12/CN11-EK User Guide 1 2 1 2 1 2 PB2 PB3 PB4 3 4 3 4 3 4 NRST R150 100K VDDBU WKUP PB3 4-17 11186A–ATARM–29-Nov-12 4.3.21 Expansion Ports Most of GPIOs are led to expansion ports J5, J6, J7. LCD and touch screen connector include J9 and J10 to interface DM board. Figure 4-26. PIO Expansion Ports +3V3 3 J P6 +5V PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 +3V3 JP8 +5V J6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 +3V3 +3V3 +3V3 3 1 2 J5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 +3V3 3 1 2 1 2 J P5 +5V J7 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PB16 PB17 PB18 PD 6 PD 7 PD 8 PD 9 PD 10 PD 11 PD 12 PD 13 PD 14 PD 17 PD 18 PD 19 PD 20 PD 21 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD17 PD18 PD19 PD20 PD21 +3V3 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 PC 8 PC 9 PC 10 PC 11 PC 12 PC 13 PC 14 PC 15 +3V3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PC 16 PC 17 PC 18 PC 19 PC 20 PC 21 PC 22 PC 23 PC 24 PC 25 PC 26 PC 27 PC 28 PC 29 PC 30 PC 31 +3V3 Figure 4-27. LCD Expansion Ports +3V3 PA2 PA31 (ZB_IRQ0) (TWCK0) R89 R91 0R 0R PC1 PC3 PC5 PC7 PC9 PC11 (LCDDAT1) (LCDDAT3) (LCDDAT5) (LCDDAT7) (LCDDAT9) (LCDDAT11) R98 R100 R102 R104 R107 R109 22R 22R 22R 22R 22R 22R J9 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 R90 R92 R93 R94 R95 R96 R97 R99 R101 R103 R105 R108 0R 0R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R (ZB_IRQ1) (TWD0) (LCDDAT15) (LCDDAT14) (LCDDAT13) (LCDDAT12) (LCDDAT0) (LCDDAT2) (LCDDAT4) (LCDDAT6) (LCDDAT8) (LCDDAT10) PA3 PA30 PC15 PC14 PC13 PC12 PC0 PC2 PC4 PC6 PC8 PC10 R115 R116 R117 R118 22R 22R 22R 22R (LCDDAT17) (LCDDAT19) (LCDDAT21) (LCDDAT23) PC17 PC19 PC21 PC23 R120 R122 R125 22R 22R 22R (LCDPWM) (LCDHSY NC) (LCDPCK) PC26 PC28 PC30 R127 R129 R123 0R 0R 0R (AD1_XM) (AD3_Y M) (ONE_WIRE) PB12 PB14 PA4 R132 R134 R138 R140 0R 0R 0R 0R PA22 (SPI1_MOSI) (SPI1_NPCS1) PA0 (LCD_DETECT) PB1 +5V_LCD PC16 PC18 PC20 PC22 (LCDDAT16) (LCDDAT18) (LCDDAT20) (LCDDAT22) R114 R111 R112 R113 22R 22R 22R 22R PC24 PC27 PC29 (LCDDISP) (LCDVSY NC) (LCDDEN) R119 R121 R124 22R 22R 22R PB11 PB13 PB15 (AD0_XP) (AD2_YP) (AD4_LR) R126 R128 R130 0R 0R 0R PA21 PA23 PB9 PB0 (SPI1_MISO) (SPI1_SPCK) R131 R133 R137 R139 0R 0R 0R 0R R141 10K VDDANA J10 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 ESQ-120-33-L-D 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 LCD_DET 4-18 11186A–ATARM–29-Nov-12 SAM9N12/CN11-EK User Guide 4.3.22 PIO Usage PIO A Pin Assignment Table 4-3. PIO A Pin Assignment and Signal Descriptions Signal Alternate Periph A Periph B Periph C PA0 TXD0 SPI1_NPCS1 PA1 RXD0 SPI0_NPCS2 PA2 RTS0 ZB_IRQ0 PA3 CTS0 ZB_IRQ1 PA4 SCK0 One Wire PA5 TXD1 ZB_RSTN PA6 RXD1 ZB_SLPTR PA7 TXD2 SPI0_NPCS1 MCI card detect PA8 RXD2 SPI1_NPCS0 ZigBee PA9 DRXD DBGU PA10 DTXD DBGU PA11 SPI0_MISO MCI_DA4 Serial DataFlash PA12 SPI0_MOSI MCI_DA5 Serial DataFlash PA13 SPI0_SPCK MCI_DA6 Serial DataFlash PA14 SPI0_NPCS0 MCI_DA7 Serial DataFlash PA15 MCI_DA0 MCI PA16 MCI_CDA MCI PA17 MCI_CK MCI PA18 MCI_DA1 MCI PA19 MCI_DA2 MCI PA20 MCI_DA3 MCI PA21 TIOA0 SPI1_MISO ZigBee PA22 TIOA1 SPI1_MOSI ZigBee PA23 TIOA2 SPI1_SPCK ZigBee PA24 TCLK0 TK Audio PA25 TCLK1 TF Audio PA26 TCLK2 TD Audio PA27 TIOB0 RD Audio PA28 TIOB1 RK Audio PA29 TIOB2 RF Audio PA30 TWD0 SPI1_NPCS3 Audio & LCD connector PA31 TWCK0 SPI1_NPCS2 Audio & LCD connector SAM9N12/CN11-EK User Guide (LCD connector) 4-19 11186A–ATARM–29-Nov-12 PIO B Pin Assignment Table 4-4. PIO B Pin Assignment and Signal Descriptions Signal 4-20 Periph A Periph B Periph C PB0 RTS2 (LCD connector) PB1 CTS2 (LCD connector) PB2 SCK2 JUMPER to GND PB3 SPI0_NPCS3 PB_USER1 PB4 USER_LED1 PB5 USER_LED2 PB6 AD7 PWR_LED PB7 AD8 EN5V_HOST PB8 AD9 OVCUR_USB PB9 AD10 PCK1 (LCD connector) PB10 AD11 PCK0 Audio PB11 AD0 PWM0 TSC PB12 AD1 PWM1 TSC PB13 AD2 PWM2 TSC PB14 AD3 PWM3 TSC PB15 AD4 (TSC) PB16 AD5 VBUS_SENSE PB17 AD6 Analog input PB18 11186A–ATARM–29-Nov-12 Alternate IRQ ADTRG LCDHSYNC (+0R) SAM9N12/CN11-EK User Guide PIO C Pin Assignment Table 4-5. PIO C Pin Assignment and Signal Descriptions Signal Alternate Periph A Periph B Periph C PC0 LCDDAT0 TWD1 LCD PC1 LCDDAT1 TWCK1 LCD PC2 LCDDAT2 TIOA3 LCD PC3 LCDDAT3 TIOB3 LCD PC4 LCDDAT4 TCLK3 LCD PC5 LCDDAT5 TIOA4 LCD PC6 LCDDAT6 TIOB4 LCD PC7 LCDDAT7 TCLK4 LCD PC8 LCDDAT8 UTXD0 LCD PC9 LCDDAT9 URXD0 LCD PC10 LCDDAT10 PWM0 LCD PC11 LCDDAT11 PWM1 LCD PC12 LCDDAT12 TIOA5 LCD PC13 LCDDAT13 TIOB5 LCD PC14 LCDDAT14 TCLK5 LCD PC15 LCDDAT15 PCK0 LCD PC16 LCDDAT16 UTXD1 LCD PC17 LCDDAT17 URXD1 LCD PC18 LCDDAT18 PWM0 LCD PC19 LCDDAT19 PWM1 LCD PC20 LCDDAT20 PWM2 LCD PC21 LCDDAT21 PWM3 LCD PC22 LCDDAT22 TXD3 LCD PC23 LCDDAT23 RXD3 LCD PC24 LCDDISP RTS3 LCD CTS3 EN5V_LCD SCK3 LCD PC25 PC26 LCDPWM PC27 LCDVSYNC RTS1 LCD PC28 LCDHSYNC CTS1 LCD PC29 LCDDEN SCK1 LCD PC30 LCDPCK PC31 FIQ SAM9N12/CN11-EK User Guide LCD PCK1 OVCUR_LCD 4-21 11186A–ATARM–29-Nov-12 PIO D Pin Assignment Table 4-6. PIO D Pin Assignment and Signal Descriptions Signal 4-22 11186A–ATARM–29-Nov-12 Alternate Periph A Periph B Periph C PD0 NANDOE NAND Flash PD1 NANDWE NAND Flash PD2 A21/NANDALE NAND Flash PD3 A22/NANDCLE NAND Flash PD4 NCS3 NAND Flash PD5 NWAIT PD6 D16 NAND Flash PD7 D17 NAND Flash PD8 D18 NAND Flash PD9 D19 NAND Flash PD10 D20 NAND Flash PD11 D21 NAND Flash PD12 D22 NAND Flash PD13 D23 NAND Flash PD14 D24 PD15 D25 A20 PD16 D26 A23 PD17 D27 A24 PD18 D28 A25 PD19 D29 NCS2 PD20 D30 NCS4 PD21 D31 NCS5 ETH INT SAM9N12/CN11-EK User Guide 4.4 Connectors 4.4.1 Power Supply Figure 4-28. Power Supply Connector J1 Table 4-7. Power Supply Connector J1 Signal Descriptions 4.4.2 Pin Mnemonic 1 Center Signal description +5V 2 Floating 3 GND JTAG/ICE Connector Figure 4-29. JTAG J4 Table 4-8. JTAG/ICE Connector J4 Signal Descriptions Pin Mnemonic Signal Description 1 VTref. 3.3V power This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators, and to control the output logic levels to the target. It is normally fed from VDD on the target board and must not have a series resistor. 2 Vsupply. 3.3V power This pin is not connected in SAM-ICE. It is reserved for compatibility with other equipment. Connect to VDD or leave open in target system. 3 nTRST TARGET RESET - Active-low output signal that resets the target JTAG Reset. Output from SAM-ICE to the reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection. 4 GND Common ground. SAM9N12/CN11-EK User Guide 4-23 11186A–ATARM–29-Nov-12 Table 4-8. JTAG/ICE Connector J4 Signal Descriptions 4.4.3 5 TDI TEST DATA INPUT - Serial data output line, sampled on the rising edge of the TCK signal. JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU. 6 GND Common ground. 7 TMS TEST MODE SELECT JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU. Output signal that sequences the target's JTAG state machine, sampled on the rising edge of the TCK signal. 8 GND Common ground. 9 TCK TEST CLOCK Output timing signal, for synchronizing test logic and control register access. JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU. 10 GND Common ground. 11 RTCK - Input return test clock signal from the target. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, a returned and retimed TCK can be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND. 12 GND Common ground. 13 TDO JTAG TEST DATA OUTPUT - Serial data input from the target. JTAG data output from target CPU. Typically connected to TDO on target CPU. 14 GND Common ground. 15 nSRST RESET Active-low reset signal. Target CPU reset signal. 16 GND Common ground. 17 RFU This pin is not connected in SAM-ICE. 18 GND Common ground 19 RFU This pin is not connected in SAM-ICE 20 GND Common ground DBGU Figure 4-30. DBGU Connector J11 4-24 11186A–ATARM–29-Nov-12 SAM9N12/CN11-EK User Guide Table 4-9. DBGU Connector J11 Signal Descriptions Pin Mnemonic PIO (Via translator) 1, 4, 6, 9 No connection 2 RXD (Received Data) PA9 RS232 serial data output signal 3 TXD (Transmitted Data) PA10 RS232 serial data input signal 5 GND Common ground 7 RTS (Request To Send) Not used 8 CTS (Clear To Send) Not used Mechanical pins 4.4.4 Description Shield USB MicroB Figure 4-31. USB Device Micro B Connector J3 Table 4-10. USB Device Micro B Connector J3 Signal Descriptions 4.4.5 Pin Mnemonic Description 1 Vbus 5V power 2 DM Data minus 3 DP Data plus 4 ID On the go identification 5 GND Common ground 6, 7, 8, 9 Shield Mechanical pins USB Type A port Figure 4-32. USB Type A Port J2 SAM9N12/CN11-EK User Guide 4-25 11186A–ATARM–29-Nov-12 Table 4-11. USB Type A Port J2 Signal Descriptions 4.4.6 Pin Mnemonic Description 1 Vbus 5V power 2 DM Data minus 3 DP Data plus 4 GND Common ground 5, 6 Shield Mechanical pins SD Card MCI Figure 4-33. SD/MMC Socket J8 Table 4-12. SD Socket J8 Signal Descriptions Pin Function PIO 1 MCI_DA3 PA20 2 MCI_CMD PA16 3 GND 4 VDDIOP0 5 MCI_CLK 6 GND 7 MCI_DA0 PA15 8 MCI_DA1 PA18 9 MCI_DA2 PA19 10 MCI_CD PA7 11 WP 12 GND 13 GND 4-26 11186A–ATARM–29-Nov-12 PA17 SAM9N12/CN11-EK User Guide 4.4.7 Ethernet RJ45 Socket Figure 4-34. Ethernet RJ45 Socket J16 Table 4-13. RJ45 Socket J16 Signal Descriptions Pin 4.4.8 Mnemonic Description 1 TX+ Differential output plus 2 TX- Differential output minus 3 RX+ Differential input plus 4 Reserved 5 Reserved 6 RX- 7 Reserved 8 Reserved Differential input minus Zigbee Socket J12 Figure 4-35. Zigbee Socket J12 Table 4-14. Zigbee Socket J12 Signal Descriptions Function Signal Name Signal Name Function Reset 2 IRQ0 Interrupt Request 3 4 SLP_TR SLP_TR /CS 5 6 MOSI SPI MOSI SPI MISO MISO 7 8 SCLK SPI CLK Power Supply GND 9 10 VCC VCC Pin Pin /RST 1 Interrupt Request IRQ1 SPI chip select SAM9N12/CN11-EK User Guide Port GND Port VCC 4-27 11186A–ATARM–29-Nov-12 4.4.9 LCD Socket Figure 4-36. LCD Socket J9 Table 4-15. LCD Socket J9 Signal Descriptions LCD ISI Pin Num Pin Num ISI LCD 3V3 3V3 1 2 GND GND VDDISI VDDISI 3 4 GND GND ZB_IRQ0 ZB_IRQ0 5 6 ZB_IRQ1 TWCK0 TWCK0 7 8 TWD0 GND GND 9 10 ISI_MCK LCDDAT15 GND GND 11 12 ISI_VSYNC LCDDAT13 GND GND 13 14 ISI_HSYNC LCDDAT14 GND GND 15 16 ISI_PCK LCDDAT12 GND GND 17 18 ISI_D0 LCDDAT0 LCDDAT1 ISI_D1 19 20 ISI_D2 LCDDAT2 LCDDAT3 ISI_D3 21 22 ISI_D4 LCDDAT4 LCDDAT5 ISI_D5 23 24 ISI_D6 LCDDAT6 LCDDAT7 ISI_D7 25 26 ISI_D8 LCDDAT8 LCDDAT9 ISI_D9 27 28 ISI_D10 LCDDAT10 LCDDAT11 ISI_D11 29 30 GND GND 4-28 11186A–ATARM–29-Nov-12 SAM9N12/CN11-EK User Guide Figure 4-37. LCD Socket J10 Table 4-16. LCD Socket J10 Signal Descriptions LCD Pin Num Pin Num LCD 5V 5V_INTER 1 2 GND GND 5V 5V_INTER 3 4 GND GND LCDDAT16 5 6 LCDDAT17 LCDDAT18 7 8 LCDDAT19 LCDDAT20 9 10 LCDDAT21 LCDDAT22 11 12 LCDDAT23 13 14 LCDDISP 15 16 LCDPWM LCDCSYNC 17 18 LCDHSYNC LCDDEN 19 20 LCDPCK GND GND GND GND GND GND 21 22 GND GND AD0_XP TSC 23 24 TSC AD1_XM AD2_YP TSC 25 26 TSC AD3_YM AD4_LR TSC 27 28 GND GND 29 30 SPI1_MISO 31 32 SPI1_MOSI SPI1_SPCK 33 34 SPI1_NPCS1 35 36 37 38 39 40 EN_PWRLCD SELCONFIG PD16 GND SAM9N12/CN11-EK User Guide GND ONE_WIRE GND LCD_DETEC T GND LCD_DETECT# PD17 GND GND 4-29 11186A–ATARM–29-Nov-12 4.4.10 IO Expansion Port Figure 4-38. IO Expansion Socket J5 Table 4-17. IO Expansion Socket J5 Signal Descriptions PIO Pin Num Pin Num 3V3, or 5V 1 2 3V3, or 5V GND 3 4 GND PA0 5 6 PA16 PA1 7 8 PA17 PA2 9 10 PA18 PA3 11 12 PA19 PA4 13 14 PA20 PA5 15 16 PA21 PA6 17 18 PA22 PA7 19 20 PA23 PA8 21 22 PA24 PA9 23 24 PA25 PA10 25 26 PA26 PA11 27 28 PA27 PA12 29 30 PA28 PA13 31 32 PA29 PA14 33 34 PA30 PA15 35 36 PA31 GND 37 38 GND 3V3 39 40 3V3 4-30 11186A–ATARM–29-Nov-12 Power Power PIO SAM9N12/CN11-EK User Guide Figure 4-39. IO Expansion Socket J6 Table 4-18. IO Expansion Socket J6 Signal Descriptions PIO Pin Num Pin Num 3V3, or 5V 1 2 3V3, or 5V GND 3 4 GND PB0 5 6 PB16 PB1 7 8 PB17 PB2 9 10 PB18 PB3 11 12 PD6 PB4 13 14 PD7 PB5 15 16 PD8 PB6 17 18 PD9 PB7 19 20 PD10 PB8 21 22 PD11 PB9 23 24 PD12 PB10 25 26 PD13 PB11 27 28 PD14 PB12 29 30 PD17 PB13 31 32 PD18 PB14 33 34 PD19 PB15 35 36 PD20 GND 37 38 PD21 3V3 39 40 SAM9N12/CN11-EK User Guide Power Power PIO 3V3 4-31 11186A–ATARM–29-Nov-12 Figure 4-40. IO Expansion Socket J7 Table 4-19. IO Expansion Socket J7 Signal Descriptions PIO Power Pin Num Pin Num 3V3, or 5V 1 2 3V3, or 5V GND 3 4 GND PC0 5 6 PC16 PC1 7 8 PC17 PC2 9 10 PC18 PC3 11 12 PC19 PC4 13 14 PC20 PC5 15 16 PC21 PC6 17 18 PC22 PC7 19 20 PC23 PC8 21 22 PC24 PC9 23 24 PC25 PC10 25 26 PC26 PC11 27 28 PC27 PC12 29 30 PC28 PC13 31 32 PC29 PC14 33 34 PC30 PC15 35 36 PC31 GND 37 38 GND 3V3 39 40 3V3 4-32 11186A–ATARM–29-Nov-12 Power PIO SAM9N12/CN11-EK User Guide Section 5 EK Schematics 5.1 SAM9N12-EK Schematics This section contains the following schematics: Top Level Power Supply AT91SAM9N12 EBI Interface PIO Interfaces DDR2 NAND Flash Serial Interfaces Audio ETH SAM9N12/CN11-EK User Guide 5-1 11186A–ATARM–29-Nov-12 7 5 4 3 2 1 3V3 POWER SUPPLY EBI DDR2 INTERFACE POWER USER INTERFACE 1V8 1V PIO EBI DATA INTERFACE EBI FLASH INTERFACE Sheet 2,5,7 ICE INTERFACE PIO A,...E Sheet 3 ATMEL ARM9 Processor SAM9N12 (LFBGA217) EBI BUS INTERFACE EBI ETH INTERFACE RS232 C (RJ 45) Sheet 6 PIO 10/100 FAST ETHERNET HOST DEVICE HE 10 EBI NANDFLASH INTERFACE EBI ADDRESS INTERFACE EBI USB HOST NAND FLASH RES.ARRAYS EBI ADAPTER FLASH D EBI D 6 DDR2 128MB 5V 8 C DBGU Sheet 9 Sheet 4 4.3" 480x272 TFT HE 14 LCD INTERFACE PIO A,...D PIO CONNECTOR TOUCH SCREEN 1-WRIE EEPROM MIC PIO TWI0 HE 14 ISI CAMERA INTERFACE Sheet 3,4,5 B LINEOUT HE 14 ZIGBEE INTERFACE AUDIO CARD READER SPI0 MMC SD SDIO HPOUT SERIAL EEPROM B SERIAL DATA FLASH Sheet 8 Sheet 5 Sheet 7 PIO MUXING PIOA A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 USAGE TXD0 RXD0 ZB_IRQ0 ZB_IRQ1 One Wire ZB_RSTN ZB_SLPTR MCI card detect SPI1_NPCS0 DRXD DTXD SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 MCI_DA0 PIOA PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 USAGE MCI_CDA MCI_CK MCI_DA1 MCI_DA2 MCI_DA3 SPI1_MISO SPI1_MOSI SPI1_SPCK TK TF TD RD RK RF TWD0 TWCKO PIOB USAGE PIOB PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 --ROM CODE PB_USER1 USER_LED1 USER_LED2 PWR_LE EN5V_HOST OVCUR_USB -PCK0 AD0 AD1 AD2 AD3 AD4 PB16 PB17 PB18 USAGE VBUS_SENSE AD6 ADTRG PIOC PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 USAGE LCDDAT0 LCDDAT1 LCDDAT2 LCDDAT3 LCDDAT4 LCDDAT5 LCDDAT6 LCDDAT7 LCDDAT8 LCDDAT9 LCDDAT10 LCDDAT11 LCDDAT12 LCDDAT13 LCDDAT14 LCDDAT15 PIOC PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 USAGE LCDDAT16 LCDDAT17 LCDDAT18 LCDDAT19 LCDDAT20 LCDDAT21 LCDDAT22 LCDDAT23 LCDDISP EN5V_LCD LCDPWM LCDVSYNC LCDHSYNC LCDDEN LCDPCK OVCUR_LCD PIOD PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 NOTE PIOD NANDOE NANDWE NANDALE/A21 NANDCLE NANDCS NWAIT D16 D17 D18 D19 D20 D21 D22 D23 D24 A20 PD16 PD17 PD18 PD19 PD20 PD21 "DNP" means the component is not populated by default D26 D27 D28 NCS2 D30 D31 A C NOR NRST EBI B A INIT EDIT REV SAM9N12-EK_RevC BGA217 TOP LEVEL MODIF. SCALE 25-NOV-11 25-SEP-11 20-AUG-11 DES. DATE 1/1 XXX XX-XXX-XX XXX XX-XXX-XX XXX XX-XXX-XX VER. DATE REV. SHEET C 1 9 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 D D TP1 MN1 RT9018A +5V FORCE POWER ON 3 4 JP1 +5V 1 + C1 10uF 2 C2 1uF 5 VIN VDD VOUT 2 R4 100K EN C7 15pF (3) SHDN 1 PGOOD ADJ C3 100nF R2 47K 1 + C4 10uF 2 5 3 4 R5 10K VDDIOP0 220ohm at 100MHz 2 TP3 L2 C5 1uF 1 7 VDDIOP1 220ohm at 100MHz 2 TP4 L3 VDDANA 220ohm at 100MHz 1 2 8 9 6 GND GND Q1 1 6 R1 100K NC L1 TP2 +3V3 R3 15K TP5 +5V TP9 PWR_EN R6 10K C MN2 LP38692MP-1.8 +5V 4 VOUT L4 TP6 +1V8 3 1 VDDIOM 220ohm at 100MHz 2 L5 1 VEN NC C9 10uF 2 1 TP7 VDDNF 220ohm at 100MHz 2 TP8 5 C8 4.7uF VIN GND C USB_+5V B B TP10 SW1 SW-SLIDE-3 MN3 +5V J1 Jack 2.1mm 1 +3V3 1 F1 SF1812_2A 2 DC_+5V 3 CR1 5V C10 10uF + C6 33uF C147 22pF EN IN OUT 3 C143 10nf ADP1715 5 6 7 8 3 1 2 2 +1V ADP1715ARMZ GND GND GND GND REGULATED 5V ONLY ADJ R10 12K 1% C11 10uF C144 100nF 4 R13 47K 1% VOUT = 0.8V x (Rtop + Rbottom)/Rbottom A A C NOR NRST EBI B A INIT EDIT REV SAM9N12-EK_RevC BGA217 POWER SUPPLY MODIF. SCALE PP 25-NOV-11 PP 25-SEPT-11 PP 20-AUG-11 DES. DATE 1/1 XXX XX-XXX-XX XXX XX-XXX-XX XXX XX-XXX-XX VER. DATE REV. SHEET C 2 9 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 7 6 5 4 3 2 1 8 7 6 5 4 +3V3 C14 100nF L6 +5V_LCD +5V 220ohm at 100MHz 1 2 TP12 8 OUTA 7 C17 100nF L7 6 220ohm at 100MHz 1 2 TP14 B MN6 + C15 33uF D R15 5 ENA IN FLGA GNG FLGB OUTB ENB 1 R16 0R 2 R17 0R PC31 3 R18 0R PB8 4 R19 0R PB7 47K MN5 SN74LVC1G32 5 1 VCC A 4 Y GND 2 3 2 1 +3V3 LCD_DET (7) PC25 VDDBU 3 D1 BAT54C JP2 +3V3 BT1 1 3 TP13 2 C16 100nF C18 2.2uF D SP2526A-2 MN7A SAM9N12_LBGA217 - POWER +1V J2 USB-AF-4 3 R21 27R P17 D2 TVS 6 1 5 N17 HDM HDP VDDIOM VDDIOM VDDIOM D3 TVS VDDNF VDDNF VDDNF USB_+5V RV1 C31 100nF 47K PB16 C32 10pF VDDIOP1 VDDIOP1 R23 68K C VDDIOP0 VDDIOP0 J3 9 6 1 2 3 4 5 R26 47K H10 H9 H8 C24 100nF D4 TVS 27R 27R R16 R17 D5 TVS C21 100nF C27 100nF L14 K14 J14 VDDNF C28 100nF L4 L3 C33 100nF C35 100nF VDDPLL GNDPLL D6 TVS U17 VDDANA GNDANA 3 20pF 4 C45 U16 C44 4.7uF XOUT +3V3 1 A4 Y2 32.768 kHz A3 2 B4 R15 T17 VDDOSC SD1 DNP R31 0R R33 0R (7,9) WKUP (2) SHDN T15 R11 T13 R12 T14 U14 R13 NRST (7) +3V3 C46 100nF R14 C48 100nF XOUT32 B C49 100nF R29 1R C51 4.7uF 1 VDDBU R30 L10 10uH/150mA VDDOSC XIN32 8 7 6 5 15pF C43 100nF R28 1R 2 1 2 3 4 RR1D RR1C RR1B RR1A C50 15pF C40 4.7uF C42 100nF XIN VDDUSB GNDUSB C47 1R VDDANA C4 B2 2 1 20pF +1V C39 100nF R27 1 1 1 VDDIOP0 1 3 5 7 9 11 13 15 17 19 L8 10uH/150mA C38 100nF Y1 16MHz 2 4 6 8 10 12 14 16 18 20 C36 100nF T16 P14 L9 10uH/150mA C41 J4 C VDDPLL V5.5MLA0603 VDDIOP0 C30 100nF VDDIOP0 DDM DDP +3V3 R35 100K C29 100nF C34 100nF P12 P9 RV2 B C19 100nF VDDIOM C26 100nF 2 2 R24 R25 2 SHD USB Micro B C23 100nF A5 B5 JTAGSEL NTRST TDI TMS TCK RTCK TDO L11 10uH/150mA VDDFUSE VDDFUSE GNDFUSE +3V3 VDDANA N16 M16 C52 100nF C53 100nF R32 R34 4.7K C54 4.7uF NRST +5V JP3 2 1R 3 + C37 10uF V5.5MLA0603 VBUS DM DP ID GND C22 100nF VDDIOP1 R22 7 8 P10 J4 G15 C8 1 USB_A 27R 2 4 C25 100nF R20 1 + C20 33uF 2 2 1 VDDCORE VDDCORE VDDCORE VDDCORE TP15 TP16 WKUP D7 SHDN ADVREF A2 C55 2.2uF LM4040-3V (5,7) PC[0..31] A R36 10K PC25 N15 U15 NC BMS PB[0..18] VDDBU GNDBU GNDBU D6 D5 B3 C57 100nF A P13 P7 P6 K10 K9 J10 J9 J8 P11 K8 H14 D8 PC31 (5,7,8) C56 100nF VDDBU GNDIOP GNDIOP GNDIOP GNDIOM GNDIOM GNDIOM GNDIOM GNDIOM GNDCORE GNDCORE GNDCORE GNDCORE VDDIOP0 JP4 C NOR NRST EBI B A INIT EDIT PB7 PB8 REV SAM9N12-EK_RevC PB16 BGA217 AT91SAM9N12 MODIF. SCALE PP 25-NOV-11 PP 25-SEPT-11 PP 20-AUG-11 DES. DATE 1/1 XXX XX-XXX-XX XXX XX-XXX-XX XXX XX-XXX-XX VER. DATE REV. SHEET C 3 9 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 7 6 5 4 3 2 1 5 4 3 2 1 EBI_D[0..15] MN7F SAM9N12_LBGA217 - EBI D C D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0/NBS0 A1/NBS2/DQM2/NWR2 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16/BA0 A17/BA1 A18/BA2 A19 DQM0 DQM1 DQS0 DQS1 RAS CAS SDWE SDCKE SDA10 SDCK SDCKN NCS0 NCS1/SDCS NWR0/NWRE NWR1/NBS1 NWR3/NBS3/DQM3 NRD B14 A14 C14 D13 C13 B13 A13 C12 D12 B12 C11 D11 A12 B11 A11 C10 EBI_D0 EBI_D1 EBI_D2 EBI_D3 EBI_D4 EBI_D5 EBI_D6 EBI_D7 EBI_D8 EBI_D9 EBI_D10 EBI_D11 EBI_D12 EBI_D13 EBI_D14 EBI_D15 D17 C17 F16 B17 A17 F15 E16 D16 E15 G14 C16 F14 B16 A16 C15 D15 B15 E14 A15 D14 EBI_A1 EBI_A2 EBI_A3 EBI_A4 EBI_A5 EBI_A6 EBI_A7 EBI_A8 EBI_A9 EBI_A10 EBI_A11 EBI_A12 EBI_A13 EBI_A14 EBI_A15 EBI_A16 EBI_A17 EBI_A18 EBI_A19 C9 A8 B8 A7 EBI_DQM0 EBI_DQM1 EBI_DQS0 EBI_DQS1 B9 D9 EBI_RAS EBI_CAS B10 D10 B6 A10 A9 EBI_SDWE EBI_SDCKE EBI_SDA10 EBI_SDCK EBI_NSDCK B7 C5 NCS0 EBI_NCS1_SDCS A6 C6 D7 NWRE C7 NRD DDR2_D[0..15] A1 (9) EBI_D0 EBI_D1 EBI_D2 EBI_D3 EBI_D4 EBI_D5 EBI_D6 EBI_D7 EBI_D8 EBI_D9 EBI_D10 EBI_D11 EBI_D12 EBI_D13 EBI_D14 EBI_D15 2 3 4 1 4 2 1 3 1 2 3 4 1 2 4 3 RR2B RR2C RR2D RR2A RR3D RR3B RR3A RR3C RR4A RR4B RR4C RR4D RR5A RR5B RR5D RR5C 7 6 5 8 5 7 8 6 8 7 6 5 8 7 5 6 DDR2_D0 DDR2_D1 DDR2_D2 DDR2_D3 DDR2_D4 DDR2_D5 DDR2_D6 DDR2_D7 DDR2_D8 DDR2_D9 DDR2_D10 DDR2_D11 DDR2_D12 DDR2_D13 DDR2_D14 DDR2_D15 EBI_D0 EBI_D1 EBI_D2 EBI_D3 EBI_D4 EBI_D5 EBI_D6 EBI_D7 EBI_D8 EBI_D9 EBI_D10 EBI_D11 EBI_D12 EBI_D13 EBI_D14 EBI_D15 4 3 2 1 1 2 3 4 1 2 3 4 1 2 3 4 RR6D RR6C RR6B RR6A RR7A RR7B RR7C RR7D RR8A RR8B RR8C RR8D RR9A RR9B RR9C RR9D 5 6 7 8 8 7 6 5 8 7 6 5 8 7 6 5 FLASH_D0 FLASH_D1 FLASH_D2 FLASH_D3 FLASH_D4 FLASH_D5 FLASH_D6 FLASH_D7 FLASH_D8 FLASH_D9 FLASH_D10 FLASH_D11 FLASH_D12 FLASH_D13 FLASH_D14 FLASH_D15 EBI_D0 EBI_D1 EBI_D2 EBI_D3 EBI_D4 EBI_D5 EBI_D6 EBI_D7 EBI_D8 EBI_D9 EBI_D10 EBI_D11 EBI_D12 EBI_D13 EBI_D14 EBI_D15 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 RR10A RR10B RR10C RR10D RR11A RR11B RR11C RR11D RR12A RR12B RR12C RR12D RR13A RR13B RR13C RR13D 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 ETH_D0 ETH_D1 ETH_D2 ETH_D3 ETH_D4 ETH_D5 ETH_D6 ETH_D7 ETH_D8 ETH_D9 ETH_D10 ETH_D11 ETH_D12 ETH_D13 ETH_D14 ETH_D15 FLASH_D[0..15] (6) NWRE (6,9) NRD (6,9) MN7E SAM9N12_LBGA217 - PIOD PD0/NANDOE PD1/NANDWE PD2/A21/NANDALE PD3/A22/NANDCLE PD4/NCS3 PD5/NWAIT PD6/D16 PD7/D17 PD8/D18 PD9/D19 PD10/D20 PD11/D21 PD12/D22 PD13/D23 PD14/D24 PD15/D25/A20 PD16/D26/A23 PD17/D27/A24 PD18/D28/A25 PD19/D29/NCS2 PD20/D30/NCS4 PD21/D31/NCS5 P15 N14 M15 M14 P16 M17 L15 L16 L17 K17 K16 K15 J17 J16 H17 J15 G17 H16 H15 F17 G16 E17 1 2 3 4 4 3 2 1 RR14A RR14B RR14C RR14D RR15D RR15C RR15B RR15A 8 7 6 5 5 6 7 8 PD15 PD16 (5) (5) (5) (5) (5) (5) (5) (5) (5) PD17 PD18 PD19 PD20 PD21 (5) (5) (5,9) (5,9) (5,9) PD0 PD1 PD2 PD3 PD4 PD5 (NANDOE) (NANDWE) (NANDALE) (NANDCLE) (NANDCS) (NANDR/B) R48 R49 R50 R51 R52 R53 0R 0R 0R 0R 0R 0R D DDR2_A2 DDR2_A3 DDR2_A4 DDR2_A5 DDR2_A6 DDR2_A7 DDR2_A8 DDR2_A9 DDR2_A10 DDR2_A11 DDR2_A12 DDR2_A13 DDR2_A14 DDR2_A15 DDR2_A16 DDR2_A17 DDR2_A18 EBI_A1 EBI_A2 EBI_A3 EBI_A4 EBI_A5 EBI_A6 EBI_A7 EBI_A8 EBI_A9 EBI_A10 EBI_A11 EBI_A12 EBI_A13 EBI_A14 EBI_A15 EBI_A16 EBI_A17 EBI_A18 EBI_A19 PD15 PD2 PD3 PD16 (9) 1 2 3 4 3 4 2 1 1 3 2 4 1 4 2 3 1 2 3 4 1 3 2 4 RR20A RR20B RR20C RR20D RR21C RR21D RR21B RR21A RR22A RR22C RR22B RR22D RR23A RR23D RR23B RR23C RR24A RR24B RR24C RR24D RR25A RR25C RR25B RR25D FLASH_A[1..23] 8 7 6 5 6 5 7 8 8 6 7 5 8 5 7 6 8 7 6 5 8 6 7 5 (6) FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 B (6) NAND_FSH_D0 NAND_FSH_D1 NAND_FSH_D2 NAND_FSH_D3 NAND_FSH_D4 NAND_FSH_D5 NAND_FSH_D6 NAND_FSH_D7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 RR16D 5 RR16C 6 RR16B 7 RR16A 8 RR17C 6 RR17D 5 RR17B 7 RR17A 8 RR18A 8 RR18B 7 RR18C 6 RR18D 5 RR19A 8 RR19B 7 RR19C 6 RR19D 5 10R (6) NAND_FSH_D[0..7] EBI_D0 EBI_D1 EBI_D2 EBI_D3 EBI_D4 EBI_D5 EBI_D6 EBI_D7 4 3 2 1 3 4 2 1 1 2 3 4 1 2 3 4 R164 (6) C ETH_D[0..15] NCS0 DDR2_A[2..18] EBI_A2 EBI_A3 EBI_A4 EBI_A5 EBI_A6 EBI_A7 EBI_A8 EBI_A9 EBI_A10 EBI_A11 EBI_SDA10 EBI_A13 EBI_A14 EBI_A15 EBI_A16 EBI_A17 EBI_A18 B A (6) NANDOE NANDWE NANDALE NANDCLE NANDCS NANDR_B (6) (6) (6) (6) (6) (6) EBI_DQM0 EBI_DQM1 EBI_DQS0 EBI_DQS1 R37 R38 R39 R40 10R 10R 10R 10R DDR2_DQM0 (6) DDR2_DQM1 (6) DDR2_DQS0 (6) DDR2_DQS1 (6) EBI_RAS EBI_CAS R41 R42 10R 10R DDR2_RAS DDR2_CAS EBI_SDWE EBI_SDCKE R43 R44 10R 10R DDR2_SDWE (6) DDR2_SDCKE (6) EBI_SDCK EBI_NSDCK R45 R46 10R 10R DDR2_SDCK (6) DDR2_NSDCK (6) EBI_NCS1_SDCS R47 10R DDR2_NCS1 (6) (6) (6) A C NOR NRST EBI B A INIT EDIT REV SAM9N12-EK_RevC BGA217 EBI_INTERFACE MODIF. SCALE PP 25-NOV-11 PP 25-SEPT-11 PP 20-AUG-11 DES. 1/1 DATE XXX XX-XXX-XX XXX XX-XXX-XX XXX XX-XXX-XX VER. DATE REV. SHEET C 4 9 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 5 4 3 2 1 JP5 +5V MN7B SAM9N12_LBGA217 - PIOA PA0/TXD0/SPI1_NPCS1 PA1/RXD0/SPI0_NPCS2 PA2/RTS0 PA3/CTS0 PA4/SCK0 PA5/TXD1 PA6/RXD1 PA7/TXD2/SPI0_NPCS1 PA8/RXD2/SPI1_NPCS0 PA9/DRXD PA10/DTXD PA11/SPI0_MISO/MCI_DA4 PA12/SPI0_MOSI/MCI_DA5 PA13/SPI0_SPCK/MCI_DA6 PA14/SPI0_NPCS0/MCI_DA7 PA15/MCI_DA0 PA16/MCI_CDA PA17/MCI_CK PA18/MCI_DA1 PA19/MCI_DA2 PA20/MCI_DA3 PA21/TIOA0/SPI1_MISO PA22/TIOA1/SPI1_MOSI PA23/TIOA2/SPI1_SPCK PA24/TCLK0/TK PA25/TCLK1/TF PA26/TCLK2/TD PA27/TIOB0/RD PA28/TIOB1/RK PA29/TIOB2/RF PA30/TWD0/SPI1_NPCS3 PA31/TWCK0/SPI1_NPCS2 D T3 U2 U3 P4 T4 U4 P5 R4 U6 R5 R6 T5 T6 U5 U7 T7 R7 U8 P8 T8 R8 U9 U10 T9 U11 T10 R9 U12 T11 U13 R10 T12 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 +3V3 3 1 (7,8) 2 PA[0..31] MN8 NL17SZ126 1 (6) OE_Dataflash 2 PA14 3 OE VCC IN OUT GND J5 VDDIOP0 5 4 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 C58 100nF VDDIOP0 R55 470K PA12 PA11 PA13 (SPI0_MOSI) R56 (SPI0_MIS0) R57 (SPI0_SPCK) R58 MN9 AT25DF321A 5 2 6 0R 0R 0R SI SO SCK 1 (SPI0_NPCS0) VDDIOP0 8 VCC 3 7 WP HOLD CS C59 100nF +3V3 4 GND SERIAL DATAFLASH 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 JP6 +3V3 +3V3 3 1 VDDIOP0 2 VDDIOP0 D TP11 +5V VDDIOP0 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 C R59 4.7K PB[0..18] (3,7,8) PA31 PA30 SAM9N12_LBGA217 - PIOB PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 VDDIOP0 VDDANA C60 100nF 4 GND 2 +3V3 R64 1.5K 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PB16 PB17 PB18 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD17 PD18 PD19 PD20 PD21 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD17 PD18 PD19 PD20 PD21 2 0R IO (3,7) JP8 +5V 3 4 5 6 +3V3 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 PB18 R78 DNP PC28 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 VDDANA PB5 B J7 1-WIRE EEPROM PB4 +3V3 3 1 1 NC1 NC2 NC3 NC4 R66 470R D8 Blue R67 470R D9 Green +3V3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 +3V3 R68 100K PB6 A 1 2 3 R69 470R D10 Red C NOR NRST EBI B A INIT EDIT Q2 IRLML2502 REV LED SAM9N12-EK_RevC BGA217 PIO_INTERFACES MODIF. SCALE PP 25-NOV-11 PP 25-SEPT-11 PP 20-AUG-11 DES. 1/1 DATE XXX XX-XXX-XX XXX XX-XXX-XX XXX XX-XXX-XX VER. DATE REV. SHEET C 5 9 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4,9) (4,9) (4,9) 2 R65 MN11 DS2431P+ SAM9N12_LBGA217 - PIOC A 7 WP VDDIOP0 PC[0..31] G2 G1 H4 J1 H3 J3 H2 H1 K2 J2 L1 K1 L2 K3 M1 M2 K4 M3 N1 N2 N3 P1 P2 P3 R1 R3 R2 T1 M4 N4 T2 U1 R62 DNP SERIAL EEPROM JP7 PB2 B PC0/LCDDAT0//TWD1 PC1/LCDDAT1//TWCK1 PC2/LCDDAT2//TIOA3 PC3/LCDDAT3//TIOB3 PC4/LCDDAT4//TCLK3 PC5/LCDDAT5//TIOA4 PC6/LCDDAT6//TIOB4 PC7/LCDDAT7//TCLK4 PC8/LCDDAT8//UTXD0 PC9/LCDDAT9//URXD0 PC10/LCDDAT10//PWM0 PC11/LCDDAT11//PWM1 PC12/LCDDAT12//TIOA5 PC13/LCDDAT13//TIOB5 PC14/LCDDAT14//TCLK5 PC15/LCDDAT15//PCK0 PC16/LCDDAT16//UTXD1 PC17/LCDDAT17//URXD1 PC18/LCDDAT18//PWM0 PC19/LCDDAT19//PWM1 PC20/LCDDAT20//PWM2 PC21/LCDDAT21//PWM3 PC22/LCDDAT22/TXD3 PC23/LCDDAT23/RXD3 PC24/LCDDISP/RTS3 PC25//CTS3 PC26/LCDPWM/SCK3 PC27/LCDVSYNC//RTS1 PC28/LCDHSYNC//CTS1 PC29/LCDDEN//SCK1 PC30/LCDPCK PC31/FIQ//PCK1 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 R63 10K PA4 MN7D (TWCKO) (TWDO) 1 E4 F3 F4 F2 G4 G3 D2 E2 D1 F1 E1 A1 C3 B1 C2 D3 C1 E3 D4 J6 3 PB0/RTS2 PB1/CTS2 PB2/SCK2 PB3/SPI0_NPCS3 PB4 PB5 PB6/AD7 PB7/AD8 PB8/AD9 PB9/AD10/PCK1 PB10/AD11/PCK0 PB11/AD0/PWM0 PB12/AD1/PWM1 PB13/AD2/PWM2 PB14/AD3/PWM3 PB15/AD4 PB16/AD5 PB17/AD6 PB18/IRQ/ADTRG MN10 AT24C512C-SSHD-T 1 SCL A0 2 SDA A1 3 A3 8 VCC C R61 10K 6 5 GND MN7C R60 4.7K 4 3 2 1 5 4 3 2 1 (4) FLASH_D[0..15] (4) FLASH_A[1..23] MN13 (4) DDR2_D[0..15] D (4) DDR2_A[2..18] MN12 DDR2_A2 DDR2_A3 DDR2_A4 DDR2_A5 DDR2_A6 DDR2_A7 DDR2_A8 DDR2_A9 DDR2_A10 DDR2_A11 DDR2_A12 DDR2_A13 DDR2_A14 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 DDR2_A16 DDR2_A17 DDR2_A18 DDR2_A15 L2 L3 L1 A0 DQ0 DDR2 SDRAM A1 DQ1 A2 MT47H64M16HR DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 A12 DQ12 DQ13 BA0 DQ14 BA1 DQ15 BA2 K9 K2 (4) DDR2_SDCKE CK CK L8 (4) DDR2_NCS1 WE B7 A8 (4) DDR2_DQS1 UDQS UDQS F7 E8 (4) DDR2_DQS0 DDR2_A15 VREF VSS VSS VSS VSS VSS LDQS LDQS B3 F3 (4) DDR2_DQM1 (4) DDR2_DQM0 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ CAS RAS K3 (4) DDR2_SDWE VDDL CS L7 K7 (4) DDR2_CAS (4) DDR2_RAS VDD VDD VDD VDD VDD CKE J8 K8 (4) DDR2_SDCK (4) DDR2_NSDCK C ODT UDM LDM A2 E2 R3 R7 R8 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL RFU1 RFU2 RFU3 RFU4 RFU5 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 DDR2_D0 DDR2_D1 DDR2_D2 DDR2_D3 DDR2_D4 DDR2_D5 DDR2_D6 DDR2_D7 DDR2_D8 DDR2_D9 DDR2_D10 DDR2_D11 DDR2_D12 DDR2_D13 DDR2_D14 DDR2_D15 +1V8 A1 E1 J9 M9 R1 C61 C62 C63 C64 C65 J1 A3 E3 J3 N1 P9 +1V8 (9) NOR_NRST 29 25 24 23 22 21 20 19 8 7 6 5 4 3 2 1 55 18 17 16 11 10 9 R70 0R 45 R71 100K 44 R72 100K 15 C67 C70 C71 C72 C73 C74 C75 C76 C77 C78 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF (4,9) (4,9) 30 32 14 NRD NWRE (4) R73 NCS0 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7 (4) PD6 NANDR_B NANDCLE NANDALE NANDOE NANDWE VDDNF R74 470K VDDNF R75 R76 470K 470K R77 DNP 1 2 NANDCS VDDIOP0 OE VCC IN OUT GND +1V8 5 4 C82 100nF +1V8 R80 1.5K 1% R54 10K R156 10K OE_Nandflash 26 27 13 RST# WP# CE# OE# WE# +1V8 VCC VCCQ VSS VSS VSS 33 38 C68 100nF 12 28 31 C69 100nF C VPP RB C8 WP C3 A1 A2 A9 A10 B1 B9 B10 D6 D7 D8 E3 E4 E5 E6 E7 E8 F3 F4 F5 F6 F8 G3 G8 L1 L2 CLE I/O0 ALE NAND FLASH I/O1 RE MT29F2G08ABD I/O2 WE I/O3 CE I/O4 I/O5 R/B I/O6 I/O7 WP N.C26 N.C27 LOCK N.C28 N.C29 N.C30 N.C1 N.C31 N.C2 N.C32 N.C3 N.C33 N.C4 N.C5 N.C6 N.C34 N.C7 N.C35 N.C8 N.C36 N.C9 N.C37 N.C10 N.C38 N.C11 N.C39 N.C12 N.C13 N.C14 VCC N.C15 VCC N.C16 VCC N.C17 VCC N.C18 N.C19 N.C20 N.C21 VSS N.C22 VSS N.C23 VSS N.C24 VSS N.C25 VFBGA-63 MT29F2G08ABDHC:D H4 J4 K4 K5 K6 J7 K7 J8 H3 J3 H5 J5 H6 G6 H7 G7 NAND_FSH_D0 NAND_FSH_D1 NAND_FSH_D2 NAND_FSH_D3 NAND_FSH_D4 NAND_FSH_D5 NAND_FSH_D6 NAND_FSH_D7 B L9 L10 M1 M2 M9 M10 VDDNF D3 G4 H8 J6 C80 C81 C83 C85 100nF 100nF 100nF 100nF C5 F7 K3 K8 NAND FLASH 2 OE_Dataflash 1 (5) CE D5 C4 D4 C7 C6 G5 MN15 NL17SZ126 R81 1.5K 1% 46 MN14 3 C88 100nF 56 NOR FLASH (DNP) (4) (4) (4) (4) (4) C87 4.7uF RFU1 RFU2 NC D (4) NAND_FSH_D[0..7] C79 100nF OE_Nandflash TP17 Test Point ADV# FLASH_D0 FLASH_D1 FLASH_D2 FLASH_D3 FLASH_D4 FLASH_D5 FLASH_D6 FLASH_D7 FLASH_D8 FLASH_D9 FLASH_D10 FLASH_D11 FLASH_D12 FLASH_D13 FLASH_D14 FLASH_D15 DDR_VREF L12 10uH/150mA 150mA DDR_VREF WAIT 34 36 39 41 47 49 51 53 35 37 40 42 48 50 52 54 JS28F128P30TF75A 470K +1V8 C86 100nF CLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 JP9 DDR2 SDRAM R79 1R 43 1V8 B C84 4.7uF A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 C66 100nF A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J2 100nF 100nF 100nF 100nF 100nF FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 D11 BAT54C A 3 A PB1 3 4 C NOR NRST EBI B A INIT EDIT 1 2 REV SAM9N12-EK_RevC BGA217 DDR2 NAND FLASH MODIF. SCALE PP 25-NOV-11 PP 25-SEPT-11 PP 20-AUG-11 DES. 1/1 DATE XXX XX-XXX-XX XXX XX-XXX-XX XXX XX-XXX-XX VER. DATE REV. SHEET C 6 9 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 8 7 6 5 4 3 2 1 PA[0..31] (5,8) VDDIOP0 +3V3 JP10 R82 10K D PA7 R83 10K R84 68K R85 68K R86 68K R87 68K R88 68K PA2 PA31 J8 SD-P09KC-M1 Up-Touch Connector 10 (MCI card detect) 11 PA18 PA15 (MCI_DA1) (MCI_DA0) 1 RR26A 2 RR26B 8 7 PA17 (MCI_CK) R106 PA16 PA20 (MCI_CDA) (MCI_DA3) R110 3 RR26C 27R 6 8 7 6 5 4 3 2 1 PA19 (MCI_DA2) 4 RR26D 5 9 C89 100nF 27R (ZB_IRQ0) (TWCK0) R89 R91 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 0R 0R UP-TOUCH nCD Shell1 Shell2 WP 12 13 PC1 PC3 PC5 PC7 PC9 PC11 DAT1(RSV) DAT0(DO) VSS2 CLK(SCLK) VDD VSS1 CMD(DI) CD/DAT3(CS) (LCDDAT1) (LCDDAT3) (LCDDAT5) (LCDDAT7) (LCDDAT9) (LCDDAT11) R98 R100 R102 R104 R107 R109 22R 22R 22R 22R 22R 22R PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 J9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 R90 R92 R93 R94 R95 R96 R97 R99 R101 R103 R105 R108 0R 0R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R (ZB_IRQ1) (TWD0) (LCDDAT15) (LCDDAT14) (LCDDAT13) (LCDDAT12) (LCDDAT0) (LCDDAT2) (LCDDAT4) (LCDDAT6) (LCDDAT8) (LCDDAT10) PA3 PA30 PC15 PC14 PC13 PC12 PC0 PC2 PC4 PC6 PC8 PC10 R115 R116 R117 R118 22R 22R 22R 22R (LCDDAT17) (LCDDAT19) (LCDDAT21) (LCDDAT23) PC17 PC19 PC21 PC23 R120 R122 R125 22R 22R 22R (LCDPWM) (LCDHSYNC) (LCDPCK) PC26 PC28 PC30 R127 R129 R123 0R 0R 0R (AD1_XM) (AD3_YM) (ONE_WIRE) PB12 PB14 PA4 R132 R134 R138 R140 0R 0R 0R 0R PA22 (SPI1_MOSI) (SPI1_NPCS1) PA0 (LCD_DETECT) PB1 DAT2(RSV) +5V_LCD SD CARD J10 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 SD CARD MN16 MAX3232CSE VDDIOP0 C 16 2 C92 100nF R135 100K PA10 PA9 6 V+ C1- V- C2+ 4 J11 1 6 2 7 3 8 4 9 5 C94 100nF 15 11 12 10 9 (DTXD) (DRXD) GND 5 C2- T1IN R1OUT T2IN R2OUT R114 R111 R112 R113 22R 22R 22R 22R PC24 PC27 PC29 (LCDDISP) (LCDVSYNC) (LCDDEN) R119 R121 R124 22R 22R 22R PB11 PB13 PB15 (AD0_XP) (AD2_YP) (AD4_LR) R126 R128 R130 0R 0R 0R PA21 PA23 PB9 PB0 (SPI1_MISO) (SPI1_SPCK) R131 R133 R137 R139 0R 0R 0R 0R R141 10K 3 C93 100nF R136 100K (LCDDAT16) (LCDDAT18) (LCDDAT20) (LCDDAT22) 1 C1+ C91 100nF C90 100nF VDDIOP0 VCC PC16 PC18 PC20 PC22 14 13 7 8 T1OUT R1IN T2OUT R2IN VDDANA ESQ-120-33-L-D 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PB[0..18] (3,5,8) LCD_DET PC[0..31] (3,5) PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 B J12 PA5 PA3 PA8 PA21 ZB_RSTN R142 ZB_IRQ1 R144 (SPI1_NPCS0) R146 (SPI1_MISO) R148 1 3 5 7 9 0R 0R 0R 0R PB2 2 4 6 8 10 C PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 11 10 (3) UART D ZB_IRQ0 0R ZB_SLPTR 0R 0R (SPI1_MOSI) 0R (SPI1_SPCK) R143 R145 R147 R149 C95 18pF C96 2.2nF PA2 PA6 PA22 PA23 NRST L13 220ohm at 100MHz 1 2 1 2 3 4 NRST (3,9) WKUP (3) +3V3 PB3 C97 2.2uF WAKE UP 1 2 R150 3 4 100K VDDBU PB4 PB_USER ZIGBEE 1 2 3 4 PB3 B VDDANA A 3 A VR1 10K R151 0R (Analog input) PB17 C98 10nF 1 2 C NOR NRST EBI B A INIT EDIT REV SAM9N12-EK_RevC BGA217 SERIAL INTERFACES MODIF. SCALE PP 25-NOV-11 PP 25-SEPT-11 PP 20-AUG-11 DES. DATE 1/1 XXX XX-XXX-XX XXX XX-XXX-XX XXX XX-XXX-XX VER. DATE REV. SHEET C 7 9 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 7 6 5 4 3 2 1 5 4 3 2 1 L14 (3,5,7) PB[0..18] AUD_1V8 PB10 AVDD1V8 1 D (5,7) PA[0..31] PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 AUD_1V8 + C100 10uF C99 100nF C101 100nF 220ohm at 100MHz 2 D R192 0R R193 0R 2 3 AGND_AUDIO J13 4 +3V3 C106 10uF C107 100nF C108 4.7uF C102 100nF C103 100nF R154 20R R155 20R R152 3.9K R153 3.9K C104 220pF C105 220pF 1 5 HEADPHONE AGND_AUDIO PB10 (PCK0) R158 22R PA24 PA28 PA25 PA29 PA26 PA27 (TK) (RK) (TF) (RF) (TD) (RD) R159 R160 R161 R162 0R 0R 0R 0R R163 0R 29 AVDD 21 AGND_AUDIO HPOUTL HPOUTR HPOUTFB MCLK 13 15 14 BCLK/GPIO4 30 32 31 LRCLK DACDAT ADCDAT 1 LINEOUTL LINEOUTR GPIO1/IRQ LINEOUTFB AVDD1V8 16 C 18 MIC1 17 1 2 AGND_AUDIO WM8904 7 CPVDD 8 C142 1uF CPCA C114 2.2uF IN1L/DMICDAT1 IN1R/DMICDAT2 10 L19 1 MICBIAS IN2R 19 R168 2.2K C117 100nF 220ohm at 100MHz 2 +3V3 C118 4.7uF 20 5 AGND_AUDIO 24 DGND CPGND MICVDD AGND 9 AVDD GND_PADDLE CPVOUTP CPVOUTN 22 11 12 33 AGND_AUDIO C116 2.2uF 27 25 CPCB IN2L C113 2.2uF C115 2.2uF VMIDC 6 4 SCLK SDA 28 DCVDD 2 3 26 C (TWCK0) (TWD0) DBVDD MN17 PA31 PA30 23 AGND_AUDIO R191 0R AGND_AUDIO AGND_AUDIO B AGND_AUDIO C120 1uF L15 10uH/150mA +1V8 B C119 4.7uF C121 1uF AGND_AUDIO R194 0R R195 0R 2 3 AUD_1V8 J15 4 R157 R173 DNP 1R R174 DNP C124 220pF C125 220pF 1 5 LINE IN C109 4.7uF AGND_AUDIO A A C NOR NRST EBI B A INIT EDIT REV SAM9N12-EK_RevC BGA217 AUDIO MODIF. SCALE PP 25-NOV-11 PP 25-SEPT-11 PP 20-AUG-11 DES. 1/1 DATE XXX XX-XXX-XX XXX XX-XXX-XX XXX XX-XXX-XX VER. DATE REV. SHEET C 8 9 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 5 4 3 2 1 L22 +1V8 D 1 C126 10uF C127 100nF C128 100nF C129 100nF A1V8 220ohm at 100MHz 2 C130 100nF C131 100nF D C132 4.7uF GND_ETH GND_ETH L23 A3V3 1 C133 100nF A1V8 +3V3 220ohm at 100MHz 2 C134 10uF +1V8 +1V8 R180 DNP R181 47K R182 47K (4) A1 (4,5) (4,6) (4,6) (4,5) PD19 NWRE NRD PD21 (4,5) PD20 12 6 5 4 R187 3 22R 21 J16 J00-0061 1 TD+ TXP1 TXM1 RXP1 RXM1 3 A GND Y 1 TX- 2 3 RD+ 17 5 CT R176 R177 EECS EESK EED_IO 49.9R 1% R183 DNP 15 10 9 R178 49.9R 1% 49.9R 1% P1LED0 P1LED1 ISET C135 10uF 75 6 75 4 5 75 8 GND_ETH GND_ETH 2 1 7 8 +3V3 P1LED0 P1LED1 22 R185 75 1nF GND_ETH R197 4.7K CSN WRN RDN INTRN RX- R179 7 NC R196 1K 3 C137 100nF C136 100nF +1V8 CMD RX+ P1LED0 P1LED1 3.01K 1% 9 R184 470R 10 11 R186 470R 12 PME 24 Y3 AGND AGND DGND DGND DGND DGND RSTN X2 25 C139 22pF 4 1 3 2 25MHz B C140 22pF 13 18 NRST R188 4.7K 23 16 49.9R 1% 7 26 28 37 (3,7) 2 C138 100nF +1V8 2 TD- 6 RD- X1 +3V3 4 CT 20 +1V8 B MN20 SN74LVC1G07 1 5 N.C. VCC 19 TX+ C KSZ8851-16MLL 11 VDD_A3.3 14 29 27 38 46 VDD_IO VDD_IO VDD_IO SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 A3V3 13 14 C 48 47 45 44 43 42 41 40 39 36 35 34 33 32 31 30 VDD_A1.8 ETH_D0 ETH_D1 ETH_D2 ETH_D3 ETH_D4 ETH_D5 ETH_D6 ETH_D7 ETH_D8 ETH_D9 ETH_D10 ETH_D11 ETH_D12 ETH_D13 ETH_D14 ETH_D15 VDD_D1.8 MN19 VDD_CO1.8 (4) ETH_D[0..15] 8 GND_ETH GND_ETH 4 GND_ETH (6) NOR_NRST +1V8 + C141 10uF R189 0R R190 0R A A GND_ETH C NOR NRST EBI B A INIT EDIT REV SAM9N12-EK_RevC BGA217 ETH MODIF. SCALE PP 25-NOV-11 PP 25-SEPT-11 PP 20-AUG-11 DES. 1/1 DATE XXX XX-XXX-XX XXX XX-XXX-XX XXX XX-XXX-XX VER. DATE REV. SHEET C 9 9 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 5.2 SAM9CN11-EK Schematics This section contains the following schematics: Block Diagram Power Supply AT91SAM9CN11 EBI Interface PIO Interfaces DDR2 NAND Flash Serial Interfaces Audio ETH 5-2 11186A–ATARM–29-Nov-12 SAM9N12/CN11-EK User Guide 7 5 4 3 2 1 3V3 POWER SUPPLY EBI DDR2 INTERFACE POWER USER INTERFACE 1V8 EBI DATA INTERFACE EBI FLASH INTERFACE Sheet 2,5,7 Sheet 6 ATMEL ARM9 Processor SAM9CN11 (LFBGA217) ICE INTERFACE PIO A,...E Sheet 3 EBI BUS INTERFACE EBI ETH INTERFACE RS232 C (RJ 45) PIO 10/100 FAST ETHERNET HOST DEVICE HE 10 EBI NANDFLASH INTERFACE EBI ADDRESS INTERFACE EBI USB HOST NAND FLASH RES.ARRAYS EBI ADAPTER FLASH D 1V PIO EBI D 6 DDR2 128MB 5V 8 C DBGU Sheet 9 Sheet 4 4.3" 480x272 TFT HE 14 LCD INTERFACE PIO A,...D PIO CONNECTOR TOUCH SCREEN 1-WRIE EEPROM MIC PIO TWI0 HE 14 ISI CAMERA INTERFACE Sheet 3,4,5 B LINEOUT HE 14 ZIGBEE INTERFACE AUDIO SPI0 MMC SD SDIO HPOUT SERIAL EEPROM B SERIAL DATA FLASH Sheet 8 CARD READER Sheet 5 Sheet 7 PIO MUXING PIOA A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 USAGE TXD0 RXD0 ZB_IRQ0 ZB_IRQ1 One Wire ZB_RSTN ZB_SLPTR MCI card detect SPI1_NPCS0 DRXD DTXD SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 MCI_DA0 PIOA PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 USAGE MCI_CDA MCI_CK MCI_DA1 MCI_DA2 MCI_DA3 SPI1_MISO SPI1_MOSI SPI1_SPCK TK TF TD RD RK RF TWD0 TWCKO PIOB USAGE PIOB PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 --ROM CODE PB_USER1 USER_LED1 USER_LED2 PWR_LE EN5V_HOST OVCUR_USB -PCK0 AD0 AD1 AD2 AD3 AD4 PB16 PB17 PB18 USAGE VBUS_SENSE AD6 ADTRG PIOC PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 USAGE LCDDAT0 LCDDAT1 LCDDAT2 LCDDAT3 LCDDAT4 LCDDAT5 LCDDAT6 LCDDAT7 LCDDAT8 LCDDAT9 LCDDAT10 LCDDAT11 LCDDAT12 LCDDAT13 LCDDAT14 LCDDAT15 PIOC PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 USAGE LCDDAT16 LCDDAT17 LCDDAT18 LCDDAT19 LCDDAT20 LCDDAT21 LCDDAT22 LCDDAT23 LCDDISP EN5V_LCD LCDPWM LCDVSYNC LCDHSYNC LCDDEN LCDPCK OVCUR_LCD PIOD PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PIOD NANDOE NANDWE NANDALE/A21 NANDCLE NANDCS NWAIT D16 D17 D18 D19 D20 D21 D22 D23 D24 A20 PD16 PD17 PD18 PD19 PD20 PD21 NOTE D26 D27 D28 NCS2 D30 D31 "DNP" means the component is not populated by default A A REV SAM9CN11-EK INIT EDIT MODIF. SCALE PP DES. 05-APR-12 PP DATE 1/1 Block Diagram This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 7 6 5 4 3 2 1 05-APR-12 VER. DATE REV. SHEET A 1 9 8 7 6 5 4 3 2 1 D D TP1 MN1 RT9018A +5V FORCE POWER ON 3 4 JP1 +5V 1 + C1 10uF 2 C2 1uF 5 VIN VDD VOUT 6 EN C7 15pF (3) SHDN 1 PGOOD ADJ C3 100nF R2 47K 1 + C4 10uF 2 5 3 4 R5 10K VDDIOP0 220ohm at 100MHz 2 TP3 L2 C5 1uF 1 7 VDDIOP1 220ohm at 100MHz 2 TP4 L3 8 9 1 2 GND GND Q1 R4 100K 6 R1 100K NC L1 TP2 +3V3 1 R3 15K VDDANA 220ohm at 100MHz 2 TP5 +5V TP9 PWR_EN R6 10K C MN2 LP38692MP-1.8 +5V 4 VOUT L4 TP6 +1V8 3 1 VDDIOM 220ohm at 100MHz 2 L5 1 VEN NC C9 10uF 2 1 TP7 VDDNF 220ohm at 100MHz 2 TP8 5 C8 4.7uF VIN GND C USB_+5V B B TP10 SW1 SW-SLIDE-3 +5V J1 Jack 2.1mm F1 SF1812_2A 1 +3V3 1 2 DC_+5V 2 3 CR1 5V C10 10uF + C6 33uF C147 22pF ADP1715ARMZ EN OUT IN C143 10nf ADJ +1V 3 ADP1715 5 6 7 8 3 1 2 MN3 GND GND GND GND REGULATED 5V ONLY R10 12K 1% C11 10uF C144 100nF 4 R13 47K 1% VOUT = 0.8V x (Rtop + Rbottom)/Rbottom A A A REV SAM9CN11-EK INIT EDIT MODIF. SCALE PP DES. 05-APR-12 PP DATE 1/1 POWER SUPPLY This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 7 6 5 4 3 2 1 05-APR-12 VER. DATE REV. SHEET A 2 9 8 7 6 5 4 +3V3 C14 100nF L6 +5V_LCD +5V 220ohm at 100MHz 1 2 TP12 8 OUTA 7 C17 100nF L7 6 220ohm at 100MHz 1 2 TP14 B MN6 + C15 33uF D R15 5 ENA IN FLGA GNG FLGB OUTB ENB 1 R16 0R 2 R17 0R PC31 3 R18 0R PB8 4 R19 0R PB7 47K MN5 SN74LVC1G32 5 1 VCC A 4 Y GND 2 3 2 1 +3V3 LCD_DET (7) PC25 VDDBU 3 D1 BAT54C JP2 +3V3 BT1 1 3 TP13 2 C16 100nF C18 2.2uF D SP2526A-2 MN7A SAM9CN11_LBGA217 - POWER +1V J2 USB-AF-4 3 USB_A 6 1 5 D2 TVS R20 27R N17 R21 27R P17 HDM HDP VDDIOM VDDIOM VDDIOM D3 TVS VDDNF VDDNF VDDNF USB_+5V RV1 47K PB16 C32 10pF VDDIOP1 VDDIOP1 R23 68K VDDIOP0 VDDIOP0 J3 9 6 1 2 3 4 5 R26 47K C26 100nF C21 100nF H10 H9 H8 C24 100nF D4 TVS 27R 27R R16 R17 D5 TVS VDDIOM C27 100nF VDDNF C28 100nF L4 L3 C33 100nF C35 100nF D6 TVS VDDPLL GNDPLL VDDANA GNDANA U17 3 20pF 4 C45 1R U16 XOUT +3V3 1 A4 Y2 32.768 kHz A3 R15 T17 VDDOSC 1 0R R33 0R (7,9) 2 SD1 DNP R31 WKUP (2) SHDN B4 T15 R11 T13 R12 T14 U14 R13 NRST (7) +3V3 C46 100nF R14 C48 100nF XOUT32 B C49 100nF R29 1R C51 4.7uF VDDBU R30 L10 10uH/150mA VDDOSC XIN32 8 7 6 5 15pF 2 1 2 3 4 RR1D RR1C RR1B RR1A C50 15pF C43 100nF R28 C44 4.7uF VDDUSB GNDUSB C47 VDDANA C40 4.7uF C42 100nF XIN C39 100nF 1R C4 B2 2 1 20pF +1V R27 1 1 1 VDDIOP0 1 3 5 7 9 11 13 15 17 19 L8 10uH/150mA C38 100nF Y1 16MHz J4 C36 100nF T16 P14 L9 10uH/150mA C41 2 4 6 8 10 12 14 16 18 20 C VDDPLL +3V3 VDDIOP0 C30 100nF VDDIOP0 DDM DDP V5.5MLA0603 R35 100K C29 100nF C34 100nF P12 P9 RV2 B C19 100nF L14 K14 J14 2 2 R24 R25 2 SHD VBUS DM DP ID GND C23 100nF A5 B5 JTAGSEL NTRST TDI TMS TCK RTCK TDO L11 10uH/150mA VDDFUSE VDDFUSE GNDFUSE +3V3 VDDANA N16 M16 C52 100nF C53 100nF R32 1R R34 4.7K C54 4.7uF NRST +5V JP3 2 3 C31 100nF C USB Micro B C22 100nF VDDIOP1 R22 + C37 10uF V5.5MLA0603 7 8 P10 J4 G15 C8 1 4 2 C25 100nF 2 + C20 33uF 2 1 1 VDDCORE VDDCORE VDDCORE VDDCORE TP15 TP16 WKUP D7 SHDN ADVREF A2 C55 2.2uF LM4040-3V (5,7) PC[0..31] A R36 10K PC25 N15 U15 NC BMS PB[0..18] P13 P7 P6 K10 K9 J10 J9 J8 P11 K8 H14 D8 PC31 (5,7,8) C56 100nF VDDBU GNDIOP GNDIOP GNDIOP GNDIOM GNDIOM GNDIOM GNDIOM GNDIOM GNDCORE GNDCORE GNDCORE GNDCORE VDDIOP0 JP4 VDDBU GNDBU GNDBU D6 D5 B3 C57 100nF A AT91SAM9CN11-CU PB7 A PB8 REV SAM9CN11-EK PB16 INIT EDIT MODIF. SCALE PP DES. 05-APR-12 PP DATE 1/1 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 7 6 5 4 3 2 DATE REV. SHEET A AT91SAM9CN11 1 05-APR-12 VER. 3 9 5 4 3 2 1 EBI_D[0..15] MN7F SAM9CN11_LBGA217 - EBI D C D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0/NBS0 A1/NBS2/DQM2/NWR2 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16/BA0 A17/BA1 A18/BA2 A19 DQM0 DQM1 DQS0 DQS1 RAS CAS SDWE SDCKE SDA10 SDCK SDCKN NCS0 NCS1/SDCS NWR0/NWRE NWR1/NBS1 NWR3/NBS3/DQM3 NRD B B14 A14 C14 D13 C13 B13 A13 C12 D12 B12 C11 D11 A12 B11 A11 C10 EBI_D0 EBI_D1 EBI_D2 EBI_D3 EBI_D4 EBI_D5 EBI_D6 EBI_D7 EBI_D8 EBI_D9 EBI_D10 EBI_D11 EBI_D12 EBI_D13 EBI_D14 EBI_D15 D17 C17 F16 B17 A17 F15 E16 D16 E15 G14 C16 F14 B16 A16 C15 D15 B15 E14 A15 D14 EBI_A1 EBI_A2 EBI_A3 EBI_A4 EBI_A5 EBI_A6 EBI_A7 EBI_A8 EBI_A9 EBI_A10 EBI_A11 EBI_A12 EBI_A13 EBI_A14 EBI_A15 EBI_A16 EBI_A17 EBI_A18 EBI_A19 C9 A8 B8 A7 EBI_DQM0 EBI_DQM1 EBI_DQS0 EBI_DQS1 B9 D9 EBI_RAS EBI_CAS B10 D10 B6 A10 A9 EBI_SDWE EBI_SDCKE EBI_SDA10 EBI_SDCK EBI_NSDCK B7 C5 NCS0 EBI_NCS1_SDCS A6 C6 D7 NWRE C7 NRD DDR2_D[0..15] A1 (9) 2 3 4 1 4 2 1 3 1 2 3 4 1 2 4 3 RR2B RR2C RR2D RR2A RR3D RR3B RR3A RR3C RR4A RR4B RR4C RR4D RR5A RR5B RR5D RR5C 7 6 5 8 5 7 8 6 8 7 6 5 8 7 5 6 DDR2_D0 DDR2_D1 DDR2_D2 DDR2_D3 DDR2_D4 DDR2_D5 DDR2_D6 DDR2_D7 DDR2_D8 DDR2_D9 DDR2_D10 DDR2_D11 DDR2_D12 DDR2_D13 DDR2_D14 DDR2_D15 EBI_D0 EBI_D1 EBI_D2 EBI_D3 EBI_D4 EBI_D5 EBI_D6 EBI_D7 EBI_D8 EBI_D9 EBI_D10 EBI_D11 EBI_D12 EBI_D13 EBI_D14 EBI_D15 4 3 2 1 1 2 3 4 1 2 3 4 1 2 3 4 RR6D RR6C RR6B RR6A RR7A RR7B RR7C RR7D RR8A RR8B RR8C RR8D RR9A RR9B RR9C RR9D 5 6 7 8 8 7 6 5 8 7 6 5 8 7 6 5 FLASH_D0 FLASH_D1 FLASH_D2 FLASH_D3 FLASH_D4 FLASH_D5 FLASH_D6 FLASH_D7 FLASH_D8 FLASH_D9 FLASH_D10 FLASH_D11 FLASH_D12 FLASH_D13 FLASH_D14 FLASH_D15 EBI_D0 EBI_D1 EBI_D2 EBI_D3 EBI_D4 EBI_D5 EBI_D6 EBI_D7 EBI_D8 EBI_D9 EBI_D10 EBI_D11 EBI_D12 EBI_D13 EBI_D14 EBI_D15 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 RR10A RR10B RR10C RR10D RR11A RR11B RR11C RR11D RR12A RR12B RR12C RR12D RR13A RR13B RR13C RR13D 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 ETH_D0 ETH_D1 ETH_D2 ETH_D3 ETH_D4 ETH_D5 ETH_D6 ETH_D7 ETH_D8 ETH_D9 ETH_D10 ETH_D11 ETH_D12 ETH_D13 ETH_D14 ETH_D15 (6) NWRE (6,9) NRD (6,9) EBI_D0 EBI_D1 EBI_D2 EBI_D3 EBI_D4 EBI_D5 EBI_D6 EBI_D7 1 2 3 4 4 3 2 1 RR14A RR14B RR14C RR14D RR15D RR15C RR15B RR15A 8 7 6 5 5 6 7 8 NAND_FSH_D0 NAND_FSH_D1 NAND_FSH_D2 NAND_FSH_D3 NAND_FSH_D4 NAND_FSH_D5 NAND_FSH_D6 NAND_FSH_D7 4 3 2 1 3 4 2 1 1 2 3 4 1 2 3 4 R164 RR16D 5 RR16C 6 RR16B 7 RR16A 8 RR17C 6 RR17D 5 RR17B 7 RR17A 8 RR18A 8 RR18B 7 RR18C 6 RR18D 5 RR19A 8 RR19B 7 RR19C 6 RR19D 5 10R (6) D DDR2_A2 DDR2_A3 DDR2_A4 DDR2_A5 DDR2_A6 DDR2_A7 DDR2_A8 DDR2_A9 DDR2_A10 DDR2_A11 DDR2_A12 DDR2_A13 DDR2_A14 DDR2_A15 DDR2_A16 DDR2_A17 DDR2_A18 (6) C ETH_D[0..15] NCS0 DDR2_A[2..18] EBI_A2 EBI_A3 EBI_A4 EBI_A5 EBI_A6 EBI_A7 EBI_A8 EBI_A9 EBI_A10 EBI_A11 EBI_SDA10 EBI_A13 EBI_A14 EBI_A15 EBI_A16 EBI_A17 EBI_A18 FLASH_D[0..15] EBI_A1 EBI_A2 EBI_A3 EBI_A4 EBI_A5 EBI_A6 EBI_A7 EBI_A8 EBI_A9 EBI_A10 EBI_A11 EBI_A12 EBI_A13 EBI_A14 EBI_A15 EBI_A16 EBI_A17 EBI_A18 EBI_A19 PD15 PD2 PD3 PD16 (9) 1 2 3 4 3 4 2 1 1 3 2 4 1 4 2 3 1 2 3 4 1 3 2 4 RR20A RR20B RR20C RR20D RR21C RR21D RR21B RR21A RR22A RR22C RR22B RR22D RR23A RR23D RR23B RR23C RR24A RR24B RR24C RR24D RR25A RR25C RR25B RR25D 8 7 6 5 6 5 7 8 8 6 7 5 8 5 7 6 8 7 6 5 8 6 7 5 FLASH_A[1..23] (6) FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 AT91SAM9CN11-CU NAND_FSH_D[0..7] MN7E SAM9CN11_LBGA217 - PIOD A EBI_D0 EBI_D1 EBI_D2 EBI_D3 EBI_D4 EBI_D5 EBI_D6 EBI_D7 EBI_D8 EBI_D9 EBI_D10 EBI_D11 EBI_D12 EBI_D13 EBI_D14 EBI_D15 (6) PD0/NANDOE PD1/NANDWE PD2/A21/NANDALE PD3/A22/NANDCLE PD4/NCS3 PD5/NWAIT PD6/D16 PD7/D17 PD8/D18 PD9/D19 PD10/D20 PD11/D21 PD12/D22 PD13/D23 PD14/D24 PD15/D25/A20 PD16/D26/A23 PD17/D27/A24 PD18/D28/A25 PD19/D29/NCS2 PD20/D30/NCS4 PD21/D31/NCS5 P15 N14 M15 M14 P16 M17 L15 L16 L17 K17 K16 K15 J17 J16 H17 J15 G17 H16 H15 F17 G16 E17 PD0 PD1 PD2 PD3 PD4 PD5 PD15 PD16 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 (5) (5) (5) (5) (5) (5) (5) (5) (5) PD17 PD18 PD19 PD20 PD21 (5) (5) (5,9) (5,9) (5,9) PD0 PD1 PD2 PD3 PD4 PD5 (NANDOE) (NANDWE) (NANDALE) (NANDCLE) (NANDCS) (NANDR/B) R48 R49 R50 R51 R52 R53 0R 0R 0R 0R 0R 0R NANDOE NANDWE NANDALE NANDCLE NANDCS NANDR_B (6) (6) (6) (6) (6) (6) B (6) EBI_DQM0 EBI_DQM1 EBI_DQS0 EBI_DQS1 R37 R38 R39 R40 10R 10R 10R 10R DDR2_DQM0 DDR2_DQM1 DDR2_DQS0 DDR2_DQS1 EBI_RAS EBI_CAS R41 R42 10R 10R DDR2_RAS (6) DDR2_CAS (6) EBI_SDWE EBI_SDCKE R43 R44 10R 10R DDR2_SDWE (6) DDR2_SDCKE (6) EBI_SDCK EBI_NSDCK R45 R46 10R 10R DDR2_SDCK (6) DDR2_NSDCK (6) EBI_NCS1_SDCS R47 10R DDR2_NCS1 (6) (6) (6) (6) (6) A AT91SAM9CN11-CU A REV SAM9CN11-EK INIT EDIT MODIF. SCALE PP DES. 05-APR-12 PP DATE 1/1 EBI_INTERFACE This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 05-APR-12 VER. DATE REV. SHEET A 4 9 5 4 3 2 1 JP5 +5V PA0/TXD0/SPI1_NPCS1 PA1/RXD0/SPI0_NPCS2 PA2/RTS0 PA3/CTS0 PA4/SCK0 PA5/TXD1 PA6/RXD1 PA7/TXD2/SPI0_NPCS1 PA8/RXD2/SPI1_NPCS0 PA9/DRXD PA10/DTXD PA11/SPI0_MISO/MCI_DA4 PA12/SPI0_MOSI/MCI_DA5 PA13/SPI0_SPCK/MCI_DA6 PA14/SPI0_NPCS0/MCI_DA7 PA15/MCI_DA0 PA16/MCI_CDA PA17/MCI_CK PA18/MCI_DA1 PA19/MCI_DA2 PA20/MCI_DA3 PA21/TIOA0/SPI1_MISO PA22/TIOA1/SPI1_MOSI PA23/TIOA2/SPI1_SPCK PA24/TCLK0/TK PA25/TCLK1/TF PA26/TCLK2/TD PA27/TIOB0/RD PA28/TIOB1/RK PA29/TIOB2/RF PA30/TWD0/SPI1_NPCS3 PA31/TWCK0/SPI1_NPCS2 D 1 T3 U2 U3 P4 T4 U4 P5 R4 U6 R5 R6 T5 T6 U5 U7 T7 R7 U8 P8 T8 R8 U9 U10 T9 U11 T10 R9 U12 T11 U13 R10 T12 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 +3V3 3 2 PA[0..31] (7,8) MN7B SAM9CN11_LBGA217 - PIOA MN8 NL17SZ126 1 (6) OE_Dataflash 2 PA14 3 OE VCC IN OUT GND J5 VDDIOP0 5 4 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 C58 100nF VDDIOP0 R55 470K PA12 PA11 PA13 (SPI0_MOSI) R56 (SPI0_MIS0) R57 (SPI0_SPCK) R58 MN9 AT25DF321A 5 2 6 0R 0R 0R SI SO SCK 1 (SPI0_NPCS0) VDDIOP0 8 VCC 3 7 WP HOLD CS C59 100nF +3V3 4 GND SERIAL DATAFLASH 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 JP6 1 +3V3 +3V3 3 VDDIOP0 2 VDDIOP0 D TP11 +5V VDDIOP0 AT91SAM9CN11-CU PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 C R59 4.7K R60 4.7K PB[0..18] (3,7,8) SAM9CN11_LBGA217 - PIOB PA31 PA30 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 (TWCKO) (TWDO) VDDIOP0 VDDANA C60 100nF 4 GND +3V3 R64 1.5K 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PB16 PB17 PB18 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD17 PD18 PD19 PD20 PD21 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD17 PD18 PD19 PD20 PD21 2 0R IO NC1 NC2 NC3 NC4 JP8 +5V 3 4 5 6 1 PB18 R78 DNP PC28 1 SAM9CN11_LBGA217 - PIOC PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 +3V3 VDDANA PB4 PB5 +3V3 3 B J7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 1-WIRE EEPROM R66 470R D8 Blue R67 470R D9 Green +3V3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 +3V3 R68 100K PB6 A 1 2 3 R69 470R D10 Red Q2 IRLML2502 AT91SAM9CN11-CU A REV LED SAM9CN11-EK INIT EDIT MODIF. SCALE PP DES. 05-APR-12 PP DATE 1/1 PIO_INTERFACES This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4) (4,9) (4,9) (4,9) 2 R65 MN11 DS2431P+ PC[0..31] (3,7) A 7 WP 2 PA4 G2 G1 H4 J1 H3 J3 H2 H1 K2 J2 L1 K1 L2 K3 M1 M2 K4 M3 N1 N2 N3 P1 P2 P3 R1 R3 R2 T1 M4 N4 T2 U1 R62 DNP VDDIOP0 B PC0/LCDDAT0//TWD1 PC1/LCDDAT1//TWCK1 PC2/LCDDAT2//TIOA3 PC3/LCDDAT3//TIOB3 PC4/LCDDAT4//TCLK3 PC5/LCDDAT5//TIOA4 PC6/LCDDAT6//TIOB4 PC7/LCDDAT7//TCLK4 PC8/LCDDAT8//UTXD0 PC9/LCDDAT9//URXD0 PC10/LCDDAT10//PWM0 PC11/LCDDAT11//PWM1 PC12/LCDDAT12//TIOA5 PC13/LCDDAT13//TIOB5 PC14/LCDDAT14//TCLK5 PC15/LCDDAT15//PCK0 PC16/LCDDAT16//UTXD1 PC17/LCDDAT17//URXD1 PC18/LCDDAT18//PWM0 PC19/LCDDAT19//PWM1 PC20/LCDDAT20//PWM2 PC21/LCDDAT21//PWM3 PC22/LCDDAT22/TXD3 PC23/LCDDAT23/RXD3 PC24/LCDDISP/RTS3 PC25//CTS3 PC26/LCDPWM/SCK3 PC27/LCDVSYNC//RTS1 PC28/LCDHSYNC//CTS1 PC29/LCDDEN//SCK1 PC30/LCDPCK PC31/FIQ//PCK1 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 SERIAL EEPROM JP7 PB2 AT91SAM9CN11-CU MN7D J6 R63 10K 1 E4 F3 F4 F2 G4 G3 D2 E2 D1 F1 E1 A1 C3 B1 C2 D3 C1 E3 D4 C R61 10K 3 PB0/RTS2 PB1/CTS2 PB2/SCK2 PB3/SPI0_NPCS3 PB4 PB5 PB6/AD7 PB7/AD8 PB8/AD9 PB9/AD10/PCK1 PB10/AD11/PCK0 PB11/AD0/PWM0 PB12/AD1/PWM1 PB13/AD2/PWM2 PB14/AD3/PWM3 PB15/AD4 PB16/AD5 PB17/AD6 PB18/IRQ/ADTRG GND MN7C MN10 AT24C512C-SSHD-T 6 1 A0 2 5 SCL SDA A1 3 A3 8 VCC 4 3 2 1 05-APR-12 VER. DATE REV. SHEET A 5 9 5 4 3 2 1 (4) FLASH_D[0..15] (4) FLASH_A[1..23] MN13 (4) DDR2_D[0..15] (4) DDR2_A[2..18] MN12 D DDR2_A2 DDR2_A3 DDR2_A4 DDR2_A5 DDR2_A6 DDR2_A7 DDR2_A8 DDR2_A9 DDR2_A10 DDR2_A11 DDR2_A12 DDR2_A13 DDR2_A14 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 DDR2_A16 DDR2_A17 DDR2_A18 DDR2_A15 L2 L3 L1 A0 DQ0 DDR2 SDRAM A1 DQ1 A2 MT47H64M16HR DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 A12 DQ12 DQ13 BA0 DQ14 BA1 DQ15 BA2 K9 K2 (4) DDR2_SDCKE CK CK L8 (4) DDR2_NCS1 CAS RAS K3 (4) DDR2_SDWE (4) DDR2_DQS1 B7 A8 (4) DDR2_DQS0 F7 E8 WE UDQS UDQS DDR2_A15 VREF VSS VSS VSS VSS VSS LDQS LDQS B3 F3 (4) DDR2_DQM1 (4) DDR2_DQM0 VDDL VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ CS L7 K7 (4) DDR2_CAS (4) DDR2_RAS VDD VDD VDD VDD VDD CKE J8 K8 (4) DDR2_SDCK (4) DDR2_NSDCK C ODT UDM LDM A2 E2 R3 R7 R8 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL RFU1 RFU2 RFU3 RFU4 RFU5 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 DDR2_D0 DDR2_D1 DDR2_D2 DDR2_D3 DDR2_D4 DDR2_D5 DDR2_D6 DDR2_D7 DDR2_D8 DDR2_D9 DDR2_D10 DDR2_D11 DDR2_D12 DDR2_D13 DDR2_D14 DDR2_D15 +1V8 A1 E1 J9 M9 R1 C61 C62 C63 C64 C65 J1 A3 E3 J3 N1 P9 +1V8 (9) NOR_NRST 29 25 24 23 22 21 20 19 8 7 6 5 4 3 2 1 55 18 17 16 11 10 9 R70 0R 45 R71 100K 44 R72 100K 15 C67 C70 C71 C72 C73 C74 C75 C76 C77 C78 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF (4,9) (4,9) 30 32 14 NRD NWRE R73 NCS0 (4) PD6 NANDR_B NANDCLE NANDALE NANDOE NANDWE VDDNF R74 470K VDDNF R75 R76 470K 470K R77 DNP 1 2 NANDCS VDDIOP0 OE VCC IN OUT GND +1V8 5 4 C82 100nF +1V8 R80 1.5K 1% R54 10K R156 10K OE_Nandflash CE# OE# WE# +1V8 VCC VCCQ VSS VSS VSS 33 38 C68 100nF 12 28 31 C69 100nF C VPP RB C8 WP C3 A1 A2 A9 A10 B1 B9 B10 D6 D7 D8 E3 E4 E5 E6 E7 E8 F3 F4 F5 F6 F8 G3 G8 L1 L2 CLE I/O0 ALE NAND FLASH I/O1 RE MT29F2G08ABD I/O2 WE I/O3 CE I/O4 I/O5 R/B I/O6 I/O7 WP N.C26 N.C27 LOCK N.C28 N.C29 N.C30 N.C1 N.C31 N.C2 N.C32 N.C3 N.C33 N.C4 N.C5 N.C6 N.C34 N.C7 N.C35 N.C8 N.C36 N.C9 N.C37 N.C10 N.C38 N.C11 N.C39 N.C12 N.C13 N.C14 VCC N.C15 VCC N.C16 VCC N.C17 VCC N.C18 N.C19 N.C20 N.C21 VSS N.C22 VSS N.C23 VSS N.C24 VSS N.C25 VFBGA-63 MT29F2G08ABDHC:D H4 J4 K4 K5 K6 J7 K7 J8 H3 J3 H5 J5 H6 G6 H7 G7 NAND_FSH_D0 NAND_FSH_D1 NAND_FSH_D2 NAND_FSH_D3 NAND_FSH_D4 NAND_FSH_D5 NAND_FSH_D6 NAND_FSH_D7 B L9 L10 M1 M2 M9 M10 VDDNF D3 G4 H8 J6 C80 C81 C83 C85 100nF 100nF 100nF 100nF C5 F7 K3 K8 NAND FLASH 2 OE_Dataflash 1 (5) CE D5 C4 D4 C7 C6 G5 MN15 NL17SZ126 R81 1.5K 1% 26 27 13 MN14 3 C88 100nF 46 NOR FLASH (DNP) (4) (4) (4) (4) A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7 (4) C87 4.7uF 56 RST# WP# D (4) NAND_FSH_D[0..7] C79 100nF OE_Nandflash TP17 Test Point RFU1 RFU2 NC FLASH_D0 FLASH_D1 FLASH_D2 FLASH_D3 FLASH_D4 FLASH_D5 FLASH_D6 FLASH_D7 FLASH_D8 FLASH_D9 FLASH_D10 FLASH_D11 FLASH_D12 FLASH_D13 FLASH_D14 FLASH_D15 DDR_VREF L12 10uH/150mA 150mA DDR_VREF WAIT ADV# 34 36 39 41 47 49 51 53 35 37 40 42 48 50 52 54 JS28F128P30TF75A 470K +1V8 C86 100nF CLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 JP9 (4) DDR2 SDRAM R79 1R 43 1V8 B C84 4.7uF A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 C66 100nF A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J2 100nF 100nF 100nF 100nF 100nF FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 D11 BAT54C A 3 A PB1 3 4 1 2 A REV SAM9CN11-EK INIT EDIT MODIF. SCALE PP DES. 05-APR-12 PP DATE 1/1 DDR2 NAND FLASH This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 05-APR-12 VER. DATE REV. SHEET A 6 9 8 7 6 5 4 3 2 1 PA[0..31] (5,8) VDDIOP0 +3V3 JP10 R82 10K D R83 10K R84 68K R85 68K R86 68K R87 68K R88 68K J8 SD-P09KC-M1 Up-Touch Connector 10 (MCI card detect) PA7 11 PA18 PA15 (MCI_DA1) (MCI_DA0) 1 RR26A 2 RR26B PA17 (MCI_CK) R106 PA16 PA20 (MCI_CDA) (MCI_DA3) R110 3 RR26C 27R 6 8 7 6 5 4 3 2 1 PA19 (MCI_DA2) 4 RR26D 5 9 8 7 C89 100nF 27R PA2 PA31 (ZB_IRQ0) (TWCK0) R89 R91 UP-TOUCH nCD Shell1 Shell2 WP 12 13 PC1 PC3 PC5 PC7 PC9 PC11 DAT1(RSV) DAT0(DO) VSS2 CLK(SCLK) VDD VSS1 CMD(DI) CD/DAT3(CS) (LCDDAT1) (LCDDAT3) (LCDDAT5) (LCDDAT7) (LCDDAT9) (LCDDAT11) R98 R100 R102 R104 R107 R109 J9 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 0R 0R 22R 22R 22R 22R 22R 22R PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 R90 R92 R93 R94 R95 R96 R97 R99 R101 R103 R105 R108 0R 0R 22R 22R 22R 22R 22R 22R 22R 22R 22R 22R (ZB_IRQ1) (TWD0) (LCDDAT15) (LCDDAT14) (LCDDAT13) (LCDDAT12) (LCDDAT0) (LCDDAT2) (LCDDAT4) (LCDDAT6) (LCDDAT8) (LCDDAT10) PA3 PA30 PC15 PC14 PC13 PC12 PC0 PC2 PC4 PC6 PC8 PC10 R115 R116 R117 R118 22R 22R 22R 22R (LCDDAT17) (LCDDAT19) (LCDDAT21) (LCDDAT23) PC17 PC19 PC21 PC23 R120 R122 R125 22R 22R 22R (LCDPWM) (LCDHSYNC) (LCDPCK) PC26 PC28 PC30 DAT2(RSV) +5V_LCD SD CARD J10 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 SD CARD MN16 MAX3232CSE VDDIOP0 C 16 VDDIOP0 2 C92 100nF R135 100K PA10 PA9 VCC 6 C1+ V+ C1- V- C2+ GND C2- 4 J11 1 6 2 7 3 8 4 9 5 C94 100nF 15 11 12 10 9 (DTXD) (DRXD) T1IN R1OUT T2IN R2OUT R114 R111 R112 R113 22R 22R 22R 22R PC24 PC27 PC29 (LCDDISP) (LCDVSYNC) (LCDDEN) R119 R121 R124 22R 22R 22R PB11 PB13 PB15 (AD0_XP) (AD2_YP) (AD4_LR) R126 R128 R130 0R 0R 0R PA21 PA23 PB9 PB0 (SPI1_MISO) (SPI1_SPCK) R131 R133 R137 R139 0R 0R 0R 0R R141 10K 3 C93 100nF R136 100K (LCDDAT16) (LCDDAT18) (LCDDAT20) (LCDDAT22) 1 C91 100nF C90 100nF PC16 PC18 PC20 PC22 5 14 13 7 8 T1OUT R1IN T2OUT R2IN VDDANA ESQ-120-33-L-D 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 0R 0R 0R (AD1_XM) (AD3_YM) (ONE_WIRE) R132 R134 R138 R140 0R 0R 0R 0R PA22 (SPI1_MOSI) (SPI1_NPCS1) PA0 (LCD_DETECT) PB1 PB[0..18] (3,5,8) PB12 PB14 PA4 LCD_DET PC[0..31] J12 ZB_RSTN ZB_IRQ1 (SPI1_NPCS0) (SPI1_MISO) R142 R144 R146 R148 1 3 5 7 9 0R 0R 0R 0R PB2 2 4 6 8 10 ZB_IRQ0 0R ZB_SLPTR 0R 0R (SPI1_MOSI) 0R (SPI1_SPCK) R143 R145 R147 R149 PA2 PA6 PA22 PA23 1 C95 18pF C96 2.2nF NRST L13 220ohm at 100MHz 2 1 2 3 4 NRST (3,9) WKUP (3) +3V3 PB3 C97 2.2uF WAKE UP 1 2 R150 3 4 100K VDDBU PB4 PB_USER ZIGBEE 1 2 3 4 (3,5) PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 B PA5 PA3 PA8 PA21 C PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 11 10 (3) UART R127 R129 R123 D PB3 B VDDANA A 3 A VR1 10K R151 0R (Analog input) PB17 C98 10nF 1 2 A REV SAM9CN11-EK INIT EDIT MODIF. SCALE PP DES. 05-APR-12 PP DATE 1/1 SERIAL INTERFACES This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 8 7 6 5 4 3 2 1 05-APR-12 VER. DATE REV. SHEET A 7 9 5 4 3 2 1 L14 (3,5,7) PB[0..18] AUD_1V8 PB10 AVDD1V8 1 (5,7) PA[0..31] PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 AUD_1V8 + C100 10uF C99 100nF C101 100nF D 220ohm at 100MHz 2 D R192 0R R193 0R 2 3 AGND_AUDIO J13 4 +3V3 C106 10uF C107 100nF C108 4.7uF C102 100nF C103 100nF R154 20R R155 20R R152 3.9K R153 3.9K C104 220pF C105 220pF 1 5 HEADPHONE AGND_AUDIO PB10 (PCK0) R158 22R PA24 PA28 PA25 PA29 PA26 PA27 (TK) (RK) (TF) (RF) (TD) (RD) R159 R160 R161 R162 0R 0R 0R 0R R163 0R 28 29 23 AVDD AGND_AUDIO HPOUTL HPOUTR HPOUTFB MCLK 13 15 14 BCLK/GPIO4 30 32 31 LRCLK DACDAT ADCDAT 1 LINEOUTL LINEOUTR GPIO1/IRQ LINEOUTFB AVDD1V8 16 C 18 MIC1 17 1 2 AGND_AUDIO WM8904 7 CPVDD 8 C142 1uF CPCA C114 2.2uF IN1L/DMICDAT1 IN1R/DMICDAT2 10 L19 1 MICBIAS 19 R168 2.2K C117 100nF 220ohm at 100MHz 2 +3V3 C118 4.7uF 20 IN2R 24 5 AGND_AUDIO AGND DGND CPGND MICVDD 22 9 AVDD GND_PADDLE CPVOUTP CPVOUTN 33 11 12 C116 2.2uF 27 25 CPCB AGND_AUDIO IN2L C113 2.2uF C115 2.2uF VMIDC 6 4 SCLK SDA DCVDD 2 3 26 C (TWCK0) (TWD0) DBVDD PA31 PA30 21 AGND_AUDIO MN17 R191 0R AGND_AUDIO AGND_AUDIO B AGND_AUDIO C120 1uF L15 10uH/150mA +1V8 B C119 4.7uF C121 1uF AGND_AUDIO R194 0R R195 0R 2 3 AUD_1V8 J15 4 R157 R173 DNP 1R R174 DNP C124 220pF C125 220pF 1 5 LINE IN C109 4.7uF AGND_AUDIO A A A REV SAM9CN11-EK INIT EDIT MODIF. SCALE PP DES. 05-APR-12 PP DATE 1/1 AUDIO This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 05-APR-12 VER. DATE REV. SHEET A 8 9 5 4 3 2 1 L22 +1V8 D 1 C126 10uF C127 100nF C128 100nF C129 100nF A1V8 220ohm at 100MHz 2 C130 100nF C131 100nF D C132 4.7uF GND_ETH GND_ETH L23 A3V3 1 C133 100nF A1V8 220ohm at 100MHz 2 +3V3 C134 10uF +1V8 +1V8 R180 DNP R181 47K R182 47K (4,5) (4,6) (4,6) (4,5) (4,5) 11 A1 12 6 5 4 PD19 NWRE NRD PD21 PD20 R187 3 22R 21 J16 J00-0061 1 TD+ TXP1 TXM1 RXM1 NRST 2 3 A GND Y 16 3 RD+ RX+ 3 17 5 CT RX- 6 R176 R177 EECS EESK EED_IO 15 10 9 R178 49.9R 1% R183 DNP 49.9R 1% R179 49.9R 1% GND_ETH ISET 2 1 75 4 5 75 8 7 8 +3V3 P1LED0 P1LED1 22 R185 75 1nF GND_ETH R197 4.7K P1LED0 P1LED1 75 7 NC GND_ETH R196 1K CSN WRN RDN INTRN C135 10uF C137 100nF C136 100nF +1V8 CMD P1LED0 3.01K 1% P1LED1 9 R184 470R 10 11 R186 470R 12 PME 24 Y3 AGND AGND RSTN DGND DGND DGND DGND R188 4.7K 2 X2 4 3 25 C139 22pF B 1 2 25MHz C140 22pF 13 18 (3,7) C138 100nF TX- 49.9R 1% 7 26 28 37 MN20 SN74LVC1G07 1 5 N.C. VCC 23 2 TD- 20 6 RD- X1 +1V8 1 4 CT +1V8 B +3V3 TX+ 19 C RXP1 KSZ8851-16MLL (4) VDD_A3.3 14 8 27 38 46 VDD_IO VDD_IO VDD_IO SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 A3V3 13 14 C 48 47 45 44 43 42 41 40 39 36 35 34 33 32 31 30 VDD_A1.8 ETH_D0 ETH_D1 ETH_D2 ETH_D3 ETH_D4 ETH_D5 ETH_D6 ETH_D7 ETH_D8 ETH_D9 ETH_D10 ETH_D11 ETH_D12 ETH_D13 ETH_D14 ETH_D15 VDD_D1.8 MN19 VDD_CO1.8 (4) ETH_D[0..15] 29 GND_ETH GND_ETH 4 GND_ETH (6) NOR_NRST +1V8 + C141 10uF R189 0R R190 0R A A GND_ETH A REV SAM9CN11-EK INIT EDIT MODIF. SCALE PP DES. 05-APR-12 PP DATE 1/1 ETH This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 05-APR-12 VER. DATE REV. SHEET A 9 9 Section 6 Display Module Hardware 6.1 Board Overview SAM9N12/CN11-DM board carries a 4.3” TFT LCD module with touch screen. The DM board also carries four QTouch pads. Figure 6-1. 6.2 DM Board Equipment List Here is the list of the DM board components: One 4.3” TFT LCD module LCD Back light driver 3.3V regulator QTouch device 1-Wire device SAM9N12/CN11-EK User Guide 6-1 11186A–ATARM–29-Nov-12 6.3 Function Blocks 6.3.1 3.3V Regulator The SAM9N12/CN11-DM board features its own LDO for local power regulation. It accepts DC 5V power from a 500 mA power switch on the EK and outputs a regulated +3.3V to most other circuits on the board. Figure 6-2. DM Board Power Supply 5V_INTER 3V3_LCD MN3 1 5 VIN 2 6.3.2 GND 3 SELCONF IG C12 10u VOUT 4 EN C13 100n C15 2.2u BY P C10 10u C11 100n SPX3819 500mA capability TFT LCD with Touch Panel The SAM9N12/CN11-DM board features an LCD controller. The 4.3" 480x272 LCD provides the DM with a low power LCD display feature, back light unit and a touch panel, similar to that used on commercial PDAs. Graphics and text can be displayed on the dot matrix panel with up to 16 million colors by supplying 24bit data signals (8 bit x RGB by default). This allows the user to develop graphical user interfaces for a wide variety of end applications. Warning: Never connect/disconnect the LCD display from the board while the power supply is on. Doing so may damage both units. 6-2 11186A–ATARM–29-Nov-12 SAM9N12/CN11-EK User Guide LCD with Touch Panel J1 M1 DGMD 41 Figure 6-3. C ond ucto rs on TOP SIDE PIN 40 4.3'' LCD, 480(H)×RGB×272(V) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VLEDVLED+ 3V3_LCD R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6 B7 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R Red0 Red1 Red2 Red3 Red4 Red5 Red6 Red7 Green0 Green1 Green2 Green3 Green4 Green5 Green6 Green7 Blue0 Blue1 Blue2 Blue3 Blue4 Blue5 Blue6 Blue7 C20 100n 3V3_LCD R44 4.7K VCLK DISP HSY NC VSYNC VDEN R89 R90 R91 R92 TP_XR TP_Y D TP_XL TP_Y U 0R 0R 0R 0R 42 DGMD PIN 1 VLEDVLED+ DGND VDD RED0 RED1 RED2 RED3 RED4 RED5 RED6 RED7 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 GREEN6 GREEN7 BLU E0 BLU E1 BLU E2 BLU E3 BLU E4 BLU E5 BLU E6 BLU E7 DGND DC LK DISP H SYNC VSYNC DE NC DGND X+ YXY+ C16 DNP 6.3.3 C17 D NP R 42 DNP C18 DNP C19 DNP Back Light The back light voltage is generated from a CP2122ST boost converter. It is powered directly by the DC 5 V from the EK board. The back light level is controlled by a PWM signal generated from the SAM9N12/CN11 processor. Figure 6-4. Back Light Control L1 22uH 880mA 5V_INTER C7 10u 10V R43 6 5 4 LCDPWM VLED+ D1 5V/217mA RB160M-60 60V/1A 0R MN1 VIN SW OVP GND SHDN# FB C9 2.2u 50V 1 2 3 CP2123ST-A1 300mV R40 10k SAM9N12/CN11-EK User Guide 2 x5 LEDs Back Light VLED- R41 7.5R 6-3 11186A–ATARM–29-Nov-12 6.3.4 QTouch The SAM9N12/CN11-DM board carries a QTouch device piloted through a TWI interface. It manages four capacitive touch buttons directly printed on the PCB. There are dual footprints for the QTouch device, and SOIC is the default mounted one. Figure 6-5. QTouch 3V3_LCD MN5 C22 3V3_LCD 3V3_LCD C21 R75 R67 R70 R73 DNPDNP 9 100n 6.3.5 VSS KEY0 KEY1 KEY2 KEY3 KEY4 KEY5 14 13 12 11 10 9 8 R65 R66 R68 R69 4.7k 4.7k 4.7k 4.7k QT1070_SOIC 16 17 1 2 3 4 5 KEY 4 KEY 3 KEY 2 KEY 1 R64 R71 R72 R74 4.7k DNP 4.7k DNP 4.7k DNP 4.7k DNP KEY K4 KEY K3 Thermal MODE(VSS) KEY6 KEY5 KEY4 KEY3 KEY2 KEY1 KEY0 KEY K2 KEY K1 21 8 VSS 6 7 10 18 19 20 SCL SDA CHANGE RESET QT1070 NC5 DNP NC4 NC3 NC2 NC1 NC0 11 15 12 14 13 VDD MODE(VSS) SDA RESET CHANGE SCL KEY6 VDD MN6 10k 4.7k 4.7k 4.7k TWCK0 TWD0 ZB_IRQ0 RESET# 1 2 3 TWD0 RESET# 4 ZB_IRQ0 5 TWCK0 6 7 100n 1-Wire The DM board also uses 1-Wire device as “soft label” to store the information such as chip type, manufacture name, production date, etc. Figure 6-6. 1-Wire on DM 3V3_LCD R45 4.7k ONE_WIRE 1 2 3 4 MN2 NC1 NC2 DATA GND NC6 NC5 NC4 NC3 8 7 6 5 DS2433S 6-4 11186A–ATARM–29-Nov-12 SAM9N12/CN11-EK User Guide Section 7 DM Schematics 7.1 DM Board Schematics This section contains the following schematic: LCD Board SAM9N12/CN11-EK User Guide 7-1 11186A–ATARM–29-Nov-12 5 4 3 2 3V3_LCD 41 R5 R6 DGMD J1 M1 D Conductors on TOP SIDE PIN 40 4.3'' LCD, 480(H)×RGB×272(V) PIN 1 VLEDVLED+ R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6 B7 0R 0R J2 DNP DNP (PA31) ZB_IRQ0 TWCK0 (LCDDAT1) (LCDDAT3) (LCDDAT5) (LCDDAT7) (LCDDAT9) (LCDDAT11) Blue1 Blue3 Blue5 Blue7 Green1 Green3 3V3_LCD R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R76 R77 R78 R79 R80 R81 R82 R83 R84 R85 R86 R87 R88 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R Red0 Red1 Red2 Red3 Red4 Red5 Red6 Red7 Green0 Green1 Green2 Green3 Green4 Green5 Green6 Green7 Blue0 Blue1 Blue2 Blue3 Blue4 Blue5 Blue6 Blue7 C20 100n 5V_INTER 3V3_LCD (LCDDAT16) (LCDDAT18) (LCDDAT20) (LCDDAT22) R44 4.7K VCLK DISP HSYNC VSYNC VDEN Red0 Red2 Red4 Red6 (PC24) (PC27) (PC29) DISP VSYNC VDEN (PB11) (PB13) TP_YU TP_XR AD4_LR 3V3 R89 R90 R91 R92 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 ZB_IRQ1 TWD0 (PA30) Green7 (LCDDAT15) Green6 (LCDDAT14) Green5 (LCDDAT13) Green4 (LCDDAT12) Blue0 (LCDDAT0) Blue2 (LCDDAT2) Blue4 (LCDDAT4) Blue6 (LCDDAT6) Green0 (LCDDAT8) Green2 (LCDDAT10) D TSM-115-01-L-DV-A 0R 0R 0R 0R TP_XR TP_YD TP_XL TP_YU R24 SELCONFIG R22 DNP 0R 42 DGMD C VLEDVLED+ DGND VDD RED0 RED1 RED2 RED3 RED4 RED5 RED6 RED7 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 GREEN6 GREEN7 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 BLUE6 BLUE7 DGND DCLK DISP HSYNC VSYNC DE NC DGND X+ YXY+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 3V3 J3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Red1 Red3 Red5 Red7 (LCDDAT17) (LCDDAT19) (LCDDAT21) (LCDDAT23) LCDPWM (PC26) HSYNC (PC28) (PC30) VCLK TP_YD TP_XL R19 C (PB12) (PB14) 0R ONE_WIRE (PA4) LCD_DETECT R23 0R TSM-120-01-L-DV-A L1 22uH 880mA 5V_INTER 3V3_LCD 5V/217mA D1 VLED+ MN5 RB160M-60 60V/1A C22 C16 DNP MN1 SW GND FB 1 2 3 C19 DNP R75 R67 R70 R73 DNP DNP 100n MN6 CP2123ST-A1 300mV R40 10k 2 x5 LEDs Back Light VLED- 10k 4.7k 4.7k 4.7k TWCK0 TWD0 ZB_IRQ0 RESET# R41 7.5R 15 12 14 13 MN3 2 3 SELCONFIG C12 10u C13 100n C15 2.2u VIN VOUT EN C10 10u BYP 3V3_LCD 5 GND 4 SPX3819 500mA capability QT1070 NC5 DNP NC4 NC3 NC2 NC1 NC0 8 1 A 3V3_LCD SCL SDA CHANGE RESET VSS 6 7 10 18 19 20 5V_INTER TWD0 RESET# ZB_IRQ0 TWCK0 3V3_LCD C21 1 2 3 4 5 6 7 VDD MODE(VSS) SDA RESET CHANGE SCL KEY6 VSS KEY0 KEY1 KEY2 KEY3 KEY4 KEY5 14 13 12 11 10 9 8 R65 R66 R68 R69 4.7k 4.7k 4.7k 4.7k B QT1070_SOIC 9 VIN OVP SHDN# C18 DNP 100n VDD 6 5 4 LCDPWM R42 DNP MODE(VSS) B C17 DNP 3V3_LCD KEY6 KEY5 KEY4 KEY3 KEY2 KEY1 KEY0 16 17 1 2 3 4 5 KEY4 KEY3 KEY2 KEY1 R64 R71 R72 R74 4.7k 4.7k 4.7k 4.7k DNP DNP DNP DNP KEY K4 KEY K3 Thermal C9 2.2u 50V 0R KEY K2 KEY K1 21 R43 11 C7 10u 10V R45 4.7k C11 100n A MN2 ONE_WIRE 1 2 3 4 NC1 NC2 DATA GND NC6 NC5 NC4 NC3 8 7 6 5 A REV DS2433S SAM9CN11-EK INIT EDIT MODIF. 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