Demonstration Note for CS51021A/CS51022A

CS51021ADEMO/D
Demonstration Note for
CS51021A/CS51022A
A 36−72 V In, 5 V/5 A Out, Forward
Converter Using the CS51021A/22A
Enhanced Current Mode Controller
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DEMONSTRATION NOTE
Features
• Forward Convertor Topology
• Undervoltage and Overvoltage Shutdown
• Overcurrent Protection
• Current Sense Transformer for Improved Efficiency
and Regulation
• Soft Start
• SYNC Function Allows External Switching Clock
(CS51021A)
• SLEEP Function Provides ON/OFF Primary Side
Power Control (CS51022A)
• Small Size (2″ × 2−1/2″), All Components Surface
Mount
• 500 V Input−to−Output Isolation
• 300 kHz Switching Frequency
• Bootstrap Section for Circuit Bias Improves Efficiency
Description
The CS51021A/22A demo board is configured as a
compact, full−featured, 25 W DC−DC convertor for telecom
applications. This board incorporates all the circuitry
required to fully evaluate the performance of the CS51021A
Current Mode PWM Controller. Input is 36 to 72 V and
output is 5 V at 5 A. Onboard is a resistive load which can
be attached to the supply output at 275 mA, 2.5 A or 5 A load,
static or dynamic. Also available is a switch for short circuit
to demonstrate overcurrent protection. This load
arrangement demonstrates the tight load regulation of the
circuit. The DC/DC converter section fits in a 2″ × 2−1/8″
space and includes optoisolation.
Figure 1. CS51021A/22A Demonstration Board
© Semiconductor Components Industries, LLC, 2009
June, 2009 − Rev. 1
1
Publication Order Number:
CS51021ADEMO/D
CS51021ADEMO/D
S1
5V
VIN
Short
Static or Dynamic
Resistive Load Section
Opto−
Isolated
Output
Section
DC−DC Converter
36−72 to 5 V/5 A
SYNC/SLEEP
S3
Half Load
S2
Half Load
S4
PGND
SGND
Dynamic Load
Figure 2. Application Diagram
MAXIMUM RATINGS
Pin Name
Maximum Voltage
Maximum Current
VIN
+100 V/−0.3 V
1.0 A DC
SLEEP/SYNC
+6.0 V/−0.3 V
4.0 mA
PGND
0V
1.0 A
5V
6.0 V/−0.3 V
5.0 A
SGND
0V
5.0 A
ELECTRICAL CHARACTERISTICS (36 V ≤ VIN ≤ 72 V, IOUT = 275 mA; unless otherwise noted)
Parameter
Min
Typ
Max
Unit
DC Output Voltage
0 ≤ IOUT ≤ 5.0 A
Test Conditions
4.85
5.00
5.15
V
Switching Frequency
Measure @ RTCT
290
330
370
kHz
Load Transient Response
500 mA < ILOAD < 5.0 A
275 mA < ILOAD < 2.5 A
120
35
160
50
220
70
μs
μs
Load Regulation
VIN = 48 V, 275 mA < ILOAD < 5.0 A
5.0
10
15
mV
Line Regulation
ILOAD = 5.0 A
10
15
25
mV
Efficiency
VOUT = 5.0 V, IOUT = 5.0 A
VOUT = 5.0 V, IOUT = 275 mA
76
35
79
40
82
45
%
%
Output Ripple
IOUT = 5.0 A
35
45
55
mVP−P
Power−Up/Soft Start Time
0 ≤ IOUT ≤ 5.0 A
−
200
−
μs
Isolation
Allowable DC level between input and output
−
500
−
V
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2
SYNC
TP4
Q2
FZT688
R78
22 k
C41
0.01 μF
C42
330 pF
R90
5.1 k
R44
10 k C53
4700 pF
D10
11 V
R41
51 k
36 V to 72 V
C43
0.1 μF
VIN
3
12
11
3
7
9
10
13
16
R38
10
C38
22 μF
LGND
CSS
SYNC
RTCT
VFB
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TP5
PGND
IS
VO
SLOPE
ISET
OV
UV
VREF
COMP
VCC
VC
CS51021A
15
2
1
4
8
6
5
14
C40
470 pF
C39
0.1 μF
D9
18 V
D8
BAS21
TP3
R42
24.3 k
R42
24.3 k
R77
100
Figure 3. Demonstration Board Schematic, Power Supply Circuitry
R6
10 k
R46
100
C46
100 pF
R45
6.98 k R4
10
R40
2.49 k
D11
BAS21
R39
200 k
R76
1.0 k
R74
62
TP2
TP1
R75
10 k
C34
100
100:1
T3
U?
MOC8102C
R27
10
Q1
IRF634
C45
1.0 μF
R9
180
4:1
T1
R36
1.0 k
C37
680 pF
R29
10
R23
5.1 k
U3
TL431
R25
2.0 k
5V
@5A
VOUT
R24
2.0 k
SGND
C23
100 μF
T2
2:5
C36
1000 pF
C18
0.1 μF
C22
100 μF
D6
MBR82060CT
CS51021ADEMO/D
CS51021ADEMO/D
R7
18
R11
18
R48
18
R49
18
R50
18
R51
18
VOUT
R57
10
R5
18
R52
18
R53
18
S1
Short
C57
0.1
S2
8
Half Load
R56
2.0 k
Q3
IRF7413
R70
18
R71
18
2
3
4
R58
10
S4
VCC
CON
TRIG
THR
OUT
DIS
RST
GND
LM555C
Dynamic Load
R68
18
R69
18
0.1
R67
100
R54
18
R55
18
C51
U4
S3
Half Load
R8
18
R3
18
R2
18
R72
18
J10
BNC
R73
100
SGND
Figure 4. Demonstration Board Schematic, Test Circuitry
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4
5
C52
0.1
6
7
1
R60 13 k
R59
2.0 k
CS51021ADEMO/D
OPERATION GUIDELINES
The CS51021A demonstration board is configured to
demonstrate the performance features of the CS51021A
Current Mode PWM Controller.
• The power supply input connectors, labeled VIN and
PGND, are the straight turret terminals and are located
on the left side of the board. Below the VIN terminal is
the SLEEP/SYNC terminal.
• The outputs (+5 V, GND) in the middle, between the
DC/DC convertor and load areas.
• The voltage output terminal, J10, is a female BNC
connector, located near the load resistors. Using a
standard BNC coax cable, the output voltage waveform
can be observed on an oscilloscope during DC and AC
load operation.
• The Half Load Switches, S2 and S3, are SPDT type
(AMP) and are located on the right side of the board.
•
•
•
By turning these switches on, a DC load of 2.5 A is
applied for each.
The Short Circuit Switch, S1, is a SPDT type (AMP)
and is located on the right side of the board. By turning
S1 on, the demo board output is shorted to ground.
The Dynamic Load Switch, S4, located on the upper
right of the board is used to enable the 555 Timer/FET
circuit which is in parallel with Half Load Switch, S2.
When enabled, this switches 2.5 A on and off rapidly.
This demonstrates the short reaction time and efficient
load handling of the circuit.
There are five test points in the convertor area;
Switching Node, NFET Gate, ISENSE pin, RTCT pin
(osc.) and GND. These single pin terminals allow easy
monitoring of the CS51021A function.
THEORY OF OPERATION
Control Method
Fault Operation
The CS51021A is a fixed frequency PWM current mode
controller that regulates the output voltage. To perform this
task, the controller varies the duration of a current pulse that
flows through transformers T1 and T3, and then across T2
to the load. The CS51021A drives FET Q1’s gate pin,
forcing the FET to switch on and off. Switching the FET
creates an AC waveform that is stepped down by T1. The
current is proportional to both the output current and the
input voltage (V = L[di/dt]) and is used to control the duty
cycle of the FET. The current ramp through current sense
transformer T3 reaches a level where the controller shuts
down the FET, hence the term Current Mode Control. Once
the FET switches off, the stored magnetic energy of the
transformers produces a current, which is directed through
rectifying diodes D6 to produce an output DC voltage. The
rectified DC voltage is sensed by the negative input of the
controller’s error amplifier, at the VFB pin. The error
amplifier’s output sets the current limit value that will shut
down the FET. For example, if the rectified voltage falls
below the desired level, the error amplifiers output will
increase thereby allowing the duty cycle, inductor current
and stored magnetic energy to increase. As a result, a larger
amount of current is directed to the rectifier causing the
output DC voltage to increase. This process occurs every
oscillator clock cycle.
Output current is tapped at 100:1 transformer T3, then is
halfwave rectified by diode D11, then voltage divided by
R46 and R74. This point connects to the PWM and Second
Threshold comparators via the ISENSE pin. The 75 ns
blanking interval is disabled if VFB is below 2 V, as in a short
circuit condition. The pulse−by−pulse overcurrent threshold
is the level present at the ISET pin. This voltage provides a
threshold for both PWM and Second Threshold
comparators. When the ISENSE exceeds the second
threshold, the soft start capacitor CSS is reset and reinitiates
the soft start sequence. This sequence repeats as long as the
fault condition is present. The rapid response to overcurrent
faults protects the components in the output section as well
as the load.
Switching Frequency
For a chosen frequency of 330 kHz, using the RTCT graph
[Figure 4 in the datasheet (document number CS51021A/D,
available through the Literature Distribution Center or via
our website at http://www.onsemi.com)], a 10 k resistor with
a 330 pF capacitor was found to produce the desired results.
Forward Converter Topology
Advantages:
• High Efficiency
• Small output filter
• Low output ripple
• Isolation between input and output
Disadvantages:
• Only one monitored output possible
• The output voltage is always lower than the input
voltage (step−down)
Startup
The CS51021A initially is powered from VIN, with D10
providing regulation and protection. D10 is an 11 V Zener.
Dropped down by the VBE of Q2, and the CS51021A sees
about 10.3 V at VC and VCC. As the circuit comes up into
operation, the transformer T2 takes over and sources power.
C41 is the soft start capacitor. The value of 0.01 μF sets the
initial output voltage to ramp up in about 200 μs.
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5
CS51021ADEMO/D
DESIGN NOTE
Design of a Forward Converter Using the
CS51022A Enhanced PWM Controller
BS
V
n + IN
BS
Specifications
VIN = 36 V to 72 V
VOUT = 5 V ± 5% @ 0.5 A to 5 A
VOUT Ripple ≤ 50 mA
Switching Frequency = 330 kHz
We begin the design on the secondary side by selecting the
minimum voltage required to keep the output voltage in
regulation. Worst case is at minimum input voltage, 36 V.
+
0.78 mH + 200 mH
L + 200 mH " 20% + 160 mH to 240 mH
We use 28 AWG wire with one strand on the primary side
and three strands on the secondary. The primary and
secondary windings are interleaved to minimize leakage
inductance.
5 V ) 0.5 V
+ 8.46 V
0.65 V
Output Inductor Calculation
VIN(min)
n+
+ 36 + 4.25 [ 4 : 1
8.46
VSEC(min)
IOUT(min) = 0.5 A
The inductor is designed so that the current remains
continuous within the specified load range.
Based on a turns ratio of 4:1 the maximum duty cycle at
low line is:
DIL + 2
5 V ) 0.5 V
4 + 0.61
36
36 + 0.30
Dmin + Dmax
72
IOUT(min) + 2
0.5 A + 1 A
The minimum duty cycle is 0.3 so the maximum off−time is:
Dmax +
tOFF(max) + 1 * 0.3 + 0.7 + 2.18 ms
320 kHz
320 kHz
Minimum inductor value is:
The transformer is designed using the basic transformer
equation:
Ae u VIN
10 − 5
+ 16.22
10 − 6
7.3
2.03 ms
+
0.0015
4.5
36 V
0.3 T
Allowing for a 20% range in inductance value gives:
The transformer turns ration is:
n
tON
tON
Ae
L + 162
Since the CS51022A includes slope compensation
circuitry, we can choose the maximum duty cycle at 0.65.
BS
Ae u VIN
We use 16 primary turns.
For 3F3 material, AL = 780 nH/T2 or 0.78 μH/T2.
The maximum inductance is:
V
) VD
VSEC(min) + OUT
Dmax
VSEC(min) +
n
L min +
tON
where:
BS = core saturation flux density in Tesla;
n = number of primary turns;
Ae = core cross sectional area in meters2;
VIN = the voltage applied to the core in volts;
tON = the maximum time for which the voltage is applied
in μs.
The core selection is an iterative process and usually
involves several attempts. This paper shows the attempt that
worked.
Using a transformer design kit from Coiltronics Inc., we
use the EFT 15 core. For the EFD 15:
AL, nH/T2 (ungapped) = 780
Ae, (min core area) mm2 = 15
Ve, (core volume) mm3 = 510
For this design fSW = 320 kHz.
+
(VOUT ) VD) tOFF(max)
DI
(5 V ) 0.5V)
10 − 6
2.18
1
+ 12 mH
The maximum inductor current is approximately:
IOUT ) DI + 6.5 A
2
IL(max) + 1.2
The inductor is designed using the basic inductor
equation:
BS
n
Ae u L
IL(max)
Rearranging gives
n+
L
IL(max)
BS Ae
where:
BS = core saturation flux density in Tesla;
n = number of primary turns;
Ae = core cross sectional area in meters2;
L = the required inductance in μH;
IL(max) = the maximum inductor current in Amps.
D
tON(max) + max + 0.65 + 2.03 ms
fSW
320 kHz
Rearranging the transformer equation:
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6
CS51021ADEMO/D
Using a Micrometals T50−26B core where:
Ae = 1.48 cm2 or 0.0000148 m2
AL = 43.5 nH/T2 or 0.0435 μH/T2
n+
V
Secondary Slope + DI + OUT
Dt
L
5.5 V
+
+ 0.45 Ańms
12 mH
10 − 6 6.5
+ 17.56
0.148 10 − 4
12
0.3
2. Calculate the slope as seen from the primary side.
With n = 18 the inductance measures 19 μH.
In addition to the acting as the output inductor we can use
a flyback winding to generate the supply voltage for the
control IC. The voltage across the inductor is approximately
5.5 V (VOUT + VD).
The turns ratio is chosen from the formula:
VCC +
NS
NP
Primary Slope + Secondary Slope
+ 0.45
(VOUT ) VD) * VD
S + 0.071 Vńms
VSlope +
Output Capacitor Calculation
+
fSW
8
320
DI
50 mV
50 + 0.057 Vńms
VSlope + 0.031 Vńms
10 + 0.31 Vńms
The slope compensation capacitor is chosen from:
+ 3.9 mF
The maximum ESR of the output capacitor is given by:
ESR +
RSense
5. The voltage on the slope pin is divided by 10 and
added to the voltage at the IS pin. The voltage at
the slope pin is 10 times the required slope
compensation voltage.
DVOUT
0.5
103
0.55 + 0.031 Vńms
Secondary Slope
n
+ 0.114
100
The output capacitor value depends on the following:
1. Maximum allowable ripple;
2. Maximum allowable voltage overshoot and
undershoot on load transients.
The capacitor is calculated from:
8
1 + 0.114 Ańms
4
3. Calculate the slope voltage at the current sense
resistor.
4. The amount of slope compensation is chosen at
0.55:
For a secondary voltage of approximately 13 volts this
gives a 2.5 turns ratio so the flyback winding has 45 turns.
COUT +
NS
NP
CS +
50 mV
DVOUT
+
+ 100 mW
DI
500 mA
+
A suitable safety margin is added to the values just
calculated, one recommendation is that the output capacitor
should be at least ten times the minimum value calculated
the the ESR should be at least half of the calculated value.
A capacitor that meets the ESR requirements usually also
easily meets the minimum capacitance requirements. In this
design we use two 100 μF Tantalum capacitors with a
maximum ESR = 100 mΩ in parallel.
50 mA
tON(max)
VSlope
50 mA
2.03 ms
+ 320 pF
0.31
Current Sense Transformer Selection
The circuit uses a current sense transformer to sense the
primary current. The total primary current is the sum of the
magnetizing current and the reflected secondary current.
Magnetizing current:
36 V 2.03 ms
V
tON
IMag + IN
+
+ 0.365 A
L
200 mH
Slope Compensation
The slope of the compensating ramp should be at least
50% of the down slope of the output inductor current as seen
from the primary side.
In a current mode control scheme such as this, the
compensating ramp can be either added to the primary
current sense signal or subtracted from the error amplifier
voltage.
In this case we will add the ramp to the current sense
signal.
IMAG = 0.365 A
1.635 A
IMAX = 2.0 A
1.04 A
0A
Steps for Slope Compensation
Figure 5. Primary Current Waveform
1. Calculate the inductor current downslope on the
secondary side.
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CS51021ADEMO/D
IL(max)
) IMag + 6.5 ) 0.365 + 2 A
n
4
IPrimary +
2nd
Threshold
Several transformer manufacturers make current
transformers with turns ratios of 50:1, 100:1 and 200:1. In
this design we use a 100:1 turns ratio transformer
manufactured by GB International (part number 3714−G).
With a primary current of approximately 2 A peak, the
second current will be:
ISecondary +
−
1.5
12.5 μA
R2
OV
VSlope
R3
VI(SET) ) 0.1 V ) 0.1
The amount of overvoltage hysteresis is determined by
R3. The internal 12.5 μA current source turns on in an
overvoltage condition and adds current to the resistor string
raising the voltage on the OV pin. The input voltage must
then drop low enough to bring the voltage on the OV pin
below 2.5 V (the internal reference) before the CS51022A
will resume operation.
In this case we design for:
VOV(Hyst) = 12.5 mA × R3
VIN(max) = 75 V
VIN(min) = 34 V
Overvoltage Hysteresis = 2.75 V
R3 is calculated from:
VSlope)
If we arbitrarily choose the maximum voltage on the IS pin
as 1 V during normal operation, we can calculate the
required voltage on the ISET pin (VI(SET)) from:
VI(SET) +
+
(VI(S) * 0.1 V * (0.1
0.8
(1 * 0.1 V * (0.1
0.8
VSlope))
0.46))
+ 1.07 V
Resistors R24 and R43 set VI(SET) = 1.1 V.
The pulse−by−pulse current limit voltage is 1 V. The
current in the secondary winding of the current sense
transformer is 20 mA, so the resistor to convert this to the
required voltage is:
RSense +
2.5
OV
Variable
Hysteresis
Figure 6. Voltage Monitoring Circuitry from
the CS51022A
VI(S)(2) +
(0.8
−
+
where:
VI(SET) = Voltage at the ISET pin;
VSlope = Voltage at the Slope Pin.
The second overcurrent threshold, (the point where the
control IC initiates a soft start) is 1.33 times the
pulse−by−pulse threshold.
1.33
75 mV
Fixed
Hysteresis
REF
IPrimary
2A
+
+ 20 mA
n
100
VI(SET) ) 0.1 V ) 0.1
REF OK
UV
UV
The voltage required at the IS pin is determined by the
voltage at the ISET pin. This voltage is set up with a voltage
divider from VREF.
The overcurrent threshold is given by:
VI(S) + 0.8
+
R1
R3 +
VOV(Hyst)
VIN(max)
2.5 V
12.5 mA
+
2.75 2.5 V
+ 7.33 kW
75 12.5 mA
The total resistance of the divider is given by:
1.0 V
+ 50 W
20 mA
RTotal +
Voltage Monitor
The CS51022A has voltage monitoring circuitry for both
overvoltage and undervoltage conditions. When the voltage
on the OV pin exceeds 2.5 V, an overvoltage condition is
detected and VO is disabled in a low impedance state.
If the voltage on the UV pin drops below 1.5 V, VO is also
disabled in a low impedance state. Both UV and OV
conditions are latched and the CS51022A goes through a
power−up sequence. The undervoltage lockout circuitry has
a fixed 75 mV of hysteresis. The overvoltage circuitry has
programmable hysteresis.
VIN(max)
2.5 V
R3
+
75 V 7.33
+ 220 kW
2.5 V
R2 is calculated based on VIN(min):
R2 +
+
1.5 V RTotal
* R3
VIN(min)
1.5 V
220 kW
* 7.33 kW + 2.37 kW
34 V
R1 + RTotal * R2 * R3
+ 220 kW * 7.33 kW * 2.73 kW + 210.3 kW
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CS51021ADEMO/D
The resistors used were 210 kΩ, 7.32 kΩ and 2.37 kΩ.
The undervoltage hysteresis is given by:
Undervoltage Hysteresis +
+
VIN(min)
34
VSS. As VSS continues to rise above the error amplifier
output voltage, the feedback loop takes control of the duty
cycle. The capacitor charges and discharges between 0.25 V
and 4.3 V. In the event of an overcurrent condition, CSS is
discharged by a 250 μA current sink circuit, and a soft start
cycle begins.
The soft start time is calculated from:
75 mV
1.5 V
75 mV
+ 1.7 V
1.5 V
Timing Components
CSS +
Frequency (kHz)
2000
1. CT = 47 pF
2. CT = 100 pF
3. CT = 150 pF
4. CT = 220 pF
5. CT = 390 pF
6. CT = 470 pF
7. CT = 560 pF
8. CT = 680 pF
1
1500
2
1000
CSS +
4
5
8
5
6
7
10
15
20
25
30
35
40
45
50
RT (kΩ)
Figure 7. Frequency vs. RT for Discrete Capacitor
Values
100
7
Duty Cycle (%)
90
8
6
IPeak +
3
5
4
70
2
60
50
5
10
15
20
25
30
35
40
45
50
VC
RS
where VC is the control voltage (the error amplifier output
voltage).
In this design we are not sensing the output current
directly, we sense the reflected output current on the primary
side and we also sense it through a current sense transformer.
The equation is modified by the turns ratio of each
transformer and becomes:
1. CT = 47 pF
2. CT = 100 pF
3. CT = 150 pF
4. CT = 220 pF
5. CT = 390 pF
6. CT = 470 pF
7. CT = 560 pF
8. CT = 680 pF
3
1
40
10 ms
+ 0.01 mF
9 104
Feedback Loop Design
1. Measure, model or calculate the control to output
gain.
2. Choose the crossover frequency or the loop
bandwidth. The transient response time will be
roughly the reciprocal of the bandwidth.
3. Design the error amplifier to have a gain that is the
inverse of the control to output gain at the chosen
crossover frequency.
As with most industry standard current mode control ICs,
the CS51022A has an internal divide by three network on the
output of the error amplifier. Current to voltage conversion
is done externally with a resistor, RS, as described
previously. The peak voltage across the sense resistor is
given by:
3
500
80
tSS
104
For a 10 ms soft start time:
2500
0
9
V
nT1 nT3
IPeak + C
3 RS
55
RT (kΩ)
The output voltage is given by:
Figure 8. Duty Cycle vs. RT for Discrete Capacitor
Values
VOUT + ILoad
RLoad
The control voltage, VC, controls the output current.
Combining the equations we get:
Method to select timing components is to use the graphs
from the data sheet.
V
VOUT + C
Soft Start
During power up when the output capacitors are
completely discharged, the voltage across the soft start
capacitor, VSS, controls the duty cycle. The soft start
capacitor, CSS, is charged by an internal 50 μA current
source. The error amplifier output voltage is clamped to
3
nT1 nT3
RS
RLoad
So the control to output gain is:
VOUT
n
+ T1
VC
3
nT3
RS
RLoad
The maximum and minimum loads are:
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CS51021ADEMO/D
The Zero due to the output capacitor ESR (max) is:
5V
+1W
5A
5V
+ 10 W
RLoad(max) +
0.5 A
RLoad(min) +
fZ +
2
+
The load poles varies between:
fP(min) +
2
+
2
fP(max) +
2
+
2
p
1
RLoad(max)
p
1
10 W
p
1
RLoad(min)
p
1
1W
200 mf
200 mf
1
ESR
p
1
50 mW
COUT
200 mf
+ 15.9 kHz
The Zero due to the output capacitor ESR (min) is:
COUT
fZ +
2
+ 79.6 Hz
+
2
COUT
p
1
ESR
p
1
25 mW
COUT
200 mf
+ 31.83 kHz
+ 796 Hz
V
IL + C
VIN
2
p
nT1
R14
nT3
5V
I
L2
φ
T3
100
V
nT3
IPK + C
3 R75
4
T1
C21
100 μF
4T
1
+
+
C22
100 μF
RL
Q1
CS51022A
VC
3
R75
50 Ω
Figure 9. Control to Output Section of a Typical Forward Converter
The control to output gain for the maximum and minimum
loads are:
The feedback loop is isolated from the primary by using an
optocoupler. The error amplifier on the secondary side is the
industry standard voltage reference circuit, the TL431. If the
output voltage drops below its nominal value, the current
through the LED decreases. This causes the emitter voltage
of the phototransistor to decrease. This results in a higher
error signal and a corresponding increase in the duty cycle.
The gain to cross at 60 kHz can be added anywhere in the
feedback loop, i.e., it can be all at the optocoupler or divided
between the optocoupler and the error amplifier. In this
design we will divide the gain between both.
1. Choose the feedback resistors. In this case R24
and R25 = 2 kΩ so the current through the divider
network is 1.25 mA. The optocoupler LED bias
current is set for 6 mA.
VOUT
n
nT3
+ T1
RLoad(max)
VC
3 RS
+ 4 100 1 + 2.66 (8.5 dB)
3 50
VOUT
n
nT3
+ T1
RLoad(max)
VC
3 RS
+ 4 100 10 + 26.6 (28.5 dB)
3 50
The crossover frequency must now be selected. It is
always a compromise between wanting to have as large a
bandwidth as possible for the best transient response and
wishing to keep it small enough to filter out the switching
frequency ripple.
For this design we choose a crossover frequency of 60 kHz.
The required loop gain to cross at 60 kHz is:
Gain + 20 log
RBias +
5 V * (2.5 V ) 1.4 V)
+ 1.8 + 180 W
IBias
6 mA
2. The gain of the TL431 is set by resistors R23 and
R24. For a gain of 8 dB:
60 kHz
* 28.5 dB + 29 dB (28)
79.6 Hz
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10
CS51021ADEMO/D
29 dB * 8 dB * 13.9 dB + 7 dB (2.16)
R24 + 5.1 kW + 2.55 + 8 dB
R23
2 kW
Choosing R6 = 10 kΩ gives R78 = 22 kΩ.
6. The error amplifier has a pole zero network to
adjust the gain at higher frequencies. At DC the
gain is determined by the ratio of R78 and R6
while at higher frequencies the gain is determined
by the ratio of R90 and R6. If we place the pole at
1 kHz, and reduce the gain by a factor of four after
the zero this means that C53 is:
3. The optocoupler gain is set by R36 and by R76 on
the primary side.
Gain + R76
R36
CTR +
900 W
+ 5 (13.9 dB)
180
4. We set a zero in the feedback loop at the TL431 to
offset the first load pole that occurs at 79 Hz.
C18 +
2
p
1
R23
fp
+
2
1
5.1 kW
p
C53 +
79 Hz
+ 0.39 mF, use 0.33 mF
+
5. On the secondary side we first set the gain of the
error amplifier to get the required loop gain.
2
p
1
(R78 ) R90)
2
p
1
27.1 kW
fp
1 kHz
+ 5.8 nF, use 4.7 nF
VREF
C53
4.7 nF
COMP
VO
R90
5.1 k
R36
1.0 k
VFB
R78
22 k
VC
−
E/A
R6
10 k
+
2.5 V
R9
180 Ω
+
−
R70
910 Ω
ID
IC
VK
R23
5.1 k
TL431
R24
2.0 k
C36
1.0 nF
C18
0.33 μF
R25
2.0 k
Figure 10. Error Amplifier Feedback with Optocoupler
Leading Edge Blanking
A common problem in current mode control is erratic
operation due to noise on the current sense input. The main
source of this noise is the leading edge noise caused by the
transformer interwinding capacitance. The CS51022A
contains leading edge blanking circuitry that ignores the first
50 ns (typical) of each current sense pulse and should help
eliminate the customary RC filter in the IS pin. This did not
prove to be the case in this design and a small RC filter was
required to add an additional 10 ns of delay.
The zero frequency is given by:
fZ +
2
+
2
p
1
R90
p
1
5.1 kW
C53
4.7 nF
+ 6.6 kHz
We also need a pole to cancel the zero due to the ESR of
the output capacitors.
C36 +
+
2
p
1
R23
2
p
1
5.1 kW
fP
31 kHz
+ 1 nF
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11
CS51021ADEMO/D
Startup and Bias Circuit
The circuit in Figure 11 is a simple linear regulator
bootstrap circuit that supplies start−up current. When the
supply is operational the emitter base junction is reverse
biased and operating current is supplied from the flyback
winding on the output inductor. D9 provides overvoltage
protection.
Resonant Reset
The circuit uses a resonant reset capacitor instead of the
more traditional reset winding. This technique uses the
resonance between the magnetizing inductance of the
transformer and the total capacitance as seen by the
transformer. The parasitic capacitance is difficult to measure
so the main reset capacitor was chosen by experiment.
fR +
VIN (36 V to 72 V)
51 k
11 V
from Aux
Winding
BAS21
FZT688
22 μF
18 V
2
p
1
ǸL
M
CR
where:
CR + CO ) COSS ) CT ) n2
100
CB
CO = resonant capacitor;
COSS = junction capacitance of the power switch;
CB = junction capacitance of the Schottky diode.
to VCC
Figure 11. Startup Supply
DEMONSTRATION BOARD BILL OF MATERIALS
Qty
Ref. Des.
Description
Pkg.
Manufacturer
100 μF, 10 V Tant
7343
KOA
Manuf. P/N
Phone
Fax
714−751−1185
714−432−7365
DC/DC Converter
2
C22, C23
1
C34
100 pF, 500 V NPO
1206
Novacap
−
805−295−5920
805−295−5928
1
C36
1000 pF, X7R
805
Novacap
−
805−295−5920
805−295−5928
1
C38
22 μF, 35 V Tant
7343
KOA
714−751−1185
714−432−7365
3
C18, C29, C43
0.1 μF
805
Novacap
−
805−295−5920
805−295−5928
1
C40
470 pF
805
Novacap
−
805−295−5920
805−295−5928
1
C41
0.01 μF X7R
805
Novacap
−
805−295−5920
805−295−5928
1
C42
330 pF
805
Novacap
−
805−295−5920
805−295−5928
1
C45
1.0 μF
1825
Novacap
−
805−295−5920
805−295−5928
1
C46
100 pF
805
Novacap
−
805−295−5920
805−295−5928
1
C37
680 pF, 100 V
805
Novacap
−
805−295−5920
805−295−5928
1
C53
4700 pF X7R
805
Novacap
−
805−295−5920
805−295−5928
1
D10
11 V Zener
SOT−23
CENTRAL
CMPZ4241B
516−435−1110
516−435−1824
1
D6
2− 60 V Schottkys
DPAK1
ON Semiconductor
MBRB2060CT
2
D8, D11
G.P. Diode, 250 V
SOT−23
DIODES
BAS21
1
D9
18 V Zener
SOT−23
CENTRAL
CMPZ5248B
1
Q1
MOS Pwr FET
DPAK1
IR
IRF634S
1
Q2
NPN Bipolar
1
R23, R90
5.1 k, 5%
2
R24, R25
2
R27, R29
2
1
SOT−223
TMC1AE1A−
D107MLRH
TMC1VE1A−
D226MLRH
−
−
516−435−1110
516−435−1824
−
−
CENTRAL
CZT3019
516−435−1110
516−435−1824
603
KOA
RM73B1J512J
714−751−1185
714−432−7365
2.0 k, 1%
603
KOA
RK73H1JT2001F
714−751−1185
714−432−7365
10 Ω, 5%
1206
KOA
RM73B2T100J
714−751−1185
714−432−7365
R36, R76
1.0 k, 5%
603
KOA
RM73B1JT102J
714−751−1185
714−432−7365
R39
200 k, 1%
805
KOA
RK73H2AT2003F
714−751−1185
714−432−7365
1
R38
10 Ω, 5%
603
KOA
RM73B1JT100J
714−751−1185
714−432−7365
1
R40
2.49 k, 1%
603
KOA
RK73H1JT2491F
714−751−1185
714−432−7365
1
R41
51 k, 5%
1206
KOA
RM73B2BT513J
714−751−1185
714−432−7365
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12
CS51021ADEMO/D
DEMONSTRATION BOARD BILL OF MATERIALS (continued)
Qty
Ref. Des.
Description
Pkg.
Manufacturer
Manuf. P/N
Phone
Fax
DC/DC Converter
1
R42
24.3 k, 1%
603
KOA
RK73H1JT2432F
714−751−1185
714−432−7365
2
R43, R45
6.98 k, 1%
603
KOA
RK73H1JT6981F
714−751−1185
714−432−7365
1
R46
100 Ω, 5%
603
KOA
RM73B1JT101J
714−751−1185
714−432−7365
3
R6, R44, R75
10 k, 5%
603
KOA
RM73B1JT103J
714−751−1185
714−432−7365
1
R74
62 Ω, 5%
603
KOA
RM73B1JT181J
714−751−1185
714−432−7365
1
R77
100 Ω, 5%
1206
Panasonic
ERJ8GEYJ101V
−
−
1
R78
22 k, 5%
603
KOA
RM73B1JT223J
714−751−1185
714−432−7365
1
R9
180 Ω, 5%
603
KOA
RM73B1JT181J
714−751−1185
714−432−7365
1
T1
25 W Pwr. Xfmr. 4:1
−
Pulse Engineering
P0513
−
−
1
T2
8 μH coil w/overwind,
100:1
−
XFRMS/spi
S26−10009
−
−
1
T3
ISENSE Xfmr, 2:5
−
GB Int’l
2405−J
607−785−938
607−785−1109
1
U1
CS51021AD16
SO−16
ON Semiconductor
CS51021AD16
1
U2
Optocoupler
SO−6
ON Semiconductor
MOC8102S
1
U3
Adjustable Reference
Zetex
ZR431FCT
−
−
−
Winpoint
201−01−S−3−02−T
−
−
218−681−3380
SOT−23
Test Components
5
TP1−TP5
1 Pin Header/Test
Point
1
J10
BNC Connector
BNC
Digi−Key
DKARKF1066ND
218−681−6674
5
J1−J3, J5, J9
Turret Terminal
Turret
MillMax
2501−1−00−44−
00−00−07−0
−
1
U4
LM555 Timer
SO−8
National Semi
LM555
−
19
R2, R3, R5,
R7, R8, R11,
R48−R55
3W
KOA
SPR3180J
−
4
S1−S4
−
1
Q3
2
2
18 Ω, 5%,
3 W Wirewound
SPDT Toggle
C&K
7101SDGCQE
MOSFET, 0.011 mΩ
SO−8
Int’l Rectifier
IRF7413
R57, R58
10 Ω, 5%
0805
Panasonic
ERJ6GEY100V
−
−
R56, R59
2.0 k, 5%
0805
KOA
RM73B2AT202J
714−751−1185
714−432−7365
1
R60
13 k, 5%
0805
KOA
RM73B2AT133J
714−751−1185
714−432−7365
3
C50−C52
0.1 μF, 25 V x7r cap
0805
Novacap
805−295−5920
805−295−5928
http://onsemi.com
13
−
617−527−6400
617−527−3062
−
−
CS51021ADEMO/D
RESULTS AND WAVEFORMS
EFFICIENCY MEASUREMENTS
VIN
IIN
50
50
THERMAL DATA: BOARD UNDER LOAD*
VOUT
IOUT
Efficiency
0.095
4.99
0.5
52%
0.319
4.986
2.5
78%
50
0.621
4.983
5.0
80%
65
0.079
4.988
0.5
48.6%
65
0.251
4.982
2.5
76.3%
65
0.478
4.98
5.0
80.1%
ILOAD =
75 mA
ILOAD =
5.0 A
ILOAD =
5.0 A
VIN = 48 V
VIN = 36 V
VIN = 72 V
T1
50°C
98°C
102°C
T2
31°C
102°C
103°C
T3
38°C
66°C
74°C
Q1 (IRF634)
35°C
76°C
75°C
D6 (MBR82060CT)
33°C
114°C
112°C
U1 (CS51021A)
35°C
55°C
55°C
C38
35°C
61°C
61°C
TA = 235C
*Board should only be run with dynamic load at elevated
temperatures.
100
Efficiency (%)
80
60
40
20
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Current (A)
Figure 12. Efficiency
Figure 13. Channel 1 Gate Drive, Channel 2 VSlope
Figure 14. Channel 1 Gate Drive, Channel 2 Vds
Reset Pulse
Figure 15. VOUT During Load Transient from 0.5 A to 5.0 A
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14
CS51021ADEMO/D
The Bode plots for the finished circuit are shown in Figures 16 through 19. These were measured using the Venable Industries
Model 260 Frequency Response Analyzer and plotted in Microsoft® Excel.
180
Gain (dB)/Phase (degrees)
135
90
Phase
45
Gain
0
Gain
−45
−90
−135
Phase
−180
1,000
10,000
100,000
1,000,000
Frequency (Hz)
Figure 16. CS51022A Gain and Phase at Half Load (2.5 A)
180
Gain (dB)/Phase (degrees)
135
Phase
90
45
Gain
0
Gain
−45
−90
−135
Phase
−180
1,000
10,000
100,000
1,000,000
Frequency (Hz)
Figure 17. CS51022A Gain and Phase at Minimum Load (500 mA)
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15
CS51021ADEMO/D
180
Gain (dB)/Phase (degrees)
135
90
Phase
45
Gain
0
Gain
−45
−90
−135
Phase
−180
1,000
10,000
100,000
1,000,000
Frequency (Hz)
Figure 18. CS51022A Gain and Phase at Full Load (5.0 A)
50
Gain Half
40
Gain Full
30
Gain Min
Gain (dB)
20
10
0
−10
−20
Gain Full
−30
Gain Half
−40
−50
Gain Min
1,000
10,000
100,000
Frequency (Hz)
Figure 19. CS51022A Gain Plots for Different Loads
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16
1,000,000
CS51021ADEMO/D
Figure 20. Startup
Figure 21. Min. Load Condition
Figure 22. Half Load
Figure 23. Half Load Showing I Probe
Figure 24. Full Load
Figure 25. Transient Response Min. to 2.5 A
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17
CS51021ADEMO/D
Figure 26. Short Circuit Condition
Figure 27. Transient Response 2.5 A to Min. Load
ELTest (Automated Power Supply Test System) Performance Graphs
0.9
5.00
0.7
4.98
(V)
(A)
4.96
0.5
4.94
0.3
4.92
0.1
0.1
1.325
2.55
(A)
3.775
4.90
0.1
5.0
Figure 28. Input Current vs Load
1.325
2.55
(A)
3.775
Figure 29. Load Regulation
http://onsemi.com
18
5.0
CS51021ADEMO/D
Figure 30. PC Board Layout
Figure 31. Component Side Copper
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19
CS51021ADEMO/D
Figure 32. Solder Side Copper
Microsoft is a registered trademark of Microsoft Corporation in the United States and/or other countries.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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CS51021ADEMO/D
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