BGU7062N2 Analog high linearity low noise variable gain amplifier Rev. 1 — 8 July 2013 Product data sheet 1. Product profile 1.1 General description The BGU7062N2 is a fully integrated analog-controlled variable gain amplifier module. Its low noise and high linearity performance makes it ideal for sensitive receivers in cellular base station applications. The BGU7062N2 is designed for the 1710 MHz to 1785 MHz frequency range. It has a gain control range of more than 35 dB. At maximum gain the noise figure is 0.77 dB. The gain is analog-controlled having maximum gain at 0 V and minimum gain at 3.3 V. The LNA can be bypassed extending the dynamic range. The BGU7062N2 is internally matched to 50 ohm, meaning no external matching is required, enabling ease of use. It is housed in a 16 pins 8 mm 8 mm 1.3 mm leadless HLQFN16R package SOT1301. 1.2 Features and benefits Input and output internally matched to 50 Low noise figure of 0.77 dB High IP3i of 1 dBm High Pi(1dB) of 12.3 dBm Bypass mode of LNA giving high dynamic gain range Gain control range of 0 dB to 35 dB Single 5 V supply Single analog gain control of 0 V to 3.3 V Unconditionally stable up to 12.75 GHz Moisture sensitivity level 3 ESD protection at all pins 1.3 Applications Cellular base stations, remote radio heads 3G, LTE infrastructure Low noise applications with variable gain and high linearity requirements Active antenna BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier 1.4 Quick reference data Table 1. Quick reference data VCC1 = 5 V; VCC2 = 5 V; f = 1750 MHz; Tamb = 25 C; input and output 50 ; unless otherwise specified. Symbol Parameter ICC(tot) NF Conditions total supply current noise figure Min Typ Max Unit high gain mode [1] 190 215 250 mA low gain mode [2] 165 185 215 mA Vctrl(Gp) = 0 V (maximum power gain) [1] - 0.77 - dB Gp = 35 dB [1] - 0.94 1.1 dB 0 1.0 - dBm 14 12.3 - dBm IP3i input third-order intercept point Gp = 35 dB; 2-tone; tone-spacing = 1.0 MHz [1] Pi(1dB) input power at 1 dB gain compression Gp = 35 dB [1] [1] high gain mode: GS1 = LOW; GS2 = HIGH (see Table 9) [2] low gain mode: GS1 = HIGH; GS2 = LOW (see Table 9) 2. Pinning information *1' 9&& 9&& *1' WHUPLQDO LQGH[DUHD 2.1 Pinning *6 QF QF 9FWUO*S *1' LF QF *1' 5)B287 *6 QF 5)B,1 DDD 7UDQVSDUHQWWRSYLHZ Fig 1. Pin configuration 2.2 Pin description Table 2. BGU7062N2 Product data sheet Pin description Symbol Pin Description RF_IN 1 RF input GND 2, 11, 13, 16 ground GS1 3 gain switch control 1 n.c. 4, 5, 7, 10 not connected, internally open All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 July 2013 © NXP B.V. 2013. All rights reserved. 2 of 16 BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier Table 2. Pin description …continued Symbol Pin Description GS2 6 gain switch control 2 i.c. 8 internally connected to ground Vctrl(Gp) 9 power gain control voltage RF_OUT 12 RF output VCC2 14 supply voltage 2 VCC1 15 supply voltage 1 3. Ordering information Table 3. Ordering information Type number Package Name BGU7062N2 Description Version HLQFN16R plastic thermal enhanced low profile quad flat package; SOT1301-1 no leads; 16 terminals; body 8 8 1.3 mm 5)B,1 9&& 9&& *1' WHUPLQDO LQGH[DUHD *1' 4. Functional diagram 5)B287 *1' %<3$663$7+ *1' *6 QF QF 9FWUO*S 9*$ QF *6 QF LF /1$ DDD Fig 2. BGU7062N2 Product data sheet Functional diagram All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 July 2013 © NXP B.V. 2013. All rights reserved. 3 of 16 BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier 5. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0 6 V Vctrl(Gp) power gain control voltage 1 +3.6 V VI(GS1) input voltage on pin GS1 1 +3.6 V VI(GS2) input voltage on pin GS2 1 +3.6 V - 10 dBm Pi(RF)CW continuous waveform RF input power high gain mode; Vctrl(Gp) = 0 V; 1710 MHz f 1785 MHz [1] low gain mode; Vctrl(Gp) = 0 V; 1710 MHz f 1785 MHz [2] - 15 dBm Tj junction temperature - 150 C Tstg storage temperature 40 +150 C VESD electrostatic discharge voltage Human Body Model (HBM); according to ANSI/ESDA-JEDEC JS-001-2010-Device Testing, Human Body Model - 2 - 750 V Charged Device Model (CDM); according to JEDEC standard 22-C101 [1] high gain mode: GS1 = LOW; GS2 = HIGH (see Table 9) [2] low gain mode: GS1 = HIGH; GS2 = LOW (see Table 9) kV 6. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC1 Conditions Min Typ Max Unit supply voltage 1 4.75 5 5.25 V VCC2 supply voltage 2 4.75 5 5.25 V Vctrl(Gp) power gain control voltage 0 - 3.3 V VI(GS1) input voltage on pin GS1 0 - 3.3 V VI(GS2) input voltage on pin GS2 0 - 3.3 V Z0 characteristic impedance - 50 - Tcase case temperature 40 - +85 C 7. Thermal characteristics Table 6. Symbol Rth(j-case) [1] BGU7062N2 Product data sheet Thermal characteristics Parameter Conditions thermal resistance from junction to case [1] Typ Unit 42 K/W The case temperature is measured at the ground solder pad. All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 July 2013 © NXP B.V. 2013. All rights reserved. 4 of 16 BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier 8. Characteristics Table 7. Characteristics high gain mode GS1 = LOW; GS2 = HIGH (see Table 9); VCC1 = 5 V; VCC2 = 5 V; f = 1750 MHz; Tamb = 25 C; input and output 50 ; unless otherwise specified. All RF parameters have been characterized at the device RF input and RF output terminals. Symbol Parameter Conditions Min Typ Max Unit ICC(tot) total supply current 190 215 250 mA Gp(min) minimum power gain Vctrl(Gp) = 3.3 V - 13.3 - dB Gp(max) maximum power gain Vctrl(Gp) = 0 V - 37.2 - dB Gp(flat) power gain flatness 1710 MHz f 1785 MHz; 18 dB Gp 35 dB - 0.3 - dB NF noise figure Vctrl(Gp) = 0 V (maximum power gain) - 0.77 - dB Gp = 35 dB - 0.94 1.1 dB Gp = 18 dB - 5.95 - dB Gp = 35 dB 0 1.0 - dBm Gp = 30 dB - 3.6 - dBm Gp = 29 dB - 4.0 - dBm Gp = 18 dB - 4.6 - dBm IP3i Pi(1dB) RLin input third-order intercept point input power at 1 dB gain compression input return loss 2-tone; tone-spacing = 1.0 MHz Gp = 35 dB 14 12.3 - dBm Gp = 30 dB - 7.2 - dBm Gp = 29 dB - 6.8 - dBm Gp = 18 dB - 6.1 - dBm Vctrl(Gp) = 0 V (maximum power gain) - 24.9 - dB Gp = 35 dB - 23.5 - dB dB RLout output return loss Vctrl(Gp) = 0 V (maximum power gain) - 17.5 - K Rollett stability factor 0 GHz f 12.75 GHz 1 - - Table 8. Characteristics low gain mode GS1 = HIGH; GS2 = LOW (see Table 9); VCC1 = 5 V; VCC2 = 5 V; f = 1750 MHz; Tamb = 25 C; input and output 50 ; unless otherwise specified. All RF parameters have been characterized at the device RF input and RF output terminals. Symbol Parameter Conditions Min Typ Max Unit 165 185 ICC(tot) total supply current 215 mA Gp(min) minimum power gain Vctrl(Gp) = 3.3 V - 6.5 - dB Gp(max) maximum power gain Vctrl(Gp) = 0 V - 18.0 - dB Gp(flat) power gain flatness 1710 MHz f 1785 MHz; 3 dB Gp 17 dB - 0.2 - dB NF noise figure Gp = 17 dB - 10.5 - dB Gp = 3 dB - 22.1 - dB IP3i input third-order intercept point BGU7062N2 Product data sheet 2-tone; tone-spacing = 1.0 MHz - Gp = 17 dB - 20.9 - dBm Gp = 12 dB - 25.1 - dBm Gp = 11 dB - 25.9 - dBm Gp = 3 dB - 30.0 - dBm All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 July 2013 © NXP B.V. 2013. All rights reserved. 5 of 16 BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier Table 8. Characteristics low gain mode …continued GS1 = HIGH; GS2 = LOW (see Table 9); VCC1 = 5 V; VCC2 = 5 V; f = 1750 MHz; Tamb = 25 C; input and output 50 ; unless otherwise specified. All RF parameters have been characterized at the device RF input and RF output terminals. Symbol Parameter Pi(1dB) Conditions Min Typ Max Unit input power at 1 dB gain compression Gp = 17 dB - 5.8 - Gp = 12 dB - 9.9 - dBm Gp = 11 dB - 10.3 - dBm Gp = 3 dB - 10.9 - dBm - dB dBm RLin input return loss Vctrl(Gp) = 0 V (maximum power gain) - 19.3 Gp = 17 dB - 22 - dB RLout output return loss Vctrl(Gp) = 0 V (maximum power gain) - 17.3 - dB K Rollett stability factor 0 GHz f 12.75 GHz 1 - - Table 9. Gain switch truth table VCC1 = 5 V; VCC2 = 5 V; 40 C Tamb +85 C Gain mode GS1 GS2 logic VGS1 logic VGS2 high gain mode LOW 0 V to 0.5 V HIGH 2 V to 3.3 V low gain mode HIGH 2 V to 3.3 V LOW 0 V to 0.5 V 8.1 Graphs DDD DDD *S G% *S G% I*+] GS1 = LOW; GS2 = HIGH; VCC1 = 5 V; VCC2 = 5 V; Vctrl(Gp) = 0 V. (1) Tamb = 40 C (2) Tamb = +25 C (2) Tamb = +25 C (3) Tamb = +85 C (3) Tamb = +85 C Power gain as a function of frequency in high gain mode; typical values BGU7062N2 Product data sheet I*+] GS1 = HIGH; GS2 = LOW; VCC1 = 5 V; VCC2 = 5 V; Vctrl(Gp) = 0 V. (1) Tamb = 40 C Fig 3. Fig 4. Power gain as a function of frequency in low gain mode; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 July 2013 © NXP B.V. 2013. All rights reserved. 6 of 16 BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier DDD DDD 5/LQ G% 5/LQ G% I*+] (2) Tamb = +25 C (3) Tamb = +85 C (3) Tamb = +85 C Input return loss as a function of frequency in high gain mode; typical values DDD VSDUV G% Fig 6. DDD 6 6 6 6 6 6 I*+] GS1 = LOW; GS2 = HIGH; VCC1 = 5 V; VCC2 = 5 V; Vctrl(Gp) = 0 V; Tamb = 25 C. Fig 7. I*+] Input return loss as a function of frequency in low gain mode; typical values VSDUV G% (1) Tamb = 40 C (2) Tamb = +25 C Fig 5. GS1 = HIGH; GS2 = LOW; VCC1 = 5 V; VCC2 = 5 V; Vctrl(Gp) = 0 V. GS1 = LOW; GS2 = HIGH; VCC1 = 5 V; VCC2 = 5 V; Vctrl(Gp) = 0 V. (1) Tamb = 40 C S-parameters as a function of frequency in high gain mode; typical values BGU7062N2 Product data sheet I*+] GS1 = HIGH; GS2 = LOW; VCC1 = 5 V; VCC2 = 5 V; Vctrl(Gp) = 0 V; Tamb = 25 C. Fig 8. S-parameters as a function of frequency in low gain mode; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 July 2013 © NXP B.V. 2013. All rights reserved. 7 of 16 BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier DDD DDD . . I*+] (2) Tamb = +25 C (3) Tamb = +85 C (3) Tamb = +85 C Rollet stability factor as a function of frequency in high gain mode; typical values DDD ,3, G%P I*+] (1) Tamb = 40 C (2) Tamb = +25 C Fig 9. GS1 = HIGH; GS2 = LOW; VCC1 = 5 V; VCC2 = 5 V; Vctrl(Gp) = 0 V. GS1 = LOW; GS2 = HIGH; VCC1 = 5 V; VCC2 = 5 V; Vctrl(Gp) = 0 V. (1) Tamb = 40 C Fig 10. Rollet stability factor as a function of frequency in low gain mode; typical values DDD ,3, G%P *SG% GS1 = LOW; GS2 = HIGH; VCC1 = 5 V; VCC2 = 5 V; f = 1750 MHz. (1) Tamb = 40 C *SG% (1) Tamb = 40 C (2) Tamb = +25 C (3) Tamb = +85 C (3) Tamb = +85 C Fig 11. Input third-order intercept point as a function of power gain in high gain mode; typical values Product data sheet GS1 = HIGH; GS2 = LOW; VCC1 = 5 V; VCC2 = 5 V; f = 1750 MHz. (2) Tamb = +25 C BGU7062N2 Fig 12. Input third-order intercept point as a function of power gain in low gain mode; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 July 2013 © NXP B.V. 2013. All rights reserved. 8 of 16 BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier DDD 3LG% G%P DDD 3LG% G%P *SG% *SG% GS1 = HIGH; GS2 = LOW; VCC1 = 5 V; VCC2 = 5 V; f = 1750 MHz. GS1 = LOW; GS2 = HIGH; VCC1 = 5 V; VCC2 = 5 V; f = 1750 MHz. (1) Tamb = 40 C (1) Tamb = 40 C (2) Tamb = +25 C (2) Tamb = +25 C (3) Tamb = +85 C (3) Tamb = +85 C Fig 13. Input power at 1 dB gain compression as a function of power gain in high gain mode; typical values Fig 14. Input power at 1 dB gain compression as a function of power gain in low gain mode; typical values DDD DDD 1) G% 1) G% *SG% (2) Tamb = +25 C (3) Tamb = +85 C (3) Tamb = +85 C Fig 15. Noise figure as a function of power gain in high gain mode; typical values Product data sheet *SG% (1) Tamb = 40 C (2) Tamb = +25 C BGU7062N2 GS1 = HIGH; GS2 = LOW; VCC1 = 5 V; VCC2 = 5 V; f = 1750 MHz. GS1 = LOW; GS2 = HIGH; VCC1 = 5 V; VCC2 = 5 V; f = 1750 MHz. (1) Tamb = 40 C Fig 16. Noise figure as a function of power gain in low gain mode; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 July 2013 © NXP B.V. 2013. All rights reserved. 9 of 16 BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier DDD DDD *S G% *S G% 9FWUO*S9 9FWUO*S9 GS1 = HIGH; GS2 = LOW; VCC1 = 5 V; VCC2 = 5 V; f = 1750 MHz. GS1 = LOW; GS2 = HIGH; VCC1 = 5 V; VCC2 = 5 V; f = 1750 MHz. (1) Tamb = 40 C (1) Tamb = 40 C (2) Tamb = +25 C (2) Tamb = +25 C (3) Tamb = +85 C (3) Tamb = +85 C Fig 17. Power gain as a function of power gain control voltage in high gain mode; typical values Fig 18. Power gain as a function of power gain control voltage in low gain mode; typical values 9. Application information Table 10. List of components For application circuit see Figure 19. Component BGU7062N2 Product data sheet Description Value Remarks C1, C2 capacitor 1 nF [1] C3, C4, C5, C6, C12 capacitor 100 pF [1] 0402 C7, C8, C9, C10, capacitor optional C11, C17 capacitor 100 nF [1] 0402 C13, C14, C15, C16 capacitor optional L1, L2 inductor 10 nH [2] 0402 [1] Murata GRM1555 series. [2] Murata LQG15 series. All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 July 2013 0402 © NXP B.V. 2013. All rights reserved. 10 of 16 BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier 9&& 9&& & & / & & & & & & & & & 5)B,1387 & *1' *1' 9&& / 9&& & 5)B287387 & 5)B287 5)B,1 %<3$663$7+ *1' *DLQB6ZLWFKBFRQWURO 9*$ /1$ *6 *1' QF & QF 9FWUO*S *DLQBFWUO & *6 LF QF QF & *DLQB6ZLWFKBFRQWURO DDD See Table 10 for a list of components. Fig 19. Schematic layout for application circuit BGU7062N2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 July 2013 © NXP B.V. 2013. All rights reserved. 11 of 16 BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier 10. Package outline HLQFN16R: plastic thermal enhanced low profile quad flat package; no leads; 16 terminals; body 8 x 8 x 1.3 mm B D SOT1301-1 A terminal 1 index area A E detail X e1 C 1/2 e b e L1 5 C A B C Øv Øw 8 y y1 C L 9 4 e Eh e2 1/2 e 1 12 terminal 1 index area 16 13 X Dh 0 5 mm scale Dimensions Unit mm A b max 1.40 0.75 nom 1.30 0.70 min 1.25 0.65 D Dh E 8.1 8.0 7.9 5.85 5.80 5.75 8.1 8.0 7.9 Eh e e1 e2 L L1 0.75 0.15 5.85 5.80 1.42 4.26 4.26 0.70 0.10 5.75 0.65 0.05 v 0.1 w y 0.05 0.08 y1 0.1 sot1301-1_po Outline version References IEC JEDEC JEITA European projection Issue date 11-08-23 11-08-29 SOT1301-1 Fig 20. Package outline SOT1301-1 (HLQFN16R) BGU7062N2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 July 2013 © NXP B.V. 2013. All rights reserved. 12 of 16 BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier 11. Abbreviations Table 11. Abbreviations Acronym Description 3G 3rd Generation ESD ElectroStatic Discharge LNA Low Noise Amplifier LTE Long Term Evolution 12. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes BGU7062N2 v.1 20130708 Product data sheet - - BGU7062N2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 July 2013 © NXP B.V. 2013. All rights reserved. 13 of 16 BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 13.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. BGU7062N2 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 July 2013 © NXP B.V. 2013. All rights reserved. 14 of 16 BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] BGU7062N2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 8 July 2013 © NXP B.V. 2013. All rights reserved. 15 of 16 BGU7062N2 NXP Semiconductors Analog high linearity low noise variable gain amplifier 15. Contents 1 1.1 1.2 1.3 1.4 2 2.1 2.2 3 4 5 6 7 8 8.1 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Thermal characteristics . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 8 July 2013 Document identifier: BGU7062N2