AC415: Migrating Designs Between SmartFusion2 M2S025 and M2S050 in VF400 Package

Application Note AC415
Migrating Designs Between SmartFusion2 M2S025
and M2S050 in VF400 Package
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Design Migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Design and Device Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
I/O Banks and Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Migration and Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Power Supply and Board-Level Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Software Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Introduction
This document describes how to migrate designs within the SmartFusion®2 system-on-chip (SoC) field
programmable gate array (FPGA) device family between the M2S025 and M2S050 devices within the
VF400 package. It addresses restrictions and specifications that need to be considered while moving a
design between M2S025 and M2S050. This includes pin compatibility between the devices, design and
device resources evaluation, I/O banks, standards, and so on. This document also describes the
software flow behavior during the migration.
Design Migration
SmartFusion2 family devices are architecturally compatible with each other. However, attention must be
paid to some key areas while migrating a design from one device to another. The following specific points
are discussed in this document:
•
Design and Device Evaluation
•
I/O Banks and Standards
•
Pin Migration and Compatibility
•
Power Supply and Board-Level Considerations
•
Software Flow
Design and Device Evaluation
One of the initial and main tasks while migrating a design should be to compare the available resources
between the two devices. The device resources can be grouped into three different categories:
•
Microcontroller Subsystem
•
Fabric Resources
•
On-Chip Oscillators
In addition, necessary design timing analysis and simulations should be performed while migrating
designs from one device to another.
Each of the following sections focuses on the different aspects of the design and device evaluation
categories.
February 2014
© 2014 Microsemi Corporation
1
Migrating Designs Between SmartFusion2 M2S025 and M2S050 in VF400 Package
Microcontroller Subsystem
Table 1 provides a high-level summary of the differences between the M2S025 and M2S050 MSS
blocks. Based on the different MSS resources and features, migration from one device to another can be
planned to avoid any resource conflicts or issues.
Table 1 • MSS Features Per Package or Device
VF400 Package
Feature
M2S025 and M2S025T
M2S050 and M2S050T
ARM®
Yes
Yes
Fabric interfaces (FIC)
1 (FIC_0)
2 (FIC_0 and FIC_1)
MSS DDR (MDDR)
X181
X182
eNVM (Kbytes)
256
256
eSRAM (Kbytes)
64
64
Cortex™-M3 processor +
instruction cache
eSRAM (non-SECDED) (Kbytes)
80
80
CAN, 10/100/1000 Ethernet
1
1
High-speed USB
1 (UTMI or ULPI)
-
Multi-Mode UART, SPI, I2C, Timer 2
2
SDRAM through SMC_FIC
Yes (AXI or AHBLite Interfaces)
Yes (AHBLite interface only)
Notes:
1. DDR supports x18, x16, x9, and x8 modes
2. DDR supports x18 and x16 modes
The following sections highlight the differences in the MSS supported features within the two
SmartFusion2 devices.
Soft Memory Controller (SMC) Fabric Interface (SMC_FIC)
MSS, as a master, through the SMC_FIC and an SMC in the FPGA fabric can access external bulk
memories other than the DDR, such as SDRAM. Instantiate a soft AMBA high-performance bus (AHB) or
advanced extensible interface (AXI) SDRAM memory controller in the FPGA fabric and connect I/O ports
to 3.3 V MSIO.
The SMC_FIC can be configured using the MDDR configurator part of the MSS to use either an AXI
64-bit bus interface or a single 32-bit AHB-Lite (AHBL) bus interface. The M2S025 device only supports
the AHBLite interface. For vertical migration between the M2S025 and M2S050 devices, design using
the common AHBL SMC_FIC interface configuration to avoid any conflicts or issues .
USB Controller
USB is not supported on M2S050 devices.
The USB controller provides two types of interfaces: UTMI and ULPI. The USB ULPI interface is
connected to four separate groups of MSIO pads on the device. Depending on the size of the device, the
group is labeled as ULPI (I/Os) A, ULPI (I/Os) B, ULPI (I/Os) C, and ULPI (I/Os) D interfaces. The set of
signals available in each of the four alternative I/O sets are the same. The USB I/Os are overlaid and
common with other MSS peripherals. The different sets of I/Os groups are provided to maximize the
flexibility of having the USB operational in the system, regardless of the other MSS peripherals.
Table 2 shows a summary of the different supported interfaces between M2S025 and M2S050 in the
VF400 package.
Table 2 • USB Supported Interfaces Per Device
VF400 Package
2
Device
ULPI (I/Os) A
ULPI (I/Os) B
ULPI (I/Os) C
ULPI (I/Os) D
UTMI
M2S025
Yes
Yes
Yes
No
Yes
M2S050
No
No
No
No
No
Design Migration
Fabric Resources
Table 3 gives a high-level summary of the differences between M2S025 and M2S050 fabric resources.
Based on the differences, effective logic count, RAM size, and number of I/Os, migration can be
evaluated and planned from one device to another without any resource conflicts or issues.
Table 3 • Summary of the Fabric Features Supported Per Device
VF400 Package
M2S025 and
M2S025T
Fabric Features (Logic, DSP, and Memory)
Logic/DSP
Logic Modules
M2S050 and
M2S050T
27,696
56,340
Mathblocks
34
72
PLLs and CCCs
6
6
(4-Input LUT)
Fabric Memory
User I/Os
LSRAM 18 K blocks
31
69
uSRAM 1K blocks
34
72
MSIO (3.3 V max)
111
87
MSIOD (2.5 V max)
32
32
DDRIO (2.5 V max)
64
88
Total user I/Os per package
207
207
On-Chip Oscillators
Table 4 shows the summary of SmartFusion2 on-chip oscillators that are the primary sources for
generating free-running clocks.
Table 4 • On-Chip Oscillator Support Per Device
VF400 Package
Feature
M2S025
M2S050
1 MHz RC oscillator
1
1
50 MHz RC oscillator
1
1
Main crystal oscillator (32 KHz - 20 MHz)
1
1
Auxiliary crystal oscillator (32 KHz - 20 MHz)
1
-
The auxiliary crystal oscillator is dedicated for real-time counter (RTC) clocking as an alternative clock
source. Refer to the SmartFusion2 Clocking Resources User’s Guide for more information.
I/O Banks and Standards
SmartFusion2 I/Os are partitioned into multiple I/O voltage banks. The number of banks depends on the
device. There are seven(7) I/O banks in M2S025 and eight(8) I/O banks in the M2S050 device. Table 5
shows a summary of organization of the I/O banks between M2S025 and M2S050 FPGA devices.
Table 5 • Organization of the I/O Banks in SmartFusion2 Devices
VF400 Package
I/O Banks
M2S025T
M2S050T
Bank 0
DDRIO: MDDR or fabric
DDRIO: MDDR or fabric
Bank 1
MSIO: MSS or fabric
MSIO: MSS or fabric
Bank 2
MSIO: MSS or fabric
–
Bank 3
MSIO: JTAG/SWD
MSIO: MSS or fabric
Bank 4
MSIO: fabric
MSIO: JTAG/SWD
3
Migrating Designs Between SmartFusion2 M2S025 and M2S050 in VF400 Package
Table 5 • Organization of the I/O Banks in SmartFusion2 Devices
VF400 Package
I/O Banks
M2S025T
M2S050T
Bank 5
MSIOD: SERDES_0 or fabric
DDRIO: fabric
Bank 6
MSIOD: fabric
MSIOD: SERDES_0 or fabric
Bank 7
MSIO: fabric
MSIOD: fabric
Bank 8
–
MSIO: fabric
Package pins VDDIx are the bank power supplies where x indicates the bank number. For example,
VDDI0 is bank0 power supply. Figure 1 and Figure 2 on page 4 show the different I/O bank locations and
numbers per device in the VF400 package.
Bank 0
DDRIO/MDDR
(32 pairs)
Bank 8
MSIO
(11 pairs)
Bank 7
MSIOD
(14 pairs)
North
West
Bank 6
MSIOD/SERDES
(2 pairs)
SmartFusion2
SoC FPGA
M2S050T-VF400
Bank 1
MSIO
(10 pairs)
East
Bank 3
MSIO
(22 pairs)
Bank 4
JTAG
South
Bank 5
DDRIO
(12 pairs)
Figure 1 • SmartFusion2 M2S050T VF400 I/O Bank Locations
Bank 0
DDRIO/MDDR
(32 pairs)
Bank 7
MSIO
(11pairs)
Bank 6
MSIOD
(14 pairs)
Bank 5
MSIOD/SERDES
(2 pairs)
North
West
SmartFusion2
SoC FPGA
M2S025T-VF400
South
Bank 4
MSIO
(12 pairs)
Figure 2 • SmartFusion2 M2S025T VF400 I/O Bank Locations
4
Bank 1
MSIO
(10 pairs)
East
Bank 2
MSIO
(22 pairs)
Bank 3
JTAG
Design Migration
An MSIO bank supports 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V voltage standards. MSIOD or DDRIO bank
supports 1.2 V, 1.5 V, 1.8 V, or 2.5 V voltage standards. The 3.3 V voltage standard is not supported for
MSIOD or DDRIO I/Os. For more details on user I/O pins (MSIO, MSIOD, and DDRIO) and supported
voltage standards, refer to the "Supported Voltage Standards" table in the SmartFusion2 FPGA Fabric
Architecture User's Guide.
Pin Migration and Compatibility
Although the SmartFusion2 devices and packaging have been designed to allow footprint compatibility
for smoother migration, some of the pins have a reduced compatibility feature set between M2S025 and
M2S050 devices in the VF400 package. This section addresses the different aspects of pin compatibility.
The differences can be grouped into three categories:
•
Global Versus Regular Pins
•
Available versus No Connect Pins
•
I/Os Technology Compatibility Per Pin or Bank
•
Oscillator Pins
•
Probe Pins
Global Versus Regular Pins
When migrating designs between SmartFusion2 devices, it is important to evaluate the different types of
pins that are available per device. The functionality of the same pin can be different between devices.
This section focuses on highlighting and comparing the global pins in one device against the other
devices. Therefore, migration can be evaluated and planned from one device to another without any
resource conflicts or issues.
•
Moving from a device, where the I/O is a global pin to a device where the same I/O is a regular
pin. In this case, replace the global clock (for example, CLKBUF) with a regular input buffer (for
example, INBUF) and then internally promote the signal to a global resource using a CLKINT or
synthesis options.
•
Moving from a device, where the I/O is a regular pin to a device where the same I/O is a global
pin. In this case, replace the INBUF with a CLKBUF or keep the INBUF and internally promote the
signal to a global using a CLKINT or synthesis options.
Table 6 provides a comparison between the global pins available in M2S025 and M2S050 devices. The
unused global pins are configured as inputs with pull-up resistors by Libero® System-on-Chip (SoC)
software.
For more information, refer to the "FPGA Fabric Global Network Architecture" chapter of the
SmartFusion2 Clocking Resources User’s Guide.
Table 6 • Non-Equivalent Global Pins Comparison Per Device
VF400 Pin Names
Package
Pin
M2S025
Bank
No
M2S050
Bank
No
A3
DDRIO62PB0/MDDR_DQ_ECC1
0
DDRIO87PB0/CCC_NW1_CLKI3/
MDDR_DQ_ECC1
0
E6
DDRIO61PB0/CCC_NW1_CLKI3
0
DDRIO88PB0
0
R13
MSIO134PB4/VCCC_SE1_CLKI
4
DDRIO164PB5/VCCC_SE1_CLKI
5
U11
MSIO125NB4/GB7/CCC_SW1_CLKI2
4
DDRIO152NB5/GB7/CCC_SW1_C
LKI2
5
U13
MSIO133PB4/GB15/VCCC_SE1_CLKI
4
DDRIO163PB5/GB15/VCCC_SE1_
CLKI
5
V11
MSIO125PB4/GB3/CCC_SW0_CLKI3
4
DDRIO152PB5/GB3/CCC_SW0_C
LKI3
5
V12
MSIO130PB4/VCCC_SE0_CLKI
4
DDRIO160PB5/VCCC_SE0_CLKI
5
W10
MSIO120NB4/CCC_SW0_CLKI2
4
DDRIO147NB5/CCC_SW0_CLKI2
5
5
Migrating Designs Between SmartFusion2 M2S025 and M2S050 in VF400 Package
Table 6 • Non-Equivalent Global Pins Comparison Per Device (continued)
VF400 Pin Names
Package
Pin
M2S025
Bank
No
W13
MSIO131PB4/GB11/VCCC_SE0_CLKI
4
DDRIO161PB5/GB11/VCCC_SE0_
CLKI
5
Y12
MSIO129PB4/CCC_SW1_CLKI3
4
DDRIO159PB5/CCC_SW1_CLKI3
5
M2S050
Bank
No
Table 7 shows the list of global pins that are similar between the two devices.
Table 7 • Equivalent Global Pins Per Device
VF400 Pin Names
Package
Pin
6
M2S025
Bank
No
M2S050
Bank
No
A1
DDRIO65PB0/GB0/CCC_NW0_
CLKI3
0
DDRIO91PB0/GB0/CCC_NW0_CLKI3
0
A11
DDRIO49PB0/CCC_NE1_CLKI3/
MDDR_DQ14
0
DDRIO75PB0/CCC_NE1_CLKI3/MDDR_
DQ14
0
B1
DDRIO65NB0/GB4/CCC_NW1_
CLKI2
0
DDRIO91NB0/GB4/CCC_NW1_CLKI2
0
B12
DDRIO45NB0/MDDR_CLK_N
0
DDRIO59NB0/MDDR_CLK_N
0
B13
DDRIO45PB0/MDDR_CLK
0
DDRIO59PB0/MDDR_CLK
0
B19
MSIO33NB1/MMUART_0_CLK/
GPIO_29_B/USB_NXT_C
1
MSIO47NB1/MMUART_0_CLK/GPIO_29
_B
1
C9
DDRIO52PB0/GB8/CCC_NE0_C
LKI3/MDDR_DQS1
0
DDRIO78PB0/GB8/CCC_NE0_CLKI3/M
DDR_DQS1
0
D10
DDRIO50PB0/GB12/CCC_NE1_
CLKI2/MDDR_DQ12
0
DDRIO76PB0/GB12/CCC_NE1_CLKI2/M
DDR_DQ12
0
D3
DDRIO66NB0/CCC_NW0_CLKI2
0
DDRIO92NB0/CCC_NW0_CLKI2
0
D9
DDRIO53PB0/CCC_NE0_CLKI2/
MDDR_DQ10
0
DDRIO79PB0/CCC_NE0_CLKI2/MDDR_
DQ10
0
E18
MSIO28PB1/GB14/VCCC_SE1_
CLKI/MMUART_1_CLK/GPIO_2
5_B/USB_DATA4_C
1
MSIO42PB1/GB14/VCCC_SE1_CLKI/M
MUART_1_CLK/GPIO_25_B
1
F19
MSIO26PB1/CCC_NE1_CLKI1/
MMUART_1_RI/GPIO_15_B
1
MSIO40PB1/CCC_NE1_CLKI1/MMUAR
T_1_RI/GPIO_15_B
1
G1
MSIO97PB7/GB2/CCC_NW0_C
LKI1
7
MSIO115PB8/GB2/CCC_NW0_CLKI1
8
G14
MSIO25PB1/CCC_NE0_CLKI1/
MMUART_1_CTS/GPIO_13_B
1
MSIO39PB1/CCC_NE0_CLKI1/MMUAR
T_1_CTS/GPIO_13_B
1
G2
MSIO96PB7/GB6/CCC_NW1_C
LKI1
7
MSIO114PB8/GB6/CCC_NW1_CLKI1
8
H1
MSIOD100PB6/GB5/CCC_SW1_
CLKI1
6
MSIOD118PB7/GB5/CCC_SW1_CLKI1
7
H20
MSIO20NB2/GB13/VCCC_SE1_
CLKI/GPIO_26_A
2
MSIO20NB3/GB13/VCCC_SE1_CLKI/G
PIO_26_A
3
H5
MSIO98PB7/CCC_NW1_CLKI0
7
MSIO116PB8/CCC_NW1_CLKI0
8
J19
MSIO20PB2/GB9/VCCC_SE0_C
LKI/GPIO_25_A
2
MSIO20PB3/GB9/VCCC_SE0_CLKI/GPI 3
O_25_A
Design Migration
Table 7 • Equivalent Global Pins Per Device
VF400 Pin Names
Package
Pin
M2S025
Bank
No
M2S050
Bank
No
J2
MSIOD102PB6/CCC_SW1_CLKI
0
6
MSIOD120PB7/CCC_SW1_CLKI0
7
J4
MSIOD101PB6/GB1/CCC_SW0_
CLKI1
6
MSIOD119PB7/GB1/CCC_SW0_CLKI1
7
J7
MSIO99PB7/CCC_NW0_CLKI0
7
MSIO117PB8/CCC_NW0_CLKI0
8
K7
MSIOD103PB6/CCC_SW0_CLKI
0
6
MSIOD121PB7/CCC_SW0_CLKI0
7
M17
MSIO11NB2/CCC_NE1_CLKI0/I
2C_1_SCL/GPIO_1_A/USB_DAT
A4_A
2
MSIO11NB3/CCC_NE1_CLKI0/I2C_1_S
CL/GPIO_1_A
3
N16
MSIO11PB2/CCC_NE0_CLKI0/I2
C_1_SDA/GPIO_0_A/USB_DAT
A3_A
2
MSIO11PB3/CCC_NE0_CLKI0/I2C_1_S
DA/GPIO_0_A
3
P2
MSIOD119PB5/SERDES_0_REF
CLK1_P
5
MSIOD146PB6/SERDES_0_REFCLK1_
P
6
P3
MSIOD119NB5/SERDES_0_REF
CLK1_N
5
MSIOD146NB6/SERDES_0_REFCLK1_
N
6
R1
MSIOD118PB5/SERDES_0_REF
CLK0_P
5
MSIOD145PB6/SERDES_0_REFCLK0_
P
6
R2
MSIOD118NB5/SERDES_0_REF
CLK0_N
5
MSIOD145NB6/SERDES_0_REFCLK0_
N
6
Refer to the "Dedicated Global I/O Naming Conventions" section in the SmartFusion2 Pin Descriptions.
7
Migrating Designs Between SmartFusion2 M2S025 and M2S050 in VF400 Package
Available versus No Connect Pins
There are pins that have one specific function in one device while those same pins are "no connect" (NC)
in the other device. Table 8 lists the summary of these pins.
For example, pin Y17 functions as the XTLOSC_AUX_EXTAL pin in the M2S025 while it is an NC in the
M2S050 device. Similarly, P13 pin is an NC in the M2S025 but it is a VREF5 pin in the M2S050 device.
When moving from a device, where the I/O is an NC pin to a device where the I/O has a defined
functionality and it is not used. Follow the recommended methods for connecting the unused I/Os
depending on the functionality of that I/O. Refer to "SmartFusion2 Unused Pin Configurations" in the
SmartFusion2 Board Design Guidelines Application Note.
When moving from a device, where the I/O has a defined functionality to a device where the I/O is an NC,
then the NC pins can be driven to any voltage or can be left floating with no effect on the operation of the
device. NC indicates that the pin is not connected to circuitry within the device.
Table 8 • Available versus NC Pins
VF400 Pin Names
Package Pin
M2S025
M2S050
Y17
XTLOSC_AUX_EXTAL
NC
W17
XTLOSC_AUX_XTAL
NC
P13
NC
VREF5
R11
NC
VREF5
I/Os Technology Compatibility Per Pin or Bank
Table 9 shows the list of I/Os that would lead to incompatibility with the different technology support while
migrating between M2S025 and M2S050 within the VF400 package. The difference is the type of I/O
technology (MSIO versus DDRIO) that is supported on those regular I/Os.
Table 9 • I/O Standards Compatibility Per Device or Package Pins
VF400 Pin Names
Package
Pin
8
M2S025
Bank
No
M2S050
Bank
No
R12
MSIO134NB4
4
DDRIO164NB5
5
R13
MSIO134PB4/VCCC_SE1_CLKI
4
DDRIO164PB5/VCCC_SE1_CLKI
5
T13
MSIO133NB4
4
DDRIO163NB5
5
T14
MSIO144PB4
4
DDRIO184PB5
5
T15
MSIO144NB4
4
DDRIO184NB5
5
U11
MSIO125NB4/GB7/CCC_SW1_CL
KI2
4
DDRIO152NB5/GB7/CCC_SW1_CL
KI2
5
U12
MSIO130NB4
4
DDRIO160NB5
5
U13
MSIO133PB4/GB15/VCCC_SE1_C 4
LKI
DDRIO163PB5/GB15/VCCC_SE1_
CLKI
5
U14
MSIO142NB4
4
DDRIO181NB5
5
V11
MSIO125PB4/GB3/CCC_SW0_CL
KI3
4
DDRIO152PB5/GB3/CCC_SW0_CL
KI3
5
V12
MSIO130PB4/VCCC_SE0_CLKI
4
DDRIO160PB5/VCCC_SE0_CLKI
5
V14
MSIO142PB4
4
DDRIO181PB5
5
V15
DDRIO181PB5
4
DDRIO190NB5
5
W10
MSIO120NB4/CCC_SW0_CLKI2
4
DDRIO147NB5/CCC_SW0_CLKI2
5
W12
MSIO121NB4/PROBE_B
DDRIO148NB5/PROBE_B
5
4
Design Migration
Table 9 • I/O Standards Compatibility Per Device or Package Pins (continued)
VF400 Pin Names
Package
Pin
W13
M2S025
Bank
No
Bank
No
M2S050
MSIO131PB4/GB11/VCCC_SE0_C
LKI
4
DDRIO161PB5/GB11/VCCC_SE0_
CLKI
5
W14
MSIO131NB4
4
DDRIO161NB5
5
W15
MSIO146PB4
4
DDRIO190PB5
5
Y10
MSIO120PB4
4
DDRIO147PB5
5
Y11
MSIO121PB4/PROBE_A
4
DDRIO148PB5/PROBE_A
5
Y12
MSIO129PB4/CCC_SW1_CLKI3
4
DDRIO159PB5/CCC_SW1_CLKI3
5
Y13
MSIO129NB4
4
DDRIO159NB5
5
Y15
MSIO145PB4
4
DDRIO187PB5
5
Y16
MSIO145NB4
4
DDRIO187NB5
5
The DDRIOs do not support single ended 3.3 V I/O standards and differential LVPECL, LVDS 3.3 V,
LVDS 2.5 V, RSDS BLVDS, MLVDS, and Mini-LVDS I/O standards, as shown in Table 10. To migrate
between M2S025 and M2S050 successfully, ensure that the correct VDDI power supply is used to power
the equivalent banks. Only I/Os with compatible standards can be assigned to the same bank.
Table 10 • Technology Support Difference Between Different I/O Types
I/O Types
I/O Standards
MSIO
DDRIO
LVTTL 3.3V
Yes
–
LVCMOS 3.3V
Yes
–
PCI
Yes
–
LVCMOS 1.2V
Yes
Yes
LVCMOS 1.5V
Yes
Yes
LVCMOS 1.8V
Yes
Yes
LVCMOS 2.5V
Yes
Yes
HSTL 1.5V
Yes
Yes
SSTL 1.8
Yes
Yes
SSTL 2.5
Yes
Yes
SSTL 2.5 V(DDR1)
Yes
Yes
SSTL 1.8 V(DDR2)
Yes
Yes
SSTL 1.5 V (DDR3)
Yes
Yes
LVPECL (input only)
Yes
–
LVDS 3.3 V
Yes
–
Single-Ended I/O
Voltage-Referenced I/O
Differential I/O
LVDS 2.5 V
Yes
–
RSDS
Yes
–
BLVDS
Yes
–
MLVDS
Yes
–
Mini-LVDS
Yes
–
9
Migrating Designs Between SmartFusion2 M2S025 and M2S050 in VF400 Package
Note: Even though the VDDI might be the same (for example, MSIO 2.5 V and DDRIO 2.5 V), the
attributes and features supported might be different between different I/O types (MSIO versus
DDRIO). Refer to the "I/O Programmable Features" section in the SmartFusion2 FPGA Fabric
Architecture User's Guide for more information on the list of features supported per I/O type.
Oscillator Pins
SmartFusion2 devices include two crystal oscillators, Main crystal oscillator and Auxiliary crystal
oscillator, except the M2S050 devices. SmartFusion2 M2S050 devices do not have an auxiliary crystal
oscillator.
The auxiliary crystal oscillator is dedicated for RTC clocking as an alternative clock source. Both the main
and auxiliary crystal oscillators have two I/O pads, as shown in Table 11, which can be connected
externally to a crystal, a ceramic resonator, or an RC circuit.
When moving from a device, where the I/O is an NC pin to a device where the I/O has a defined
functionality but not used, follow the recommended methods for connecting the unused I/Os depending
on the functionality of that I/O. Refer to "SmartFusion2 Unused Pin Configurations" in the SmartFusion2
Board Design Guidelines Application Note.
When moving from a device, where the I/O has a defined function to a device where the I/O is an NC, the
NC pins can be driven to any voltage or can be left floating with no effect on the operation of the device.
Table 11 • Crystal Oscillator Pins Per Device
VF400 Pin Names
Package Pin
M2S025
M2S050
W17
XTLOSC_AUX_XTAL
NC
Y17
XTLOSC_AUX_EXTAL
NC
Y18
XTLOSC_MAIN_XTAL
XTLOSC_MAIN_XTAL
W18
XTLOSC_MAIN_EXTAL
XTLOSC_MAIN_EXTAL
Probe Pins
Probe pins locations are compatible between the two devices. Table 12 shows the different probe I/Os
location per device within the VF400 package. By default, probe pins are reserved for the probe
functionality. Unreserve these pins by clearing the Reserve Pins for Probes check box in the "Device
I/O Settings" under Project Setting in Libero SoC software. When the pins are not reserved, the probe
I/Os can be used as regular I/Os.
Note: Different I/O technologies are supported on these pins (MSIO versus DDRIO). Refer to "I/Os
Technology Compatibility Per Pin or Bank" on page 8 for more information.
Table 12 • Probe Pins Per Device
VF400 Pin Names
Package
Pin
M2S025
Bank
No
M2S050
Bank
No
W12
MSIO121NB4/PROBE_B
4
DDRIO148NB5/PROBE_B
5
Y11
MSIO121PB4/PROBE_A
4
DDRIO148PB5/PROBE_A
5
Power Supply and Board-Level Considerations
I/O power supply requirements are one of the key aspects to consider for design migrations. Since the
migration is within the SmartFusion2 family, there is no issue regarding the core voltage (VDD), charge
pumps voltage (VPP), and analog sense circuit supply of the eNVM voltage (VPPNVM). The ground pins
(VSS) are also equivalent between M2S025 and M2S050 devices. Refer to the SmartFusion2 Pin
Descriptions for more details. The bank supply voltages VDDI pins must be connected appropriately. All
the bank supplies that are located on the east-side must be powered even if the associated bank I/Os are
not used. Refer to the "Recommendation for Unused Bank Supplies" connections table in the
SmartFusion2 Board Design Guidelines Application Note for more information in case where the specific
banks are not used. An MSIO bank supports 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V voltages and an MSIOD
10
Design Migration
and DDRIO bank supports 1.2 V, 1.5 V, 1.8 V, or 2.5 V voltages. For more details on user I/O pins (MSIO,
MSIOD, and DDRIO) and supported voltage standards, refer to the "Supported Voltage Standards" table
in the SmartFusion2 FPGA Fabric Architecture User's Guide.
The banks have dedicated supplies. Therefore, only I/Os with compatible voltage standards can be
assigned to the same I/O voltage bank. The correct bank supply must be used when migrating between
the different devices per the appropriate voltages (I/O Standards) selected for the bank. Table 13 shows
the different banks power supply compatibility per device in the VF400 package.
Table 13 • Power Supply Compatibility Per Device
VF400 Pin Names
Package Pin
M2S025
M2S050
F2
VDDI7
VDDI8
G5
VDDI7
VDDI8
H18
VDDI2
VDDI3
J1
VDDI6
VDDI7
J8
VDDI7
VDDI8
K4
VDDI6
VDDI7
L17
VDDI2
VDDI3
L8
VDDI6
VDDI7
M20
VDDI2
VDDI3
N14
VDDI2
VDDI3
N3
VDDI6
VDDI7
P16
VDDI2
VDDI3
R14
VDDI3
VDDI4
R19
VDDI2
VDDI3
R3
VDDI5
VDDI6
T12
VDDI4
VDDI5
U15
VDDI4
VDDI5
V18
VDDI2
VDDI3
W11
VDDI4
VDDI5
Y14
VDDI4
VDDI5
For the other bank supplies that are equivalent, refer to the provided recommendations in the
SmartFusion2 Pin Descriptions.
Any other board-level considerations are common among the three devices. Refer to the SmartFusion2
Board Design Guidelines Application Note for more details.
Software Flow
The Libero® SoC Software provides the option of reserving pins for moving between different devices
within the SmartFusion2 family where pins within the current device that are not bonded in the
destination device can be automatically reserved. This option is available in I/O Constraints Editor which
can be accessed from the Design Flow window as shown in Figure 3. This is done in the early stages of
the design cycle.
Follow the procedure given below to reserve pins:
11
Migrating Designs Between SmartFusion2 M2S025 and M2S050 in VF400 Package
1. After finishing the Compile process, select the I/O Constraints option from the Design Flow
window as shown in Figure 3.
Figure 3 • I/O Constraint Editor Option part of the Design Flow
2. Select the Reserve Pins for Device Migration option from the Tools menu. The window shown
below in Figure 4 is displayed.
12
Design Migration
Figure 4 • Reserve Pins for Device Migration
The first option shows the device that is currently being used in the Libero SoC project. From the
drop-down list, select the device that eventually will be migrated to as the target device. Refer to the
Libero Soc software online help for more details on this window and other options.
The Libero SoC software provides the option of moving between different devices within the
SmartFusion2 family by changing the device selection using the Project Settings option in the Libero
SoC software. Upon changing the device, Libero SoC software validates the features that are used within
the design against the supported features within the new targeted device and package. Feedback
messages are provided as part of the Libero SoC software flow listing the different actions taken by
Libero SoC and the action required.
The first step that Libero SoC performs upon changing the device is to invalidate the original design
components and the design flows. The message is displayed as shown in Figure 5.
Figure 5 • Invalidating Component and Design Flow Message
13
As part of re-running the design flow, Libero SoC checks the different steps needed to be performed for
completing and updating the design flow. Furthermore, Libero SoC converts the MSS configurations to
be compatible with the selected device and package combination. Libero SoC displays the message as
shown in Figure 6.
Figure 6 • Converting the MSS Configurations
As part of the MSS conversion, any changes that were made automatically to be compatible with the
device and package selected will be printed to the log window. Libero SoC disables or defaults to
different options if the current selected options are not supported in the new targeted device and
package.
After the MSS configuration conversion is done, the MSS must be regenerated. To regenerate the MSS
component, open the MSS component from Libero SoC Design Hierarchy Flow window and proceed
through the different MSS pages to complete the generation.
Conclusion
This application note describes the design migration among SmartFusion2 family devices focusing on
migration between M2S025 and M2S050 within the VF400 package. SmartFusion2 family devices share
many common architectural features. During design migration, architecture differences between devices
should be kept in mind to ensure seamless migration flow. Additionally, a key requirement is to run the
functional simulation and timing analysis before and after the migration using Microsemi tools.
List of Changes
The following table lists critical changes that were made in the current version of the document.
Revision
Revision 1
(February 2014)
Changes
First version
Page
N/A
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