Data Sheet

Freescale Semiconductor
Technical Data
Document Number: A2I20H060N
Rev. 0, 2/2016
RF LDMOS Wideband Integrated
Power Amplifiers
The A2I20H060N wideband integrated circuit is an asymmetrical Doherty
designed with on--chip matching that makes it usable from 1800 to 2200 MHz.
This multi--stage structure is rated for 26 to 32 V operation and covers all typical
cellular base station modulation formats.
1800 MHz
 Typical Doherty Single--Carrier W--CDMA Characterization Performance:
VDD = 28 Vdc, IDQ1A = 24 mA, IDQ2A = 145 mA, VGS1B = 1.65 Vdc,
VGS2B = 1.3 Vdc, Pout = 12 W Avg., Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF. (1)
Frequency
Gps
(dB)
PAE
(%)
ACPR
(dBc)
1805 MHz
28.5
42.7
–37.4
1840 MHz
28.4
43.8
–37.8
1880 MHz
28.1
43.1
–34.7
A2I20H060NR1
A2I20H060GNR1
1800–2200 MHz, 12 W AVG., 28 V
AIRFAST RF LDMOS WIDEBAND
INTEGRATED POWER AMPLIFIERS
TO--270WB--15
PLASTIC
A2I20H060NR1
2100 MHz
 Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc,
IDQ1A = 24 mA, IDQ2A = 145 mA, VGS1B = 1.65 Vdc, VGS2B = 1.3 Vdc,
Pout = 12 W Avg., Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. (1)
Frequency
Gps
(dB)
PAE
(%)
ACPR
(dBc)
2110 MHz
27.8
42.3
–36.0
2140 MHz
27.5
42.2
–38.3
2170 MHz
27.3
42.2
–37.7
TO--270WBG--15
PLASTIC
A2I20H060GNR1
Features
 Advanced High Performance In--Package Doherty
 On--Chip Matching (50 Ohm Input, DC Blocked)
 Integrated Quiescent Current Temperature Compensation with
Enable/Disable Function (2)
 Designed for Digital Predistortion Error Correction Systems
1. All data measured in fixture with device soldered to heatsink.
2. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current Control
for the RF Integrated Circuit Device Family. Go to http://www.nxp.com/RF and search for AN1977 or AN1987.
 Freescale Semiconductor, Inc., 2016. All rights reserved.
RF Device Data
Freescale Semiconductor, Inc.
A2I20H060NR1 A2I20H060GNR1
1
VDS1A
RFinA
VDS1A
VGS2A
VGS1A
RFinA
N.C.
GND
GND
N.C.
RFinB
VGS1B
VGS2B
VDS1B
RFout1/VDS2A
VGS1A
Quiescent Current
Temperature Compensation (1)
VGS2A
VGS1B
Quiescent Current
Temperature Compensation (1)
VGS2B
RFinB
1
2 Carrier
15
3
4
5
6
14
7
8
13
9
10
11 Peaking
12
RFout1/VDS2A
GND
RFout2/VDS2B
(Top View)
RFout2/VDS2B
Note: Exposed backside of the package is
the source terminal for the transistors.
VDS1B
Figure 1. Functional Block Diagram
Figure 2. Pin Connections
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Drain--Source Voltage
VDSS
–0.5, +65
Vdc
Gate--Source Voltage
VGS
–0.5, +10
Vdc
Operating Voltage
VDD
32, +0
Vdc
Storage Temperature Range
Tstg
–65 to +150
C
TC
–40 to +150
C
TJ
–40 to +225
C
Pin
20
dBm
Symbol
Value (3,4)
Unit
Case Operating Temperature Range
Operating Junction Temperature Range
(2,3)
Input Power
Table 2. Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Case
Case Temperature 73C, 12 W Avg., W--CDMA, 1840 MHz
Stage 1, 28 Vdc, IDQ1A = 24 mA, VGS1B = 1.65 Vdc
Stage 2, 28 Vdc, IDQ2A = 145 mA, VGS2B = 1.3 Vdc
RJC
C/W
5.2
1.6
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22--A114)
1C
Machine Model (per EIA/JESD22--A115)
A
Charge Device Model (per JESD22--C101)
III
Table 4. Moisture Sensitivity Level
Test Methodology
Per JESD22--A113, IPC/JEDEC J--STD--020
Rating
Package Peak Temperature
Unit
3
260
C
1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current
Control for the RF Integrated Circuit Device Family. Go to http://www.nxp.com/RF and search for AN1977 or AN1987.
2. Continuous use at maximum temperature will affect MTTF.
3. MTTF calculator available at http://www.nxp.com/RF/calculators.
4. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.nxp.com/RF and search for AN1955.
A2I20H060NR1 A2I20H060GNR1
2
RF Device Data
Freescale Semiconductor, Inc.
Table 5. Electrical Characteristics (TA = 25C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 1.0 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage (1)
(VDS = 10 Vdc, ID = 3 Adc)
VGS(th)
0.8
1.3
1.6
Vdc
Gate Quiescent Voltage
(VDS = 28 Vdc, IDQ1A = 24 mAdc)
VGS(Q)
—
2.2
—
Vdc
Fixture Gate Quiescent Voltage
(VDD = 28 Vdc, IDQ1A = 24 mAdc, Measured in Functional Test)
VGG(Q)
3.4
4.4
4.9
Vdc
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 1.0 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage (1)
(VDS = 10 Vdc, ID = 24 Adc)
VGS(th)
0.8
1.3
1.6
Vdc
Gate Quiescent Voltage
(VDS = 28 Vdc, IDQ2A = 145 mAdc)
VGS(Q)
—
1.8
—
Vdc
Fixture Gate Quiescent Voltage
(VDD = 28 Vdc, IDQ2A = 145 mAdc, Measured in Functional Test)
VGG(Q)
2.7
3.7
4.2
Vdc
Drain--Source On--Voltage (1)
(VGS = 10 Vdc, ID = 280 mAdc)
VDS(on)
0.1
0.34
1.5
Vdc
Characteristic
Carrier Stage 1 -- Off Characteristics (1)
Carrier Stage 1 -- On Characteristics
Carrier Stage 2 -- Off Characteristics (1)
Carrier Stage 2 -- On Characteristics
1. Each side of device measured separately.
(continued)
A2I20H060NR1 A2I20H060GNR1
RF Device Data
Freescale Semiconductor, Inc.
3
Table 5. Electrical Characteristics (TA = 25C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 1.0 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
VGS(th)
0.8
1.3
1.6
Vdc
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 1.0 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 40 Adc)
VGS(th)
0.8
1.3
1.6
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 350 mAdc)
VDS(on)
0.1
0.17
1.5
Vdc
Peaking Stage 1 -- Off Characteristics
(1)
Peaking Stage 1 -- On Characteristics (1)
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 8 Adc)
Peaking Stage 2 -- Off Characteristics (1)
Peaking Stage 2 -- On Characteristics (1)
1. Each side of device measured separately.
(continued)
A2I20H060NR1 A2I20H060GNR1
4
RF Device Data
Freescale Semiconductor, Inc.
Table 5. Electrical Characteristics (TA = 25C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
(1,2,3)
Functional Tests
(In Freescale Doherty Production Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQ1A = 24 mA, IDQ2A = 145 mA,
VGS1B = 1.65 Vdc, VGS2B = 1.3 Vdc, Pout = 12 W Avg., f = 1842.5 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in 3.84 MHz Channel Bandwidth @ 5 MHz Offset.
Power Gain
Power Added Efficiency
Gps
27.5
28.9
30.9
dB
PAE
42.0
47.3
—
%
Adjacent Channel Power Ratio
ACPR
—
–34.5
–30.0
dBc
Pout @ 3 dB Compression Point, CW
P3dB
65
74
—
W
(2)
Load Mismatch
(In Freescale Doherty Production Test Fixture, 50 ohm system) IDQ1A = 24 mA, IDQ2A = 145 mA, VGS1B = 1.65 Vdc,
VGS2B = 1.3 Vdc, f = 1840 MHz
VSWR 10:1 at 32 Vdc, 80 W CW Output Power
(3 dB Input Overdrive from 69 W CW Rated Power)
No Device Degradation
Typical Performance (2) (In Freescale Doherty Characterization Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQ1A = 24 mA,
IDQ2A = 145 mA, VGS1B = 1.65 Vdc, VGS2B = 1.3 Vdc, 1805–1880 MHz Bandwidth
Pout @ 1 dB Compression Point, CW
P1dB
—
63
—
W
Pout @ 3 dB Compression Point (4)
P3dB
—
74
—
W

—
–15
—

VBWres
—
120
—
MHz
—
—
1.0
2.0
—
—
AM/PM
(Maximum value measured at the P3dB compression point across
the 1805–1880 MHz frequency range.)
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
Quiescent Current Accuracy over Temperature (5)
with 2 k Gate Feed Resistors (–30 to 85C) Stage 1
with 2 k Gate Feed Resistors (–30 to 85C) Stage 2
IQT
Gain Flatness in 75 MHz Bandwidth @ Pout = 12 W Avg.
GF
—
0.3
—
dB
Gain Variation over Temperature
(–30C to +85C)
G
—
0.026
—
dB/C
P1dB
—
0.011
—
dB/C
Output Power Variation over Temperature
(–30C to +85C)
%
Table 6. Ordering Information
Device
A2I20H060NR1
A2I20H060GNR1
Tape and Reel Information
R1 Suffix = 500 Units, 44 mm Tape Width, 13--inch Reel
Package
TO--270WB--15
TO--270WBG--15
1. Part internally input matched.
2. Measurements made with device in an asymmetrical Doherty configuration.
3. Measurements made with device in straight lead configuration before any lead forming operation is applied. Lead forming is used for gull
wing (GN) parts.
4. P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W--CDMA single--carrier input signal
where output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
5. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current
Control for the RF Integrated Circuit Device Family. Go to http://www.nxp.com/RF and search for AN1977 or AN1987.
A2I20H060NR1 A2I20H060GNR1
RF Device Data
Freescale Semiconductor, Inc.
5
VGG2A
R1
VGG1A
R2
A2I20H060N
Rev. 0
VDD1A
VDD2A
C8
C1 C2
C7
C11
C15
C17
C3
C20
C19
CUT OUT AREA
C12
Z1
C24*
R5
C14
C
P
C22
C21
C18
C16
C13
C23
C4 C5 C6
C9
C10
R4
VGG1B
R3
VGG2B
VDD1B
D73426
VDD2B
*C24 is mounted vertically.
Figure 3. A2I20H060NR1 Production Test Circuit Component Layout
Table 7. A2I20H060NR1 Production Test Circuit Component Designations and Values
Part
C1, C2, C3, C4, C5, C6, C7, C8,
C9, C10, C11, C12, C13, C14
Description
10 F Chip Capacitors
Part Number
C3225X7S1H106K250AB
Manufacturer
TDK
C15, C16, C17, C18
10 nF Chip Capacitors
08055C103KAT2A
AVX
C19, C20, C21, C22, C23
10 pF Chip Capacitors
ATC600S100JT250XT
ATC
C24
1.3 pF Chip Capacitor
ATC100B1R3BT500XT
ATC
R1, R2, R3, R4
2.2 k, 1/8 W Chip Resistors
WCR0805-2K2FI
Welwyn
R5
50 , 8 W Chip Resistor
C8A50Z4A
Anaren
Z1
1700–2000 MHz Band, 5 dB Directional Coupler
X3C19P1-05S
Anaren
PCB
RF35, 0.020, r = 3.55
D73426
MTL
A2I20H060NR1 A2I20H060GNR1
6
RF Device Data
Freescale Semiconductor, Inc.
VGG2A
R1
VGG1A
R2
A2I20H060N
Rev. 0
VDD1A
VDD2A
C8
C1 C2
C7
C11
C15
C17
C3
C20
C25
C19
C12
C
Z1
C24*
Q1
P
R5
C22
C21
C14
C18
C16
C13
C23
C4 C5 C6
C9
C10
R4
VGG1B
R3
VGG2B
VDD1B
D73426
VDD2B
*C24 is mounted vertically.
Note: All data measured in fixture with device soldered to heatsink.
Figure 4. A2I20H060NR1 Characterization Test Circuit Component Layout
Table 8. A2I20H060NR1 Characterization Test Circuit Component Designations and Values
Part
Description
Part Number
Manufacturer
C1, C2, C3, C4, C5, C6, C7, C8,
C9, C10, C11, C12, C13, C14
10 F Chip Capacitors
C3225X7S1H106K250AB
TDK
C15, C16, C17, C18
10 nF Chip Capacitors
08055C103KAT2A
AVX
C19, C20, C21, C22, C23
10 pF Chip Capacitors
ATC600S100JT250XT
ATC
C24
1.3 pF Chip Capacitor
ATC100B1R3BT500XT
ATC
C25
0.3 pF Chip Capacitor
ATC600S0R3BT250XT
ATC
Q1
RF LDMOS Power Amplifier
A2I20H060NR1
Freescale
R1, R2, R3, R4
2.2 k, 1/8 W Chip Resistors
WCR0805-2K2FI
Welwyn
R5
50 , 8 W Chip Resistor
C8A50Z4A
Anaren
Z1
1700–2000 MHz Band, 5 dB Directional Coupler
X3C19P1-05S
Anaren
PCB
RF35, 0.020, r = 3.55
D73426
MTL
A2I20H060NR1 A2I20H060GNR1
RF Device Data
Freescale Semiconductor, Inc.
7
TYPICAL CHARACTERISTICS — 1805–1880 MHz
3.84 MHz Channel Bandwidth, Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF
28.6
44
PAE
42
40
28.4
28.2
PARC
28
27.8
27.4
1760
–33
–1.8
–37
Gps
1780
–1.6
–35
ACPR
27.6
–31
1800
1820 1840 1860
f, FREQUENCY (MHz)
1880
1900
–39
–41
1920
–2
–2.2
–2.4
PARC (dB)
Gps, POWER GAIN (dB)
29
28.8
46
ACPR (dBc)
VDD = 28 Vdc, Pout = 12 W (Avg.), IDQ1A = 24 mA, IDQ2A = 145 mA
VGS1B = 1.65 Vdc, VGS2B = 1.3 Vdc, Single--Carrier W--CDMA
29.2
PAE, POWER ADDED
EFFICIENCY (%)
48
29.4
–2.6
IMD, INTERMODULATION DISTORTION (dBc)
Figure 5. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 12 Watts Avg.
–10
VDD = 28 Vdc, Pout = 25 W (PEP), IDQ1A = 24 mA
IDQ2A = 145 mA, VGS1B = 1.65 Vdc, VGS2B = 1.3 Vdc
Two--Tone Measurements, (f1 + f2)/2 = Center
Frequency of 1840 MHz
–20
IM3--U
–30
IM3--L
–40
IM5--U
IM5--L
–50
IM7--L
–60
1
IM7--U
10
100
200
TWO--TONE SPACING (MHz)
28.4
0
28
27.6
27.2
26.8
26.4
VDD = 28 Vdc, IDQ1A = 24 mA, IDQ2A = 145 mA, VGS1B = 1.65 Vdc
VGS2B = 1.3 Vdc, f = 1840 MHz, Single--Carrier W--CDMA
–1 dB = 9.86 W
–1
–2
50
–4
5
ACPR
40
3.84 MHz Channel Bandwidth, Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF
–5
45
–3 dB = 17.56 W
PAE
–3
55
Gps
–2 dB = 13.56 W
10
15
20
Pout, OUTPUT POWER (WATTS)
35
PARC
25
–15
60
30
30
–20
–25
–30
ACPR (dBc)
1
PAE, POWER ADDED EFFICIENCY (%)
28.8
OUTPUT COMPRESSION AT 0.01%
PROBABILITY ON CCDF (dB)
Gps, POWER GAIN (dB)
Figure 6. Intermodulation Distortion Products
versus Two--Tone Spacing
–35
–40
–45
Figure 7. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2I20H060NR1 A2I20H060GNR1
8
RF Device Data
Freescale Semiconductor, Inc.
TYPICAL CHARACTERISTICS — 1805–1880 MHz
60
55
50
45
40
ACPR
25
1805 MHz
24
5
1840 MHz
35
1880 MHz
10
30
35
10
Pout, OUTPUT POWER (WATTS) AVG.
0
–10
–20
–30
ACPR (dBc)
VDD = 28 Vdc, IDQ1A = 24 mA, IDQ2A = 145 mA, VGS1B = 1.65 Vdc
VGS2B = 1.3 Vdc, Single--Carrier W--CDMA, 3.84 MHz Channel
29 Bandwidth, Input Signal PAR = 9.9 dB @ 0.01% Probability on
CCDF
Gps
28
1805 MHz 1840 MHz 1880 MHz
PAE
27
1880 MHz
1805 MHz
26 1840 MHz
PAE, POWER ADDED EFFICIENCY (%)
Gps, POWER GAIN (dB)
30
–40
–50
Figure 8. Single--Carrier W--CDMA Power Gain, Power Added
Efficiency and ACPR versus Output Power
30
29
Gain
GAIN (dB)
28
27
26
VDD = 28 Vdc
Pin = 0 dBm
IDQ1A = 24 mA, IDQ2A = 145 mA
VGS1B = 1.65 Vdc, VGS2B = 1.3 Vdc
25
24
1400
1500
1600
1700 1800 1900
f, FREQUENCY (MHz)
2000
2100
2200
Figure 9. Broadband Frequency Response
A2I20H060NR1 A2I20H060GNR1
RF Device Data
Freescale Semiconductor, Inc.
9
Table 9. Carrier Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQ1A = 24 mA, IDQ2A = 149 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
1805
43.9 – j21.6
41.6 + j19.1
1840
49.1 – j21.7
45.4 + j19.9
1880
54.0 – j19.0
51.9 + j17.3
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
4.30 + j0.95
32.2
44.3
27
55.7
–7
3.91 + j1.32
32.4
44.4
28
57.7
–7
3.92 + j1.42
32.3
44.4
28
58.3
–8
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
43.9 – j21.6
43.8 + j18.4
4.55 + j0.70
30.0
45.0
32
57.1
–11
1840
49.1 – j21.7
47.9 + j18.3
4.31 + j1.06
30.2
45.1
32
58.6
–11
1880
54.0 – j19.0
53.9 + j14.6
4.31 + j1.12
30.0
45.1
32
58.4
–11
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 10. Carrier Side Load Pull Performance — Maximum Efficiency Tuning
VDD = 28 Vdc, IDQ1A = 24 mA, IDQ2A = 149 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
43.9 – j21.6
41.9 + j25.2
2.87 + j4.44
33.8
41.9
16
65.5
–12
1840
49.1 – j21.7
47.7 + j27.1
2.25 + j4.50
33.9
41.6
14
69.2
–13
1880
54.0 – j19.0
55.7 + j23.0
2.35 + j4.13
33.7
42.1
16
69.0
–13
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2.62 + j4.15
32.0
42.7
19
66.4
–17
48.7 + j24.0
2.47 + j4.20
31.9
42.8
19
70.0
–17
56.7 + j20.7
2.17 + j4.13
31.7
42.5
18
69.3
–19
f
(MHz)
Zsource
()
Zin
()
1805
43.9 – j21.6
42.7 + j23.9
1840
49.1 – j21.7
1880
54.0 – j19.0
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2I20H060NR1 A2I20H060GNR1
10
RF Device Data
Freescale Semiconductor, Inc.
Table 11. Peaking Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQ1B = 43 mA, VGS2B = 1.3 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
1805
35.1 – j7.58
36.1 + j8.10
1840
33.9 – j9.77
35.8 + j8.91
1880
36.6 – j10.5
37.3 + j8.43
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2.33 – j0.53
28.6
46.5
45
57.5
–16
2.23 – j0.44
28.6
46.6
45
58.0
–17
2.22 – j0.35
28.5
46.5
45
57.0
–15
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
35.1 – j7.58
38.7 + j9.21
2.56 – j0.71
26.5
47.2
52
58.2
–21
1840
33.9 – j9.77
38.7 + j9.51
2.44 – j0.60
26.4
47.2
52
58.4
–22
1880
36.6 – j10.5
40.5 + j8.27
2.43 – j0.48
26.4
47.1
51
57.6
–20
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 12. Peaking Side Load Pull Performance — Maximum Efficiency Tuning
VDD = 28 Vdc, IDQ1B = 43 mA, VGS2B = 1.3 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1805
35.1 – j7.58
32.3 + j11.3
0.81 + j2.03
29.2
41.8
15
73.5
–56
1840
33.9 – j9.77
32.9 + j12.8
0.84 + j1.97
28.8
41.8
15
72.7
–62
1880
36.6 – j10.5
35.1 + j12.5
0.96 + j1.83
28.9
42.4
17
70.3
–67
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
0.83 + j1.85
27.4
42.7
19
72.9
–49
34.8 + j12.0
1.07 + j1.56
27.5
43.8
24
71.8
–53
37.7 + j10.8
1.45 + j1.41
27.4
44.9
31
69.5
–32
f
(MHz)
Zsource
()
Zin
()
1805
35.1 – j7.58
34.1 + j11.5
1840
33.9 – j9.77
1880
36.6 – j10.5
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2I20H060NR1 A2I20H060GNR1
RF Device Data
Freescale Semiconductor, Inc.
11
P1dB – TYPICAL CARRIER LOAD PULL CONTOURS — 1840 MHz
6
41
40.5
IMAGINARY ()
4
E
2
P
1
–1
–2
2
43.5
4
3
5
REAL ()
6
7
8
56
2
54
P
1
1
3
2
4
5
REAL ()
6
7
8
9
Figure 11. P1dB Load Pull Efficiency Contours (%)
6
6
5
5
E
34
33.5
3
33
32.5
32
2
P
1
31.5
0
2
3
4
5
6
REAL ()
–12
3
–14
2
–8
–6
–10
P
1
–1
30.5
1
E
0
31
–1
–16
4
IMAGINARY ()
4
IMAGINARY ()
58
3
–2
9
Figure 10. P1dB Load Pull Output Power Contours (dBm)
–2
60
68
–1
40.5 41.5
1
62
0
44
41
64
E
4
3
0
66
5
43
IMAGINARY ()
5
6
42.5
42
7
8
9
Figure 12. P1dB Load Pull Gain Contours (dB)
NOTE:
–2
–8
1
2
3
4
5
REAL ()
6
7
8
9
Figure 13. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I20H060NR1 A2I20H060GNR1
12
RF Device Data
Freescale Semiconductor, Inc.
P3dB – TYPICAL CARRIER LOAD PULL CONTOURS — 1840 MHz
7
41
6
6
41.5
5
5
E
4
IMAGINARY ()
IMAGINARY ()
7
42
3
2
43
1
45
0
–2
41
42.5
2
1
43.5
4
5
REAL ()
6
7
7
6
6
31
30.5
2
1
IMAGINARY ()
32
3
30
P
29.5
0
1
1
2
3
4
5
REAL ()
6
7
8
Figure 16. P3dB Load Pull Gain Contours (dB)
NOTE:
3
–20
4
4
5
REAL ()
6
7
8
3
–22
–8
–16
2
–14
1
–2
E
–18
P
–10
–12
–1
28.5
28
2
–6
0
29
–1
54
P
5
E
31.5
56
Figure 15. P3dB Load Pull Efficiency Contours (%)
5
IMAGINARY ()
1
7
–2
58
2
–2
8
Figure 14. P3dB Load Pull Output Power Contours (dBm)
4
60
62
–1
44
3
66
3
0
44.5
42
–1
P
64
68
E
4
1
2
3
4
5
REAL ()
6
7
8
Figure 17. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I20H060NR1 A2I20H060GNR1
RF Device Data
Freescale Semiconductor, Inc.
13
P1dB – TYPICAL PEAKING LOAD PULL CONTOURS — 1840 MHz
3
43
2.5
44
42.5
E
44.5
IMAGINARY ()
2
45
1.5
45.5
1
0.5
46
0
P
–0.5
–1
2
2.5
REAL ()
3
3.5
2.5
2
0
P
2
IMAGINARY ()
29.5
1
0.5
29
0
–0.5
28
–1
28.5
P
26.5
25.5
1
1.5
1.5
–32
E
58
56
2
2.5
REAL ()
3
3.5
4
–28
1.5
–24
1
–18
–16
–26
0.5
–22
–20
0
–0.5
P
–1
26
–1.5
1
2.5
1.5
IMAGINARY ()
60
3
E
–2
0.5
1
Figure 19. P1dB Load Pull Efficiency Contours (%)
27.5 28
27
62
0.5
–2
0.5
4
Figure 18. P1dB Load Pull Output Power Contours (dBm)
3
1.5
58
64
68
–1.5
1.5
1
70
72
–1
44
–2
0.5
66
E
–0.5
46.5
43
–1.5
56
2.5
IMAGINARY ()
2
3
43.5
2
2.5
REAL ()
–1.5
27.5
27
3
3.5
4
Figure 20. P1dB Load Pull Gain Contours (dB)
NOTE:
–2
0.5
1
1.5
2
2.5
REAL ()
3
3.5
4
Figure 21. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I20H060NR1 A2I20H060GNR1
14
RF Device Data
Freescale Semiconductor, Inc.
P3dB – TYPICAL PEAKING LOAD PULL CONTOURS — 1840 MHz
2
45
44 44.5
1.5 E
1
IMAGINARY ()
46.5
0.5
0
47
–0.5
P
–1
45.5
1.5
1
2
2.5
2
3.5
3
REAL ()
4.5
4
62
0
P
56
2
1.5 E
1
27
0
–0.5
IMAGINARY ()
27.5
0.5
26.5
P
26
–1
1.5
2
2.5
3
REAL ()
4
4.5
5
–26
–22
–34
0.5
–30
0
–24
–28
–0.5
P
–1.5
25.5
25
3.5
3
REAL ()
–1
24
24.5
2.5
2
–38
–36 –32
1
1
1.5
1
Figure 23. P3dB Load Pull Efficiency Contours (%)
27
–1.5
60
58
–0.5
–2
5
1.5 E
IMAGINARY ()
64
–1.5
45
Figure 22. P3dB Load Pull Output Power Contours (dBm)
–2
66
0.5
–1
–1.5
–2
68
70
1.5 E
46
1
IMAGINARY ()
2
45.5
3.5
4
5
4.5
Figure 24. P3dB Load Pull Gain Contours (dB)
NOTE:
–2
1
1.5
2
2.5
3
3.5
REAL ()
4
4.5
5
Figure 25. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I20H060NR1 A2I20H060GNR1
RF Device Data
Freescale Semiconductor, Inc.
15
VGG2A
VGG1A
VDD2A
A2I20H060N
Rev. 1
VDD1A
R1
R2
C5
C6
C17
C1 C2
C10
C14
C18
C13
C9
C
Z1
Q1
1
C22 R5
C15
C11
C16
C12
C7
R4
VGG1B
R3
VGG2B
P
C19
C20
C21
C3 C4
C8
VDD1B
D71621
VDD2B
Note: All data measured in fixture with device soldered to heatsink.
Figure 26. A2I20H060NR1 Test Circuit Component Layout — 2110–2170 MHz
Table 13. A2I20H060NR1 Test Circuit Component Designations and Values — 2110–2170 MHz
Part
Description
Part Number
Manufacturer
C1, C2, C3, C4, C5, C6, C7,
C8, C9, C10, C11, C12
10 F Chip Capacitors
C3225X7S1H106K250AB
TDK
C13, C14, C15, C16
10 nF Chip Capacitors
08055C103KAT2A
AVX
C17, C18, C19, C20, C21
10 pF Chip Capacitors
ATC600S100JT250XT
ATC
C22
0.7 pF Chip Capacitor
ATC600S0R7BT250XT
ATC
Q1
RF LDMOS Power Amplifier
A2I20H060NR1
Freescale
R1, R2, R3, R4
2.2 k, 1/8 W Chip Resistors
WCR0805-2K2FI
Welwyn
R5
50 , 8 W Chip Resistor
C8A50Z4A
Anaren
Z1
2000–2300 MHz Band, 5 dB Directional Coupler
X3C21P1-05S
Anaren
PCB
RF35, 0.020, r = 3.55
D71621
MTL
A2I20H060NR1 A2I20H060GNR1
16
RF Device Data
Freescale Semiconductor, Inc.
TYPICAL CHARACTERISTICS — 2110–2170 MHz
46
44
42
PAE
27.6
40
Gps
27.4
27.2
PARC
27
–1.6
–33
–2
–35
ACPR
26.8
–31
–37
26.6 Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
26.4
2060 2080 2100 2120 2140 2160
f, FREQUENCY (MHz)
–39
2180
–2.4
–2.8
–3.2
–3.6
–41
2220
2200
PARC (dB)
27.8
PAE, POWER ADDED
EFFICIENCY (%)
28
Gps, POWER GAIN (dB)
48
VDD = 28 Vdc, Pout = 12 W (Avg.), IDQ1A = 24 mA
IDQ2A = 145 mA, VGS1B = 1.65 Vdc, VGS2B = 1.3 Vdc
Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth
28.2
ACPR (dBc)
28.4
Figure 27. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 12 Watts Avg.
28
50
PAE
2170 MHz
27
55
2170 MHz
2110 MHz
2140 MHz
26
45
40
ACPR
25
2110 MHz
24
2170 MHz
35
2140 MHz
30
35
10
Pout, OUTPUT POWER (WATTS) AVG.
5
10
0
–10
–20
–30
ACPR (dBc)
29
Gps, POWER GAIN (dB)
60
VDD = 28 Vdc, IDQ1A = 24 mA, IDQ2A = 145 mA, VGS1B = 1.65 Vdc
VGS2B = 1.3 Vdc, Single--Carrier W--CDMA, 3.84 MHz Channel
Bandwidth, Input Signal PAR = 9.9 dB @ 0.01% Probability on
CCDF
Gps
2110 MHz
2140 MHz
PAE, POWER ADDED EFFICIENCY (%)
30
–40
–50
Figure 28. Single--Carrier W--CDMA Power Gain, Power Added
Efficiency and ACPR versus Output Power
29
28
Gain
GAIN (dB)
27
26
25
VDD = 28 Vdc
Pin = 0 dBm
IDQ1A = 24 mA, IDQ2A = 145 mA
VGS1B = 1.65 Vdc, VGS2B = 1.3 Vdc
24
23
1600
1700
1800
1900 2000 2100
f, FREQUENCY (MHz)
2200
2300
2400
Figure 29. Broadband Frequency Response
A2I20H060NR1 A2I20H060GNR1
RF Device Data
Freescale Semiconductor, Inc.
17
Table 14. Carrier Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQ1A = 24 mA, IDQ2A = 149 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2110
69.5 + j18.1
70.6 – j18.1
3.84 + j1.66
31.7
44.1
26
53.2
–8
2140
65.9 + j18.2
69.2 – j19.8
4.08 + j1.52
31.6
44.2
26
53.8
–8
2170
69.5 + j20.2
69.1 – j20.1
3.94 + j1.55
31.7
44.2
27
55.3
–9
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2110
69.5 + j18.1
67.0 – j19.9
4.38 + j1.42
29.5
44.8
30
53.4
–12
2140
65.9 + j18.2
65.6 – j21.2
4.45 + j1.31
29.4
44.9
31
54.2
–11
2170
69.5 + j20.2
65.5 – j20.8
4.24 + j1.26
29.5
44.9
31
55.2
–12
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 15. Carrier Side Load Pull Performance — Maximum Efficiency Tuning
VDD = 28 Vdc, IDQ1A = 24 mA, IDQ2A = 149 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2110
69.5 + j18.1
74.2 – j19.6
2.36 + j3.84
32.7
42.3
17
61.2
–12
2140
65.9 + j18.2
73.0 – j21.6
2.42 + j3.87
32.6
42.3
17
62.1
–11
2170
69.5 + j20.2
72.4 – j21.5
2.60 + j3.58
32.6
42.8
19
63.2
–11
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2.62 + j3.53
30.7
43.5
22
60.9
–15
69.3 – j21.7
2.66 + j3.46
30.6
43.5
23
61.8
–15
69.5 – j21.7
2.48 + j3.34
30.6
43.5
22
63.0
–16
f
(MHz)
Zsource
()
Zin
()
2110
69.5 + j18.1
70.8 – j20.0
2140
65.9 + j18.2
2170
69.5 + j20.2
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2I20H060NR1 A2I20H060GNR1
18
RF Device Data
Freescale Semiconductor, Inc.
Table 16. Peaking Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQ1B = 43 mA, VGS2B = 1.3 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2110
63.5 + j9.31
67.9 – j12.2
2.29 + j0.28
27.7
46.3
43
54.8
–15
2140
68.4 + j14.6
70.3 – j18.9
2.35 + j0.19
27.6
46.3
43
54.0
–15
2170
73.3 + j22.8
72.1 – j25.6
2.32 + j0.09
27.6
46.3
43
54.0
–16
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2110
63.5 + j9.31
67.3 – j18.4
2.42 + j0.19
25.6
46.9
49
55.2
–19
2140
68.4 + j14.6
68.2 – j25.0
2.50 + j0.10
25.6
46.8
48
54.3
–19
2170
73.3 + j22.8
68.6 – j31.3
2.55 – j0.04
25.5
46.8
48
53.9
–21
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 17. Peaking Side Load Pull Performance — Maximum Efficiency Tuning
VDD = 28 Vdc, IDQ1B = 43 mA, VGS2B = 1.3 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2110
63.5 + j9.31
71.0 – j8.08
1.53 + j1.79
28.3
44.6
29
64.0
–20
2140
68.4 + j14.6
74.6 – j15.1
1.51 + j1.73
28.2
44.5
28
63.3
–21
2170
73.3 + j22.8
76.8 – j23.1
1.67 + j1.62
28.2
44.8
30
62.8
–22
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1.61 + j1.61
26.4
45.5
35
63.1
–26
72.6 – j20.3
1.57 + j1.51
26.3
45.5
35
62.4
–26
74.0 – j27.8
1.67 + j1.49
26.3
45.4
35
61.9
–28
f
(MHz)
Zsource
()
Zin
()
2110
63.5 + j9.31
70.4 – j13.3
2140
68.4 + j14.6
2170
73.3 + j22.8
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2I20H060NR1 A2I20H060GNR1
RF Device Data
Freescale Semiconductor, Inc.
19
P1dB – TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 2140 MHz
7
40.5 41 41.5
6
43
E
43.5
3
44
2
P
1
0
2
30
3
4
REAL ()
6
5
IMAGINARY ()
IMAGINARY ()
32
31.5
2
31
P
1
–1
46
1
2
3
4
REAL ()
5
3
6
7
Figure 32. P1dB Load Pull Gain Contours (dB)
6
5
7
–6
–6
–8
–10
–14
4
–12
E
–16
–18
3
2
P
0
NOTE:
4
REAL ()
1
30.5
30
29 29.5
2
1
6
3
28.5
48
Figure 31. P1dB Load Pull Efficiency Contours (%)
31
E
52
P
5
0
54
58
50
2
–1
7
5
32.5
60
3
7
30.5
6
4
56
E
0
Figure 30. P1dB Load Pull Output Power Contours (dBm)
7
4
1
40 41 41.5
1
48
5
IMAGINARY ()
IMAGINARY ()
40
4
46
6
42.5
5
–1
7
42
–1
–8
–10
1
–8
2
3
–8
4
REAL ()
5
6
7
Figure 33. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I20H060NR1 A2I20H060GNR1
20
RF Device Data
Freescale Semiconductor, Inc.
P3dB – TYPICAL CARRIER LOAD PULL CONTOURS — 2140 MHz
6
5
6
43.5
44
44.5
2
P
1
–1
1
2
4
3
5
REAL ()
6
8
7
E
3
52
2
48
50
P
1
–2
9
46
2
1
4
3
5
REAL ()
6
7
8
9
Figure 35. P3dB Load Pull Efficiency Contours (%)
6
6
5
5
30.5
E
3
30
29.5
2
29
P
1
28.5
0
–8
–18
–20
4
IMAGINARY ()
4
IMAGINARY ()
54
–1
41
Figure 34. P3dB Load Pull Output Power Contours (dBm)
3
–22
2
E
–16
–12
–10
–14
P
1
0
28
–1
–2
56
0
0
–2
58
60
4
E
3
46
5
IMAGINARY ()
IMAGINARY ()
42
41
4
43
42.5
41.5
26.5
1
2
27.5
27
3
–12
–1
4
5
REAL ()
6
7
9
8
Figure 36. P3dB Load Pull Gain Contours (dB)
NOTE:
–2
1
2
3
4
5
REAL ()
6
7
8
9
Figure 37. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I20H060NR1 A2I20H060GNR1
RF Device Data
Freescale Semiconductor, Inc.
21
P1dB – TYPICAL PEAKING LOAD PULL CONTOURS — 2140 MHz
3
IMAGINARY ()
4
43
43.5
42.5
44
3
44.5
2
45
E
IMAGINARY ()
4
45.5
1
46
P
0
–1
–2
43 43.5 44
1.5
1
45
44.5
2.5
2
3.5
3
REAL ()
4
4.5
62
1
58
56
54
52
50
P
0
–2
5
48
1
2
1.5
2.5
3
3.5
REAL ()
4
4.5
5
Figure 39. P1dB Load Pull Efficiency Contours (%)
4
4
26.5
27
2
E
28
1
27.5
P
0
24.5
1
1.5
25
2
E
–18
1
2.5
3
3.5
REAL ()
–16
–14
–20
–12
P
0
–16
–1
26
25.5
–10
–24
2
27
26.5
–1
–8
3
IMAGINARY ()
26
3
IMAGINARY ()
E
–1
Figure 38. P1dB Load Pull Output Power Contours (dBm)
–2
60
2
–12
–16
4
5
4.5
Figure 40. P1dB Load Pull Gain Contours (dB)
NOTE:
–2
1
1.5
2
2.5
3
3.5
REAL ()
4
4.5
5
Figure 41. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I20H060NR1 A2I20H060GNR1
22
RF Device Data
Freescale Semiconductor, Inc.
P3dB – TYPICAL PEAKING LOAD PULL CONTOURS — 2140 MHz
4
44
43.5
43
4
44.5
45
3
46
3
IMAGINARY ()
IMAGINARY ()
45.5
2
E
1
P
0
46.5
–1
45
44.5
44
–2
1.5
1
2.5
2
3.5
3
REAL ()
4
4.5
26
1
25.5
P
0
1.5
46
1
2
1.5
23
–30
1
2.5
2.5
3
3.5
REAL ()
4
5
4.5
Figure 44. P3dB Load Pull Gain Contours (dB)
NOTE:
–20
E
–26 –24
3
3.5
REAL ()
4
5
4.5
–2
–14
–18
–22
–16
P
0
–16
–22
–1
24
23.5
2
2
25
24.5
1
IMAGINARY ()
IMAGINARY ()
E
–2
48
3
2
22.5
50
52
P
0
54
Figure 43. P3dB Load Pull Efficiency Contours (%)
25
3
–1
56
4
24.5
24
58
1
–2
5
Figure 42. P3dB Load Pull Output Power Contours (dBm)
4
60
E 62
–1
46
45.5
2
1
1.5
2
2.5
3
3.5
REAL ()
4
4.5
5
Figure 45. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I20H060NR1 A2I20H060GNR1
RF Device Data
Freescale Semiconductor, Inc.
23
PACKAGE DIMENSIONS
A2I20H060NR1 A2I20H060GNR1
24
RF Device Data
Freescale Semiconductor, Inc.
A2I20H060NR1 A2I20H060GNR1
RF Device Data
Freescale Semiconductor, Inc.
25
A2I20H060NR1 A2I20H060GNR1
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RF Device Data
Freescale Semiconductor, Inc.
A2I20H060NR1 A2I20H060GNR1
RF Device Data
Freescale Semiconductor, Inc.
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A2I20H060NR1 A2I20H060GNR1
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RF Device Data
Freescale Semiconductor, Inc.
A2I20H060NR1 A2I20H060GNR1
RF Device Data
Freescale Semiconductor, Inc.
29
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
AN1907: Solder Reflow Attach Method for High Power RF Devices in Over--Molded Plastic Packages
AN1955: Thermal Measurement Methodology of RF Power Amplifiers
AN1977: Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family
AN1987: Quiescent Current Control for the RF Integrated Circuit Device Family




Engineering Bulletins
 EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
 Electromigration MTTF Calculator
 RF High Power Model
 .s2p File
Development Tools
 Printed Circuit Boards
To Download Resources Specific to a Given Part Number:
1. Go to http://www.nxp.com/RF
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
0
Feb. 2016
Description
 Initial release of data sheet
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RF Device Data
Freescale Semiconductor, Inc.
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