APPLICATION NOTE APT9501 By: Kenneth Dierberger Bobby McDonald Lee B. Max A High-Efficiency 400 Watt 13.56 MHz RF Power Amplifier Presented at RF EXPO WEST 1995 1 A High-Efficiency 400 Watt 13.56 MHz RF Power Amplifier Kenneth Dierberger Applications Engineering Manager Advanced Power Technology, Inc. 405 S. W. Columbia Street Bend, Oregon 97702 USA Bobby McDonald Lee B. Max UNI-WEST ENGINEERING Independent Consultant PO Box 919 6284 Squiredell Dr. Bethel Island, CA 94511 San Jose, California 95129 ABSTRACT This paper details the design, development, assembly and performance of a low cost, highefficiency, 400Watt, 13.56MHz RF power amplifier (PA) operated from a 100VDC supply and with an efficiency of 75%. The PA is built around a “Symmetric Pair” of low cost RF power MOSFETs from Advanced Power Technology (APT). The transistors are from a new generation of high quality, commercial, HF/VHF, silicon, 300V RF power MOSFETs in TO-247 plastic packages. The paper addresses both the theoretical design and physical construction of the input network, the output matching circuit and the DC supply network of the amplifier. The paper also contains a technical description of the RF power transistors. INTRODUCTION The RF equipment industry has experienced tremendous growth over the past few decades. This growth has primarily been in the area of wireless communication and control at ultrahigh frequency. This growth has overshadowed the growth in lower frequency Industrial, Scientific and Medical (ISM) systems. As a result there has been a proliferation of new devices to address the ultrahigh frequency market and the lower frequency ISM applications have been required to make do with devices which are optimized for the higher operating frequencies. This has resulted in extra cost to the lower frequency systems. Some ISM equipment manufacturers have tried to mitigate the higher transistor cost by stretching the performance of lower cost plastic devices designed for the switched mode power supply market. In particular the power MOSFET has served this market reasonably well but with limitations. One disadvantage with the use of these devices lies in the package’s metal back heat spreader, used for heat sinking the device, which is electrically tied to the drain of the MOSFET. This common drain construction results in a significant amount of source inductance and requires the use of an insulator between the package and the heat sink. This adds cost to the assembly of the PA and 2 J1 RF INPUT Q1 L1 BFC1 C9 T2 T1 J2 RF OUTPUT C1 R1 C10 C7 Q2 C8 L1 J3 100VDC C3 C2 C4 C5 C6 Figure 1. Circuit of class-C Power Amplifier 500 incorporates the potential for failures due to incorrect installation. Not to mention the poor thermal transfer characteristics of the insulator. 450 OUTPUT (Watts) 400 CIRCUIT TOPOLOGY To demonstrate the power handling capability and ease of use of the new MOSFET devices a simple class-C PA shown in Figure 1 was chosen (see Appendix A for parts list). The PA is a classical push-pull configuration of a straight forward nature using a simple LC input network for impedance matching with a transformer coupled gate drive for complementary signal generation and a wide band transmission line transformer output. 350 300 250 200 150 100 50 0 0 1 2 3 4 5 6 7 8 INPUT POWER (Watts) Figure 2. Output Power versus Input Power 3 9 AMPLIFIER PERFORMANCE 100 Figure 2 presents a plot of the POUT versus PIN and Figure 3 is a plot of the gain versus PIN. The curves show the classical characteristics of a ClassC amplifier, having low gain at low power output and improving as the output power is increased. The PA continues to improve until the gain plateaus at around 19db and begins to roll off above 400W. However, the gain is still a respectable 17.5db at 500W output. 80 70 60 50 40 30 20 10 0 0 100 200 300 400 500 OUTPUT POWER (Watts) Figure 4. Efficiency versus Output Power The efficiency versus POUT is illustrated in Figure 4. Again the curve represents classical class-C amplifier performance with the efficiency below 50% at the lower power output levels and rising to an outstanding 75.5% efficiency at the 400W rated output power level. The efficiency continues to improve to 79.4% at the 500W output power level. 20 18 16 14 GAIN (db) 90 EFFICIENCY (%) The PA was operated with a 100VDC input, the input network was adjusted for return losses of less than -16db and a 50Ω load was applied to the output. A fan was used to cool the heat sink. Tests were conducted at a room ambient of 25°C. 12 10 Figures 5 and 6 offer other plots of interest, DC supply current versus POUT and total amplifier power dissipation versus POUT. 8 6 4 2 INPUT NETWORK 0 The input network provides 50Ω impedance matching between the Lab Amplifier, used to drive the PA, and the power MOSFETs. The transformer T1 provides impedance transformation of the power MOSFET gates impedance and the balanced drive necessary for push-pull operation. 0 1 2 3 4 5 6 7 8 INPUT POWER (Watts) Figure 3. Gain versus Input Power 9 4 Total Amplifier Power Dissipation (Watts) The input pi network is comprised of capacitor C1, inductor L1 and the input capacitance of the power MOSFETs transformed by T1. The network is tuned for minimum return losses at the operating frequency by adjusting capacitor C1. The transformer T1, illustrated in Figure 7, provides a 4:1 impedance transformation of the input impedance of the power MOSFETs. It is constructed using a Fair-Rite #2843000202 two hole balun core, µi=850, with 2 turns on the primary and 1 turn on the secondary. The 120 100 80 60 40 20 0 0 secondary center tap is connected to ground through a 10KΩ resistor to provide the DC return to ground improving the stability and ruggedness of the PA. Without this resistor the gate voltages may become unbalanced due to slight differences in the input 100 200 300 400 500 OUTPUT POWER (Watts) Figure 6. Total Amplifier Power Dissipation versus Output Power of the MOSFETs or a small imbalance in the transformer voltage. RF INPUT 7 DC Supply Current (Amps) 140 To R1 6 GROUND 5 Q1 GATE Q2 GATE 4 Figure 7. Construction of Input Transformer T1 3 RF POWER DEVICES 2 The RF power devices used in the PA are the new, 200W, 300V, ARF442 and ARF443 RF power MOSFETs from APT. In the previous section we have demonstrated these devices have high performance at 13.56MHz. This performance results from the interdigitated chip structure of Power MOS IV, excellent thermal characteristics and symmetric package design, facilitating easy 1 0 0 100 200 300 400 500 OUTPUT POWER (Watts) Figure 5. DC Supply Current versus Output Power 5 gate resistance is accomplished by depositing a circuit layout and amplifier construction. MOSFETs are majority carrier devices making them theoretically capability of hundreds of megahertz operation. However, in practice high frequency operation of standard plastic power MOSFETs is limited. The input capacitance coupled with the internal series gate resistance combine to form a distributed RC circuit, Figure 8, which creates a pole causing the gate signal to be attenuated.[1] The internal source lead inductance acts to limit the upper frequency response through negative feedback. All three of these parameters need to be reduced to increase the frequency of operation. GATE AL POLY GATE OXIDE PASSIVATION n+ AL SOURCE p Fgiure n- DRAIN POWER MOS IV 9. Cross Section of APT Open Cell Power MOS IV® PASSIVATION AL SOURCE METAL OXIDE DIELECTRIC GATE n+ Vgsn Cgsn VgsnGm Cgs3 Vgs3Gm Cgs2 p DRAIN Vgs2Gm Cgs1 Rgn Vgs1Gm GATE Rg3 Vgs3 Rg2 Vgs2 Vgs1 DRAIN Rg1 SOURCE POLY Fgiure CELLULAR Figure 10. Cross Section of Closed Cell Type MOSFET Ls SOURCE 8. Simplified MOSFET Equivalent Circuit The APT Power MOS IV® technology shown in Figure 9, with it’s open cell structure, reduces both the series gate resistance and input capacitance (CISS).[2] The CISS is reduced in two ways; First the open cell structure does not have source metal overlapping the gate, as with closed cell type MOSFETs, see Figure 10, thus eliminating this component of the input capacitance. Second the gate oxide thickness has been increased to reduce the remaining capacitive components of CISS . The reduction of the series layer of metal over the gate poly silicon gate bus thus increasing the cross-sectional area and improving it’s conductivity. The open cell structure of Power MOS IV® makes this metal deposition possible. Plastic power MOSFETs are packaged to service their primary market, the switched mode power supply. As a result most manufacturers only use a single wire to connect the source pad to the source lead of the package, see Figure 11. This single wire is about 13nH [3] [4] of inductance and represents an impedance of about 1.1Ω at the operating frequency of 13.56MHz. This impedance will represent a significant negative 6 feedback thus reducing the gain of the device. Multiple Source Wires Single Source Wire erugF i G G Figure 11. Source Wiring Diagram of Cellular Type G MOSFET APT power MOSFETs have always enjoyed lower source inductance, less than 5nH [5], through the use of multiple source bond wires in the packages, see Figure 12. Optimizing the new package for better operation in the VHF Lo band, the number of source bond wires has been increased to further lower the source inductance, see Figure 13. Figure 13. Source Wiring Diagram of APT RF Power MOS IV® MECHANICAL LAYOUT A major drawback of the standard plastic package is the drain of the MOSFET is electrically and mechanically connected to the heat spreader of the package. This makes the back of the package at the drain potential, which is usually at a high voltage. This high voltage on the package requires an insulator be installed between the package and the heat sink. The addition of the insulator adds complexity and cost to the system assembly, not to mention the increase in junction to sink thermal resistance. Two Source Wires G G In the ARF package a high thermal conductivity insulating substrate has been inserted between the back of the die and the package heat spreader which allows the source to be bonded to Figure 12. Source Wiring Diagram of APT Open Cell Power MOS IV® 7 the heat spreader and creates a common source package configuration. As the gate and drain are then bonded to the outer floating pins of the package the choice of which pin is to become which electrode is arbitrary. This allows for the devices to be offered with the gate and drain leads to be on alternate sides. The user can then mount the devices in a symmetrical layout thus reducing the complexity of the layout and improving the performance.(see Appendix B for package diagrams) Although the inclusion of the substrate does add some thermal resistance to the package, the die has been thinned to mitigate this. The total thermal resistance junction to sink, using this package with thermal grease, is lower than the thermal resistance junction to sink using standard TO-247 packages with a typical insulator. The performance of the PA not only lies in the performance of the power devices used but also in the ability of the designer to keep the stray inductance in the gate drive loop to a minimum. They must keep the gate signal path balanced by maintaining the lead distance the same for both gate circuits. This design requirement is facilitated by the symmetric design of the ARF442 and ARF443. The ability to achieve a tight layout, with the APT devices, can be seen in Figure 14, Here the symmetry of the devices lends itself well to this layout. The devices can be positioned such that an axis of symmetry exists between the input and the output circuitry. This allows for the shortest possible connection between the output of T1 and the gates of the devices. DC RETURN 100VDC C1 RF INPUT T1 R1 BF Q1 L1 C1 C4 T2 G S D C23 C G S D C9 RF C10 OUTPUT L1 Q2 Figure 14. PA Layout 8 C7 C8 gluing two Fair-Rite #2643102002, µi=850, cores together to form a large two hole balun core. DC FEED CHOKE DESIGN The 100V DC input is delivered through a balanced feed choke. The balanced feed choke is designed to create a zero DC magnetic bias in the toroidal core when both transistors draw the same average current. With the two transistors operating 180 degrees out of phase, the construction of the windings presents an extremely high impedance at 13.56MHz to the drain of each RF MOSFET. This high impedance makes the feed choke invisible to the RF output matching network. The balanced feed choke, shown in Figure 15, was constructed by winding seven turns of #22 stranded PTFE twisted pair wire around an Indiana General #F624-19-Q1 Toroid core (0.5" OD, µi=125). VDC Q1 DRAIN RF OUTPUT Q2 DRAIN GROUND Figure 16. Output Transformer CONCLUSION This paper demonstrated a recent breakthrough in commercial solid state RF power device and circuit technology. The high quality, low cost, components and circuits described here, now make it possible to deliver solid state, 10,000 watt (or more), 13.56 MHz power supplies costing no more than an equivalent tube RF power supply. Q1 Q2 Figure 15. Balanced DC Feed Choke The combination of high voltage operation, high gain, and efficiency of 75 percent make this technology exciting just for performance alone. Combine that performance with component costs that allow for multi—kilowatt, 13.56 MHz amplifiers to be built at less than $0.25 per watt and you now have the first real break through in commercial HF, RF power technology in over a decade. OUTPUT TRANSFORMER DESIGN The output of the power devices is coupled to the load through a wideband 1:1 transmission line transformer. No output tuning or filtering was used as the amplifier provided low harmonic output with the third harmonic 16db down and the second harmonic 45db down at the 400W output power level. This is only the beginning. The commercial technology detailed in this paper will be evolving quickly into solid state devices and circuits for higher frequency, higher power, and even higher operating voltages. The transformer is illustrated in Figure 16. A 22 inch length of mini 50Ω PTFE coax was wound around a specially constructed core for a total of 4 turns. The transformer core was constructed by 9 REFERENCES [1] Ken Dierberger, “Gate Drive Design for Large Die MOSFETs”, PCIM ’93 Europe ,APT Application Note APT9302 [2] Tom Daly, “New Technology Makes Power MOSFETs Faster, More Efficient”, PCIM Magazine, January 1988 [3] International Rectifier, “HEXFET Power MOSFET Designer’s Manual”, IRFP440 Data Sheet Page C-538, HBD-4, 1987 [4] Motorola, “TMOS Power MOSFET Transistor Device Data”, MTW16N40E Data Sheet Page 1033, Q1/95 DL135D REV 5 [5] Advanced Power Technology, “POWER MOS IV ® PLASTIC PACKAGES IGBT PRODUCTS”., APT35GL60BN Data Sheet Page 7, Nov. 1992 10 APPENDIX A POWER AMPLIFIER PARTS LIST REFERENCE DESIGNATOR PART DESCRIPTION C1 C2, C3., C4, C5, C6, C7 C8 C9 C10 R1 Q1 Q2 L1 BFC1 75-480pF Compression Mica 0.01µF 200V CK06 0.1µF 100V CK06 10µF 100V Electrolytic 10K 5% 1/4W Carbon ARF442 ARF443 7T of #18AWG, ID=0.438", L=0.5µH Balanced DC Feed Choke; 7T fo #22 stranded PTFE twisted pair on an Indiana General #F62419-Q1 toroid µi=125 2T of #18 stranded PTFE on a Fair-Rite #2677006301 shield bead µi=2000 4:1 (Z) Conventional Transformer; 2:1 T of #22 stranded PTFE on a Fair-Rite #2843000202 Balun Core µi=850 1:1 (Z) Transmission Line Transformer using 22" of mini 50Ω PTFE coax OD=0.095. Wound on a large 2-hole Balun core constructed by gluing two Fair-Rite #2643102002 cores together µi=850. The transformer is constructed by winding 4 turns of the coax around the center of the Balun core. 0.062" G10 Epoxy Glass RFC1 T1 T2 PCB 11 ARF442/443 TO-247AD Package Outline ARF442 4.69 (.185) 5.31 (.209) 1.49 (.059) 2.49 (.098) 15.49 (.610) 16.26 (.640) 5.38 (.212) 6.20 (.244) Source 6.15 (.242) BSC 20.80 (.819) 21.46 (.845) 3.55 (.140) 3.81 (.150) ARF44E 2.87 (.113) 3.12 (.123) 4.50 (.177) Max. 0.40 (.016) 0.79 (.031) 1.65 (.065) 2.13 (.084) 19.81 (.780) 20.32 (.800) GATE SOURCE DRAIN 1.01 (.040) 1.40 (.055) 2.21 (.087) 2.59 (.102) 5.45 (.215) BSC 2-Plcs. Dimensions in Millimeters and (Inches) ARF443 4.69 (.185) 5.31 (.209) 1.49 (.059) 2.49 (.098) 15.49 (.610) 16.26 (.640) 5.38 (.212) 6.20 (.244) Source 6.15 (.242) BSC 20.80 (.819) 21.46 (.845) 3.55 (.140) 3.81 (.150) ARF44O 4.50 (.177) Max. 0.40 (.016) 0.79 (.031) 1.65 (.065) 2.13 (.084) 19.81 (.780) 20.32 (.800) 1.01 (.040) 1.40 (.055) 2.21 (.087) 2.59 (.102) 2.87 (.113) 3.12 (.123) DRAIN SOURCE GATE 5.45 (.215) BSC 2-Plcs. 050-4506 Rev B NOTE: The ARF442 and ARF443 comprise a symmetric pair of RF power transistors and meet the same electrical specifications. The device pin-outs are the mirror image of each other to allow ease of use as a push-pull pair. CAUTION: These Devices are Sensitive to Electrostatic Discharge. Proper Handling Procedures Should Be Followed. USA 405 S.W. Columbia Street Bend, Oregon 97702-1035 Phone: (541) 382-8028 FAX: (541) 388 -0364 EUROPE Avenue J.F. Kennedy Bât B4 Parc Cadéra Nord F-33700 Merignac - France Phone: (33) 5 57 92 15 15 FAX: (33) 5 56 47 97 61 12 405 S.W. Columbia Street Bend, Oregon 97702 USA Phone: (541) 382-8028 Fax: (541) 388-0364 http://www.advancedpower.com Parc Cadera Nord - Av. Kennedy BAT B4 33700 Merignac, France Phone: 33-557 92 15 15 Fax: 33-556 47 97 61 Printed - February 1995 13