Data Sheet

Freescale Semiconductor
Technical Data
Document Number: A2T20H330W24S
Rev. 0, 5/2015
RF Power LDMOS Transistor
N--Channel Enhancement--Mode Lateral MOSFET
This 58 W asymmetrical Doherty RF power LDMOS transistor is designed for
cellular base station applications requiring very wide instantaneous bandwidth
capability covering the frequency range of 1880 to 2025 MHz.
 Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc,
IDQA = 700 mA, VGSB = 0.3 Vdc, Pout = 58 W Avg., Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF.
Frequency
Gps
(dB)
D
(%)
Output PAR
(dB)
ACPR
(dBc)
1880 MHz
16.5
50.9
7.9
–33.1
1960 MHz
16.9
50.5
7.8
–36.0
2025 MHz
16.3
50.1
7.8
–36.8
A2T20H330W24SR6
1880–2025 MHz, 58 W AVG., 28 V
AIRFAST RF POWER LDMOS
TRANSISTOR
Features
 Advanced High Performance In--Package Doherty
 Designed for Wide Instantaneous Bandwidth Applications
 Greater Negative Gate--Source Voltage Range for Improved Class C
Operation
 Able to Withstand Extremely High Output VSWR and Broadband Operating
Conditions
 Designed for Digital Predistortion Error Correction Systems
NI--1230S--4L2L
6 VBWA(2)
Carrier
5 RFoutA/VDSA
RFinA/VGSA 1
(1)
RFinB/VGSB 2
4 RFoutB/VDSB
Peaking
3 VBWB(2)
(Top View)
Figure 1. Pin Connections
1. Pin connections 4 and 5 are DC coupled
and RF independent.
2. Device cannot operate with VDD current
supplied through pin 3 and pin 6.
 Freescale Semiconductor, Inc., 2015. All rights reserved.
RF Device Data
Freescale Semiconductor, Inc.
A2T20H330W24SR6
1
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Drain--Source Voltage
VDSS
–0.5, +65
Vdc
Gate--Source Voltage
VGS
–6.0, +10
Vdc
Operating Voltage
VDD
32, +0
Vdc
Storage Temperature Range
Tstg
–65 to +150
C
Case Operating Temperature Range
TC
–40 to +125
C
Operating Junction Temperature Range (1,2)
TJ
–40 to +225
C
CW
268
1.2
W
W/C
Symbol
Value (2,3)
Unit
RJC
0.25
C/W
CW Operation @ TC = 25C
Derate above 25C
Table 2. Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Case
Case Temperature 79C, 58 W W--CDMA, 28 Vdc, IDQA = 700 mA,
VGSB = 0.3 Vdc, f = 1960 MHz
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22--A114)
2
Machine Model (per EIA/JESD22--A115)
B
Charge Device Model (per JESD22--C101)
IV
Table 4. Electrical Characteristics (TA = 25C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
5
Adc
Gate--Source Leakage Current
(VGS = 5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 140 Adc)
VGS(th)
1.4
1.3
2.2
Vdc
Gate Quiescent Voltage
(VDD = 28 Vdc, ID = 700 mAdc, Measured in Functional Test)
VGSA(Q)
2.2
2.6
3.0
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 1.4 Adc)
VDS(on)
0.1
0.15
0.3
Vdc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 180 Adc)
VGS(th)
0.8
1.2
1.6
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 1.8 Adc)
VDS(on)
0.1
0.15
0.3
Vdc
Characteristic
Off Characteristics (4)
On Characteristics -- Side A, Carrier (4)
On Characteristics -- Side B, Peaking (4)
1.
2.
3.
4.
Continuous use at maximum temperature will affect MTTF.
MTTF calculator available at http://www.freescale.com/rf/calculators.
Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf and search for AN1955.
VDDA and VDDB must be tied together and powered by a single DC power supply.
(continued)
A2T20H330W24SR6
2
RF Device Data
Freescale Semiconductor, Inc.
Table 4. Electrical Characteristics (TA = 25C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
(1,2,3)
Functional Tests
(In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 700 mA, VGSB = 0.3 Vdc,
Pout = 58 W Avg., f = 1880 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF.
ACPR measured in 3.84 MHz Channel Bandwidth @ 5 MHz Offset.
Power Gain
Gps
15.5
16.5
18.5
dB
Drain Efficiency
D
48.5
50.9
—
%
PAR
7.2
7.9
—
dB
ACPR
—
–33.1
–29.0
dBc
Output Peak--to--Average Ratio @ 0.01% Probability on CCDF
Adjacent Channel Power Ratio
Load Mismatch
(3) (In
Freescale Doherty Test Fixture, 50 ohm system) IDQA = 700 mA, VGSB = 0.3 Vdc, f = 1960 MHz
VSWR 10:1 at 32 Vdc, 354 W Pulse Output Power
(3 dB Input Overdrive from 240 W Pulse Rated Power)
No Device Degradation
Typical Performance (3) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 700 mA, VGSB = 0.3 Vdc,
1880–2025 MHz Bandwidth
Pout @ 1 dB Compression Point, CW
P1dB
—
240
—
W
Pout @ 3 dB Compression Point (4)
P3dB
—
380
—
W

—
–19
—

VBWres
—
140
—
MHz
Gain Flatness in 145 MHz Bandwidth @ Pout = 58 W Avg.
GF
—
0.6
—
dB
Gain Variation over Temperature
(–30C to +85C)
G
—
0.005
—
dB/C
P1dB
—
0.006
—
dB/C
AM/PM
(Maximum value measured at the P3dB compression point across
the 1880–2025 MHz bandwidth)
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
Output Power Variation over Temperature
(–30C to +85C) (5)
Table 5. Ordering Information
Device
A2T20H330W24SR6
Tape and Reel Information
R6 Suffix = 150 Units, 56 mm Tape Width, 13--Reel
Package
NI--1230S--4L2L
1.
2.
3.
4.
VDDA and VDDB must be tied together and powered by a single DC power supply.
Part internally matched both on input and output.
Measurement made with device in an asymmetrical Doherty configuration.
P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W--CDMA single--carrier input signal where
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
5. Exceeds recommended operating conditions. See CW operation data in Maximum Ratings table.
A2T20H330W24SR6
RF Device Data
Freescale Semiconductor, Inc.
3
R4
C17 C5
C1
R1
C10
C
P
C12
R2
A2T20H330W24S
Rev. 0
C14
C2
R5
CUT OUT AREA
R3
C3
C4
C8
C9
C6
C7
C18
C15
VGGB
--
D64762
C11
VDDA
C16
C13
Z1
--
C19
VGGA
VDDB
C20
Note: VDDA and VDDB must be tied together and powered by a single DC power supply.
Figure 2. A2T20H330W24SR6 Test Circuit Component Layout
Table 6. A2T20H330W24SR6 Test Circuit Component Designations and Values
Part
Description
Part Number
Manufacturer
C1, C2, C3, C4, C5, C6, C7
8.2 pF Chip Capacitors
ATC600F8R2BT250XT
ATC
C8
5.6 pF Chip Capacitor
ATC600F5R6BT250XT
ATC
C9, C10
0.8 pF Chip Capacitors
ATC600F0R8BT250XT
ATC
C11, C12
0.6 pF Chip Capacitors
ATC600F0R6AT250XT
ATC
C13, C14, C15, C16, C17,
C18
10 F Chip Capacitors
C5750X7S2A106K230KB
TDK
C19, C20
220 F, 63 V Electrolytic Capacitors
SK063M0220B5S-1012
Yageo
R1, R2
2.2 , 1/4 W Chip Resistor
CRCW12062R20JNEA
Vishay
R3
50 , 10 W Chip Resistor
CW12010T0050GBK
ATC
R4, R5
1 K, 1/4 W Chip Resistors
CRCW12061K00FKEA
Vishay
Z1
1700–2000 MHz Band, 90, 5 dB Directional Coupler
X3C19P1-05S
Anaren
PCB
Rogers RO4350B, 0.020, r = 3.66
D64762
MTL
A2T20H330W24SR6
4
RF Device Data
Freescale Semiconductor, Inc.
TYPICAL CHARACTERISTICS
17
16.8
16.6
Gps
16.4
16.2
16
15.6
1850
1900
1925 1950 1975
f, FREQUENCY (MHz)
–33
–1.9
–35
–36
PARC
1875
–1.8
–34
ACPR
15.8
–32
2000
2025
–2
–2.1
–2.2
PARC (dB)
Gps, POWER GAIN (dB)
17.2
ACPR (dBc)
17.4
D, DRAIN
EFFICIENCY (%)
54
VDD = 28 Vdc, Pout = 58 W (Avg.), IDQA = 700 mA
53
VGSB = 0.3 Vdc, Single--Carrier W--CDMA, 3.84 MHz
Channel Bandwidth, Input Signal PAR = 9.9 dB @ 0.01%
52
Probability on CCDF
51
D
50
17.6
–2.3
–37
2050
IMD, INTERMODULATION DISTORTION (dBc)
Figure 3. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 58 Watts Avg.
–20
IM3--U
–30
IM3--L
IM5--L
–40
IM5--U
–50
IM7--L IM7--U
–60
–70
VDD = 28 Vdc, Pout = 30 W (PEP), IDQA = 700 mA
VGSB = 0.3 Vdc, Two--Tone Measurements
(f1 + f2)/2 = Center Frequency of 1960 MHz
1
10
300
100
TWO--TONE SPACING (MHz)
17.5
0
17
16.5
16
15.5
15
VDD = 28 Vdc, IDQA = 700 mA, VGSB = 0.3 Vdc, f = 1960 MHz
Single--Carrier W--CDMA
D
–1 dB = 34.7 W
–1
ACPR
–2
60
–20
50
–25
40
30
–2 dB = 53.5 W
–3
20
Gps
–3 dB = 73.5 W
–4
10
3.84 MHz Channel Bandwidth, Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF
–5
5
30
55
80
Pout, OUTPUT POWER (WATTS)
–30
–35
ACPR (dBc)
1
D DRAIN EFFICIENCY (%)
18
OUTPUT COMPRESSION AT 0.01%
PROBABILITY ON CCDF (dB)
Gps, POWER GAIN (dB)
Figure 4. Intermodulation Distortion Products
versus Two--Tone Spacing
–40
–45
PARC
105
0
130
–50
Figure 5. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2T20H330W24SR6
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS
Gps, POWER GAIN (dB)
18
1880 MHz
16
1960 MHz
D
1960 MHz
ACPR
2025 MHz
1960 MHz
12
3.84 MHz Channel Bandwidth
Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
1
50
–10
30
20
1880 MHz
10
8
1880 MHz
2025 MHz
0
40
2025 MHz
14
Gps
60
10
0
500
10
100
Pout, OUTPUT POWER (WATTS) AVG.
–20
–30
–40
ACPR (dBc)
VDD = 28 Vdc, IDQA = 700 mA, VGSB = 0.3 Vdc
Single--Carrier W--CDMA
D, DRAIN EFFICIENCY (%)
20
–50
–60
Figure 6. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
21
18
Gain
GAIN (dB)
15
12
9
VDD = 28 Vdc
Pin = 0 dBm
IDQA = 700 mA
VGSB = 0.3 Vdc
6
3
1600
1700
1800
1900 2000 2100
f, FREQUENCY (MHz)
2200
2300
2400
Figure 7. Broadband Frequency Response
A2T20H330W24SR6
6
RF Device Data
Freescale Semiconductor, Inc.
Table 7. Carrier Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQA = 774 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
1880
1.73 – j3.99
1.65 + j4.16
1960
3.43 – j5.25
3.31 + j5.46
2025
6.42 – j5.02
6.81 + j5.80
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1.09 – j3.27
19.2
52.2
167
59.4
–12
1.18 – j3.50
19.3
52.2
165
59.6
–13
1.20 – j3.67
19.5
52.1
163
58.7
–13
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1880
1.73 – j3.99
1.54 + j4.30
1.07 – j3.44
17.0
53.0
199
61.1
–16
1960
3.43 – j5.25
3.22 + j5.82
1.15 – j3.65
17.0
52.9
196
60.6
–17
2025
6.42 – j5.02
7.20 + j6.40
1.22 – j3.82
17.3
52.9
194
60.2
–17
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 8. Carrier Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, IDQA = 774 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1880
1.73 – j3.99
1.80 + j4.54
2.56 – j2.40
22.3
50.1
103
72.8
–18
1960
3.43 – j5.25
3.81 + j5.93
2.29 – j2.45
22.2
50.2
104
71.5
–19
2025
6.42 – j5.02
8.06 + j5.78
2.00 – j2.60
22.2
50.4
110
69.8
–18
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
2.72 – j2.37
20.4
50.6
114
74.9
–25
3.70 + j6.23
2.29 – j2.41
20.3
50.8
120
73.0
–26
8.59 + j6.16
2.06 – j2.48
20.4
50.9
123
72.0
–25
f
(MHz)
Zsource
()
Zin
()
1880
1.73 – j3.99
1.73 + j4.63
1960
3.43 – j5.25
2025
6.42 – j5.02
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T20H330W24SR6
RF Device Data
Freescale Semiconductor, Inc.
7
Table 9. Peaking Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, VGSB = 0.6 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
1880
1.21 – j4.59
1.07 + j4.59
1960
1.99 – j5.85
1.82 + j6.09
2025
3.66 – j7.62
3.48 + j7.91
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1.71 – j3.44
14.6
53.5
222
57.0
–33
1.77 – j3.38
15.0
53.5
226
57.7
–33
1.67 – j3.37
15.2
53.7
235
59.4
–35
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1880
1.21 – j4.59
1.07 + j4.78
1.63 – j3.56
12.4
54.3
268
58.0
–39
1960
1.99 – j5.85
1.92 + j6.43
1.77 – j3.58
12.8
54.3
270
58.5
–40
2025
3.66 – j7.62
3.91 + j8.48
1.82 – j3.65
13.0
54.4
276
60.0
–42
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 10. Peaking Side Load Pull Performance — Maximum Drain Efficiency Tuning
VDD = 28 Vdc, VGSB = 0.6 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
1880
1.21 – j4.59
0.93 + j4.56
3.89 – j2.29
15.8
51.9
156
67.3
–37
1960
1.99 – j5.85
1.61 + j6.06
3.07 – j2.05
16.2
52.3
170
67.7
–37
2025
3.66 – j7.62
3.07 + j7.90
2.72 – j1.91
16.3
52.3
170
69.5
–39
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
3.44 – j3.07
13.6
53.1
204
66.8
–44
1.75 + j6.42
3.25 – j2.35
14.1
53.0
200
67.7
–46
3.60 + j8.50
2.92 – j2.29
14.2
53.2
207
68.8
–47
f
(MHz)
Zsource
()
Zin
()
1880
1.21 – j4.59
0.99 + j4.78
1960
1.99 – j5.85
2025
3.66 – j7.62
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2T20H330W24SR6
8
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL CARRIER LOAD PULL CONTOURS — 1960 MHz
–1.5
–1.5
48 48.5
48.5
49.5
EE
–2.5
50
50.5
–3
52
–3.5
51.5
–2
49
IMAGINARY ()
IMAGINARY ()
–2
51
PP
–4
EE
–2.5
70
–3
–3.5
–4
50.5
–4.5
0.5
1
1.5
2
REAL ()
3
2.5
Figure 8. P1dB Load Pull Output Power Contours (dBm)
66
56
–4.5
0.5
3.5
68
P
P
1
58
1.5
2
REAL ()
–28
–2
–2
–26 –24
–22
IMAGINARY ()
EE
22
21.5
–3.5
PP
20
19
–4
21
20.5
1
1.5
2
REAL ()
–20
EE
–2.5
–16
–3
–3.5
PP
–14
–4
19.5
–4.5
0.5
3.5
–18
22.5
–3
3
2.5
–1.5
23
IMAGINARY ()
62
60
Figure 9. P1dB Load Pull Efficiency Contours (%)
–1.5
–2.5
64
–12
2.5
3
3.5
Figure 10. P1dB Load Pull Gain Contours (dB)
NOTE:
–4.5
0.5
1
1.5
2
REAL ()
2.5
3
3.5
Figure 11. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T20H330W24SR6
RF Device Data
Freescale Semiconductor, Inc.
9
P3dB – TYPICAL CARRIER LOAD PULL CONTOURS — 1960 MHz
–1.5
49
–2
–2
50
IMAGINARY ()
EE
–2.5
IMAGINARY ()
–1.5
49
49.5
50.5
–3
51.5
–3.5
PP
52.5
51
E
E
–2.5
72
–3
70
–3.5
68
PP
52
66
–4
–4
–4.5
0.5
–4.5
0.5
58
1
1.5
2
REAL ()
3
2.5
3.5
Figure 12. P3dB Load Pull Output Power Contours (dBm)
1
60 62
1.5
2
REAL ()
3
2.5
3.5
Figure 13. P3dB Load Pull Efficiency Contours (%)
–1.5
–1.5
21
IMAGINARY ()
–2.5
20
–3
19.5
19
–3.5
PP
17
1
1.5
17.5
–2.5
–22
–3
–20
–3.5
–18
PP
–4
18
2
REAL ()
–24
EE
18.5
–4
–4.5
0.5
–26
20.5
EE
–28
–30
–2
–2
IMAGINARY ()
64
2.5
3
3.5
Figure 14. P3dB Load Pull Gain Contours (dB)
NOTE:
–16
–4.5
0.5
–14
1
1.5
2
REAL ()
2.5
3
3.5
Figure 15. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T20H330W24SR6
10
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL PEAKING LOAD PULL CONTOURS — 1960 MHz
0
0
50
49.5
–1
51
–2
EE
IMAGINARY ()
IMAGINARY ()
–1
51.5
–3
53.5
–4
P
P
52.5
52
2
EE
3
4
REAL ()
–3
P
5
6
–5
7
Figure 16. P1dB Load Pull Output Power Contours (dBm)
60
52
54
2
1
58
56
3
4
REAL ()
0
–46
–44
–42
–1
IMAGINARY ()
–1
EE
16
–3
PP
–4
13
–5
1
13.5
2
3
5
6
7
–40
E
E
–36
–3
PP
–34
–4
15
14.5
52
–38
–2
15.5
14
54
Figure 17. P1dB Load Pull Efficiency Contours (%)
0
–2
62
66
–4
52 52.5
1
64
–2
P
53
–5
IMAGINARY ()
56
50
50.5
–32
4
REAL ()
5
6
7
Figure 18. P1dB Load Pull Gain Contours (dB)
NOTE:
–5
1
2
3
4
REAL ()
5
6
7
Figure 19. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T20H330W24SR6
RF Device Data
Freescale Semiconductor, Inc.
11
P3dB – TYPICAL PEAKING LOAD PULL CONTOURS — 1960 MHz
0
50.5
0
50.5
–1
51
51.5
–2
EE
53
–3
54
PP
IMAGINARY ()
IMAGINARY ()
–1
52
52.5
–2
EE
66
–3
53.5
64
P
P
62
53
–5
2
1
3
4
REAL ()
5
6
–5
7
Figure 20. P3dB Load Pull Output Power Contours (dBm)
2
1
3
4
REAL ()
–52
–3
–46
11
–5
1
–44
–2
12
–3
2
3
4
REAL ()
–40
PP
–4
13
12.5
11.5
–42
EE
13.5
PP
–4
7
–48
–50
–1
IMAGINARY ()
–1
EE
6
5
0
14
52
54
Figure 21. P3dB Load Pull Efficiency Contours (%)
0
–2
54
56
58
52
IMAGINARY ()
60
–4
–4
–38
5
6
7
Figure 22. P3dB Load Pull Gain Contours (dB)
NOTE:
–5
1
–38
2
3
4
REAL ()
5
6
7
Figure 23. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2T20H330W24SR6
12
RF Device Data
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
A2T20H330W24SR6
RF Device Data
Freescale Semiconductor, Inc.
13
A2T20H330W24SR6
14
RF Device Data
Freescale Semiconductor, Inc.
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
 AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
 EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
 Electromigration MTTF Calculator
 RF High Power Model
 .s2p File
Development Tools
 Printed Circuit Boards
To Download Resources Specific to a Given Part Number:
1. Go to http://www.freescale.com/rf
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
0
May 2015
Description
 Initial Release of Data Sheet
A2T20H330W24SR6
RF Device Data
Freescale Semiconductor, Inc.
15
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A2T20H330W24SR6
Document Number: A2T20H330W24S
Rev. 0, 5/2015
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RF Device Data
Freescale Semiconductor, Inc.
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