Data Sheet

Document Number: AFT23H200−4S2L
Rev. 1, 5/2013
Freescale Semiconductor
Technical Data
RF Power LDMOS Transistor
N−Channel Enhancement−Mode Lateral MOSFET
AFT23H200−4S2LR6
This 45 watt asymmetrical Doherty RF power LDMOS transistor is designed
for cellular base station applications covering the frequency range of
2300 to 2400 MHz.
• Typical Doherty Single−Carrier W−CDMA Performance: VDD = 28 Volts,
IDQA = 500 mA, VGSB = 0.5 Vdc, Pout = 45 Watts Avg., Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF.
Frequency
Gps
(dB)
hD
(%)
Output PAR
(dB)
ACPR
(dBc)
2300 MHz
15.3
42.8
8.4
−27.6
2350 MHz
15.4
43.3
8.3
−31.1
2400 MHz
15.2
42.8
8.3
−33.9
2300−2400 MHz, 45 W AVG., 28 V
Features
• Advanced High Performance In−Package Doherty
• Greater Negative Gate−Source Voltage Range for Improved Class C
Operation
• Designed for Digital Predistortion Error Correction Systems
• In Tape and Reel. R6 Suffix = 150 Units, 56 mm Tape Width, 13−inch Reel.
NI−1230−4LS2L
6 VBWA (1)
Carrier
RFinA/VGSA 1
5 RFoutA/VDSA
RFinB/VGSB 2
4 RFoutB/VDSB
Peaking
3 VBWB (1)
(Top View)
Figure 1. Pin Connections
1. Device cannot operate with the VDD current
supplied through pin 3 and pin 6.
© Freescale Semiconductor, Inc., 2013. All rights reserved.
RF Device Data
Freescale Semiconductor, Inc.
AFT23H200−4S2LR6
1
Table 1. Maximum Ratings
Symbol
Value
Unit
Drain−Source Voltage
Rating
VDSS
−0.5, +65
Vdc
Gate−Source Voltage
VGS
−6.0, +10
Vdc
Operating Voltage
VDD
32, +0
Vdc
Storage Temperature Range
Tstg
−65 to +150
°C
Case Operating Temperature Range
TC
−40 to +150
°C
TJ
−40 to +225
°C
CW
294
1.7
W
W/°C
Operating Junction Temperature Range
(1,2)
CW Operation @ TC = 25°C
Derate above 25°C
Table 2. Thermal Characteristics
Characteristic
Symbol
Value (2,3)
Unit
Thermal Resistance, Junction to Case
Case Temperature 75°C, 45 W W−CDMA, 28 Vdc, IDQA = 500 mA, VGSB = 0.5 Vdc, 2350 MHz
RθJC
0.32
°C/W
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22−A114)
2
Machine Model (per EIA/JESD22−A115)
B
Charge Device Model (per JESD22−C101)
IV
Table 4. Electrical Characteristics (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
μAdc
Zero Gate Voltage Drain Leakage Current
(VDS = 28 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
μAdc
Gate−Source Leakage Current
(VGS = 5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
μAdc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 140 μAdc)
VGS(th)
0.8
1.2
1.6
Vdc
Gate Quiescent Voltage
(VDD = 28 Vdc, IDA = 500 mAdc, Measured in Functional Test)
VGS(Q)
1.4
1.8
2.2
Vdc
Drain−Source On−Voltage
(VGS = 6 Vdc, ID = 1.4 Adc)
VDS(on)
0.1
0.14
0.4
Vdc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 200 μAdc)
VGS(th)
0.8
1.2
1.6
Vdc
Drain−Source On−Voltage
(VGS = 6 Vdc, ID = 2 Adc)
VDS(on)
0.1
0.14
0.4
Vdc
Off Characteristics
(4)
On Characteristics − Side A (4) (Carrier)
On Characteristics − Side B (4) (Peaking)
1. Continuous use at maximum temperature will affect MTTF.
2. MTTF calculator available at http://www.freescale.com/rf. Select Software & Tools/Development Tools/Calculators to access MTTF
calculators by product.
3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf.
Select Documentation/Application Notes − AN1955.
4. Each side of device measured separately.
(continued)
AFT23H200−4S2LR6
2
RF Device Data
Freescale Semiconductor, Inc.
Table 4. Electrical Characteristics (TA = 25°C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Functional Tests (1,2,3) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 500 mA, VGSB = 0.5 Vdc, Pout = 45 W Avg.,
f = 2300 MHz, Single−Carrier W−CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in
3.84 MHz Channel Bandwidth @ ±5 MHz Offset.
Power Gain
Gps
14.6
15.3
17.6
dB
Drain Efficiency
ηD
38.0
42.8
—
%
PAR
7.6
8.4
—
dB
ACPR
—
−27.6
−25.0
dBc
Output Peak−to−Average Ratio @ 0.01% Probability on CCDF
Adjacent Channel Power Ratio
Load Mismatch (In Freescale Test Fixture, 50 ohm system) IDQA = 500 mA, f = 2350 MHz
VSWR 10:1 at 32 Vdc, 330 W CW (4) Output Power
(3 dB Input Overdrive from 200 W CW (4) Rated Power)
No Device Degradation
Typical Performances (2) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 500 mA, VGSB = 0.5 Vdc,
2300−2400 MHz Bandwidth
Pout @ 1 dB Compression Point, CW
P1dB
—
210 (4)
—
W
Pout @ 3 dB Compression Point (5)
P3dB
—
290
—
W
Φ
—
34
—
°
VBWres
—
150
—
MHz
Gain Flatness in 100 MHz Bandwidth @ Pout = 45 W Avg.
GF
—
0.3
—
dB
Gain Variation over Temperature
(−30°C to +85°C)
ΔG
—
0.007
—
dB/°C
ΔP1dB
—
0.002
—
dB/°C
AM/PM
(Maximum value measured at the P3dB compression point across
the 2300−2400 MHz frequency range)
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
Output Power Variation over Temperature
(−30°C to +85°C) (4)
1.
2.
3.
4.
5.
Part internally matched both on input and output.
VDDA and VDDB must be tied together and powered by a single DC power supply.
Measurements made with device in an asymmetrical Doherty configuration.
Exceeds recommended operating conditions. See CW operation data in Maximum Ratings table.
P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W−CDMA single−carrier input signal where
output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
AFT23H200−4S2LR6
RF Device Data
Freescale Semiconductor, Inc.
3
VDDA
VGGA
C16
C10
C4
C5
R2
C8
C9
AFT23H200_4WS
Rev. 2
C
Z1
C11
C1
C3
R1
R3
CUT OUT AREA
C2
C12
P
C13
C7
C14
C15
C6
VDDB
C17
VGGB
Figure 2. AFT23H200−4S2LR6 Test Circuit Component Layout
Table 5. AFT23H200−4S2LR6 Test Circuit Component Designations and Values
Part
Description
Part Number
Manufacturer
C1
0.3 pF Chip Capacitor
ATC100B0R3BT500XT
ATC
C2, C3, C5, C7, C9, C12,
C14
6.8 pF Chip Capacitors
ATC100B6R8CT500XT
ATC
C4, C6
2.2 μF Chip Capacitors
GRM55DR72H225KA88L
Murata
C8, C10, C13, C15
10 μF Chip Capacitors
GRM55DR61H106KA88L
Murata
C11
5.1 pF Chip Capacitor
ATC100B5R1CT500XT
ATC
C16, C17
220 μF, 50 V Electrolytic Capacitors
MVY50VC221MJ10TP
United Chem
R1
50 Ω, 10 W Chip Resistor
060120A15Z50−2
Anaren
R2, R3
2.7 Ω, 1/16 W Chip Resistors
CR10-120J-B
Kyocera
Z1
2300−2700 MHz Band, 90°, 3 dB Hybrid Coupler
X3C25P1-05S
Anaren
PCB
0.020″, εr = 3.5
RO4350B
Rogers
AFT23H200−4S2LR6
4
RF Device Data
Freescale Semiconductor, Inc.
16
43
15.8
42
41.5
15.2
Gps
14.8
ACPR
14.6
PARC
3.84 MHz Channel Bandwidth, Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF
14
2290
2305
2320
2335
2350
2365
-1.5
-28
-1.6
-30
14.4
14.2
-26
-32
-34
2380
-1.7
-1.8
-1.9
-36
2410
2395
PARC (dB)
41
15
ACPR (dBc)
Gps, POWER GAIN (dB)
15.6
15.4
42.5
ηD
VDD = 28 Vdc, Pout = 45 W (Avg.)
IDQA = 500 mA, VGSB = 0.5 Vdc
Single-Carrier W-CDMA
ηD, DRAIN
EFFICIENCY (%)
TYPICAL CHARACTERISTICS
-2
f, FREQUENCY (MHz)
IMD, INTERMODULATION DISTORTION (dBc)
Figure 3. Single−Carrier Output Peak−to−Average Ratio Compression
(PARC) Broadband Performance @ Pout = 45 Watts Avg.
-10
VDD = 28 Vdc, Pout = 24 W (PEP), IDQA = 500 mA
VGSB = 0.5 Vdc, Two-Tone Measurements
-20 (f1 + f2)/2 = Center Frequency of 2350 MHz
IM3-U
-30
IM3-L
-40
IM5-L
-50
IM7-U
IM7-L
IM5-U
-60
10
1
200
100
TWO-TONE SPACING (MHz)
Figure 4. Intermodulation Distortion Products
versus Two−Tone Spacing
15.5
-1
15
14.5
14
13.5
OUTPUT COMPRESSION AT 0.01%
PROBABILITY ON CCDF (dB)
Gps, POWER GAIN (dB)
-1 dB = 35 W
13
ηD
55
-25
50
-26
Gps
-2
45
-2 dB = 47 W
-3
ACPR
-3 dB = 63 W
40
VDD = 28 Vdc
IDQA = 500 mA
VGSB = 0.5 Vdc
f = 2350 MHz
-4
-5
PARC
35
Single-Carrier W-CDMA 3.84 MHz Channel
Bandwidth, Input Signal PAR = 9.9 dB
@ 0.01% Probability on CCDF
-6
25
40
55
70
85
-27
-28
ACPR (dBc)
0
ηD, DRAIN EFFICIENCY (%)
16
-29
30
-30
25
-31
100
Pout, OUTPUT POWER (WATTS)
Figure 5. Output Peak−to−Average Ratio
Compression (PARC) versus Output Power
AFT23H200−4S2LR6
RF Device Data
Freescale Semiconductor, Inc.
5
TYPICAL CHARACTERISTICS
2400 MHz
14.5
Gps
ACPR
2300 MHz
2350 MHz
14
60
0
50
-10
40
30
2300 MHz
2400 MHz
2350 MHz
2350 MHz
2300 MHz
13.5
13
3.84 MHz Channel Bandwidth, Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF
12.5
1
10
100
20
10
0
300
-20
-30
-40
ACPR (dBc)
15
Gps, POWER GAIN (dB)
ηD
VDD = 28 Vdc, IDQA = 500 mA, VGSB = 0.5 Vdc
Single-Carrier W-CDMA
ηD, DRAIN EFFICIENCY (%)
15.5
-50
-60
Pout, OUTPUT POWER (WATTS) AVG.
Figure 6. Single−Carrier W−CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
24
20
GAIN (dB)
16
VDD = 28 Vdc
Pin = 0 dBm
IDQA = 500 mA
VGSB = 0.5 Vdc
Gain
12
8
4
0
2000
2100
2200
2300
2400
2500
2600
2700
2800
f, FREQUENCY (MHz)
Figure 7. Broadband Frequency Response
AFT23H200−4S2LR6
6
RF Device Data
Freescale Semiconductor, Inc.
VDD = 28 Vdc, IDQA = 734 mA, Pulsed CW, 10 μsec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
(W)
Zin
(W)
Zload (1)
(W)
Gain (dB)
(dBm)
(W)
hD
(%)
AM/PM
(5)
2300
4.98 - j10.2
5.10 + j9.68
2.07 - j3.84
18.4
51.9
154
57.8
-12
2350
8.15 - j11.4
7.40 + j10.5
2.02 - j3.81
18.4
51.8
153
57.3
-13
2400
12.1 - j11.3
11.0 + j10.5
1.89 - j3.59
18.3
51.8
153
56.7
-13
Max Output Power
P3dB
Gain (dB)
(dBm)
(W)
hD
(%)
AM/PM
(5)
1.89 - j3.98
16.1
52.7
186
58.3
-17
7.86 + j11.5
1.83 - j4.03
16.0
52.6
184
57.4
-17
12.4 + j11.6
1.78 - j3.84
16.1
52.6
183
57.2
-18
f
(MHz)
Zsource
(W)
Zin
(W)
2300
4.98 - j10.2
5.13 + j10.4
2350
8.15 - j11.4
2400
12.1 - j11.3
Zload
(W)
(2)
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Figure 8. Carrier Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQA = 734 mA, Pulsed CW, 10 μsec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
Gain (dB)
(dBm)
(W)
hD
(%)
AM/PM
(5)
4.33 - j3.62
20.4
50.4
110
65.8
-17
7.45 + j11.2
3.92 - j2.92
20.3
50.5
113
65.8
-18
11.4 + j11.0
3.72 - j2.68
20.3
50.4
111
65.5
-18
f
(MHz)
Zsource
(W)
Zin
(W)
2300
4.98 - j10.2
5.15 + j10.1
2350
8.15 - j11.4
2400
12.1 - j11.3
Zload
(W)
(1)
Max Drain Efficiency
P3dB
f
(MHz)
Zsource
(W)
Zin
(W)
2300
4.98 - j10.2
5.00 + j10.7
2350
8.15 - j11.4
7.58 + j12.1
2400
12.1 - j11.3
12.3 + j12.3
Gain (dB)
(dBm)
(W)
hD
(%)
AM/PM
(5)
3.99 - j3.52
18.2
51.3
136
66.6
-24
3.77 - j2.92
18.2
51.2
133
66.3
-25
3.44 - j2.68
18.2
51.3
134
66.1
-26
Zload
(W)
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Figure 9. Carrier Side Load Pull Performance — Maximum Drain Efficiency Tuning
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
AFT23H200−4S2LR6
RF Device Data
Freescale Semiconductor, Inc.
7
VDD = 28 Vdc, VGSB = 1.8 Vdc, Pulsed CW, 10 μsec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
(W)
Zin
(W)
Zload (1)
(W)
Gain (dB)
(dBm)
(W)
hD
(%)
AM/PM
(5)
2300
4.16 - j8.18
3.52 + j7.55
2.12 - j4.32
17.5
53.0
200
54.8
-11
2350
6.03 - j8.44
4.66 + j8.11
2.09 - j4.32
17.7
53.0
201
55.0
-11
2400
8.93 - j7.56
6.30 + j8.25
2.07 - j4.25
17.8
53.0
201
55.0
-11
Max Output Power
P3dB
Gain (dB)
(dBm)
(W)
hD
(%)
AM/PM
(5)
2.02 - j4.65
15.2
53.8
242
55.8
-15
4.76 + j8.79
2.00 - j4.52
15.5
53.8
241
55.8
-15
6.76 + j9.07
2.02 - j4.47
15.5
53.8
239
55.5
-16
f
(MHz)
Zsource
(W)
Zin
(W)
2300
4.16 - j8.18
3.48 + j8.04
2350
6.03 - j8.44
2400
8.93 - j7.56
Zload
(W)
(2)
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Figure 10. Peaking Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, VGSB = 1.8 Vdc, Pulsed CW, 10 μsec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
Gain (dB)
(dBm)
(W)
hD
(%)
AM/PM
(5)
4.02 - j2.94
19.5
51.7
148
63.4
-16
4.63 + j8.38
3.77 - j2.78
19.7
51.7
147
63.7
-17
6.25 + j8.53
3.29 - j2.37
19.8
51.5
142
63.7
-18
f
(MHz)
Zsource
(W)
Zin
(W)
2300
4.16 - j8.18
3.44 + j7.85
2350
6.03 - j8.44
2400
8.93 - j7.56
Zload
(W)
(1)
Max Drain Efficiency
P3dB
f
(MHz)
Zsource
(W)
Zin
(W)
2300
4.16 - j8.18
3.31 + j8.22
2350
6.03 - j8.44
4.53 + j8.99
2400
8.93 - j7.56
6.50 + j9.33
Gain (dB)
(dBm)
(W)
hD
(%)
AM/PM
(5)
3.97 - j3.19
17.4
52.5
176
64.4
-22
3.45 - j2.78
17.6
52.4
175
64.6
-24
3.17 - j2.43
17.8
52.2
166
64.2
-25
Zload
(W)
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Figure 11. Peaking Side Load Pull Performance — Maximum Drain Efficiency Tuning
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
AFT23H200−4S2LR6
8
RF Device Data
Freescale Semiconductor, Inc.
P1dB − TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 2350 MHz
0
0
50 52 56
48
49
49.5
50
50.5
48
48.5
-2
IMAGINARY (Ω)
IMAGINARY (Ω)
58 60
62
-1
-1
51
E
-3
51.5
P
-4
54
64
-2
E
-3
P
-4
-5
-5
50
-6
-6
3
2
1
4
5
7
6
2
1
3
4
5
6
7
REAL (Ω)
REAL (Ω)
Figure 12. P1dB Load Pull Output Power Contours (dBm)
Figure 13. P1dB Load Pull Efficiency Contours (%)
0
0
-1
-1
-26
-2
IMAGINARY (Ω)
IMAGINARY (Ω)
-24
E
-3
21
P
-4
18
19
-22
-2
-20
E
-3
-18
P
-4
20.5
-5
-16
-5
20
19.5
18.5
17.5
-6
1
2
3
4
5
6
7
-12
-10
-6
1
2
-14
3
4
5
6
REAL (Ω)
REAL (Ω)
Figure 14. P1dB Load Pull Gain Contours (dB)
Figure 15. P1dB Load Pull AM/PM Contours (5)
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
7
Power Gain
Drain Efficiency
Linearity
Output Power
AFT23H200−4S2LR6
RF Device Data
Freescale Semiconductor, Inc.
9
P3dB − TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 2350 MHz
0
0
48.5
49
60
62
-1
-1
52 56
49.5
50
50.5
51
-2
IMAGINARY (Ω)
IMAGINARY (Ω)
58
54
50
51.5
52
-3
E
52.5
-4
P
64
-2
E
-3
66
-4
P
60
-5
-5
58
49
-6
-6
3
2
1
4
5
7
6
2
1
3
4
5
6
7
REAL (Ω)
REAL (Ω)
Figure 16. P3dB Load Pull Output Power Contours (dBm)
Figure 17. P3dB Load Pull Efficiency Contours (%)
0
0
16.5
16
15.5
-3
-4
-32
19
17
-2
-34
-1
IMAGINARY (Ω)
IMAGINARY (Ω)
18.5
17.5 18
-1
E
P
-2
-30
E
-3
-26
-4
-24
P
-18
-5
-28
-22
-20
-5
-6
-6
1
2
3
4
5
6
7
1
2
3
4
5
6
REAL (Ω)
REAL (Ω)
Figure 18. P3dB Load Pull Gain Contours (dB)
Figure 19. P3dB Load Pull AM/PM Contours (5)
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
7
Power Gain
Drain Efficiency
Linearity
Output Power
AFT23H200−4S2LR6
10
RF Device Data
Freescale Semiconductor, Inc.
P1dB − TYPICAL PEAKING LOAD PULL CONTOURS — 2350 MHz
-2.5
-2.5
50.5
E
E
-3
-3
51
IMAGINARY (Ω)
IMAGINARY (Ω)
51.5
-3.5
52
-4
52.5
P
-4.5
53
62
-3.5
60
-4
P
-4.5
58
-5
-5
-5.5
-5.5
52
46
56
48 50
-6
1.5
2.5
2
3
3.5
4
4.5
5
5.5
-6
1.5
6
2.5
2
54
3
3.5
4
4.5
5
5.5
6
REAL (Ω)
REAL (Ω)
Figure 20. P1dB Load Pull Output Power Contours (dBm)
Figure 21. P1dB Load Pull Efficiency Contours (%)
-2.5
-2.5
20
E
E
-3
-3
-3.5
-3.5
IMAGINARY (Ω)
IMAGINARY (Ω)
-16
19.5
-4
19
P
-4.5
18.5
-5
-5.5
-4
-14
P
-4.5
-12
-5
17.5
16.5
16
-6
1.5
18
-10
-5.5
17
2
2.5
3
3.5
4
4.5
5
5.5
6
-6
1.5
2
2.5
3
3.5
4
4.5
5
5.5
REAL (Ω)
REAL (Ω)
Figure 22. P1dB Load Pull Gain Contours (dB)
Figure 23. P1dB Load Pull AM/PM Contours (5)
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
6
Power Gain
Drain Efficiency
Linearity
Output Power
AFT23H200−4S2LR6
RF Device Data
Freescale Semiconductor, Inc.
11
P3dB − TYPICAL PEAKING LOAD PULL CONTOURS — 2350 MHz
-2.5
-2.5
EE
E
-3
52.5
IMAGINARY (Ω)
52
-3.5
IMAGINARY (Ω)
64
-3
51.5
53
-4
53.5
-4.5
PP
-3.5
62
-4
-4.5
P
60
-5
-5
-5.5
-5.5
58
50
48
-6
1.5
2.5
2
3
3.5
4
4.5
5
5.5
-6
1.5
6
52
2
56
54
2.5
3
3.5
54
4
4.5
5
5.5
6
REAL (Ω)
REAL (Ω)
Figure 24. P3dB Load Pull Output Power Contours (dBm)
Figure 25. P3dB Load Pull Efficiency Contours (%)
-2.5
-2.5
18
E
-24
E
-3
-3
-3.5
-3.5
IMAGINARY (Ω)
IMAGINARY (Ω)
-22
-4
17.5
-4.5
P
17
16.5
-5
-20
-4
-18
-4.5
P
-16
-5
14.5
15.5
14
15
16
-5.5
-5.5
-6
1.5
2
-14
2.5
3
3.5
4
4.5
5
5.5
6
-6
1.5
2
2.5
3
3.5
4
4.5
5
5.5
REAL (Ω)
REAL (Ω)
Figure 26. P3dB Load Pull Gain Contours (dB)
Figure 27. P3dB Load Pull AM/PM Contours (5)
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
6
Power Gain
Drain Efficiency
Linearity
Output Power
AFT23H200−4S2LR6
12
RF Device Data
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
AFT23H200−4S2LR6
RF Device Data
Freescale Semiconductor, Inc.
13
AFT23H200−4S2LR6
14
RF Device Data
Freescale Semiconductor, Inc.
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following documents, software and tools to aid your design process.
Application Notes
• AN1955: Thermal Measurement Methodology of RF Power Amplifiers
Engineering Bulletins
• EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
• Electromigration MTTF Calculator
• RF High Power Model
• .s2p File
Development Tools
• Printed Circuit Boards
For Software and Tools, do a Part Number search at http://www.freescale.com, and select the “Part Number” link. Go to the
Software & Tools tab on the part’s Product Summary page to download the respective tool.
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
Description
0
May 2013
• Initial Release of Data Sheet
1
May 2013
• On Characteristics tables: Gate threshold voltage, VGS(th), updated to reflect actual test condition,
VDS = 10 Vdc, p. 2
AFT23H200−4S2LR6
RF Device Data
Freescale Semiconductor, Inc.
15
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E 2013 Freescale Semiconductor, Inc.
AFT23H200−4S2LR6
Document Number: AFT23H200−4S2L
Rev.
16 1, 5/2013
RF Device Data
Freescale Semiconductor, Inc.
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