Freescale Semiconductor Technical Data Document Number: A2T07D160W04S Rev. 0, 8/2014 RF Power LDMOS Transistor N--Channel Enhancement--Mode Lateral MOSFET This 30 W symmetrical Doherty RF power LDMOS transistor is designed for cellular base station applications requiring very wide instantaneous bandwidth capability covering the frequency range of 716 to 960 MHz. A2T07D160W04SR3 780 MHz Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc, IDQA = 450 mA, VGSB = 1.2 Vdc, Pout = 30 W Avg., Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. Frequency Gps (dB) D (%) Output PAR (dB) ACPR (dBc) 758 MHz 22.2 47.7 7.3 –29.3 780 MHz 22.1 47.9 7.3 –30.1 803 MHz 21.5 48.5 7.2 –31.4 716–960 MHz, 30 W AVG., 28 V AIRFAST RF POWER LDMOS TRANSISTOR 880 MHz Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc, IDQA = 450 mA, VGSB = 1.3 Vdc, Pout = 30 W Avg., Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. Frequency Gps (dB) D (%) Output PAR (dB) ACPR (dBc) 865 MHz 20.5 48.4 7.4 –31.5 880 MHz 20.5 48.6 7.4 –31.6 895 MHz 20.3 49.2 7.3 –31.6 Features Designed for Wide Instantaneous Bandwidth Applications Greater Negative Gate--Source Voltage Range for Improved Class C Operation Able to Withstand Extremely High Output VSWR and Broadband Operating Conditions Designed for Digital Predistortion Error Correction Systems In Tape and Reel. R3 Suffix = 250 Units, 32 mm Tape Width, 13--inch Reel. Freescale Semiconductor, Inc., 2014. All rights reserved. RF Device Data Freescale Semiconductor, Inc. NI--780S--4L Carrier RFinA/VGSA 3 1 RFoutA/VDSA (1) 2 RFoutB/VDSB RFinB/VGSB 4 Peaking (Top View) Figure 1. Pin Connections 1. Pin connections 1 and 2 are DC coupled and RF independent. A2T07D160W04SR3 1 Table 1. Maximum Ratings Symbol Value Unit Drain--Source Voltage Rating VDSS –0.5, +70 Vdc Gate--Source Voltage VGS –6.0, +10 Vdc Operating Voltage VDD 32, +0 Vdc Storage Temperature Range Tstg –65 to +150 C Case Operating Temperature Range TC –40 to +125 C TJ –40 to +225 C CW 94 0.87 W W/C Operating Junction Temperature Range (1,2) CW Operation @ TC = 25C Derate above 25C Table 2. Thermal Characteristics Characteristic Thermal Resistance, Junction to Case Case Temperature 77C, 30 W W--CDMA, 28 Vdc, IDQA = 450 mA, VGSB = 1.2 Vdc, 780 MHz Symbol Value (2,3) Unit RJC 0.63 C/W Table 3. ESD Protection Characteristics Test Methodology Class Human Body Model (per JESD22--A114) 2 Machine Model (per EIA/JESD22--A115) A Charge Device Model (per JESD22--C101) IV Table 4. Electrical Characteristics (TA = 25C unless otherwise noted) Symbol Min Typ Max Unit Zero Gate Voltage Drain Leakage Current (VDS = 70 Vdc, VGS = 0 Vdc) IDSS — — 10 Adc Zero Gate Voltage Drain Leakage Current (VDS = 32 Vdc, VGS = 0 Vdc) IDSS — — 5 Adc Gate--Source Leakage Current (VGS = 5 Vdc, VDS = 0 Vdc) IGSS — — 1 Adc Gate Threshold Voltage (VDS = 10 Vdc, ID = 112 Adc) VGS(th) 1.0 1.5 2.0 Vdc Gate Quiescent Voltage (VDD = 28 Vdc, IDA = 450 mAdc, Measured in Functional Test) VGS(Q) 1.7 2.2 2.7 Vdc Drain--Source On--Voltage (VGS = 10 Vdc, ID = 1.12 Adc) VDS(on) 0.05 0.14 0.3 Vdc Gate Threshold Voltage (VDS = 10 Vdc, ID = 112 Adc) VGS(th) 1.0 1.5 2.0 Vdc Drain--Source On--Voltage (VGS = 10 Vdc, ID = 1.12 Adc) VDS(on) 0.05 0.2 0.3 Vdc Characteristic Off Characteristics (4,5) On Characteristics -- Side A (4,6) (Carrier) On Characteristics -- Side B (4,6) (Peaking) 1. Continuous use at maximum temperature will affect MTTF. 2. MTTF calculator available at http://www.freescale.com/rf. Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. 3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf. Select Documentation/Application Notes -- AN1955. 4. VDDA and VDDB must be tied together and powered by a single DC power supply. 5. Side A and Side B are tied together for these measurements. 6. Each side of device measured separately. (continued) A2T07D160W04SR3 2 RF Device Data Freescale Semiconductor, Inc. Table 4. Electrical Characteristics (TA = 25C unless otherwise noted) (continued) Characteristic Symbol Min Typ Max Unit Functional Tests (1,2,3) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 450 mA, VGSB = 1.2 Vdc, Pout = 30 W Avg., f = 803 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in 3.84 MHz Channel Bandwidth @ 5 MHz Offset. Power Gain Gps 20.2 21.5 23.2 dB Drain Efficiency D 46.0 48.5 — % PAR 6.8 7.2 — dB ACPR — –31.4 –28.0 dBc Output Peak--to--Average Ratio @ 0.01% Probability on CCDF Adjacent Channel Power Ratio Load Mismatch (3) (In Freescale Doherty Test Fixture, 50 ohm system) IDQA = 450 mA, VGSB = 1.2 Vdc, f = 780 MHz No Device Degradation VSWR 10:1 at 32 Vdc, 132 W Pulse Output Power (3 dB Input Overdrive from 85 W Pulse Rated Power) Typical Performance (3) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQA = 450 mA, VGSB = 1.2 Vdc, 758 to 803 MHz Bandwidth Pout @ 1 dB Compression Point, CW P1dB — 79 — W Pout @ 3 dB Compression Point (4) P3dB — 186 — W — –18 — VBWres — 120 — MHz Gain Flatness in 45 MHz Bandwidth @ Pout = 30 W Avg. GF — 0.4 — dB Gain Variation over Temperature (–30C to +85C) G — 0.01 — dB/C P1dB — 0.3 — dB/C AM/PM (Maximum value measured at the P3dB compression point across the 758–803 MHz frequency range) VBW Resonance Point (IMD Third Order Intermodulation Inflection Point) Output Power Variation over Temperature (–30C to +85C) (5) 1. 2. 3. 4. VDDA and VDDB must be tied together and powered by a single DC power supply. Part internally matched both on input and output. Measurement made with device in a symmetrical Doherty configuration. P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W--CDMA single--carrier input signal where output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF. 5. Exceeds recommended operating conditions. See CW operation data in Maximum Ratings table. A2T07D160W04SR3 RF Device Data Freescale Semiconductor, Inc. 3 -C31 C35 C32 C3 VGGA C28 C27 C1 C13 C9 C10 C14 C C11 C12 C15 P Z1 C8 R2 C29 C23 CUT OUT AREA R1 C7 R3 VDDA C17 C20 C18 C21 C5 C24 C25 C19 C22 C26 C30 C2 C16 C4 VGGB C34 A2T07D160W04S Rev. 3 C6 VDDB C33 D58628 C36 -- Note: VDDA and VDDB must be tied together and powered by a single DC power supply. Figure 2. A2T07D160W04SR3 Test Circuit Component Layout — 758–803 MHz Table 5. A2T07D160W04SR3 Test Circuit Component Designations and Values — 758–803 MHz Part Description Part Number Manufacturer C1, C2, C3, C4, C5, C6 100 pF Chip Capacitors ATC600F101JT250XT ATC C7, C8 30 pF Chip Capacitors ATC600F300JT250XT ATC C9, C10, C11, C12 3.3 pF Chip Capacitors ATC600F3R3BT250XT ATC C13, C15 4.7 pF Chip Capacitors ATC600F4R7BT250XT ATC C14, C16 6.8 pF Chip Capacitors ATC600F6R8BT250XT ATC C17, C18 5.6 pF Chip Capacitors ATC600F5R6BT250XT ATC C19, C20, C21, C22 3.9 pF Chip Capacitors ATC600F3R9BT250XT ATC C23, C24, C25, C26 2.7 pF Chip Capacitors ATC600F2R7BT250XT ATC C27, C30 10 F Chip Capacitors GRM31CR61H106KA12 Muruta C28, C29, C31, C33 1 F Chip Capacitors GRM31CR72A105KA01L Muruta C32, C34 10 F Chip Capacitors C5750X7S2A106M230KB TDK C35, C36 330 F, 63 V Electrolytic Capacitors MCRH63V337M13X21--RH Multicomp R1, R2 2.2 , 1/4 W Chip Resistors CRCW12062R20JNEA Vishay R3 50 , 10 W Termination 81A7031--50--5F Florida RF Labs Z1 620–900 MHz Band, 90, 3 dB Hybrid Coupler CMX07Q03 RN2 Technologies PCB Rogers RO4350B, 0.020, r = 3.66 D58628 MTL A2T07D160W04SR3 4 RF Device Data Freescale Semiconductor, Inc. 22 52 50 48 46 Gps 21 20 PARC --24 --2 --26 --2.5 19 --28 18 --30 ACPR 17 16 720 --32 --3 --3.5 --4 --34 740 760 780 800 820 840 860 PARC (dB) 54 VDD = 28 Vdc, Pout = 30 W (Avg.), IDQA = 450 mA, VGSB = 1.2 Vdc 25 Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth 24 Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF D 23 ACPR (dBc) Gps, POWER GAIN (dB) 26 D, DRAIN EFFICIENCY (%) TYPICAL CHARACTERISTICS — 758–803 MHz --4.5 880 f, FREQUENCY (MHz) IMD, INTERMODULATION DISTORTION (dBc) Figure 3. Single--Carrier Output Peak--to--Average Ratio Compression (PARC) Broadband Performance @ Pout = 30 Watts Avg. 0 VDD = 28 Vdc, Pout = 32 W (PEP), IDQA = 450 mA VGSB = 1.2 Vdc, Two--Tone Measurements (f1 + f2)/2 = Center Frequency of 780 MHz --15 IM3--U --30 IM3--L --45 IM5--U --60 --75 IM5--L IM7--U IM7--L 1 10 100 200 TWO--TONE SPACING (MHz) 22.5 0 22 21.5 21 20.5 20 VDD = 28 Vdc, IDQA = 450 mA, VGSB = 1.2 Vdc f = 780 MHz, Single--Carrier W--CDMA 60 --20 55 --25 --1 dB = 13.5 W --1 50 3.84 MHz Channel Bandwidth Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF 45 --2 ACPR --3 40 Gps --2 dB = 19.9 W --4 --3 dB = 32.2 W D --5 10 20 30 40 PARC 50 --30 --35 ACPR (dBc) 1 D DRAIN EFFICIENCY (%) 23 OUTPUT COMPRESSION AT 0.01% PROBABILITY ON CCDF (dB) Gps, POWER GAIN (dB) Figure 4. Intermodulation Distortion Products versus Two--Tone Spacing --40 35 --45 30 --50 60 Pout, OUTPUT POWER (WATTS) Figure 5. Output Peak--to--Average Ratio Compression (PARC) versus Output Power A2T07D160W04SR3 RF Device Data Freescale Semiconductor, Inc. 5 TYPICAL CHARACTERISTICS — 758–803 MHz Gps, POWER GAIN (dB) 22 D 803 MHz 758 MHz 780 MHz 20 18 12 1 --10 30 758 MHz 780 MHz 20 Gps 3.84 MHz Channel Bandwidth Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF 14 50 40 803 MHz 758 MHz 0 ACPR 803 MHz 780 MHz 16 60 10 10 100 0 200 --20 --30 --40 ACPR (dBc) VDD = 28 Vdc, IDQA = 450 mA, VGSB = 1.2 Vdc Single--Carrier W--CDMA D, DRAIN EFFICIENCY (%) 24 --50 --60 Pout, OUTPUT POWER (WATTS) AVG. Figure 6. Single--Carrier W--CDMA Power Gain, Drain Efficiency and ACPR versus Output Power 24 Gain 22 GAIN (dB) 20 VDD = 28 Vdc Pin = 0 dBm IDQA = 450 mA VGSB = 1.2 Vdc 18 16 14 12 600 650 700 750 800 850 900 950 1000 f, FREQUENCY (MHz) Figure 7. Broadband Frequency Response A2T07D160W04SR3 6 RF Device Data Freescale Semiconductor, Inc. Table 6. Carrier Side Load Pull Performance — Maximum Power Tuning VDD = 28 Vdc, IDQA = 438 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle Max Output Power P1dB f (MHz) Zsource () Zin () 748 2.46 – j4.48 2.43 + j4.57 790 3.06 – j5.44 3.03 + j5.57 806 3.32 – j5.90 3.30 + j6.00 Zload () (1) Gain (dB) (dBm) (W) D (%) AM/PM () 2.31 – j4.78 21.1 50.1 102 51.5 –8 2.02 – j4.88 20.6 50.5 112 53.2 –8 1.92 – j5.08 20.2 50.1 103 50.0 –8 Max Output Power P3dB f (MHz) Zsource () Zin () Zload (2) () Gain (dB) (dBm) (W) D (%) AM/PM () 748 2.46 – j4.48 2.42 + j4.80 2.08 – j5.25 18.7 51.3 134 53.8 –12 790 3.06 – j5.44 3.04 + j5.81 1.94 – j5.25 18.4 51.6 145 56.8 –12 806 3.32 – j5.90 3.33 + j6.24 1.81 – j5.44 17.9 51.4 137 53.3 –12 (1) Load impedance for optimum P1dB power. (2) Load impedance for optimum P3dB power. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device at the package reference plane. Table 7. Carrier Side Load Pull Performance — Maximum Drain Efficiency Tuning VDD = 28 Vdc, IDQA = 438 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle Max Drain Efficiency P1dB Gain (dB) (dBm) (W) D (%) AM/PM () 8.41 – j2.61 24.9 47.4 55 68.0 –13 2.96 + j5.51 6.20 – j2.16 24.2 47.9 61 69.9 –15 3.25 + j5.90 6.00 – j2.35 23.9 47.6 58 66.9 –14 f (MHz) Zsource () Zin () 748 2.46 – j4.48 2.35 + j4.51 790 3.06 – j5.44 806 3.32 – j5.90 Zload () (1) Max Drain Efficiency P3dB f (MHz) Zsource () Zin () 748 2.46 – j4.48 2.40 + j4.77 790 3.06 – j5.44 3.04 + j5.78 806 3.32 – j5.90 3.32 + j6.18 Zload () (2) Gain (dB) (dBm) (W) D (%) AM/PM () 7.65 – j4.43 22.5 48.9 78 71.9 –18 7.12 – j2.62 22.4 48.4 70 72.7 –21 6.10 – j3.14 21.8 48.8 76 70.5 –19 (1) Load impedance for optimum P1dB efficiency. (2) Load impedance for optimum P3dB efficiency. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device at the package reference plane. Input Load Pull Tuner and Test Circuit Output Load Pull Tuner and Test Circuit Device Under Test Zsource Zin Zload A2T07D160W04SR3 RF Device Data Freescale Semiconductor, Inc. 7 Table 8. Peaking Side Load Pull Performance — Maximum Power Tuning VDD = 28 Vdc, VGSB = 1.2 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle Max Output Power P1dB f (MHz) Zsource () Zin () 748 2.58 – j4.22 2.49 + j4.51 790 3.29 – j5.33 3.04 + j5.49 806 3.44 – j5.61 3.33 + j5.94 Zload () (1) (W) D (%) AM/PM () 50.0 99 51.7 –14 50.5 111 50.6 –14 50.3 107 50.5 –14 Gain (dB) (dBm) 2.39 – j5.81 16.9 1.84 – j5.81 16.6 1.88 – j5.93 16.4 Max Output Power P3dB f (MHz) Zsource () Zin () Zload (2) () Gain (dB) (dBm) (W) D (%) AM/PM () 748 2.58 – j4.22 2.51 + j4.76 2.09 – j6.19 14.4 51.2 131 53.5 –18 790 3.29 – j5.33 3.10 + j5.74 1.73 – j6.07 14.3 51.5 142 52.4 –17 806 3.44 – j5.61 3.40 + j6.19 1.81 – j6.16 14.2 51.4 139 53.3 –17 (1) Load impedance for optimum P1dB power. (2) Load impedance for optimum P3dB power. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device at the package reference plane. Table 9. Peaking Side Load Pull Performance — Maximum Drain Efficiency Tuning VDD = 28 Vdc, VGSB = 1.2 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle Max Drain Efficiency P1dB Gain (dB) (dBm) (W) D (%) AM/PM () 9.57 – j3.66 18.8 47.3 54 71.6 –21 2.80 + j5.22 7.77 – j1.84 18.6 47.2 52 72.4 –20 3.09 + j5.65 7.33 – j2.01 18.4 47.2 53 71.4 –18 f (MHz) Zsource () Zin () 748 2.58 – j4.22 2.28 + j4.33 790 3.29 – j5.33 806 3.44 – j5.61 Zload () (1) Max Drain Efficiency P3dB f (MHz) Zsource () Zin () 748 2.58 – j4.22 2.33 + j4.59 790 3.29 – j5.33 2.92 + j5.54 806 3.44 – j5.61 3.22 + j5.98 Zload () (2) Gain (dB) (dBm) (W) D (%) AM/PM () 8.90 – j5.28 16.6 48.4 69 72.6 –24 6.52 – j4.24 16.6 49.0 80 73.8 –22 6.58 – j4.08 16.3 48.9 77 72.8 –21 (1) Load impedance for optimum P1dB efficiency. (2) Load impedance for optimum P3dB efficiency. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device at the package reference plane. Input Load Pull Tuner and Test Circuit Output Load Pull Tuner and Test Circuit Device Under Test Zsource Zin Zload A2T07D160W04SR3 8 RF Device Data Freescale Semiconductor, Inc. 2 2 0 0 --2 IMAGINARY () IMAGINARY () P1dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 790 MHz E 48.5 46.5 47.5 --4 P --6 --8 49 50 47 48 2 E 66 68 --4 64 P 62 --6 49.5 0 --2 4 6 REAL () 8 --8 12 10 Figure 8. P1dB Load Pull Output Power Contours (dBm) 60 54 2 0 4 58 56 6 REAL () 56 8 10 12 Figure 9. P1dB Load Pull Efficiency Contours (%) 2 2 0 --20 --18 0 --2 E 25 --4 P 23.5 22 23 --6 21 --8 0 2 IMAGINARY () IMAGINARY () --16 24.5 24 --2 E --4 P --6 --6 22.5 21.5 4 6 REAL () 8 10 12 Figure 10. P1dB Load Pull Gain Contours (dB) NOTE: --14 --8 --12 --10 --8 --4 0 2 4 6 REAL () 8 10 12 Figure 11. P1dB Load Pull AM/PM Contours () P = Maximum Output Power E = Maximum Drain Efficiency Gain Drain Efficiency Linearity Output Power A2T07D160W04SR3 RF Device Data Freescale Semiconductor, Inc. 9 2 2 0 0 --2 IMAGINARY () IMAGINARY () P3dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 790 MHz 47.5 E 48 --4 P 51 50 70 68 P 0 2 49.5 4 64 48.5 6 REAL () 8 --8 12 10 Figure 12. P3dB Load Pull Output Power Contours (dBm) 56 0 2 58 4 6 REAL () 66 62 8 60 10 12 Figure 13. P3dB Load Pull Efficiency Contours (%) 2 2 23.5 0 23 --2 E --4 P --6 19.5 0 2 22.5 22 20 20.5 4 21 --26 0 IMAGINARY () IMAGINARY () 72 --4 --6 50.5 --8 E 49 --6 --8 --2 --24 --22 --2 E --18 P --16 --6 21.5 6 REAL () --12 --10 8 10 12 Figure 14. P3dB Load Pull Gain Contours (dB) NOTE: --20 --4 --8 0 2 4 --14 6 REAL () 8 10 12 Figure 15. P3dB Load Pull AM/PM Contours () P = Maximum Output Power E = Maximum Drain Efficiency Gain Drain Efficiency Linearity Output Power A2T07D160W04SR3 10 RF Device Data Freescale Semiconductor, Inc. 2 2 0 0 IMAGINARY () IMAGINARY () P1dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 790 MHz E --2 48.5 --4 50 48 49 P --6 47.5 E --2 68 69 72 70 --4 46.5 47 67 71 72 65 P --6 64 49.5 --8 2 0 4 6 8 REAL () 10 --8 14 12 Figure 16. P1dB Load Pull Output Power Contours (dBm) 18.5 17.5 0 --24 2 10 12 14 Figure 18. P1dB Load Pull Gain Contours (dB) NOTE: --22 --18 --4 --16 P --14 --10 6 8 REAL () 14 --20 --6 4 12 E --2 18 17 --8 IMAGINARY () 16.5 IMAGINARY () 16 P 10 0 18 E --6 6 8 REAL () --26 --2 --4 4 2 15 0 2 0 Figure 17. P1dB Load Pull Efficiency Contours (%) 15.5 2 66 --8 0 --12 2 4 6 8 REAL () 10 12 14 Figure 19. P1dB Load Pull AM/PM Contours () P = Maximum Output Power E = Maximum Drain Efficiency Gain Drain Efficiency Linearity Output Power A2T07D160W04SR3 RF Device Data Freescale Semiconductor, Inc. 11 2 2 0 0 --2 47.5 --4 E P 50 50.5 2 0 49.5 4 49 71 --2 --4 6 8 REAL () 10 --8 14 12 2 P 0 2 4 6 8 REAL () 10 12 14 2 13 --28 14 0 13.5 12.5 0 --2 16.5 --4 E E P 16 15 14.5 2 --22 --4 --6 P 0 --24 --2 --20 15.5 --6 --26 16 IMAGINARY () IMAGINARY () 66 Figure 21. P3dB Load Pull Efficiency Contours (%) Figure 20. P3dB Load Pull Output Power Contours (dBm) --8 67 E 73 --6 48.5 68 69 70 72 48 51 --6 --8 IMAGINARY () IMAGINARY () P3dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 790 MHz 4 6 8 REAL () 10 12 14 Figure 22. P3dB Load Pull Gain Contours (dB) NOTE: --8 --18 --12 --14 0 2 --16 4 6 8 REAL () 10 12 14 Figure 23. P3dB Load Pull AM/PM Contours () P = Maximum Output Power E = Maximum Drain Efficiency Gain Drain Efficiency Linearity Output Power A2T07D160W04SR3 12 RF Device Data Freescale Semiconductor, Inc. -- 865–895 MHz CHARACTERISTICS C27 VDDA C25 C3 C23 VGGA C20 C19 C1 C11 R3 C9 C Z1 J1 J2 C10 C8 R2 C21 C12 P C17 CUT OUT AREA R1 C7 C15 C13 D59371 C5 C14 C16 C22 C2 VGGB J3 C6 C24 C4 A2T07D160W04S 865–895 MHz Rev. 1 C18 C26 VDDB C28 -- Note: VDDA and VDDB must be tied together and powered by a single DC power supply. Figure 24. A2T07D160W04SR3 Test Circuit Component Layout — 865–895 MHz Table 10. A2T07D160W04SR3 Test Circuit Component Designations and Values — 865–895 MHz Part Description Part Number Manufacturer C1, C2, C3, C4, C5, C6 100 pF Chip Capacitors ATC600F101JT250XT ATC C7, C8 30 pF Chip Capacitors ATC600F300JT250XT ATC C9, C10 3.3 pF Chip Capacitors ATC600F3R3BT250XT ATC C11, C12 4.7 pF Chip Capacitors ATC600F4R7BT250XT ATC C13, C14, C15, C16 5.6 pF Chip Capacitors ATC600F5R6BT250XT ATC C17, C18 2.7 pF Chip Capacitors ATC600F2R7BT250XT ATC C19, C22 10 F Chip Capacitors GRM31CR61H106KA12 Muruta C20, C21, C23, C24 1 F Chip Capacitors GRM31CR72A105KA01L Muruta C25, C26 10 F Chip Capacitors C5750X7S2A106M230KB TDK C27, C28 330 F, 63 V Electrolytic Capacitors MCRH63V337M13X21--RH Multicomp J1, J2, J3 Copper Foil R1, R2 2.2 , 1/4 W Chip Resistors CRCW12062R20JNEA Vishay R3 50 , 10 W Termination 81A7031--50--5F Florida RF Labs Z1 620–900 MHz Band, 90, 3 dB Hybrid Coupler CMX07Q03 RN2 Technologies PCB Rogers RO4350B, 0.020, r = 3.66 D59371 MTL A2T07D160W04SR3 RF Device Data Freescale Semiconductor, Inc. 13 Gps, POWER GAIN (dB) 22 52 50 D 21 48 20 46 19 3.84 MHz Channel Bandwidth, Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF 18 Gps 17 --28 --1 --29 --1.8 --30 PARC 16 --31 15 --32 ACPR 14 820 840 860 880 900 920 940 --33 980 960 --2.6 --3.4 --4.2 PARC (dB) 54 VDD = 28 Vdc, Pout = 30 W (Avg.) IDQA = 450 mA VGSB = 1.3 Vdc Single--Carrier W--CDMA 23 ACPR (dBc) 24 D, DRAIN EFFICIENCY (%) TYPICAL CHARACTERISTICS — 865–895 MHz --5 f, FREQUENCY (MHz) Figure 25. Single--Carrier Output Peak--to--Average Ratio Compression (PARC) Broadband Performance @ Pout = 30 Watts Avg. Gps, POWER GAIN (dB) 24 22 Gps 20 880 MHz 895 MHz D 865 MHz 895 MHz 865 MHz 865 MHz 880 MHz 895 MHz 880 MHz 18 16 60 0 50 --10 40 30 20 Single--Carrier W--CDMA 3.84 MHz Channel Bandwidth Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF ACPR 14 1 10 10 100 0 200 --20 --30 --40 ACPR (dBc) VDD = 28 Vdc, IDQA = 450 mA VGSB = 1.3 Vdc D, DRAIN EFFICIENCY (%) 26 --50 --60 Pout, OUTPUT POWER (WATTS) AVG. Figure 26. Single--Carrier W--CDMA Power Gain, Drain Efficiency and ACPR versus Output Power 22 Gain 20 GAIN (dB) 18 16 VDD = 28 Vdc Pin = 0 dBm IDQA = 450 mA VGSB = 1.3 Vdc 14 12 10 660 715 770 825 880 935 990 1045 1100 f, FREQUENCY (MHz) Figure 27. Broadband Frequency Response A2T07D160W04SR3 14 RF Device Data Freescale Semiconductor, Inc. Table 11. Carrier Side Load Pull Performance — Maximum Power Tuning VDD = 28 Vdc, IDQA = 434 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle Max Output Power P1dB f (MHz) Zsource () Zin () 865 4.65 – j7.47 5.05 + j7.41 880 5.83 – j8.00 5.80 + j7.75 895 7.11 – j8.39 6.76 + j8.03 Zload () (1) Gain (dB) (dBm) (W) D (%) AM/PM () 1.80 – j5.49 19.8 50.8 121 55.0 –7 1.80 – j5.61 19.7 50.9 122 55.6 –8 1.73 – j5.70 19.5 50.9 123 55.3 –8 Max Output Power P3dB f (MHz) Zsource () Zin () Zload (2) () Gain (dB) (dBm) (W) D (%) AM/PM () 865 4.65 – j7.47 5.18 + j7.65 1.74 – j5.86 17.5 51.8 152 57.1 –11 880 5.83 – j8.00 5.97 + j7.98 1.75 – j5.96 17.4 51.8 153 58.1 –11 895 7.11 – j8.39 6.99 + j8.24 1.68 – j6.06 17.1 51.8 153 57.4 –11 (1) Load impedance for optimum P1dB power. (2) Load impedance for optimum P3dB power. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device at the package reference plane. Table 12. Carrier Side Load Pull Performance — Maximum Drain Efficiency Tuning VDD = 28 Vdc, IDQA = 434 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle Max Drain Efficiency P1dB Gain (dB) (dBm) (W) D (%) AM/PM () 4.56 – j2.53 23.4 48.0 64 71.5 –17 5.83 + j7.61 4.21 – j2.63 23.2 48.0 63 70.8 –17 6.78 + j7.77 4.30 – j3.29 22.9 48.2 65 69.3 –15 f (MHz) Zsource () Zin () 865 4.65 – j7.47 5.06 + j7.28 880 5.83 – j8.00 895 7.11 – j8.39 Zload () (1) Max Drain Efficiency P3dB f (MHz) Zsource () Zin () 865 4.65 – j7.47 5.27 + j7.55 880 5.83 – j8.00 6.03 + j7.85 895 7.11 – j8.39 7.02 + j8.06 Zload () (2) Gain (dB) (dBm) (W) D (%) AM/PM () 4.99 – j2.61 21.5 48.7 74 74.3 –23 4.42 – j3.17 21.0 49.1 81 74.2 –22 3.97 – j3.55 20.7 49.3 84 72.2 –22 (1) Load impedance for optimum P1dB efficiency. (2) Load impedance for optimum P3dB efficiency. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device at the package reference plane. Input Load Pull Tuner and Test Circuit Output Load Pull Tuner and Test Circuit Device Under Test Zsource Zin Zload A2T07D160W04SR3 RF Device Data Freescale Semiconductor, Inc. 15 Table 13. Peaking Side Load Pull Performance — Maximum Power Tuning VDD = 28 Vdc, VGSB = 1.2 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle Max Output Power P1dB f (MHz) Zsource () Zin () 865 5.24 – j6.88 5.26 + j7.37 880 6.04 – j7.55 6.11 + j7.76 895 6.85 – j7.68 7.15 + j8.00 Zload () (1) Gain (dB) (dBm) (W) D (%) AM/PM () 1.82 – j6.25 16.2 50.8 120 54.9 –12 1.64 – j6.44 15.9 51.0 125 53.7 –12 1.69 – j6.53 15.9 51.0 127 55.6 –12 Max Output Power P3dB f (MHz) Zsource () Zin () Zload (2) () Gain (dB) (dBm) (W) D (%) AM/PM () 865 5.24 – j6.88 5.49 + j7.64 1.73 – j6.60 13.9 51.8 151 56.6 –15 880 6.04 – j7.55 6.38 + j8.00 1.68 – j6.73 13.8 51.9 154 56.5 –15 895 6.85 – j7.68 7.52 + j8.23 1.62 – j6.79 13.7 52.0 158 57.1 –16 (1) Load impedance for optimum P1dB power. (2) Load impedance for optimum P3dB power. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device at the package reference plane. Table 14. Peaking Side Load Pull Performance — Maximum Drain Efficiency Tuning VDD = 28 Vdc, VGSB = 1.2 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle Max Drain Efficiency P1dB Gain (dB) (dBm) (W) D (%) AM/PM () 5.19 – j1.71 18.0 47.2 52 75.0 –23 5.64 + j7.43 4.50 – j2.89 17.9 47.9 62 74.3 –21 6.63 + j7.71 4.17 – j3.30 17.6 48.1 64 73.3 –21 f (MHz) Zsource () Zin () 865 5.24 – j6.88 4.85 + j7.03 880 6.04 – j7.55 895 6.85 – j7.68 Zload () (1) Max Drain Efficiency P3dB f (MHz) Zsource () Zin () 865 5.24 – j6.88 5.14 + j7.35 880 6.04 – j7.55 5.96 + j7.71 895 6.85 – j7.68 7.09 + j8.01 Zload () (2) Gain (dB) (dBm) (W) D (%) AM/PM () 5.55 – j3.10 15.9 48.6 72 76.0 –25 4.88 – j3.27 15.8 48.7 74 75.6 –26 3.95 – j4.44 15.6 49.6 91 74.6 –24 (1) Load impedance for optimum P1dB efficiency. (2) Load impedance for optimum P3dB efficiency. Zsource = Measured impedance presented to the input of the device at the package reference plane. Zin = Impedance as measured from gate contact to ground. Zload = Measured impedance presented to the output of the device at the package reference plane. Input Load Pull Tuner and Test Circuit Output Load Pull Tuner and Test Circuit Device Under Test Zsource Zin Zload A2T07D160W04SR3 16 RF Device Data Freescale Semiconductor, Inc. P1dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 880 MHz 2 2 0 0 --2 --2 IMAGINARY () IMAGINARY () 56 54 E --4 P 50.5 --6 50 49 49.5 --10 2 0 70 66 62 60 64 --4 56 P --6 54 --8 48 47 E 58 47.5 48.5 --8 68 47 4 6 8 --10 10 2 0 4 6 8 10 REAL () REAL () Figure 28. P1dB Load Pull Output Power Contours (dBm) Figure 29. P1dB Load Pull Efficiency Contours (%) 2 2 0 0 24 --2 E 23.5 --4 23 22.5 P --6 22 --8 20 --10 IMAGINARY () IMAGINARY () --22 0 2 4 6 --20 --2 --16 E --14 --4 --12 P --6 --10 --8 21.5 20.5 21 --18 8 10 --10 --8 --6 2 0 4 6 8 REAL () REAL () Figure 30. P1dB Load Pull Gain Contours (dB) Figure 31. P1dB Load Pull AM/PM Contours () NOTE: P = Maximum Output Power E = Maximum Drain Efficiency 10 Gain Drain Efficiency Linearity Output Power A2T07D160W04SR3 RF Device Data Freescale Semiconductor, Inc. 17 P3dB -- TYPICAL CARRIER SIDE LOAD PULL CONTOURS — 880 MHz 2 2 0 0 --2 --2 E --4 --6 51.5 P 50 49.5 51 50.5 --8 --10 IMAGINARY () IMAGINARY () 60 2 0 4 --6 70 68 64 62 66 60 P 58 48.5 --8 49 48 72 E --4 48 6 8 --10 10 2 0 4 6 8 10 REAL () REAL () Figure 32. P3dB Load Pull Output Power Contours (dBm) Figure 33. P3dB Load Pull Efficiency Contours (%) 2 2 0 0 --26 --24 --22 22 21.5 E --4 21 20.5 --6 P 20 --8 --10 IMAGINARY () IMAGINARY () --2 18 0 2 --18 E --4 --16 --6 P --12 --10 --8 --14 19.5 18.5 19 4 --20 --2 6 8 10 --10 2 0 4 6 8 REAL () REAL () Figure 34. P3dB Load Pull Gain Contours (dB) Figure 35. P3dB Load Pull AM/PM Contours () NOTE: P = Maximum Output Power E = Maximum Drain Efficiency 10 Gain Drain Efficiency Linearity Output Power A2T07D160W04SR3 18 RF Device Data Freescale Semiconductor, Inc. 2 2 0 0 --2 IMAGINARY () IMAGINARY () P1dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 880 MHz E --4 50 --6 P 50.5 --8 --10 47.5 49 49.5 48 48.5 47.5 47 2 4 6 8 72 E 74 68 70 66 --4 64 --6 P 60 --8 48 0 --2 --10 10 2 0 4 6 62 58 8 10 REAL () REAL () Figure 36. P1dB Load Pull Output Power Contours (dBm) Figure 37. P1dB Load Pull Efficiency Contours (%) 2 16.5 17 0 17.5 14 15 16 E --4 --6 P --2 E --10 --10 4 6 8 10 --16 --14 --6 --8 2 --18 --20 --4 --8 0 --22 --24 --2 IMAGINARY () IMAGINARY () 0 2 14.5 15.5 P --12 --10 --8 2 0 4 6 8 REAL () REAL () Figure 38. P1dB Load Pull Gain Contours (dB) Figure 39. P1dB Load Pull AM/PM Contours () NOTE: P = Maximum Output Power E = Maximum Drain Efficiency 10 Gain Drain Efficiency Linearity Output Power A2T07D160W04SR3 RF Device Data Freescale Semiconductor, Inc. 19 P3dB -- TYPICAL PEAKING SIDE LOAD PULL CONTOURS — 880 MHz 2 2 0 0 --2 --2 62 IMAGINARY () IMAGINARY () 64 E --4 48.5 50.5 --6 P 51.5 51 50 49.5 49 74 66 70 68 --6 P 48 --8 --10 72 E --4 64 62 60 --8 49 2 0 4 6 8 --10 10 2 0 4 6 8 10 REAL () REAL () Figure 40. P3dB Load Pull Output Power Contours (dBm) Figure 41. P3dB Load Pull Efficiency Contours (%) 2 0 2 12.5 13.5 12 13 14.5 14 15 IMAGINARY () E --4 --6 --22 --2 --20 E --4 --18 --16 --6 P P --8 --10 --24 --26 15.5 --2 IMAGINARY () --30 --28 0 --14 --8 0 2 4 6 8 10 --10 2 0 4 6 8 REAL () REAL () Figure 42. P3dB Load Pull Gain Contours (dB) Figure 43. P3dB Load Pull AM/PM Contours () NOTE: P = Maximum Output Power E = Maximum Drain Efficiency 10 Gain Drain Efficiency Linearity Output Power A2T07D160W04SR3 20 RF Device Data Freescale Semiconductor, Inc. PACKAGE DIMENSIONS A2T07D160W04SR3 RF Device Data Freescale Semiconductor, Inc. 21 A2T07D160W04SR3 22 RF Device Data Freescale Semiconductor, Inc. PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS Refer to the following resources to aid your design process. Application Notes AN1955: Thermal Measurement Methodology of RF Power Amplifiers Engineering Bulletins EB212: Using Data Sheet Impedances for RF LDMOS Devices Software Electromigration MTTF Calculator RF High Power Model .s2p File Development Tools Printed Circuit Boards For Software and Tools, do a Part Number search at http://www.freescale.com, and select the “Part Number” link. Go to the Software & Tools tab on the part’s Product Summary page to download the respective tool. REVISION HISTORY The following table summarizes revisions to this document. Revision Date 0 Aug. 2014 Description Initial Release of Data Sheet A2T07D160W04SR3 RF Device Data Freescale Semiconductor, Inc. 23 How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. 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U.S. Pat. & Tm. Off. Airfast is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. E 2014 Freescale Semiconductor, Inc. A2T07D160W04SR3 Document Number: A2T07D160W04S Rev. 24 0, 8/2014 RF Device Data Freescale Semiconductor, Inc.