Data Sheet

Freescale Semiconductor
Technical Data
Document Number: A2I08H040N
Rev. 0, 1/2016
RF LDMOS Wideband Integrated
Power Amplifiers
The A2I08H040N wideband integrated circuit is an asymmetrical Doherty
designed with on--chip matching that makes it usable from 728 to 960 MHz.
This multi--stage structure is rated for 26 to 32 V operation and covers all
typical cellular base station modulation formats.
900 MHz
 Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc,
IDQ1A = 25 mA, IDQ2A = 105 mA, VGS1B = 2.65 Vdc, VGS2B = 2.3 Vdc,
Pout = 9 W Avg., Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF.
Frequency
Gps
(dB)
PAE
(%)
Output PAR
(dB)
ACPR
(dBc)
920 MHz
30.7
45.9
8.5
–36.0
940 MHz
30.6
46.7
8.4
–39.3
960 MHz
30.4
45.2
8.1
–34.5
A2I08H040NR1
A2I08H040GNR1
728–960 MHz, 9 W AVG., 28 V
AIRFAST RF LDMOS WIDEBAND
INTEGRATED POWER AMPLIFIERS
TO--270WB--15
PLASTIC
A2I08H040NR1
700 MHz
 Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Vdc,
IDQ1A = 25 mA, IDQ2A = 105 mA, VGS1B = 2.65 Vdc, VGS2B = 2.3 Vdc,
Pout = 9 W Avg., Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF.
Frequency
Gps
(dB)
PAE
(%)
Output PAR
(dB)
ACPR
(dBc)
728 MHz
29.1
49.1
7.9
–32.7
748 MHz
28.8
48.6
7.8
–36.4
768 MHz
28.5
46.9
7.8
–36.7
TO--270WBG--15
PLASTIC
A2I08H040GNR1
Features
 Advanced High Performance In--Package Doherty
 On--Chip Matching (50 Ohm Input, DC Blocked)
 Integrated Quiescent Current Temperature Compensation with
Enable/Disable Function (1)
 Designed for Digital Predistortion Error Correction Systems
1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current
Control for the RF Integrated Circuit Device Family. Go to http://www.nxp.com/RF and search for AN1977 or AN1987.
 Freescale Semiconductor, Inc., 2016. All rights reserved.
RF Device Data
Freescale Semiconductor, Inc.
A2I08H040NR1 A2I08H040GNR1
1
VDS1A
RFinA
VDS1A
VGS2A
VGS1A
RFinA
N.C.
N.C.
N.C.
N.C.
RFinB
VGS1B
VGS2B
VDS1B
RFout1/VDS2A
VGS1A
Quiescent Current
Temperature Compensation (1)
VGS2A
VGS1B
Quiescent Current
Temperature Compensation (1)
VGS2B
RFinB
Carrier
1
2
15
3
4
5
6
14
7
8
13
9
10
11
12 Peaking
RFout1/VDS2A
N.C.
RFout2/VDS2B
(Top View)
RFout2/VDS2B
Note: Exposed backside of the package is
the source terminal for the transistors.
VDS1B
Figure 1. Functional Block Diagram
Figure 2. Pin Connections
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Drain--Source Voltage
VDSS
–0.5, +65
Vdc
Gate--Source Voltage
VGS
–0.5, +10
Vdc
Operating Voltage
VDD
32, +0
Vdc
Storage Temperature Range
Tstg
–65 to +150
C
TC
–40 to +150
C
TJ
–40 to +225
C
Pin
20
dBm
Symbol
Value (3,4)
Unit
Case Operating Temperature Range
Operating Junction Temperature Range
(2,3)
Input Power
Table 2. Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Case
Case Temperature 73C, 9 W, 940 MHz
Stage 1, 28 Vdc, IDQ1A = 24 mA, VGS1B = 1.65 Vdc
Stage 2, 28 Vdc, IDQ2A = 145 mA, VGS2B = 1.3 Vdc
RJC
C/W
5.5
3.4
Table 3. ESD Protection Characteristics
Test Methodology
Class
Human Body Model (per JESD22--A114)
1B
Machine Model (per EIA/JESD22--A115)
A
Charge Device Model (per JESD22--C101)
II
Table 4. Moisture Sensitivity Level
Test Methodology
Per JESD22--A113, IPC/JEDEC J--STD--020
Rating
Package Peak Temperature
Unit
3
260
C
1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current
Control for the RF Integrated Circuit Device Family. Go to http://www.nxp.com/RF and search for AN1977 or AN1987.
2. Continuous use at maximum temperature will affect MTTF.
3. MTTF calculator available at http://www.nxp.com/RF/calculators.
4. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.nxp.com/RF and search for AN1955.
A2I08H040NR1 A2I08H040GNR1
2
RF Device Data
Freescale Semiconductor, Inc.
Table 5. Electrical Characteristics (TA = 25C unless otherwise noted)
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 1.5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage (1)
(VDS = 10 Vdc, ID = 4 Adc)
VGS(th)
1.2
2.0
2.7
Vdc
Gate Quiescent Voltage
(VDS = 28 Vdc, IDQ1A = 25 mAdc)
VGS(Q)
—
2.8
—
Vdc
Fixture Gate Quiescent Voltage
(VDD = 28 Vdc, IDQ1A = 25 mAdc, Measured in Functional Test)
VGG(Q)
3.5
4.1
5.0
Vdc
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 1.5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage (1)
(VDS = 10 Vdc, ID = 19 Adc)
VGS(th)
1.2
2.0
2.7
Vdc
Gate Quiescent Voltage
(VDS = 28 Vdc, IDQ2A = 105 mAdc)
VGS(Q)
—
2.8
—
Vdc
Fixture Gate Quiescent Voltage
(VDD = 28 Vdc, IDQ2A = 105 mAdc, Measured in Functional Test)
VGG(Q)
3.5
4.1
5.0
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 190 mAdc)
VDS(on)
0.1
0.2
2.5
Vdc
Characteristic
Carrier Stage 1 -- Off Characteristics (1)
Carrier Stage 1 -- On Characteristics
Carrier Stage 2 -- Off Characteristics (1)
Carrier Stage 2 -- On Characteristics
1. Each side of device measured separately.
(continued)
A2I08H040NR1 A2I08H040GNR1
RF Device Data
Freescale Semiconductor, Inc.
3
Table 5. Electrical Characteristics (TA = 25C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 1.5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
VGS(th)
1.2
2.0
2.7
Vdc
Zero Gate Voltage Drain Leakage Current
(VDS = 65 Vdc, VGS = 0 Vdc)
IDSS
—
—
10
Adc
Zero Gate Voltage Drain Leakage Current
(VDS = 32 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
Adc
Gate--Source Leakage Current
(VGS = 1.5 Vdc, VDS = 0 Vdc)
IGSS
—
—
1
Adc
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 34 Adc)
VGS(th)
1.2
2.0
2.7
Vdc
Drain--Source On--Voltage
(VGS = 10 Vdc, ID = 340 mAdc)
VDS(on)
0.1
0.2
2.5
Vdc
Peaking Stage 1 -- Off Characteristics (1)
Peaking Stage 1 -- On Characteristics (1)
Gate Threshold Voltage
(VDS = 10 Vdc, ID = 6 Adc)
Peaking Stage 2 -- Off Characteristics (1)
Peaking Stage 2 -- On Characteristics (1)
1. Each side of device measured separately.
(continued)
A2I08H040NR1 A2I08H040GNR1
4
RF Device Data
Freescale Semiconductor, Inc.
Table 5. Electrical Characteristics (TA = 25C unless otherwise noted) (continued)
Characteristic
Symbol
Min
Typ
Max
Unit
(1,2,3)
Functional Tests
(In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQ1A = 25 mA, IDQ2A = 105 mA,
VGS1B = 2.65 Vdc, VGS2B = 2.3 Vdc, Pout = 9 W Avg., f = 920 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF. ACPR measured in 3.84 MHz Channel Bandwidth @ 5 MHz Offset.
Power Gain
Gps
27.0
30.7
33.0
dB
Power Added Efficiency
PAE
42.0
45.9
—
%
Output Peak--to--Average Ratio @ 0.01% Probability on CCDF
PAR
7.3
8.5
—
dB
Adjacent Channel Power Ratio
ACPR
—
–36.0
–30.0
dBc
Pout @ 3 dB Compression Point, CW
P3dB
42.2
51.8
—
W
Load Mismatch (2) (In Freescale Doherty Test Fixture, 50 ohm system) IDQ1A = 25 mA, IDQ2A = 10.5 mA, VGS1B = 2.65 Vdc,
VGS2B = 2.3 Vdc, f = 940 MHz
VSWR 10:1 at 32 Vdc, 56 W CW Output Power
(3 dB Input Overdrive from 48 W CW Rated Power)
No Device Degradation
Typical Performance (2) (In Freescale Doherty Test Fixture, 50 ohm system) VDD = 28 Vdc, IDQ1A = 25 mA, IDQ2A = 105 mA,
VGS1B = 2.65 Vdc, VGS2B = 2.3 Vdc, 920–960 MHz Bandwidth
Pout @ 1 dB Compression Point, CW
P1dB
—
(4)
P3dB
AM/PM
(Maximum value measured at the P3dB compression point across
the 920–960 MHz frequency range.)

VBWres
Pout @ 3 dB Compression Point
VBW Resonance Point
(IMD Third Order Intermodulation Inflection Point)
Quiescent Current Accuracy over Temperature (5)
with 2 k Gate Feed Resistors (–30 to 85C) Stage 1
with 2 k Gate Feed Resistors (–30 to 85C) Stage 2
IQT
46.8
—
W
—
56
—
W
—
–15.9
—

—
70
—
MHz
—
—
1.1
1.9
—
—
%
Gain Flatness in 40 MHz Bandwidth @ Pout = 9 W Avg.
GF
—
0.3
—
dB
Gain Variation over Temperature
(–30C to +85C)
G
—
0.029
—
dB/C
P1dB
—
0.006
—
dB/C
Output Power Variation over Temperature
(–30C to +85C)
Table 6. Ordering Information
Device
A2I08H040NR1
A2I08H040GNR1
Tape and Reel Information
R1 Suffix = 500 Units, 44 mm Tape Width, 13--inch Reel
Package
TO--270WB--15
TO--270WBG--15
1. Part internally input matched.
2. Measurements made with device in an asymmetrical Doherty configuration.
3. Measurements made with device in straight lead configuration before any lead forming operation is applied. Lead forming is used for gull
wing (GN) parts.
4. P3dB = Pavg + 7.0 dB where Pavg is the average output power measured using an unclipped W--CDMA single--carrier input signal
where output PAR is compressed to 7.0 dB @ 0.01% probability on CCDF.
5. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family, and to AN1987, Quiescent Current Control
for the RF Integrated Circuit Device Family. Go to http://www.nxp.com/RF and search for AN1977 or AN1987.
A2I08H040NR1 A2I08H040GNR1
RF Device Data
Freescale Semiconductor, Inc.
5
VGG1A
VGG2A
R1
C1
VDD1A
A2I08H040N
Rev. 2
D60265
C23
R2
VDD2A
C2*
C4* C3
CUT OUT AREA
C6*
Z1
C7*
R5
C21*
C
C5*
C26*
C9*
C8*
C25*
C20*
C24
C19
Z2
P
C10*
C11* C12
C15*
C13*
C18*
C16
R4
R3
VGG1B
C22
VGG2B
VDD1B
C14
C17
VDD2B
*C2, C4, C5, C6, C7, C8, C9, C10, C11, C13, C15, C18, C20, C21, C25, and C26 are mounted vertically.
Figure 3. A2I08H040NR1 Test Circuit Component Layout
Table 7. A2I08H040NR1 Test Circuit Component Designations and Values
Part
Description
Part Number
Manufacturer
C1, C14, C17, C23
10 F Chip Capacitors
C5750X7S2A106M230KB
TDK
C2, C4, C5, C6, C7, C10, C11,
C13, C15, C18, C21, C25
47 pF Chip Capacitors
ATC100B470JT500XT
ATC
C3, C12, C16, C22
2.2 F Chip Capacitors
C3225X7R2A225M230AB
TDK
C8
1.8 pF Chip Capacitor
ATC100B1R8BT500XT
ATC
C9
0.5 pF Chip Capacitor
ATC00B0R5BT500XT
ATC
C19
9.1 pF Chip Capacitor
ATC100B9R1BT500XT
ATC
C20
10 pF Chip Capacitor
ATC100B100GT500XT
ATC
C24
1.1 pF Chip Capacitor
ATC100B1R1BT500XT
ATC
C26
0.7 pF Chip Capacitor
ATC100B0R7BT500XT
ATC
R1, R2, R3, R4
2 k, 1/4 W Chip Resistors
WCR1206-2K0FI
Welwyn
R5
50 , 8 W Termination
C8A50Z4A
Anaren
Z1
800–1000 MHz Band, 5 dB Directional Coupler
XC0900A-05S
Anaren
Z2
925–960 MHz Band, Doherty Combiner
X3DC09E2S
Anaren
PCB
Rogers RO4350B, 0.020, r = 3.66
D60265
MTL
A2I08H040NR1 A2I08H040GNR1
6
RF Device Data
Freescale Semiconductor, Inc.
TYPICAL CHARACTERISTICS
30
30
VDD = 28 Vdc, Pout = 9 W (Avg.)
IDQ1A = 25 mA, IDQ2A = 105 mA
VGS1B = 2.65 Vdc, VGS2B = 2.3 Vdc
ACPR
29.5
35
29
–25
–0.6
–30
–0.9
28.5
–35
28 Single--Carrier W--CDMA, 3.84 MHz Channel
27.5 Bandwidth, Input Signal PAR = 9.9 dB @ 0.01%
Probability on CCDF
27
840
860
880
900
920
820
f, FREQUENCY (MHz)
–40
PARC
940
–45
–50
960
–1.2
–1.5
–1.8
PARC (dB)
40
Gps
30.5
ACPR (dBc)
Gps, POWER GAIN (dB)
45
PAE
31
PAE, POWER ADDED
EFFICIENCY (%)
50
32
31.5
–2.1
IMD, INTERMODULATION DISTORTION (dBc)
Figure 4. Single--Carrier Output Peak--to--Average Ratio Compression
(PARC) Broadband Performance @ Pout = 9 Watts Avg.
0
VDD = 28 Vdc, Pout = 23 W (PEP), IDQ1A = 25 mA
IDQ2A = 105 mA, VGS1B = 2.65 Vdc, VGS2B = 2.3 Vdc
Two--Tone Measurements, (f1 + f2)/2 = Center
Frequency of 940 MHz
–10
–20
IM3--U
IM3--L
–30
–40
IM5--U
IM5--L
IM7--L
–50
IM7--U
–60
1
10
100
150
TWO--TONE SPACING (MHz)
Figure 5. Intermodulation Distortion Products
versus Two--Tone Spacing
30.5
30.4
30.3
30.2
0
PAE
PARC
–1
ACPR
–1 dB = 7.8 W
–2
–3 dB = 12.6 W
–2 dB = 10 W
–3
–5
4
6
12
8
10
Pout, OUTPUT POWER (WATTS)
50
45
40
35
VDD = 28 Vdc, IDQ1A = 25 mA, IDQ2A = 105 mA
VGS1B = 2.65 Vdc, VGS2B = 2.3 Vdc, f = 940 MHz
Single--Carrier W--CDMA, 3.84 MHz, Channel Bandwidth
Input Signal PAR = 9.9 dB @ 0.01% Probability on CCDF
–4
–30
55
Gps
14
30
25
16
–33
–36
–39
ACPR (dBc)
30.6
OUTPUT COMPRESSION AT 0.01%
PROBABILITY ON CCDF (dB)
Gps, POWER GAIN (dB)
30.7
1
PAE, POWER ADDED EFFICIENCY (%)
30.8
–42
–45
–48
Figure 6. Output Peak--to--Average Ratio
Compression (PARC) versus Output Power
A2I08H040NR1 A2I08H040GNR1
RF Device Data
Freescale Semiconductor, Inc.
7
TYPICAL CHARACTERISTICS
PAE
50
960 MHz
30
920 MHz
940 MHz
940 MHz
960 MHz
960 MHz 920 MHz
29
920 MHz
28
40
ACPR
940 MHz
30
20
Gps
Single--Carrier W--CDMA
3.84 MHz Channel Bandwidth, Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF
27
26
1
10
Pout, OUTPUT POWER (WATTS) AVG.
10
0
50
0
–10
–20
–30
–40
ACPR (dBc)
31
Gps, POWER GAIN (dB)
60
VDD = 28 Vdc, IDQ1A = 25 mA, IDQ2A = 105 mA
VGS1B = 2.65 Vdc, VGS2B = 2.3 Vdc
PAE, POWER ADDED EFFICIENCY (%)
32
–50
–60
Figure 7. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
34
32
Gain
GAIN (dB)
30
28
26
VDD = 28 Vdc
Pin = 0 dBm
IDQ1A = 25 mA, IDQ2A = 105 mA
VGS1B = 2.65 Vdc, VGS2B = 2.3 Vdc
24
22
700
750
800
850
900
950
f, FREQUENCY (MHz)
1000
1050
1100
Figure 8. Broadband Frequency Response
A2I08H040NR1 A2I08H040GNR1
8
RF Device Data
Freescale Semiconductor, Inc.
Table 8. Carrier Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQ1A = 25 mA, IDQ2A = 100 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
920
51.1 – j12.0
58.6 + j15.3
940
54.9 – j7.00
62.0 + j11.7
960
57.0 – j4.01
63.0 + j7.73
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
8.16 + j5.47
32.9
43.4
22
58.3
–5
8.70 + j5.35
32.8
43.4
22
58.6
–5
9.38 + j4.95
32.7
43.3
21
58.1
–6
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
920
51.1 – j12.0
58.7 + j12.7
8.80 + j4.28
30.6
44.1
26
58.5
–6
940
54.9 – j7.00
61.6 + j9.15
9.44 + j4.22
30.6
44.1
25
58.9
–7
960
57.0 – j4.01
62.1 + j5.47
9.96 + j3.98
30.5
44.0
25
58.5
–8
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 9. Carrier Load Pull Performance — Maximum Efficiency Tuning
VDD = 28 Vdc, IDQ1A = 25 mA, IDQ2A = 100 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
920
51.1 – j12.0
63.7 + j16.2
9.09 + j13.8
35.4
41.2
13
70.1
–9
940
54.9 – j7.00
67.8 + j12.0
8.74 + j14.9
35.5
40.8
12
70.3
–11
960
57.0 – j4.01
67.6 + j7.31
9.78 + j14.6
35.2
41.0
13
69.6
–10
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
7.87 + j13.6
33.5
41.7
15
71.3
–15
66.4 + j10.4
8.45 + j14.0
33.4
41.7
15
71.2
–15
66.2 + j5.95
9.24 + j13.7
33.1
41.9
15
70.5
–14
f
(MHz)
Zsource
()
Zin
()
920
51.1 – j12.0
63.5 + j14.8
940
54.9 – j7.00
960
57.0 – j4.01
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2I08H040NR1 A2I08H040GNR1
RF Device Data
Freescale Semiconductor, Inc.
9
Table 10. Peaking Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQ1B = 30 mA, VGS2B = 2.3 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
920
38.7 – j2.27
35.4 + j2.30
940
39.2 – j5.06
36.2 + j0.98
960
38.0 + j0.79
36.1 – j1.16
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
4.19 + j1.68
30.0
45.5
36
58.6
–16
4.27 + j1.85
29.9
45.3
34
59.6
–17
4.53 + j1.73
29.7
45.1
32
59.4
–18
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
920
38.7 – j2.27
36.5 + j0.74
4.35 + j1.68
28.0
45.8
38
60.0
–21
940
39.2 – j5.06
37.3 – j0.71
4.51 + j1.85
27.9
45.6
36
61.0
–21
960
38.0 + j0.79
37.3 – j2.62
4.53 + j1.73
27.7
45.3
34
60.2
–20
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 11. Peaking Side Load Pull Performance — Maximum Efficiency Tuning
VDD = 28 Vdc, IDQ1B = 30 mA, VGS2B = 2.3 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
920
38.7 – j2.27
37.7 + j3.57
4.26 + j6.49
30.9
43.0
20
69.9
–19
940
39.2 – j5.06
38.6 + j1.50
4.13 + j6.62
30.8
42.7
19
70.7
–21
960
38.0 + j0.79
38.0 – j0.71
4.10 + j6.31
30.6
42.7
19
69.5
–21
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
4.18 + j5.42
29.0
44.3
27
69.4
–28
37.2 – j0.30
4.20 + j5.43
28.8
44.1
26
69.7
–29
36.6 – j2.33
4.10 + j5.58
28.6
43.7
23
68.4
–30
f
(MHz)
Zsource
()
Zin
()
920
38.7 – j2.27
36.8 + j1.64
940
39.2 – j5.06
960
38.0 + j0.79
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2I08H040NR1 A2I08H040GNR1
10
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL CARRIER LOAD PULL CONTOURS — 940 MHz
20
39.5
18
IMAGINARY ()
IMAGINARY ()
42
10
42.5
8
6
P
4
43
2
0
4
6
6
8
14
10
12
REAL ()
16
–2
18
20
36.5
18
36
54
16
34.5
34
10
8
33.5
6
P
4
33
2
8
6
P
–4
2
0
–2
10
12
REAL ()
18
–6
10
–2
8
16
–8
12
0
6
14
10
12
REAL ()
E
4
32.5
56
–10
–18
14
IMAGINARY ()
12
8
–12
–16 –14
18
E
14
6
4
20
35.5
35
16
4
60
58
P
Figure 10. P1dB Load Pull Efficiency Contours (%)
Figure 9. P1dB Load Pull Output Power Contours (dBm)
IMAGINARY ()
8
0
41
62
10
2
41.5
64
70
12
4
42
66
E
14
41.5
12
68
16
41
E
14
60
18
40.5
16
–2
20
40
14
16
18
Figure 11. P1dB Load Pull Gain Contours (dB)
NOTE:
4
6
8
10
12
REAL ()
14
16
18
Figure 12. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I08H040NR1 A2I08H040GNR1
RF Device Data
Freescale Semiconductor, Inc.
11
P3dB – TYPICAL CARRIER LOAD PULL CONTOURS — 940 MHz
20
20
40.5
40
16
IMAGINARY ()
14
41
41.5
E
16
42.5
10
43
8
43.5
P
4
2
44
6
8
14
10
12
REAL ()
34
18
16
18
64
62
6
P
60
58
56
20
E
8
31.5
6
31
P
4
2
6
8
10
12
REAL ()
16
–6
–12 –10
E
12
10
8
6
P
–2
0
14
16
18
Figure 15. P3dB Load Pull Gain Contours (dB)
NOTE:
18
–2
–4
2
30
0
–8
4
30.5
14
10
12
REAL ()
–14
14
32
10
8
–16
16
32.5
IMAGINARY ()
14
–18
18
33
12
6
4
Figure 14. P3dB Load Pull Efficiency Contours (%)
33.5
16
IMAGINARY ()
66
8
0
20
4
68
10
–2
Figure 13. P3dB Load Pull Output Power Contours (dBm)
–2
70
2
42
4
E
12
4
42.5
0
–2
14
42
12
6
60
18
IMAGINARY ()
18
–2
4
6
8
10
12
REAL ()
14
16
18
Figure 16. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I08H040NR1 A2I08H040GNR1
12
RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL PEAKING LOAD PULL CONTOURS — 940 MHz
12
12
41.5
42
8
43.5
44
4
45
2
44.5
P
0
–2
42.5
43
E
6
42
66
68
4
7
5
6
REAL ()
8
62
–2
9
64
P
60
58
56
54
3
2
4
5
6
REAL ()
7
8
9
Figure 18. P1dB Load Pull Efficiency Contours (%)
12
28
28.5
10
70
4
43.5
3
56
58
60
E
6
2
Figure 17. P1dB Load Pull Output Power Contours (dBm)
12
62
8
0
43
2
54
10
IMAGINARY ()
IMAGINARY ()
10
29.5
29
10
30
8
E
6
4
30.5
2
P
29.5
27
2
3
4
5
6
REAL ()
–26
E
–22
4
–18
–16
–14
–10
–12
–20
P
0
29
28.5
27.5
–24
6
2
30
28
0
–2
IMAGINARY ()
IMAGINARY ()
8
7
8
9
Figure 19. P1dB Load Pull Gain Contours (dB)
NOTE:
–2
2
3
4
5
6
REAL ()
7
8
9
Figure 20. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I08H040NR1 A2I08H040GNR1
RF Device Data
Freescale Semiconductor, Inc.
13
P3dB – TYPICAL PEAKING LOAD PULL CONTOURS — 940 MHz
12
12
42
41.5
8
42.5
43
43.5
6
44
E
44.5
4
45
2
P
0
–2
4
5
6
REAL ()
7
27.5
6
E
4
28.5
2
P
2
3
4
58
5
6
REAL ()
7
56
8
9
26
25.5
28
4
5
6
REAL ()
–34
E
–24
4
–22
–20
–18
P
0
27
26.5
–30
–28 –26
–32
6
2
27.5
3
60
54
8
2
64
P
10
IMAGINARY ()
IMAGINARY ()
66
12
27
25
60
Figure 22. P3dB Load Pull Efficiency Contours (%)
8
–2
4
9
8
28
0
62
E
45.5
Figure 21. P3dB Load Pull Output Power Contours (dBm)
10
68
6
–2
3
26
26.5
8
0
51
12
56
58
2
43 43.5
44
2
54
10
IMAGINARY ()
IMAGINARY ()
10
7
8
9
Figure 23. P3dB Load Pull Gain Contours (dB)
NOTE:
–2
2
3
4
5
6
REAL ()
7
8
9
Figure 24. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I08H040NR1 A2I08H040GNR1
14
RF Device Data
Freescale Semiconductor, Inc.
VGG1A
VGG2A
A2I08H040N
C1
VDD1A Rev. 1
R2
R1
C22
D71533
VDD2A
C13
C11
C10*
C12*
C2*
C14*
C
C4*
C3*
CUT OUT AREA
R6
Z1
R5
C23*
C5*
C21*
C15*
Z2
C16*
P
C20*
C17*
C6* C9
C8*
C18
R4
R3
VGG1B
VGG2B
VDD1B
C7
C19
VDD2B
*C2, C3, C4, C5, C6, C8, C10, C12, C14, C15, C16, C17, C20, C21, and C23 are mounted vertically.
Figure 25. A2I08H040NR1 Production Test Circuit Component Layout — 728–768 MHz
Table 12. A2I08H040NR1 Production Test Circuit Component Designations and Values — 728–768 MHz
Part
Description
Part Number
Manufacturer
C1, C7, C19, C22
10 F Chip Capacitors
C5750X7S2A106M230KB
TDK
C2, C3, C4, C5, C6, C8,
C10, C12, C17, C20
68 pF Chip Capacitors
ATC100B680JT500XT
ATC
C9, C11, C13, C18
2.2 F Chip Capacitors
C3225X7R2A225M230AB
TDK
C14
5.6 pF Chip Capacitor
ATC100B5R6BT500XT
ATC
C15, C21
4.7 pF Chip Capacitors
ATC100B4R7BT500XT
ATC
C16
12 pF Chip Capacitor
ATC100B120GT500XT
ATC
C23
3.6 pF Chip Capacitor
ATC100B3R6BT500XT
ATC
R1, R2, R3, R4
2 k, 1/4 W Chip Resistors
WCR1206-2K0FI
Welwyn
R5
50 , 8 W Termination
C8A50Z4A
Anaren
R6
3 dB, 10 W Chip Attenuator
D10AA3Z4
Anaren
Z1
600–900 MHz Band, 90, 4 dB Directional Coupler
X3C07P1-04S
Anaren
Z2
728–768 MHz Band, Doherty Combiner
X3DC07E2S
Anaren
PCB
Rogers RO4350B, 0.020, r = 3.66
D71533
MTL
A2I08H040NR1 A2I08H040GNR1
RF Device Data
Freescale Semiconductor, Inc.
15
TYPICAL CHARACTERISTICS
Gps, POWER GAIN (dB)
29
46
3.84 MHz Channel
28.8 Bandwidth, Input Signal
28.6 PAR = 9.9 dB @ 0.01%
Probability on CCDF
28.4
44
ACPR
28.2
Gps
720
–30
–2
–36
27.8
27.6
710
–1.9
–33
PARC
28
–27
730
740
750
760
f, FREQUENCY (MHz)
770
780
–39
–2.1
–2.2
–2.3
PARC (dB)
PAE
29.2
ACPR (dBc)
29.4
PAE, POWER ADDED
EFFICIENCY (%)
52
VDD = 28 Vdc, IDQ1A = 25 mA, IDQ2A = 105 mA
50
VGS1B = 2.65 Vdc, VGS2B = 2.3 Vdc
Single--Carrier W--CDMA
48
29.6
–2.4
–42
790
Figure 26. Single--Carrier Output Peak--to--Average Ratio
Compression (PARC) Broadband Performance @ Pout = 9 Watts Avg.
728 MHz
60
PAE
748 MHz
29
50
768 MHz
768 MHz
ACPR
728 MHz
748 MHz
28
27
748 MHz
26
728 MHz
768 MHz
Gps
30
20
3.84 MHz Channel Bandwidth, Input Signal
PAR = 9.9 dB @ 0.01% Probability on CCDF
1
40
10
50
10
Pout, OUTPUT POWER (WATTS) AVG.
0
–10
–20
–30
–40
ACPR (dBc)
Gps, POWER GAIN (dB)
30
25
70
VDD = 28 Vdc, IDQ1A = 25 mA, IDQ2A = 105 mA, VGS1B = 2.65 Vdc
VGS2B = 2.3 Vdc, Single--Carrier W--CDMA
PAE, POWER ADDED EFFICIENCY (%)
31
–50
–60
Figure 27. Single--Carrier W--CDMA Power Gain, Drain
Efficiency and ACPR versus Output Power
40
35
Gain
GAIN (dB)
30
25
20
VDD = 28 Vdc
Pin = 0 dBm
IDQ1A = 25 mA, IDQ2A = 105 mA
VGS1B = 2.65 Vdc, VGS2B = 2.3 Vdc
15
10
550
600
650
700
750
800
f, FREQUENCY (MHz)
850
900
950
Figure 28. Broadband Frequency Response
A2I08H040NR1 A2I08H040GNR1
16
RF Device Data
Freescale Semiconductor, Inc.
Table 13. Carrier Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQ1A = 25 mA, IDQ2A = 100 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
728
24.7 – j1.50
25.7 + j0.73
748
23.8 – j4.10
26.6 + j4.02
768
24.1 – j7.86
27.0 + j8.40
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
4.92 + j5.15
32.2
41.7
15
42.2
–7
4.92 + j4.60
31.8
41.6
15
40.3
–3
6.79 + j6.25
33.2
42.6
18
55.2
–2
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
728
24.7 – j1.50
26.7 + j1.45
5.35 + j4.77
30.3
42.9
19
47.1
–9
748
23.8 – j4.10
27.6 + j4.63
5.63 + j4.20
30.0
42.9
19
46.6
–5
768
24.1 – j7.86
28.4 + j8.44
7.45 + j5.33
31.0
43.6
23
59.0
–4
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 14. Carrier Load Pull Performance — Maximum Efficiency Tuning
VDD = 28 Vdc, IDQ1A = 25 mA, IDQ2A = 100 mA, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
728
24.7 – j1.50
28.1 + j7.23
19.7 + j26.7
35.4
37.8
6
52.4
–5
748
23.8 – j4.10
24.2 + j9.57
8.94 + j17.9
37.7
38.2
7
59.8
–2
768
24.1 – j7.86
26.2 + j11.9
8.70 + j14.0
36.4
40.7
12
68.9
–4
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
16.6 + j22.7
34.3
39.6
9
65.1
–1
26.0 + j10.0
9.44 + j18.6
35.7
39.6
9
68.8
–5
27.7 + j11.6
8.98 + j13.7
34.3
41.6
15
72.8
–7
f
(MHz)
Zsource
()
Zin
()
728
24.7 – j1.50
27.5 + j6.67
748
23.8 – j4.10
768
24.1 – j7.86
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2I08H040NR1 A2I08H040GNR1
RF Device Data
Freescale Semiconductor, Inc.
17
Table 15. Peaking Side Load Pull Performance — Maximum Power Tuning
VDD = 28 Vdc, IDQ1B = 30 mA, VGS2B = 2.3 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Output Power
P1dB
f
(MHz)
Zsource
()
Zin
()
728
22.4 + j1.93
20.3 + j0.94
748
22.1 – j0.64
21.0 + j2.44
768
22.4 – j1.08
21.9 + j4.31
Zload
()
(1)
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
4.44 + j3.21
29.3
45.0
32
57.7
–5
3.99 + j2.31
28.8
45.3
34
54.1
–5
4.32 + j2.46
29.4
45.6
36
58.4
–5
Max Output Power
P3dB
f
(MHz)
Zsource
()
Zin
()
Zload (2)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
728
22.4 + j1.93
21.2 + j0.96
4.74 + j2.36
27.0
46.0
40
58.3
–9
748
22.1 – j0.64
22.0 + j2.51
4.58 + j2.21
26.9
46.2
42
58.8
–10
768
22.4 – j1.08
23.2 + j4.05
4.52 + j1.59
27.0
46.3
43
57.4
–9
(1) Load impedance for optimum P1dB power.
(2) Load impedance for optimum P3dB power.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Table 16. Peaking Side Load Pull Performance — Maximum Efficiency Tuning
VDD = 28 Vdc, IDQ1B = 30 mA, VGS2B = 2.3 Vdc, Pulsed CW, 10 sec(on), 10% Duty Cycle
Max Drain Efficiency
P1dB
f
(MHz)
Zsource
()
Zin
()
Zload (1)
()
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
728
22.4 + j1.93
20.1 + j1.53
5.25 + j5.68
30.0
43.9
25
63.8
–8
748
22.1 – j0.64
20.8 + j4.24
5.21 + j9.70
30.2
42.0
16
69.8
–11
768
22.4 – j1.08
21.6 + j5.73
4.94 + j7.47
30.8
43.5
22
71.9
–11
Max Drain Efficiency
P3dB
Gain (dB)
(dBm)
(W)
D
(%)
AM/PM
()
5.89 + j5.15
27.9
45.0
32
66.2
–11
21.6 + j3.60
6.00 + j7.89
28.2
43.9
25
69.5
–13
22.7 + j5.43
5.81 + j7.57
28.6
44.1
26
72.9
–15
f
(MHz)
Zsource
()
Zin
()
728
22.4 + j1.93
20.9 + j1.52
748
22.1 – j0.64
768
22.4 – j1.08
Zload
()
(2)
(1) Load impedance for optimum P1dB efficiency.
(2) Load impedance for optimum P3dB efficiency.
Zsource = Measured impedance presented to the input of the device at the package reference plane.
Zin
= Impedance as measured from gate contact to ground.
Zload = Measured impedance presented to the output of the device at the package reference plane.
Input Load Pull
Tuner and Test
Circuit
Output Load Pull
Tuner and Test
Circuit
Device
Under
Test
Zsource Zin
Zload
A2I08H040NR1 A2I08H040GNR1
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RF Device Data
Freescale Semiconductor, Inc.
35
35
30
30
37.5
25
38
20
38.5
E
15
10
P
0
41.5
48
E
5
10
56
54
0
25
20
52
48
5
15
50
58
15
P
40.5
41
44
46
20
10
40
5
0
39
39.5
42
25
IMAGINARY ()
IMAGINARY ()
P1dB – TYPICAL CARRIER LOAD PULL CONTOURS — 748 MHz
44
5
0
10
15
46
20
25
REAL ()
REAL ()
Figure 29. P1dB Load Pull Output Power Contours (dBm)
Figure 30. P1dB Load Pull Efficiency Contours (%)
35
35
34
30
30
–4
37 36.5
20
25
36
35.5
E
35
15
34.5
10
P
0
5
33.5
15
E
15
–16
25
20
–10
5
33
10
20
10
34
5
0
IMAGINARY ()
IMAGINARY ()
25
0
–8
–6 –4
P
–2
5
0
10
15
20
REAL ()
REAL ()
Figure 31. P1dB Load Pull Gain Contours (dB)
Figure 32. P1dB Load Pull AM/PM Contours ()
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
25
Gain
Drain Efficiency
Linearity
Output Power
A2I08H040NR1 A2I08H040GNR1
RF Device Data
Freescale Semiconductor, Inc.
19
P3dB – TYPICAL CARRIER LOAD PULL CONTOURS — 748 MHz
35
35
30
39
25
25
39.5
20
IMAGINARY ()
IMAGINARY ()
30
40
E
40.5
15
41
10
0
42.5
5
10
15
15
66
64 62
0
25
20
60
58
56
54
5
P
0
E
10
41.5
42
5
20
P
52
5
0
10
15
50
25
20
REAL ()
REAL ()
Figure 33. P3dB Load Pull Output Power Contours (dBm)
Figure 34. P3dB Load Pull Efficiency Contours (%)
35
35
30
30
35.5
35 34.5
20
34
33
33.5
E
15
32.5
10
0
31.5
5
10
15
–10
–8
20
–6
E
15
5
P
0
–14
10
32
5
–4
–12
25
IMAGINARY ()
IMAGINARY ()
25
0
–2
25
20
0
P
5
0
–2
10
15
20
REAL ()
REAL ()
Figure 35. P3dB Load Pull Gain Contours (dB)
Figure 36. P3dB Load Pull AM/PM Contours ()
NOTE:
P
= Maximum Output Power
E
= Maximum Drain Efficiency
25
Gain
Drain Efficiency
Linearity
Output Power
A2I08H040NR1 A2I08H040GNR1
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RF Device Data
Freescale Semiconductor, Inc.
P1dB – TYPICAL PEAKING LOAD PULL CONTOURS — 748 MHz
12
42
E
10
42.5
8
43
6
43.5
44
4
45
P
2
0
IMAGINARY ()
IMAGINARY ()
10
–2
12
41.5
44.5
3
4
7
5
6
REAL ()
8
64
6
62
60
4
–2
9
58
P
56
54
2
3
4
5
6
REAL ()
7
8
9
Figure 38. P1dB Load Pull Efficiency Contours (%)
12
12
10
–14
10
E
30
6
4
29.5
P
2
28.5
0
27
26.5
2
3
4
5
6
REAL ()
–6
4
–4
P
0
28
27.5
–8
–12
6
2
29
–10
E
–16
8
IMAGINARY ()
8
IMAGINARY ()
66
0
Figure 37. P1dB Load Pull Output Power Contours (dBm)
–2
68
8
2
43.5
43
2
E
7
8
9
Figure 39. P1dB Load Pull Gain Contours (dB)
NOTE:
–2
–2
2
3
4
5
6
REAL ()
7
8
9
Figure 40. P1dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I08H040NR1 A2I08H040GNR1
RF Device Data
Freescale Semiconductor, Inc.
21
P3dB – TYPICAL PEAKING LOAD PULL CONTOURS — 748 MHz
12
42
42.5
43
IMAGINARY ()
10
8
43.5
44
E
44.5
6
45
4
45.5
46
P
2
44
2
44.5
3
4
7
5
6
REAL ()
8
64
62
P
10
10
IMAGINARY ()
28
6
4
27.5
P
2
27
26.5
0
25
24.5
2
3
4
5
6
REAL ()
3
4
5
6
REAL ()
–16
–20
7
8
9
Figure 43. P3dB Load Pull Gain Contours (dB)
NOTE:
9
–12
E
6
–10
4
–8
P
–6
0
7
8
–14
–18
2
27
26
25.5
2
8
E
56
54
60
58
Figure 42. P3dB Load Pull Efficiency Contours (%)
12
8
66
4
–2
9
68
6
12
–2
E
0
Figure 41. P3dB Load Pull Output Power Contours (dBm)
IMAGINARY ()
8
2
0
–2
64
10
IMAGINARY ()
12
–2
–4
2
3
4
5
6
REAL ()
7
8
9
Figure 44. P3dB Load Pull AM/PM Contours ()
P
= Maximum Output Power
E
= Maximum Drain Efficiency
Gain
Drain Efficiency
Linearity
Output Power
A2I08H040NR1 A2I08H040GNR1
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RF Device Data
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
A2I08H040NR1 A2I08H040GNR1
RF Device Data
Freescale Semiconductor, Inc.
23
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RF Device Data
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RF Device Data
Freescale Semiconductor, Inc.
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RF Device Data
Freescale Semiconductor, Inc.
PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS
Refer to the following resources to aid your design process.
Application Notes
 AN1955: Thermal Measurement Methodology of RF Power Amplifiers
 AN1977: Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family
 AN1987: Quiescent Current Control for the RF Integrated Circuit Device Family
Engineering Bulletins
 EB212: Using Data Sheet Impedances for RF LDMOS Devices
Software
 Electromigration MTTF Calculator
 RF High Power Model
 .s2p File
Development Tools
 Printed Circuit Boards
To Download Resources Specific to a Given Part Number:
1. Go to http://www.nxp.com/RF
2. Search by part number
3. Click part number link
4. Choose the desired resource from the drop down menu
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
0
Jan. 2016
Description
 Initial release of data sheet
A2I08H040NR1 A2I08H040GNR1
RF Device Data
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29
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E 2016 Freescale Semiconductor, Inc.
A2I08H040NR1 A2I08H040GNR1
Document Number: A2I08H040N
Rev. 0, 1/2016
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RF Device Data
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