ATW300 Family Programming Guide ATW300 Family Programming Guide Atrua Proprietary and Confidential. Do not disseminate without permission of Atrua Technologies Copyright © 2004-6, Atrua Technologies, Incorporated. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 1 of 67 ATW300 Family Programming Guide Introduction......................................................................................................................... 4 Conventions ........................................................................................................................ 5 Sensor Operation................................................................................................................. 5 Sensor Array ................................................................................................................... 5 Analog-to-Digital Converter........................................................................................... 6 Frame Buffer................................................................................................................... 6 Standby and Power-down Modes ....................................................................................... 6 Bus Operations.................................................................................................................... 7 8-bit Bidirectional Bus Interface..................................................................................... 7 Serial Peripheral Interface (SPI) ................................................................................. 7 Register Write Procedure............................................................................................ 8 Register Read Procedure............................................................................................. 9 Persistent Read-Command Protocol ........................................................................... 9 Non-Persistent Read-Command Protocol ................................................................. 11 Additional Information ............................................................................................. 13 Register Description.......................................................................................................... 14 Index Register (IDX_REG) ...................................................................................... 16 Command Register (CMD_REG)............................................................................. 17 Data Register (DAT_REG)....................................................................................... 20 Status Register (STA_REG) ..................................................................................... 21 Interrupt Status Register (INT_STAT_REG) ........................................................... 22 Frame Interval Timer Control (FCON_REG)........................................................... 23 Auxiliary Register (AUX_REG)............................................................................... 25 Chip ID 0 Register (CID0_REG).............................................................................. 26 Chip ID 1 Register (CID1_REG).............................................................................. 27 Sensor Test Register (OPS_REG) ............................................................................ 28 Buffer Control Register (BUFC_REG) .................................................................... 29 Clock Control Register (CLK0_REG)...................................................................... 30 I/O Drive Strength Configuration Register (IOC_REG) .......................................... 31 Bulk Capacitance Detection Configuration Register (BCC_REG) .......................... 32 Interrupt Enable Register (IEN_REG)...................................................................... 33 Threshold Crossing High and Low Register (THR_REG) ....................................... 34 Lower Mean Interrupt Threshold Register (LMT_REG) ......................................... 35 Upper Variance Interrupt Threshold (UVT_REG) ................................................... 36 Upper Threshold-crossing Count Interrupt Threshold (UCT_REG) ........................ 37 Timestamp, Buffer 0, LSB Register (F0T0_REG) ................................................... 38 Timestamp, Buffer 0, MSB Register (F0T1_REG) .................................................. 39 Timestamp, Buffer 1, LSB Register (F1T0_REG) ................................................... 40 Timestamp, Buffer 1, MSB Register (F1T1_REG) .................................................. 41 Mean, right region, buffer 0 (MRF0_REG).............................................................. 42 Mean, center region, buffer 0 (MCF0_REG)............................................................ 43 Mean, left region, buffer 0 (MRF0_REG) ................................................................ 44 Mean, right region, buffer 1 (MLF1_REG) .............................................................. 45 Mean, center region, buffer 1 (MCF1_REG)............................................................ 46 Mean, left region, buffer 1 (MLF1_REG) ................................................................ 47 Mean, right region, least significant nibble, buffer 0 (MRXF0_REG)..................... 48 Mean, center region, least significant nibble, buffer 0 (MCXF0_REG) .................. 49 Mean, left region, least significant nibble, buffer 0 (MLXF0_REG) ....................... 50 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 2 of 67 ATW300 Family Programming Guide Mean, right region, least significant nibble, buffer 1 (MRXF1_REG)..................... 51 Mean, center region, least significant nibble, buffer 1 (MCXF1_REG) .................. 52 Mean, left region, least significant nibble, buffer 1 (MLXF1_REG) ....................... 53 Variance, right region (VRT_REG).......................................................................... 54 Variance, center region (VCN_REG) ....................................................................... 55 Variance, left region (VLF_REG) ............................................................................ 56 Threshold crossing count, right region (TRT_REG) ................................................ 57 Threshold crossing count, center region (TCN_REG) ............................................. 58 Threshold crossing count, left region (TLF_REG)................................................... 59 AGC, Buffer 0 (GSKF0_REG)................................................................................. 60 AGC, Buffer 1 (GSKF1_REG)................................................................................. 61 AGC Current (GSKC_REG) .................................................................................... 62 ATW300 Measurement Data ............................................................................................ 63 Sample Operation Flowcharts........................................................................................... 65 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 3 of 67 ATW300 Family Programming Guide Introduction This document is the Programmer’s Guide for the Atrua family of Adaptive Capacitive touch sensors. Electrical specifications, physical dimensions and pin descriptions are contained in the ATW300 Family Datasheet, which is available from Atrua upon request. ATW300 family sensors are high performance, low power, low cost sensors with an integrated 124 x 8 sensing array of metal electrodes utilizing Atrua’s Adaptive Capacitive sensing technology. Each electrode acts as one plate of a capacitor, while the contacting finger acts as the second plate. An insulating layer on the device surface forms the dielectric between the two plates. Ridges and valleys on the finger yield varying capacitor values across the array, which is read to form a partial image of the fingerprint. Internal circuits within ATW300 family of sensors convert the sensed data into a stream of digital data (a frame) that is presented to the host microprocessor via an 8-bit bidirectional bus interface compatible with most microprocessors, or via a high-speed synchronous serial interface compatible with SPI™. Processing algorithms running on the host perform image reconstruction by assembling the frames that are delivered as the finger is moved across the sensor array. This data is used to determine X-Y movement, rotation and pressure for the navigation and control algorithms. Other algorithms perform minutiae extraction and matching to form and compare templates that are stored and used for fingerprint authentication. ATW300 sensors include the analog-to-digital converters necessary to digitize the sensed data, an automatic finger detection (AFD) circuit that sends an interrupt signal to the host microprocessor when a finger is placed on the sensor, and an automatic gain control (AGC) function that provides high quality fingerprint images from all types of skin, dry to moist, in a wide range of climatic conditions. The ATW300 sensors also integrate all recommended external components except for a few small resistors and capacitors. The AFD interrupt allows the host microprocessor to remain in standby mode until a finger is placed on the sensor, eliminating the need for the host CPU to continually poll the fingerprint sensor to determine whether a finger is present. The interrupt function also permits the host to place the sensor into standby mode, dramatically reducing operating current. The current can be even further reduced by placing the device in power-down mode. The AGC function widens the application range of the sensor and reduces the false acceptance rate (FAR) and false rejection rate (FRR) for the fingerprint recognition function. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 4 of 67 ATW300 Family Programming Guide Conventions Unless otherwise noted, a positive logic (active High) convention is assumed throughout this document. A lowercase ‘n’ following a signal name (e.g., INTRn) indicates that the signal is active Low. Fixed-point values containing fractional parts are notated in “n.m” format, where n is the number of bits of the integer part, and m is the number of bits of the fractional part. For example, a 12-bit value consisting of a 4-bit integer part in the most significant bits and an 8-bit fractional part (resolving to 1/256th) in the least significant bits would be described as 4.8 format, for short. The designation 0xNNNN indicates a hexadecimal number. The designation 0bNNNN indicates a binary number. SPI™ is a trademark of Motorola, Inc. Sensor Operation Figure 1 is a block diagram of the ATW300 sensor, showing the major internal blocks. In addition to the bus interface logic, the registers and the state controller, the chip contains a sensor array, an analog-to-digital converter and a frame buffer. SENSOR ARRAY D[7:0]/SPI A[0] CSn WRn RDn INTRn TCLKIN BUS CONTROLLER AND I/O BUFFERS CONTROL AND STATUS REGISTERS STATE CONTROLLER INDEX REGISTER ANALOG-TO-DIGITAL CONVERTER FRAME BUFFERS Figure 1. ATW300 block diagram Sensor Array The sensor consists of an array of 992 metal electrode pixels arranged in a matrix of 124 columns by 8 rows. Each electrode forms one side of a capacitor, with the finger placed on the sensor forming the second electrode. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 5 of 67 ATW300 Family Programming Guide Analog-to-Digital Converter When a finger is placed on the sensor array, a capacitance is formed by each electrode and the finger. Valleys and ridges on the finger will yield varying capacitance values. All 124 columns (pixels) in a single row of the sensor array are measured simultaneously, with the process being repeated eight times to capture the data for the eight rows of pixels in the sensor array. The capacitance for each pixel is digitized into a four-bit value ranging from 0x00 to 0x0F, with 0x00 representing black and 0x0F representing white. The data for two adjacent pixels is formed into a byte, with the data for the even pixel (columns 0, 2, 4, … 122) in the lower nibble of the byte and the data for the odd pixel (columns 1, 3, 5, … 123) in the upper nibble. Frame Buffer The frame buffer provides temporary storage for the digitized sensor data. When data is available to be read, a data available bit in one of the device’s status registers is asserted. The host can then read the data for that frame by reading from the Data Register. Each read of that register automatically increments the read pointer for the data buffer, so that the data is read sequentially, starting with the byte containing the data for row 0, columns 0 and 1, continuing to the end of that row (row 0, columns 122 and 123), and then proceeding to the next row, until all data for that frame of the finger swipe has been output to the host. When a complete frame has been read, the data available bit will be cleared. Standby and Power-down Modes ATW300 offers two power saving modes, standby mode and power-down mode. Standby mode turns off the majority of the operating circuits within the sensor, but allows the surface contact detection function to operate. This mode can be invoked to reduce the operating current while waiting for the finger to be placed on the sensor’s surface.To invoke the standby (partial power down) mode, the partial power down bit P_PWR_DN[6] in the IOC_REG should be set. In this mode, sensor registers cannot be read, and only certain registers can be written. Power-down mode consumes the least power and can be invoked when operation of the sensor is not required. To enter in power-down mode, the full power down bit F_PWR_DN[7] in the IOC_REG should be set. Power-down mode is invoked when CMD_REG is set to 0x00 and the timestamp timer bit SCLK_EN, CLK0_REG[6] is cleared. When the CMD_REG[2] bit is set, the device operates in the standby mode, and it remains in that mode until a surface contact is detected. If AUTO_RUN_EN, CMD_REG[4] is also set at the same time, the device will then automatically enter the normal operating mode and begin calibration and fingerprint data acquisition once a surface contact is detected. If AUTO_RUN_EN is not set, the sensor will remain in standby mode until the host specifically invokes an operating function by setting appropriate bits in the Command Register. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 6 of 67 ATW300 Family Programming Guide Bus Operations Communications between the host processor and the ATW300 sensor are executed over one of two interfaces: an 8-bit bidirectional bus, using read, write and chip select control signals that are compatible with most microprocessors, or an SPI™-compatible synchronous serial interface. If interrupts are enabled, the occurrence of certain events is signaled to the host via an interrupt output signal. 8-bit Bidirectional Bus Interface Table 1 describes the possible bus operations for the 8-bit bidirectional bus interface. A single address line (A0) is used to select the register for the read or write transaction. When A0 is Low, the Index register is selected. When A0 is High, one of the control or status registers is selected, using the current contents of the Index register as a pointer. Thus, two cycles are required to access a specific register for the transaction. In the first cycle, the register’s pointer value should be written into the Index Register and then the required transaction with the desired register is performed during the second cycle. Table 1. ATW300 8-bit Bidirectional Bus Operations1 Operation Deselected Selected/Idle Read Index Register Write Index Register Read Data/Control/Status Register3 Write Data/Control/Status Register3 CSn H L L L L L RDn X H L H L H WRn2 X H H L H L A0 X X L L H H D[7:0] Hi-Z Hi-Z DOUT DIN DOUT DIN Notes: 1. L = VIL, H = VIH, X = Don’t Care. See “ATW300 Family Data Sheet” for Voltage Levels. 2. Data is latched on the rising (trailing) edge of WRn. 3. The location read from or written to is the register pointed to by the contents of the Index Register. Serial Peripheral Interface (SPI) In the Serial Peripheral Interface (SPI) mode the sensor functions as a slave device. The SPI interface uses four signals, SCSn, SCK, MOSI, and MISO. Signal SCSn SCK MOSI Description Slave Chip Select. Active-low input to slave. The SPI master drives SCSn low to initiate a read transaction or write transaction. The SPI master drives SCSn high to terminate a read or write transaction. Slave Clock. Input to slave. SCK is driven by the SPI master. Data as shifted out of the master or slave on the falling edge of SCK. Data is sampled by the master or slave on the rising edge of SCK. Master Output Slave Input. The MOSI pin is driven by the SPI master, 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 7 of 67 ATW300 Family Programming Guide which shifts data out to the slave device on the falling edge of SCK. The slave device samples the input data on the rising edge of SCK. Data is shifted out from the master most-significant-bit (MSB) first and LSB last. Master Input Slave Output. The MISO pin is driven by the SPI slave, which shifts the data out to the master on the falling edge of SCK. The SPI master samples data from the slave device on the rising edge of SCK. Data is shifted out from the slave MSB first and LSB last. MISO There are two types of data transfers–Write Register and Read Register. A data transfer consists of two phases–a Command Phase and Data Phase. During the Command Phase, the SPI master sends an 8-bit command, which has two fields. Bits [7:1] specify the register address to be read or written. Bit 0 specifies whether the data transaction will write or read a register. If a register is to be written, the SPI master sends an 8-bit value during the data phase. If a register is to be read, then the SPI slave will send the contents of the register that was addressed. Table 2. SPI Bus Operations Command Bit Field [7:1] Register Address [6:0] [0] Read/Write Description Specifies the register address to be read or written. Specifies whether the command is a Read or Write command. 0=Write to the specified register. 1=Read from the specified register. Register Write Procedure To write a register, the SPI master (i.e., host controller) drives SCSn low, sends two bytes to the slave, and then drives SCSn high. The first byte is the Write Command and the second byte is the data to be written into the specified register. Refer to Figure 2. SCSn SCK MOSI A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 WRITE COMMAND MISO D7 D6 D5 D4 D3 D2 IDLE DATA OUT D4 D3 D2 D1 D0 D2 D1 D0 DATA IN D1 D0 D7 D6 D5 D4 D3 IDLE DATA OUT Figure 2. SPI Single-Byte Write 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 8 of 67 ATW300 Family Programming Guide By holding SCSn low, the master can continue to write to the slave by sending the additional Command/Data byte pairs. Refer to Figure 3. SCSn SCK MOSI A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 WRITE COMMAND MISO D7 D6 D5 D4 D3 D2 D4 D3 D2 D1 D0 A6 A5 DATA IN D1 D0 D7 IDLE DATA OUT D6 D5 D4 D3 A4 A3 A2 A1 A0 0 D7 D6 D5 WRITE COMMAND D2 D1 D0 D7 IDLE DATA OUT D6 D5 D4 D3 D2 D4 D3 D2 D1 D0 D2 D1 D0 DATA IN D1 D0 D7 IDLE DATA OUT D6 D5 D4 D3 IDLE DATA OUT Figure 3. SPI Multiple Writes Register Read Procedure The ATW300 family of sensors support two different protocols for reading a register. These two read protocols are called “Persistent Read-Command” and “Non-Persistent Read-Command.” Upon reset the ATW300 defaults to the Persistent Read-Command protocol. The Non-Persistent Read-Command protocol (compatible with the ATW2xx family of sensors) can be selected by setting the SPI_PCL bit (IOC_REG[4]). The following sections describe the differences between the two read-command protocols. SPI_PCL Bit (IOC_REG[4]) 0 (Default upon reset) 1 Selected SPI Read Protocol Persistent Read-Command Non-Persistent Read-Command Persistent Read-Command Protocol In the Persistent Read-Command protocol, the slave accepts only the first read command after the assertion of SCSn. After receiving the first read command, the slave ignores MOSI as long as SCSn remains asserted. The register address specified in the first read command “persists” until the de-assertion of SCSn. Following the read command, the data transfer transitions into the Data Phase and the slave transmits the contents of the register specified in the read command. The Data Phase is repeated until SCSn is deasserted. Figure 4 shows a single-byte read, a method of reading a register one time. To read a register, the SPI master first drives SCSn low, sends the read command during the Command Phase (Time Slot 0), receives one data byte during the Data Phase (Time Slot 1), and then drives SCSn high. The master must issue a separate single-byte read for each separate register access. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 9 of 67 ATW300 Family Programming Guide Figure 4. Single-Byte Read (Persistent Read-Command Protocol) Figure 5 shows a multiple-byte read, a method of reading a register multiple times. During the Command Phase (Time Slot 0), the master sends a read command, specifying the address to be read. After the Command Phase, the data transfer remains in the Data Phase (Time Slots 1 through 4) until SCSn is de-asserted. For each time slot in the Data Phase, the slave reads the same register and transmits the data back to the master. Figure 5. Multiple-Byte Read (Persistent Read-Command Protocol) Figure 6 shows an example of the two separate read commands separated by the deassertion of SCSn. In Time Slot 0, the master sends the first read command. In Time Slots 1 and 2, the slave reads the register and transmits the data back to the master. After Time Slot 2, the master drives SCSn high to terminate the data transmission. Then the master drives SCSn low and sends the second read command in Time slot 3. The slave reads the register and sends the data during Time Slot 4. After Time Slot 4, the master drives SCSn high to terminate the data transmission. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 10 of 67 ATW300 Family Programming Guide Figure 6. Multiple-Byte Read Separated by SCSn High (Persistent Read-Command Protocol) Figure 7 shows an example of the SPI master pausing the data transfer by stopping SCK after Time Slot 2. SCSn remains asserted during the entire data transfer. The master resumes the data transfer by restarting SCK at the beginning of Time Slot 3. Figure 7. Multiple-Byte Read with SCK controlled Flow Control (Persistent Read-Command Protocol) Non-Persistent Read-Command Protocol In the Non-Persistent Read-Command Protocol, the slave monitors MOSI for a read command as the slave transmits the requested data back to the master. The master must send a read command to the slave for each time slot that master is clocking data from the slave. Unlike the Persistent Read-Command Protocol, the Non-Persistent ReadCommand Protocol does not require the host to de-assert SCSn before transmitting a read command. The master is allowed to read multiple registers while keeping SCSn asserted. Figure 8 shows a single-byte read. To read a register, the master drives SCSn low, transmits the read command to the slave, receives one data byte from the slave, and then drives SCSn high. The master sends a second read command while the slave is sending the data. The slave will transmit the data requested by the second read command during the next read or write command. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 11 of 67 ATW300 Family Programming Guide Figure 8. Single-Byte Read (Non-Persistent Read-Command Protocol) Figure 9 shows a multiple-byte read. During Time Slot 0, the master sends a read command. During Time Slot 1, the slave sends the data for the register specified in Time Slot 0. In Time Slot 1 the master sends another read command. In Time Slot 2, the slave sends the data that was requested by the read command in Time Slot 1. Figure 9. Multiple-Byte Read (Non-Persistent Read-Command Protocol) The read command can be used to read the same register multiple times or to read multiple registers while SCSn is low. For example, in Figure 8, if identical read commands are issued in time slots 0 through 3, the same register will be read in time slots 1 through 4. However if four different register addresses are issued in time slots 0 through 3, then data from four different registers would be returned during time slots 1 through 4. When using the Non-Persistent Read-Command Protocol to read a frame, ensure that the last read command of the frame is to read STA_REG instead of DAT_REG to avoid reading the first byte of the next frame. Figure 10 shows an example of the SPI master using SCSn to pause and resume the data transfer. After time slot 2, the master drives SCSn high to pause data transmission. The data transfer pauses even though SCK continues to toggle. Then the master drives SCSn low and slave resumes transmission in Time Slot 3. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 12 of 67 ATW300 Family Programming Guide Figure 10. Multiple-Byte Read with SCSn controlled Flow Control (Non-Persistent Read-Command Protocol) Figure 11 shows an example of the master pausing the data transfer by stopping SCK after Time Slot 2. SCSn remains asserted during the entire data transfer. The master resumes the data transfer by restarting SCK at the beginning of Time Slot 3. Figure 4. Multiple-Byte Read with SCK controlled Flow Control (Non-Persistent Read-Command Protocol) Additional Information Please consult the “ATW300 Family Datasheet” for more information on bus and serial interface signals, timing, and other parameters. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 13 of 67 ATW300 Family Programming Guide Register Description Tables 3 lists the user accessible registers of ATW300 family of sensors. Subsequent tables detail each of the internal user-accessible registers. Table 3. ATW300 User Accessible Register Map A0 L H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H [IDX_REG] X 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 855-0004-001 Rev 1 May 2006 Function Index Command Data Status Interrupt Frame Interval Timer Control Auxiliary Chip ID 0 Chip ID 1 Sensor Test Buffer Control Clock Control 1 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED I/O Drive Strength Configuration Bulk Capacitance Detection Configuration Interrupt Enable RESERVED Threshold Crossing High and Low Lower Mean Interrupt Threshold Upper Variance Interrupt Threshold Upper Threshold Crossing Count Interrupt RESERVED RESERVED RESERVED RESERVED Timestamp, Buffer 0, LSB Timestamp, Buffer 0, MSB Timestamp, Buffer 1, LSB Timestamp, Buffer 1, MSB Mean, right region, buffer 0 Atrua Technologies Confidential and Proprietary Acronym IDX_REG CMD_REG DAT_REG STA_REG INT_REG FCON_REG AUX_REG CID0_REG CID1_REG OPS_REG BUFC_REG CLK0_REG IOC_REG BCC_REG IEN_REG THR_REG LMT_REG UVT_REG UCT_REG F0T0_REG F0T1_REG F1T0_REG F1T1_REG MRF0_REG Page 14 of 67 ATW300 Family Programming Guide A0 H H H H H H [IDX_REG] 0x25 0x26 0x27 0x28 0x29 0x2A H 0x2B H 0x2C H 0x2D H 0x2E H 0x2F H H H H H H H H H H H H H 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 855-0004-001 Rev 1 May 2006 Function Mean, center region, buffer 0 Mean, left region, buffer 0 Mean, right region, buffer 1 Mean, center region, buffer 1 Mean, left region, buffer 1 Mean, right region, least significant nibble, buffer 0 Mean, center region, least significant nibble, buffer 0 Mean, left region, least significant nibble, buffer 0 Mean, right region, least significant nibble, buffer 1 Mean, center region, least significant nibble, buffer 1 Mean, left region, least significant nibble, buffer 1 Variance, right region Variance, center region Variance, left region Threshold crossing count, right region Threshold crossing count, center region Threshold crossing count, left region AGC, buffer 0 AGC, buffer 1 AGC, current RESERVED RESERVED RESERVED RESERVED Atrua Technologies Confidential and Proprietary Acronym MCF0_REG MLF0_REG MRF1_REG MCF1_REG MLF1_REG MRXF0_REG MCXF0_REG MLXF0_REG MRXF1_REG MCXF1_REG MLXF1_REG VRT_REG VCN_REG VLF_REG TRT_REG TCN_REG TLF_REG GSKF0_REG GSKF1_REG GSKC_REG Page 15 of 67 ATW300 Family Programming Guide Index Register (IDX_REG) Access Conditions Access Type Bit Function Reset Value A0 = 0 Read/Write 7 6 5 0 0 0 Bit Function 7:0 REG_INDEX 855-0004-001 Rev 1 May 2006 4 3 REG_INDEX 0 0 2 1 0 0 0 0 Description Register Index. This value is used as an index to access the data, control, and status registers. Set the index address of the register to be accessed into this register before reading from or writing to that register. Atrua Technologies Confidential and Proprietary Page 16 of 67 ATW300 Family Programming Guide Command Register (CMD_REG) Access Conditions Access Type A0 = 1; [IDX_REG] = 0x00 Read/Write Bit 7 6 5 Function ADDR _RES ET MEAS URE FIND_ GRAY Reset Value 0 0 0 Bit 7 6 5 4 3 2 4 3 FRAM AUTO E_TIM _RUN ER_E _EN N 0 0 2 SURF _CON TX_E N 0 1 0 MCLK _EN RESE RVED 0 0 Function Description Reset frame buffer addresses. 0 = Data buffer address reset disabled. Must be negated by the host processor to allow reading and ADDR_RESET writing the buffer. 1 = Resets the read and write pointers for the data buffer. Also clears DATA_RDY and STA_REG[3:0]. Start measure operation. This performs an analog-todigital conversion of the sensor array. MEASURE 0 = Measure operation disabled. 1 = The transition of this bit from 0 to 1 starts the measure operation. Start gray level seek operation. 0 = Gray level seek operation is disabled. FIND_GRAY 1 = The transition of this bit from 0 to 1 enables a gray level seek operation of the current surface. Auto-run enable 0 = Disables automatic run operation. 1 = If CMD_REG[2] is also 1, enables automatic run operation when a surface contact is detected. This AUTO_RUN_EN invokes a gray level seek cycle followed by a measurement cycle. If bit[3] = 1, measurement cycles repeat automatically. Frame interval timer enable. 0 = Disables the frame interval timer. 1 = Enables the frame interval timer. The frame timer FRAME_TIMER_EN interval is programmed by the FRAME_DIV[3:0] bits. To enable the frame interval timer feature, set FRAME_TIMER_EN at the same time as the MEASURE bit. Surface contact detector enable 0 = Disables the surface contact detection function SURF_CONTX_EN and puts the sensor into the power-down mode. 1 = Enables the surface contact detection function, 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 17 of 67 ATW300 Family Programming Guide 1 MCLK_EN 0 RESERVED CMD_REG_[7:0] 0x22 0x42 0x62 0x4A 0x04 0x14 puts the sensor into the standby mode, and enables operation of the surface contact detect interrupt. If CMD_REG[4], AUTO_RUN_EN = 1, detection of a surface contact will automatically begin a calibration and measurement cycle. Master clock enable 0 = Turns the internal clock off 1 = Starts the internal clock. This clock must be enabled for the sensor to function. Reserved. Operating Mode FindGray Operation. Measure Operation. Atomic FindGray-Measure Operation Frame Timer Mode. Basic Finger Detect Mode AutoRun Mode. FindGray operation. The MCLK_EN bit must be written to ‘1’ before setting the FIND_GRAY bit. A ‘0’ to ‘1’ transition of the FIND_GRAY bit initiates a single FindGray operation. Do a FindGray operation before the initial Measure operation to calibrate the sensor. Optionally, do periodic FindGray operations as the finger traverses the sensor surface. Measure operation. The MCLK_EN bit must be written to ‘1’ before setting the MEASURE bit. A ‘0’ to ‘1’ transition of the MEASURE bit initiates a single Measure operation. The Measure operation performs an A/D conversion on the sensor array and stores the results into one frame of the frame buffer. The MEASURE bit must be cleared and set for each sensor array conversion (unless the Frame Interval Timer is enabled). Atomic FindGray-Measure operation. If the FIND_GRAY, MEASURE, and MCLK_EN bits are set at the same time, the device will do a FindGray operation followed by a Measure operation. Frame Timer mode. It uses the Frame Interval Timer feature. The Frame Interval Timer feature allows image frames to be captured at a regular interval. The Frame Interval Timer is enabled if the FRAME_TIMER_EN bit is set concurrently with the MEASURE bit. When the frame timer is enabled, the sensor will automatically initiate measure operations at the programmed frame-timer interval as long as there is at least one empty frame buffer. If both frame buffers are full at the frame-timer interval, then the sensor will wait until the next frame-timer interval to attempt the Measure operation. As long as both buffers are full, the sensor will continue postponing the Measure operation by the frame-timer interval. The FRAME_DIV_[3:0] bits of the FCON register set the periodicity of the frame interval timer. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 18 of 67 ATW300 Family Programming Guide Basic Finger Detect Mode. It uses the Surface Contact Detector feature. Surface Contact Detector feature. The Surface Contact Detector feature can be used to generate an interrupt when an increase in bulk capacitance is detected. Set the SURF_CONTX_EN bit to enable the Surface Contact Detector feature. The Surface Contact Detector is implemented as a Bulk Capacitance Detector. When the Surface Contact Detect feature is enabled, the sensor sleeps in a low power state and periodically wakes up and momentarily activates the Bulk Capacitance Detector. The period that the sensor sleeps is called the Finger Detect Interval and its periodicity is programmed by the DETECT_ON_[1:0] of the BUFC register. The Bulk Capacitance Detector triggers if the bulk capacitance exceeds a programmed threshold. The threshold or sensitivity of the Bulk Capacitance Detector can be adjusted by the BULK_CAP_[4:0] bits of the BCC register. If the Bulk Capacitance Detector triggers, the BULK_INT_STAT bit in the INT register will set. If the AutoRun feature was also enabled, then the sensor automatically initiates a Find Gray operation followed by a Measure operation. AutoRun feature. The AutoRun feature can only be used when Advanced Finger Detect mode (Surface Contact Detector Enabled with comparator for the Mean, Variance and Threshold crossing) is used. When the AutoRun feature is enabled, the sensor waits in a low power state and periodically activates the Surface Contact Detector (Bulk Capacitance Detector). If the Bulk Capacitance Detector triggers, the sensor automatically initiates a FindGray operation followed by a Measure operation. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 19 of 67 ATW300 Family Programming Guide Data Register (DAT_REG) Access Conditions Access Type A0 = 1; [IDX_REG] = 0x01 Read Only Bit Function Reset Value 6 5 DATA_ODD[3:0] Bit 7:4 3:0 7 4 3 2 1 DATA_EVEN[3:0] 0 Not reset Function Description Frame buffer data for odd columns (1, 3, 5, … , 121, DATA_ODD[3:0] 123) Frame buffer data for even columns (0, 2, 4, …, 120, DATA_EVEN[3:0] 122) Note: the 4-bit sensor data from each of two adjacent columns in one row is read from the data buffer as one byte. Thus, the data for the 124 columns is read in 62 bytes. A read of the data register increments the data buffer read pointer on the trailing (rising) edge of RDn. Note: the frame buffers are not cleared on reset. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 20 of 67 ATW300 Family Programming Guide Status Register (STA_REG) A0 = 1; [IDX_REG] = 0x02 Read Only Access Conditions Access Type Bit 7 6 5 4 Function RESERVED Reset Value 0x00 Bit 7:2 Function RESERVED 1 BUF_FULL_1 0 BUF_FULL_0 855-0004-001 Rev 1 May 2006 3 2 1 0 BUF_FULL_[1: 0] 0x00 Description Reserved. Frame buffer 1 full. A ‘1’ indicates that a complete frame has been stored in the buffer. The bit remains set until the data for the frame is completely read out and then resets to ‘0’ automatically. Frame buffer 0 full. A ‘1’ indicates that a complete frame has been stored in the buffer. The bit remains set until the data for the frame is completely read out and then resets to ‘0’ automatically. Atrua Technologies Confidential and Proprietary Page 21 of 67 ATW300 Family Programming Guide Interrupt Status Register (INT_STAT_REG) A0 = 1; [IDX_REG] = 0x03 Read/Write Access Conditions Access Type Bit 7 Bit 7:5 4 3 2 1 0 5 0 0 0 Function RESERVED TC_IRQ_STAT VAR_IRQ_STAT MEAN_IRQ_STAT BULK_IRQ_STAT FR_RDY_IRQ_STAT 4 3 2 TC_IR VAR_I MEAN Q_ST RQ_S _IRQ_ AT TAT STAT RESERVED Function Reset Value 6 0 0 0 1 BULK _IRQ_ STAT 0 0 FR_R DY_IR A_ST AT 0 Description Reserved. Threshold-crossing interrupt flag. Variance interrupt flag. Mean interrupt flag. Surface contact interrupt flag. Frame ready interrupt flag. Note: These interrupt status bits do not clear when read. An atomic read/clear would be needed to eliminate possible race conditions. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 22 of 67 ATW300 Family Programming Guide Frame Interval Timer Control (FCON_REG) Access Conditions Access Type A[0] = 1; [IDX_REG] = 0x04 Read/Write Bit Function 7 WRIT E_ER R 6 MEAS URE_ ERR Reset Value 0 0 Bit 7 6 5 4 3:0 5 MISS_ FRAM E_ER R 0 4 READ _EMP TY_E RR 0 3 1 2 1 FRAME_DIV_[3:0] 1 1 0 1 Function WRITE_ERR Description Buffer Write Error. 0 = No error. 1 = Indicates that an attempt was made to write into the frame buffer when it is full. Write a ‘0’ to clear this bit. MEASURE_ERR Measure Error. 0 = No error. 1 = Indicates that an attempt was made to initiate a measure operation when the frame buffer is full. Write a ‘0’ to clear this bit. MISS_FRAME_ERR Missed Frame Error. 0 = No error. 1 = Indicates than an internal operation was completed that required writing data into the frame buffer but the buffer was full. Write a ‘0’ to clear this bit. READ_EMPTY_ERR Read Empty Buffer Error. 0 = No error. 1 = Indicates than an attempt was made to read from the frame buffer when it is empty. Write a ‘0’ to clear this bit. FRAME_DIV_[3:0] Frame Divider. FRAME_DIV[3:0] sets the frame timer interval, which is the delay between automatic Measure operations. This value is loaded into the internal frame interval timer when FRAME_TIM_EN, CMD_REG[3], is written to ‘0’. FRAME_DIV[3:0] sets the frame timer interval from the last Measure operation to the start of the next Measure operation. The smallest frame timer interval unit is t_MEASURE (see CLK0 description). The value of FRAME_DIV[3:0] selects the number of interval units to delay before the start of the next Measure operation. For example, for MCLK_F2X = 1 and FRAME_DIV[3:0] = 3, there will be nominally 3*256 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 23 of 67 ATW300 Family Programming Guide us between the last Measure operation and the start of the next Measure operation. The table below shows the time spent during Measure (actual A/D conversion) and the Delay between Measure operations. The table assumes that a buffer was emptied some time between Measure 1 and 2. Measure 0 256 us Delay 3*256 us Measure 1 256 us Delay 3*256 us Measure 3 256 us The frame rate can be computed with the following equation: Frame Rate = 1/[ ( (1 + FRAME_DIV[3:0]) * t_MEASURE ) /frame] The following table shows the computed frame rate for a given FRAME_DIV[3:0] and MCLK_F2X setting. FRAME_DIV[3:0] 0 1 2 3 4 5 6 7 8 9 A B C D E F Nominal Frame Rate (fps) MCLK_F2X = 0 Not Valid 977 651 488 391 326 279 244 217 195 178 163 150 140 130 122 Nominal Frame Rate (fps) MCLK_F2X = 1 Not Valid 1953 1302 977 781 651 558 488 434 391 355 326 300 279 260 244 FRAME_DIV[3:0] = 0 is not a valid setting. The frame timer won’t initiate Measure operations if FRAME_DIV[3:0] = 0. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 24 of 67 ATW300 Family Programming Guide Auxiliary Register (AUX_REG) A0 = 1; [IDX_REG] = 0x05 Read Only Access Conditions Access Type Bit Function Reset Value 7 6 RESERVED Not reset Bit 7:5 Function RESERVED 4 BUSY 3:0 RESERVED 855-0004-001 Rev 1 May 2006 5 4 BUSY 0 3 2 1 RESERVED Not reset 0 Description Reserved. Busy. 0 = A measure or find gray operation is not in progress. 1 = A measure or find gray operation is in progress. Reserved. Atrua Technologies Confidential and Proprietary Page 25 of 67 ATW300 Family Programming Guide Chip ID 0 Register (CID0_REG) Access Conditions Access Type Bit Function Reset Value (REV AA) Bit 7:0 A0 = 1, [IDX_REG] = 0x06 Read Only 7 6 5 0 0 0 Function CHIP_ID_ROM0 [7:0] 855-0004-001 Rev 1 May 2006 4 3 2 CHIP_ID_ROM0 [7:0] 1 0 0 1 0 1 0 Description Chip ID ROM 0, bits [7:0] Atrua Technologies Confidential and Proprietary Page 26 of 67 ATW300 Family Programming Guide Chip ID 1 Register (CID1_REG) Access Conditions Access Type Bit Function Reset Value (REV AA) Bit 7:0 A0 = 1, [IDX_REG] = 0x07 Read Only 7 6 5 0 0 1 Function CHIP_ID_ROM1 [7:0] 855-0004-001 Rev 1 May 2006 4 3 2 CHIP_ID_ROM1 [7:0] 1 0 0 1 0 0 0 Description Chip ID ROM 1, bits [7:0] Atrua Technologies Confidential and Proprietary Page 27 of 67 ATW300 Family Programming Guide Sensor Test Register (OPS_REG) Access Conditions Access Type Bit 7 6 5 4 RESERVED Function Reset Value A0 = 1; [IDX_REG] = 0x08 Read/Write 0 0 0 Bit 7:4 Function RESERVED 3 INTEG_CAP_3 2 INTEG_CAP_2 1 INTEG_CAP_1 0 INTEG_CAP_0 0 3 INTE G_CA P_3 1 2 INTE G_CA P_2 1 1 INTE G_CA P_1 1 0 INTE G_CA P_0 1 Description Reserved. These bits should be set to 0 Select integration capacitor 3. 0 = Integration capacitor 3 is not selected. 1 = Integration capacitor 3 is selected. Select integration capacitor 2. 0 = Integration capacitor 2 is not selected. 1 = Integration capacitor 2 is selected. Select integration capacitor 1. 0 = Integration capacitor 1 is not selected. 1 = Integration capacitor 1 is selected. Select integration capacitor 0. 0 = Integration capacitor 0 is not selected. 1 = Integration capacitor 0 is selected. Notes: 1. A value of OPS_REG[3:0] = 0b0011, which selects capacitors 0 and 1, is recommended for ideal sensitivity. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 28 of 67 ATW300 Family Programming Guide Buffer Control Register (BUFC_REG) Access Conditions Access Type Bit A0 = 1; [IDX_REG] = 0x09 Read/Write 7 Function TR_EN Reset Value 0 6 5 DETECT_ON[1:0] 0 0 Bit Function 7 TR_EN 6:5 DETECT_ON 4:1 RESERVED 0 FORCE_RESET 855-0004-001 Rev 1 May 2006 4 3 2 1 RESERVED 0 0 0 0 FORCE _RESE T 0 0 Description Trailer Enable. 0 = Do not append the trailer to the frame data. 1 = Append the trailer to the frame data. Nominal Finger Detect Interval. Programs the surface contact detect rate as follows: 00 = Detect every ~ 0.05 s 01 = Detect every ~ 0.10 s 10 = Detect every ~ 0.20 s 11 = Detect every ~ 0.40 s The Finger Detect Interval is based on the internal SCLK and has no relationship to MCLK or the MCLK_F2X bit. Reserved. Force reset. 0 = The force reset function is not active. 1 = A 0-to-1 transition of this bit replicates the power-on reset function. The bit is self clearing and does not need to be reset. Atrua Technologies Confidential and Proprietary Page 29 of 67 ATW300 Family Programming Guide Clock Control Register (CLK0_REG) Access Conditions Access Type Bit Function Reset Value Bit 7 6 5 4:0 A0 = 1; [IDX_REG] = 0x0A Read/Write 7 AUTO _VAR _EN 0 6 5 SCLK _EN MCLK _F2X 0 0 4 3 2 1 0 0 0 RESERVED 0 0 0 Function Description Auto Variance Calculation Enable. 0 = Don’t automatically calculate the variance and threshold crossings in Auto-Run mode. AUTO_VAR_EN 1 = Automatically calculate the variance and threshold crossings after the completion of the MEASURE operation in Auto-Run mode. SCLK Enable. SCLK_EN 0 = Disable the SCLK. 1 = Enable the SCLK for Timestamping. Main clock rate control 0 = The sensor main internal clock operates at normal MCLK_F2X speed (~8 MHz) 1 = The sensor main internal clock operates at approximately 2x normal speed (~16 MHz) RESERVED Reserved. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 30 of 67 ATW300 Family Programming Guide I/O Drive Strength Configuration Register (IOC_REG) Access Conditions Access Type Bit Function Reset Value 7 F_PW R_DN 0 A0 = 1; [IDX_REG] = 0x14 Read/Write 6 P_PW R_DN 0 Bit Function 7 F_PWR_DN 6 P_PWR_DN 5 4 RESERVED SPI_PCL 3:2 RESERVED 1:0 DRV_EN_[1:0] 855-0004-001 Rev 1 May 2006 5 RESE RVED 0 4 SPI_P CL 0 3 2 RESERVED 0 0 1 0 DRV_EN_[1:0] 1 1 Description Full Power Down 0 = Sensor operational 1 = Full Power Down mode Partial Power Down 0 = Normal active mode of operation 1 = Partial Power Down mode IMPORTANT: When this bit is set (sensor in partial power down mode), sensor registers cannot be read, only certain registers can be written. In order to read any status register, this bit must be set to 0. Reserved Select SPI Protocol. The SPI_PCL bit selects between the Persistent Read-Command protocol and the Non-Persistent Read-Command protocol 0 = Persistent Read-Command Protocol. The SPI Read Command transmitted at the beginning of the SPI transfer remains in effect until SCS- is deasserted after which The SPI Read Command is “forgotten.” The MOSI bits after the first Read Command are “don’t cares” while SCS- is asserted. 1 = Non-Persistent Read-Command Protocol. An SPI Read Command must be transmitted before each byte to be read. Reserved. Drive Strength Enable. Configures the output drive strength of the D[7:0] pins. 00 = Minimum drive strength. 01 = Medium drive strength. Suggested for 2.5V VDDO. 10 = Same as 01 setting. 11 = Maximum drive strength. Suggested for 1.8V VDDO. Atrua Technologies Confidential and Proprietary Page 31 of 67 ATW300 Family Programming Guide Bulk Capacitance Detection Configuration Register (BCC_REG) Access Conditions Access Type Bit 7 Function RESER VED Reset Value 0 A0 = 1; [IDX_REG] = 0x15 Read/Write 6 5 0 0 Function RESERVED 6:5 BULK_CMP[1:0] BULK_CAP[4:0] 855-0004-001 Rev 1 May 2006 3 BULK_CMP[1:0] Bit 7 4:0 4 2 1 0 0 0 BULK_CAP[4:0] 0 0 0 Description Reserved. Comparator hysteresis. Provides finer adjustment to the base sensitivity setting. Bulk reference capacitor. Increasing values of BULK_CAP[4:0] decreases the surface contact detector sensitivity. 0b00000 = Most sensitive setting 0b11111 = Least sensitive setting Note: The least sensitive setting would cause the surface contact detector to self trigger even without a finger touching the sensor. The least sensitive setting may not trigger some fingers. Atrua Technologies Confidential and Proprietary Page 32 of 67 ATW300 Family Programming Guide Interrupt Enable Register (IEN_REG) Access Conditions Access Type Bit A0 = 1; [IDX_REG] = 0x16 Read/Write Function 7 RESE RVED 6 FD_IR Q_EN 5 SEL_ AND Reset Value 0 0 0 Bit 7 6 5 4 3 2 1 0 4 3 2 TC_IR VAR_I MEAN Q_EN RQ_E _IRQ_ N EN 0 0 0 1 BULK _IRQ_ EN 0 0 FR_R DY_IR Q_EN 0 Function RESERVED FD_IRQ_EN Description Reserved. Enable finger detect interrupt Select the “AND” of the interrupt sources 0 = Interrupt sources are OR’d to generate interrupt SEL_AND 1 = Interrupt sources are AND’d to generate interrupt TC_IRQ_EN Enable threshold-crossing interrupt VAR_IRQ_EN Enable variance interrupt MEAN_IRQ_EN Enable mean interrupt BULK_IRQ_EN Enable contact interrupt FR_RDY_IRQ_EN Enable frame ready interrupt 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 33 of 67 ATW300 Family Programming Guide Threshold Crossing High and Low Register (THR_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:4 3:0 7 0 A[0] = 1; [IDX_REG] = 0x18 Read/Write 6 5 THR_UPPER_[3:0] 0 0 4 3 0 0 Function THR_UPPER_[3:0] Upper threshold. THR_LOWER_[3:0] Lower threshold. 855-0004-001 Rev 1 May 2006 2 1 THR_LOWER_[3:0] 0 0 0 0 Description Atrua Technologies Confidential and Proprietary Page 34 of 67 ATW300 Family Programming Guide Lower Mean Interrupt Threshold Register (LMT_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A[0] = 1; [IDX_REG] = 0x19 Read/Write 7 6 5 0 0 0 Function LMT_[7:0] 855-0004-001 Rev 1 May 2006 4 3 LMT_[7:0] 0 0 2 1 0 0 0 0 Description Lower mean interrupt threshold. The MEAN_IRQ flag will set after a bulk finger detect event if at least one of the means from the three regions (right, center, or left) meets or falls below value in the LMT register. Atrua Technologies Confidential and Proprietary Page 35 of 67 ATW300 Family Programming Guide Upper Variance Interrupt Threshold (UVT_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A[0] = 1; [IDX_REG] = 0x1A Read/Write 7 6 5 0 0 0 Function UVT_[7:0] 855-0004-001 Rev 1 May 2006 4 3 UVT_[7:0] 0 0 2 1 0 0 0 0 Description Upper variance interrupt threshold. The VAR_IRQ flag will set after a bulk finger detect event if at least one of the variances from the three regions (left, center, or right) exceeds the UVT. Atrua Technologies Confidential and Proprietary Page 36 of 67 ATW300 Family Programming Guide Upper Threshold-crossing Count Interrupt Threshold (UCT_REG) Access Conditions Access Type Bit Function Reset Value Bit 7 6:0 A[0] = 1; [IDX_REG] = 0x1B Read/Write 7 RESE RVED 0 Function RESERVED UCT_[6:0] 855-0004-001 Rev 1 May 2006 6 5 4 3 UCT_[6:0] 2 1 0 0 0 0 0 0 0 0 Description Reserved. Upper threshold-crossing interrupt threshold. The TC_IRQ flag will set after a bulk finger detect event if at least one of the threshold-crossing counts from the three regions (left, center, or right) exceeds the UCT. Atrua Technologies Confidential and Proprietary Page 37 of 67 ATW300 Family Programming Guide Timestamp, Buffer 0, LSB Register (F0T0_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A0 = 1; [IDX_REG] = 0x20 Read Only 7 6 5 0 0 0 Function F0T0_[7:0] 855-0004-001 Rev 1 May 2006 4 3 F0T0_[7:0] 0 0 2 1 0 0 0 0 Description LSB of timestamp for frame 0 Atrua Technologies Confidential and Proprietary Page 38 of 67 ATW300 Family Programming Guide Timestamp, Buffer 0, MSB Register (F0T1_REG) Access Conditions Access Type Bit Function Reset Value Bit 15:8 A0 = 1; [IDX_REG] = 0x21 Read Only 7 6 5 0 0 0 Function F0T1_[15:8] 855-0004-001 Rev 1 May 2006 4 3 F0T1_[15:8] 0 0 2 1 0 0 0 0 Description MSB of timestamp for frame 0 Atrua Technologies Confidential and Proprietary Page 39 of 67 ATW300 Family Programming Guide Timestamp, Buffer 1, LSB Register (F1T0_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A0 = 1; [IDX_REG] = 0x22 Read Only 7 6 5 0 0 0 Function F1T0_[7:0] 855-0004-001 Rev 1 May 2006 4 3 F1T0_[7:0] 0 0 2 1 0 0 0 0 Description LSB of timestamp for frame 1 Atrua Technologies Confidential and Proprietary Page 40 of 67 ATW300 Family Programming Guide Timestamp, Buffer 1, MSB Register (F1T1_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A0 = 1; [IDX_REG] = 0x23 Read Only 7 6 5 0 0 0 Function F1T1_[15:8] 855-0004-001 Rev 1 May 2006 4 3 F1T1_[15:8] 0 0 2 1 0 0 0 0 Description MSB of timestamp for frame 1 Atrua Technologies Confidential and Proprietary Page 41 of 67 ATW300 Family Programming Guide Mean, right region, buffer 0 (MRF0_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A[0] = 1; [IDX_REG] = 0x24 Read Only 7 6 5 0 0 0 Function MRF0_[7:0] 4 3 MRF0_[7:0] 0 0 2 1 0 0 0 0 Description Mean of right region of frame 0, in 4.4 format. The mean is undefined during the Measure operation, but is valid immediately after the Measure operation completes. Note: For mean and variance, 60 of the 124 columns are used for the computation. The 60 columns include every even-numbered column except columns 0 and 122. The left region spans columns 2 through 60. The center region spans columns 32 through 90. The right region spans columns 62 through 120. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 42 of 67 ATW300 Family Programming Guide Mean, center region, buffer 0 (MCF0_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A[0] = 1; [IDX_REG] = 0x25 Read Only 7 6 5 0 0 0 Function MCF0_[7:0] 855-0004-001 Rev 1 May 2006 4 3 MCF0_[7:0] 0 0 2 1 0 0 0 0 Description Mean of center region of frame 0, in 4.4 format. The mean is undefined during the Measure operation, but is valid immediately after the Measure operation completes. Atrua Technologies Confidential and Proprietary Page 43 of 67 ATW300 Family Programming Guide Mean, left region, buffer 0 (MRF0_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A[0] = 1; [IDX_REG] = 0x26 Read Only 7 6 5 0 0 0 Function MLF0_[7:0] 855-0004-001 Rev 1 May 2006 4 3 MLF0_[7:0] 0 0 2 1 0 0 0 0 Description Mean of left region of frame 0, in 4.4 format. The mean is undefined during the Measure operation, but is valid immediately after the Measure operation completes. Atrua Technologies Confidential and Proprietary Page 44 of 67 ATW300 Family Programming Guide Mean, right region, buffer 1 (MLF1_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A[0] = 1; [IDX_REG] = 0x27 Read Only 7 6 5 0 0 0 Function MRF1_[7:0] 855-0004-001 Rev 1 May 2006 4 3 MRF1_[7:0] 0 0 2 1 0 0 0 0 Description Mean of right region of frame 1, in 4.4 format. The mean is undefined during the Measure operation, but is valid immediately after the Measure operation completes. Atrua Technologies Confidential and Proprietary Page 45 of 67 ATW300 Family Programming Guide Mean, center region, buffer 1 (MCF1_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A[0] = 1; [IDX_REG] = 0x28 Read Only 7 6 5 0 0 0 Function MCF1_[7:0] 855-0004-001 Rev 1 May 2006 4 3 MCF1_[7:0] 0 0 2 1 0 0 0 0 Description Mean of center region of frame 1, in 4.4 format. The mean is undefined during the Measure operation, but is valid immediately after the Measure operation completes. Atrua Technologies Confidential and Proprietary Page 46 of 67 ATW300 Family Programming Guide Mean, left region, buffer 1 (MLF1_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A[0] = 1; [IDX_REG] = 0x29 Read Only 7 6 5 0 0 0 Function MLF1_[7:0] 855-0004-001 Rev 1 May 2006 4 3 MLF1_[7:0] 0 0 2 1 0 0 0 0 Description Mean of left region of frame 1, in 4.4 format. The mean is undefined during the Measure operation, but is valid immediately after the Measure operation completes. Atrua Technologies Confidential and Proprietary Page 47 of 67 ATW300 Family Programming Guide Mean, right region, least significant nibble, buffer 0 (MRXF0_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:4 3:0 A[0] = 1; [IDX_REG] = 0x2A Read Only 7 0 Function RESERVED MRXF0_[3:0] 855-0004-001 Rev 1 May 2006 6 5 RESERVED 0 0 4 3 0 1 2 1 MRXF0_[3:0] 0 0 0 0 Description Reserved. Least significant bits of mean of right region of frame 0. Atrua Technologies Confidential and Proprietary Page 48 of 67 ATW300 Family Programming Guide Mean, center region, least significant nibble, buffer 0 (MCXF0_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:4 3:0 A[0] = 1; [IDX_REG] = 0x2B Read Only 7 0 Function RESERVED MCXF0_[3:0] 855-0004-001 Rev 1 May 2006 6 5 RESERVED 0 0 4 3 0 1 2 1 MCXF0_[3:0] 0 0 0 0 Description Reserved. Least significant bits of mean of center region of frame 0. Atrua Technologies Confidential and Proprietary Page 49 of 67 ATW300 Family Programming Guide Mean, left region, least significant nibble, buffer 0 (MLXF0_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:4 3:0 A[0] = 1; [IDX_REG] = 0x2C Read Only 7 0 Function RESERVED MLXF0_[3:0] 855-0004-001 Rev 1 May 2006 6 5 RESERVED 0 0 4 3 0 1 2 1 MLXF0_[3:0] 0 0 0 0 Description Reserved. Least significant bits of mean of left region of frame 0. Atrua Technologies Confidential and Proprietary Page 50 of 67 ATW300 Family Programming Guide Mean, right region, least significant nibble, buffer 1 (MRXF1_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:4 3:0 A[0] = 1; [IDX_REG] = 0x2D Read Only 7 0 Function RESERVED MRXF1_[3:0] 855-0004-001 Rev 1 May 2006 6 5 RESERVED 0 0 4 3 0 1 2 1 MRXF1_[3:0] 0 0 0 0 Description Reserved. Least significant bits of mean of right region of frame 1. Atrua Technologies Confidential and Proprietary Page 51 of 67 ATW300 Family Programming Guide Mean, center region, least significant nibble, buffer 1 (MCXF1_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:4 3:0 A[0] = 1; [IDX_REG] = 0x2E Read Only 7 0 Function RESERVED MCXF1_[3:0] 855-0004-001 Rev 1 May 2006 6 5 RESERVED 0 0 4 3 0 1 2 1 MCXF1_[3:0] 0 0 0 0 Description Reserved. Least significant bits of mean of center region of frame 1. Atrua Technologies Confidential and Proprietary Page 52 of 67 ATW300 Family Programming Guide Mean, left region, least significant nibble, buffer 1 (MLXF1_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:4 3:0 A[0] = 1; [IDX_REG] = 0x2F Read Only 7 0 Function RESERVED MLXF1_[3:0] 855-0004-001 Rev 1 May 2006 6 5 RESERVED 0 0 4 3 0 1 2 1 MLXF1_[3:0] 0 0 0 0 Description Reserved. Least significant bits of mean of right region of frame 1. Atrua Technologies Confidential and Proprietary Page 53 of 67 ATW300 Family Programming Guide Variance, right region (VRT_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A[0] = 1; [IDX_REG] = 0x30 Read Only 7 6 5 0 0 0 Function VRT_[7:0] 855-0004-001 Rev 1 May 2006 4 3 VRT_[7:0] 0 0 2 1 0 0 0 0 Description Variance of right region of frame most recently output to host, in 4.4 format. The variance is undefined while reading a frame. The variance is valid after reading the last byte of the current frame and before reading the first byte of the next frame. Atrua Technologies Confidential and Proprietary Page 54 of 67 ATW300 Family Programming Guide Variance, center region (VCN_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A[0] = 1; [IDX_REG] = 0x31 Read Only 7 6 5 0 0 0 Function VCN_[7:0] 855-0004-001 Rev 1 May 2006 4 3 VCN_[7:0] 0 0 2 1 0 0 0 0 Description Variance of center region of frame most recently output to host, in 4.4 format. The variance is undefined while reading a frame. The variance is valid after reading the last byte of the current frame and before reading the first byte of the next frame. Atrua Technologies Confidential and Proprietary Page 55 of 67 ATW300 Family Programming Guide Variance, left region (VLF_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A[0] = 1; [IDX_REG] = 0x32 Read Only 7 6 5 0 0 0 Function VLF_[7:0] 855-0004-001 Rev 1 May 2006 4 3 VLF_[7:0] 0 0 2 1 0 0 0 0 Description Variance of left region of frame most recently output to host, in 4.4 format. The variance is undefined while reading a frame. The variance is valid after reading the last byte of the current frame and before reading the first byte of the next frame. Atrua Technologies Confidential and Proprietary Page 56 of 67 ATW300 Family Programming Guide Threshold crossing count, right region (TRT_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A[0] = 1; [IDX_REG] = 0x33 Read Only 7 6 5 0 0 0 Function TRT_[7:0] 4 3 TRT_[7:0] 0 0 2 1 0 0 0 0 Description Threshold crossing count of right region of frame most recently output to host. The threshold-crossing count is undefined while reading a frame. The threshold-crossing is valid after reading the last byte of the current frame and before reading the first byte of the next frame. Note: The right region spans from column 62 through column 123, inclusive. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 57 of 67 ATW300 Family Programming Guide Threshold crossing count, center region (TCN_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A[0] = 1; [IDX_REG] = 0x34 Read Only 7 6 5 0 0 0 Function TCN_[7:0] 4 3 TCN_[7:0] 0 0 2 1 0 0 0 0 Description Threshold crossing count of center region of frame most recently output to host. The threshold-crossing count is undefined while reading a frame. The threshold-crossing is valid after reading the last byte of the current frame and before reading the first byte of the next frame. Note: The center region spans columns 32 through 93, inclusive. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 58 of 67 ATW300 Family Programming Guide Threshold crossing count, left region (TLF_REG) Access Conditions Access Type Bit Function Reset Value Bit 7:0 A[0] = 1; [IDX_REG] = 0x35 Read Only 7 6 5 0 0 0 Function TLF_[7:0] 4 3 TLF_[7:0] 0 0 2 1 0 0 0 0 Description Threshold crossing count of left region of frame most recently output to host. The threshold-crossing count is undefined while reading a frame. The threshold-crossing is valid after reading the last byte of the current frame and before reading the first byte of the next frame. Note: The left region spans from column 0 through 61, inclusive. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 59 of 67 ATW300 Family Programming Guide AGC, Buffer 0 (GSKF0_REG) Access Conditions Access Type Bit Function Reset Value Bit 7 6:0 A[0] = 1; [IDX_REG] = 0x36 Read/Write 7 RESE RVED 0 Function RESERVED AGCF0_[6:0] 6 5 4 0 0 0 3 2 AGCF0_[6:0] 0 0 1 0 0 0 Description Reserved. AGCF0_[6:0] is the saved FindGray value returned in the trailer for frame buffer 0. AGCF0_[6:0] is the FindGray value computed for frame buffer 0, but not necessarily the FindGray value used in the Measure operation for frame buffer 0. Note: This register can be read in lieu of reading the FindGray value in the trailer. The value in GSKF0_REG is the output of the FindGray circuit at the time of the Measure operation for buffer 0. GSKF0_REG isn’t intended to reflect the current state of the FindGray circuit. Instead GSKF0_REG saves the FindGray state for the Measure operation for buffer 0. The value in GSKF0_REG won’t change until the next Measure operation for buffer 0, regardless of how many FindGray operations are executed. To get the current state of the FindGray circuit, read the GSKC_REG instead. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 60 of 67 ATW300 Family Programming Guide AGC, Buffer 1 (GSKF1_REG) Access Conditions Access Type Bit Function Reset Value Bit 7 6:0 A[0] = 1; [IDX_REG] = 0x37 Read/Write 7 RESE RVED 0 Function RESERVED GSKF1_[6:0] 6 5 4 0 0 0 3 2 GSKF1_[6:0] 0 0 1 0 0 0 Description Reserved. GSKF1_[6:0] is the saved FindGray value returned in the trailer for frame buffer 1. GSKF1_[6:0] is the FindGray value computed for frame buffer 1, but not necessarily the FindGray value used in the Measure operation for frame buffer 1. Note: This register can be read in lieu of reading the FindGray value in the trailer. The value in GSKF1_REG is the output of the FindGray circuit at the time of the Measure operation for buffer 1. GSKF1_REG isn’t intended to reflect the current state of the FindGray circuit. Instead GSKF1_REG saves the FindGray state for the Measure operation for buffer 1. The value in GSKF1_REG won’t change until the next Measure operation for buffer 1, regardless of how many FindGray operations are executed. To get the current state of the FindGray circuit, read the GSKC_REG instead. 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 61 of 67 ATW300 Family Programming Guide AGC Current (GSKC_REG) Access Conditions Access Type Bit Function Reset Value Bit 7 6:0 A[0] = 1; [IDX_REG] = 0x38 Read Only 7 RESE RVED 0 Function RESERVED GSKC_[6:0] 855-0004-001 Rev 1 May 2006 6 5 4 3 GSKC_[6:0] 2 1 0 0 0 0 0 1 1 1 Description Reserved. Find Gray Result. GSKC_[6:0] is the current FindGray (recalibration) result. Atrua Technologies Confidential and Proprietary Page 62 of 67 ATW300 Family Programming Guide ATW300 Measurement Data A measurement image (‘frame’) from the Atrua sensor is either 496 bytes (3,968 bits) or 512 bytes (4,096 bits) long. The frame contains 4-bit gray values for each of the 992 sensing elements (8 rows, each with 124 columns), plus, if BUFC_REG_[7] (TR_EN) is set, a 14-byte trailer, including a 2-byte timestamp. If TR_EN is clear, then no trailer is sent. Table 4. ATW300 Measurement Data Structure Bit 4 3 2 1 0 0 O O O O E E E E 1 O O O O E E E 2 O O O O E E E Byte 7 6 5 Description Row 0, columns 0 and 1 Row 0, columns 2 E and 3 Row 0, columns 4 E and 5 … 61 O O O O E E E 62 O O O O E E E Row 0, columns 122 and 123 Row 1, columns 0 E and 1 E Format E = 4-bit gray value, even pixel. O = 4-bit gray value, odd pixel. … Row 7, columns 122 and 123 LSB of 16-bit timestamp MSB of 16-bit timestamp Estimated mean of right region of frame Estimated mean of center region of Estimated mean of left region of frame Remainder of estimated mean of right region of frame 495 O O O O E E E E 496 T T T T T T T T 497 T T T T T T T T 498 I I I I F F F F 499 I I I I F F F F 500 I I I I F F F F 501 X X X X F F F F 502 X X X X F F F 503 X X X X F F F F Remainder of estimated mean of center region of F Remainder of estimated mean of left region of frame 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary 16-bit integer timestamp in 16.0 format, 100 microsecond resolution. 8-bit estimated means in 4.4 format; I = integer part, F = fractional part Least significant 4 bits of estimated means; X = not used, F = fractional part Page 63 of 67 ATW300 Family Programming Guide 504 7 I 6 I 5 I Bit 4 3 I F 505 I I I I F F F 506 I I I I F F F 507 Z Z Z Z Z Z Z 508 Z Z Z Z Z Z Z 509 Z Z Z Z Z Z Z 510 U U U U L L L 511 X I I I Byte I I I 855-0004-001 Rev 1 May 2006 2 F 1 F Description 0 F Estimated variance of right region of frame F Estimated variance of center region of frame F Estimated variance of left region of frame Z Zero-crossing count for right region of frame Z Zero-crossing count for center region of frame Z Zero-crossing count for left region of frame L Threshold High and Low (THR_REG contents) I AGC result of the frame (GSKFx_REG contents) Atrua Technologies Confidential and Proprietary Format 8-bit estimated variances in 4.4 format; I = integer part, F = fractional part 8-bit zero crossing count in 8.0 format; Z = integer part Page 64 of 67 ATW300 Family Programming Guide Sample Operation Flowcharts Figures 12 and 13 are sample flowcharts describing the operations required to perform an automatic gain control (AGC) operation and to digitize a single frame of data for the Atrua’s sensor. Figure 14 is a flowchart describing a GetImage() function implemented in a driver for acquiring a frame from the sensor. This procedure includes the AGC and Digitize Frame operations in slightly modified form. The data acquired in this manner would next be passed onto the fingerprint reconstruction software running on the host processor or other device to construct the full fingerprint from the various frames of acquired data, and to extract the minutiae points necessary for the fingerprint authentication process. The read and write operations normally require two cycles. The first cycle writes the Index register with the address of the target register. The second cycle performs the actual read or write transaction with the target register. The Index register is static, and will hold its contents until power is removed or the device is reset. When reading (or writing) the same register twice or more, the Index register need only be written once. For example, when reading a frame from the Data buffer, write 0x01 into IDX_REG once, and then read DAT_REG 496 times or 512 times, depending on the status of TR_EN (trailer enabled). Automatic Gain Control Operation This is the procedure for performing an automatic gain control operation. Write CMD with 0x02 Write CMD with 0x22 This starts the automatic gain control operation. Read AUX Yes Is the Busy flag set? The Busy flag will set during the automatic gain control operation. Wait until the Busy flag clears. No Finished Figure 12. Automatic Gain Control Operation Flowchart 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 65 of 67 ATW300 Family Programming Guide Figure 13. Measurement Operation Flowchart 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 66 of 67 ATW300 Family Programming Guide Start GetImage Is this the first frame? Yes GetImage retrieves one frame of data. Read STA In the example source code, the presence of the ATW_FLAG_STARTIMG flag indicates that this is the first frame and an A/D conversion needs to be started because there isn't a frame of data already waiting to be read. Are all two status flags set? Check the status register. If the two low-order bits are all set, then another A/D conversion is not necessary. No Write CMD with 0x82 Read AUX No Write CMD with 0x02 Write CMD with 0x42 Read STA Is the Busy flag set? This starts the A/D conversion operation. Data is available for reading when any of the two loworder bits of the STA register is set. No Time to adjust the gain? No If the Busy flag is set, then an A/D conversion operation is already in progress; therefore, it is not necessary to start either a gain adjustment operation or an A/D conversion operation. The GetImage function of the example source code has a variable that specifies when the gain should be re-adjusted. Data Available? Yes Yes Read DAT No One frame of data is 496 bytes if TR_EN is clear, or 512 bytes if TR_EN is set. The DAT register must be read 496 or 512 (respectively) times to retrieve one image frame. Write CMD with 0x02 Yes Write CMD with 0x22 496 or 512 Bytes Read? This starts the automatic gain control operation. Yes Read AUX No Yes Yes Is the Busy flag set? The Busy flag will set during the automatic gain control operation. Wait until the Busy flag clears. No Write CMD with 0x02 Write CMD with 0x42 Unpack Data For efficiency, start another A/D conversion operation so that the sensor can be doing an A/D conversion while the host is processing the image data. Data is packed two nibbles per byte. The upacking operation separates the two nibbles into two bytes. GetImage Finished Figure 14. Get Image Operation Flowchart 855-0004-001 Rev 1 May 2006 Atrua Technologies Confidential and Proprietary Page 67 of 67