Data Sheet

MXO45LV & MXO45HSLV
HCMOS/TTL Clock Oscillator
FEATURES
•
•
•
•
•
•
•
•
•
•
Standard 14 Pin or 8 Pin DIP Packages
HCMOS/TTL Compatible Output
Fundamental and 3rd Overtone Crystal Designs
Frequency Range 1 – 200 MHz
Frequency Stability ±50 ppm Standard
Operating Voltage +3.3Vdc
Operating Temperature to -40°C to +85°C
Output Enable Standard
Plastic Tray Packaging
RoHS/Green Compliant (6/6)
APPLICATIONS
Applications for MXO45LV and MXO45HSLV include microprocessors/DSP/FPGA,
networking equipment, broadband access, storage area networks, computers and peripherals,
test and measurement, Ethernet/Gigabit Ethernet.
ORDERING INFORMATION
MXO
-
-
M
SUPPLY VOLTAGE
FREQUENCY IN MHz
45LV = 14 Pin DIP/STD Output
45TLV = 14 Pin DIP/Tristate Output
45HSLV = 8 Pin DIP/STD Output
45HSTLV = 8 Pin DIP/Tristate Output
M - indicates MHz and decimal point.
OPERATING TEMPERATURE RANGE
C = -20°C to +70°C [standard]
I = -40°C to +85°C 1
FREQUENCY STABILITY
6
5
3
2
=
=
=
=
±
±
±
±
2
20 ppm 1
25 ppm
50 ppm [standard]
100 ppm
1] 6I Stability/Temperature combination is not available. Check availability for 6C combination.
2] Frequency is recorded with only leading significant digits before the ‘M’ and 4 - 6 significant digits after the ‘M’ (including zeros).
[Ex. XMXXXXXX (3M579545), XXMXXXXX (14M31818), XXXMXXXX (125M0000)]
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
PACKAGING INFORMATION [reference]
Product is packaged in plastic trays. Typical packaging format is as follows:
ƒ
50 pcs./Plastic Tray.
Tray size is approximately 180 x 136 x 18mm [LxWxH].
ƒ
2 Trays per Anti-Static Bag [100 pcs.] or 10 Trays per Anti-Static Bag [500 pcs.].
Bag height for 10 Trays is approximately 175mm.
ƒ
1 anti-static bag per cardboard carton.
ƒ
Master-pack multiple cardboard cartons in a larger carton.
8 cardboard cartons [10 trays per carton] is approximately 460 x 380 x 400mm [LxWxH].
Document No. 008-0278-0
Page 1- 3
www.ctscorp.com
Rev. F
MXO45LV & MXO45HSLV
Metal DIP Low Cost
HCMOS/TTL Clock Oscillator
ELECTRICAL CHARACTERISTICS
PARAMETER
Maximum Supply Voltage
Storage Temperature
Frequency Range
Frequency Stability
Aging
Operating Temperature
Commercial
Industrial
Supply Voltage
Supply Current
SYMBOL
VCC
CONDITIONS
-
MIN
-0.5
TYP
-
MAX
+7.0
TSTG
-
-40
-
+100
°C
fO
-
1.0
-
200
MHz
Δf/fO
Δf
See Note 1 and Ordering Information
-
-
20,25,50 or 100
± ppm
First year
-
3
5
± ppm
°C
3.3
+70
+85
3.63
-
7
15
20
30
45
17
25
35
45
65
-
-
50
30
15
10
90%VCC
2.4
-
-
-
-
10%VCC
0.4
-
-
-8
-
-
8
45
-
55
-
8
5
2.5
-
10
8
5
2
10
ms
V
TA
VCC
UNIT
V
-
-20
-40
2.97
±10%
Frequency Range
+25
V
Tested load condition noted for typical values.
ICC
1.0MHz to 20MHz
20.001MHz to 40MHz
40.001MHz to 80MHz
80.001MHz to 125MHz
125.001MHz to 200MHz
CL=15pF
CL=15pF
CL=15pF
CL=15pF
CL=15pF
mA
Output Load
ELECTRICAL PARAMETERS
CMOS
CL
TTL
Output Voltage Levels
Logic '1' Level
Logic '0' Level
VOH
VOL
1.0MHz to 50MHz
50.001MHz to 80MHz
80.001MHz to 200MHz
1.0MHz to 200MHz
CMOS Load
10 TTL LOAD
CMOS
TTL Load
pF
TTL
V
Output Current
Logic '1' Level
IOH
VOH = 2.2V
Logic '0' Level
IOL
VOL = 0.4V
Output Duty Cycle
Rise and Fall Time
SYM
VCC = 3.0V
@ 50% Level
@ 10% - 90% Levels
mA
%
Tested load condition noted for typical values.
TS
1.0MHz to 20MHz
20.001MHz to 80MHz
80.001MHz to 125MHz
125.001MHz to 200MHz
Application of VCC
TR, TF
Start Up Time
VCC = 3.0V
CL=50pF
CL=30pF
CL=15pF
CL=15pF
ns
Enable Function
Enable Input Voltage
VIH
Pin 1 Logic '1', Output Enabled
2.0
-
-
Disable Input Voltage
VIL
Pin 1 Logic '0', Output Disabled
-
-
0.8
Enable Time
TPLZ
Pin 1 Logic '1'
-
-
200
ns
Standby Current
IST
Pin 1 Logic '0', Output Disabled
-
-
10
µA
Period Jitter, Pk-Pk
-
-
-
-
50
Period Jitter, RMS
-
-
-
-
Bandwidth 12kHz - 20MHz
Phase Jitter, RMS
Notes:
1. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.
Document No. 008-0278-0
Page 2 - 3
5
ps
1
Rev. F
MXO45LV & MXO45HSLV
Metal DIP Low Cost
HCMOS/TTL Clock Oscillator
ELECTRICAL CHARACTERISTICS
LVCMOS OUTPUT WAVEFORM
TEST CIRCUIT, CMOS LOAD
ENABLE TRUTH TABLE
D.U.T. PIN ASSIGNMENTS
PIN
SYMBOL
PIN 1
Logic ‘1’
Open
Logic ‘0’
PIN 5 or PIN 8
Output
Output
High Imp.
1
DESCRIPTION
EOH
Enable Input or No Connect
7 or 4
GND
Circuit & Package Ground
8 or 5
Output
14 or 8
VCC
RF Output
Supply Voltage
MECHANICAL SPECIFICATIONS
MARKING INFORMATION
1. Model Name:
DIP-14 – MXO45LV or MXO45TLV.
DIP-8 – MXO45HSLV or MXO45HSTLV.
2. XXXMXXXXXX – Frequency is marked with only
leading significant digits before the ‘M’ and
4 – 6 digits after the ‘M’ (including zeros).
PACKAGE DRAWING
DIP-14
Ex. XMXXXXXX [3M579545]
XXMXXXXX [14M31818]
XXXMXXXX [125M0000]
3. ST – Frequency stability/temperature code.
[Refer to Ordering Information.]
4. YYWW – Date code, YY – year, WW – week.
5. ** – Manufacturing Site Code.
MXO45LV
XXXMXXXXXX
CTS ST
● YYWW **
NOTES
1. Lead finish [e1], SnAgCu.
2. Reflow conditions per JEDEC J-STD-020,
260°C maximum.
3. Moisture Sensitivity Level 1, per JEDEC J-STD020.
DIP-8
MXO45HSLV
XXXMXXXXXX
CTS ST
● YYWW **
Document No. 008-0278-0
Page 3 - 3
Rev. F
Similar pages