Model 653 Very Low Jitter LVPECL or LVDS Clock Features Ceramic Surface Mount Package Very Low Phase Jitter Performance, 500fs Maximum Fundamental or 3rd Overtone Crystal Design Frequency Range 10 – 320MHz * +2.5V or +3.3V Operation Output Enable Standard Tape and Reel Packaging, EIA‐418 Part Dimensions: 5.0 × 3.2 × 1.2mm • 62.00mg Applications SerDes Storage Area Networking Broadband Access SONET/SDH/DWDM PON Ethernet/GbE/SyncE Fiber Channel Test and Measurement Standard Frequencies ‐ 25.00MHz ‐ 50.00MHz ‐ 100.00MHz ‐ 125.00MHz ‐ 155.52MHz ‐ 156.25MHz ‐ 161.1328MHz ‐ 187.50MHz ‐ 200.00MHz ‐ 212.50MHz ‐ 250.00MHz ‐ 312.50MHz * Check with factory for availability. Description CTS Model 653 is a low cost, high performance clock oscillator supporting differential LVPECL or LVDS outputs. Employing the latest IC technology, M653 has excellent stability and very low jitter/phase noise performance. Ordering Information Model Output Type 653 P Code P L E V Frequency Stability 3 Frequency Code [MHz] X X X or X X XX Output LVPECL ‐ Pin 1 Enable LVDS ‐ Pin 1 Enable LVPECL ‐ Pin 2 Enable LVDS ‐ Pin 2 Enable Stability Code 6 5 3 2 Code Temperature Range I Supply Voltage 3 Code 2 3 2 ±20ppm ±25ppm ±50ppm ±100ppm Code Temp. Range ‐10°C to +60°C A ‐20°C to +70°C C ‐40°C to +85°C I Frequency 1 Product Frequency Code Packaging T Voltage +2.5Vdc +3.3Vdc Packing Code 1k pcs./reel T Notes: 1] Refer to document 016‐1454‐0, Frequency Code Tables. 3‐digits for frequencies <100MHz, 4‐digits for frequencies 100MHz or greater. 2] Consult factory for availability of 6I Stability/Temperature combination. Not all performance combinations and frequencies may be available. Contact your local CTS Representative or CTS Customer Service for availability. DOC# 008‐0367‐0 Rev. B Page 1 of 8 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 653 Very Low Jitter LVPECL or LVDS Clock Electrical Specifications Operating Conditions P ARAMETER SYMBO L CO NDITIO NS MIN TYP MAX UNIT Maximum Supply Voltage VCC ‐ ‐0.5 ‐ 5.0 V Supply Voltage VCC ±5% 2.375 2.5 2.625 3.135 3.3 3.465 ICC Maximum Load ‐ 55 88 ‐ 45 66 V Supply Curren t LVP ECL LVDS O perating Temperature Storage Temperature ‐20 +70 +25 mA TA ‐ TSTG ‐ ‐40 ‐ +125 °C SYMBO L CO NDITIO NS MIN TYP MAX UNIT fO ‐ ‐40 +85 °C Frequency Stability P ARAMETER Freq uenc y Range LVP ECL 10 ‐ 320 Freq uenc y Stability [Note 1] Agin g MHz 10 ‐ 320 LVDS 20, 25, 50 or 100 Δf/fO ‐ Δf/f25 First Year @ +25°C, nominal VCC ±ppm ‐3 ‐ 3 ppm MIN TYP MAX UNIT Ohms 1.] Inc lusive of initial toleranc e at time of shipment, c hanges in supply voltage, load, temperature and 1st year aging. Output Parameters P ARAMETER SYMBO L CO NDITIO NS LVPECL O utput Ty pe ‐ ‐ O utput Load RL Terminated to VCC ‐ 2.0V VOH O utput Voltage Levels VOL VOH VOL PECL Load, ‐20°C to +70°C PECL Load, ‐40°C to +85°C ‐ ‐ 50 ‐ VCC ‐ 1.025 ‐ VCC ‐ 0.880 VCC ‐ 1.810 ‐ VCC ‐ 1.620 VCC ‐ 1.085 ‐ VCC ‐ 0.880 VCC ‐ 1.830 ‐ VCC ‐ 1.555 V V O utput Duty Cyc le SYM @ VCC ‐ 1.3V 45 ‐ 55 % Rise and Fall Time TR, TF @ 20%/80% Levels, RL = 50 Ohms ‐ 0.3 0.7 ns Ohms LVDS O utput Ty pe ‐ ‐ O utput Load RL Between Outputs O utput Voltage Levels VOH VOL LVDS Load ‐ ‐ 100 ‐ ‐ 1.43 1.60 0.90 1.10 ‐ V O utput Duty Cyc le SYM @ 1.25V 45 ‐ 55 % Differential O utput Voltage VOD RL = 100 Ohms 247 330 454 mV VOS LVDS Load 1.125 1.25 1.375 V TR, TF @ 20%/80% Levels, RL = 100 Ohms ‐ 0.4 0.7 ns O ffset Voltage Rise and Fall Time DOC# 008‐0367‐0 Rev. B Page 2 of 8 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 653 Very Low Jitter LVPECL or LVDS Clock Electrical Specifications Output Parameters P ARAMETER SYMBO L CO NDITIO NS MIN TYP MAX UNIT TS Application of VCC ‐ 2 5 ms Start Up Time Enable Func tion [Standby ] Enable Input Voltage VIH Pin 1 or 2 Logic '1', Output Enabled 0.7VCC ‐ ‐ V Disable Input Voltage VIL Pin 1 or 2 Logic '0', Output Disabled ‐ ‐ 0.3VCC V Disable Time TPLZ Pin 1 or 2 Logic '0', Output Disabled ‐ ‐ 200 ns Enable Time TPLZ Pin 1 or 2 Logic '1', Output Enabled ‐ ‐ 2 ms P hase Jitter, RMS tjrms Bandwidth 12 kHz ‐ 20 MHz ‐ 300 500 fs pjpk‐pk ‐ ‐ 2.6 ‐ ps pjrms ‐ ‐ 25 ‐ ps P eriod Jitter, pk‐pk P eriod Jitter, RMS Enable Truth Table Pin 1 or Pin 2 Pin 4 & Pin 5 Logic ‘1’ Open Logic ‘0’ Output Output High Imp. Test Circuit LVDS LVPECL Output Waveform LVPECL or LVDS DOC# 008‐0367‐0 Rev. B Page 3 of 8 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 653 Very Low Jitter LVPECL or LVDS Clock Electrical Specifications Performance Data Phase Noise [typical] 25MHz, LVPECL, VCC = 3.3V, TA = +25°C 100MHz, LVPECL, VCC = 3.3V, TA = +25°C DOC# 008‐0367‐0 Rev. B Page 4 of 8 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 653 Very Low Jitter LVPECL or LVDS Clock Electrical Specifications Performance Data Phase Noise [typical] 312.50MHz, LVPECL, VCC = 3.3V, TA = +25°C 155.52MHz, LVDS, VCC = 3.3V, TA = +25°C DOC# 008‐0367‐0 Rev. B Page 5 of 8 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 653 Very Low Jitter LVPECL or LVDS Clock Electrical Specifications Phase Noise Tabulated Typical, VCC = 3.3V, TA = +25°C P ARAMETER SYMBO L CO NDITIO NS TYP UNIT P ARAMETER LVP ECL @ 2 5 .0 0 MHz P h ase No ise Single Side Band ‐ P h ase Jitter, RMS P ARAMETER CO NDITIO NS TYP tjrms P hase Noise UNIT Single Side Band @ 10Hz ‐75.14 @ 10Hz ‐65.65 @ 100Hz ‐112.50 @ 100Hz ‐100.19 @ 1kHz ‐142.15 @ 10kHz ‐155.01 dBc/Hz ‐ @ 1kHz ‐131.02 @ 10kHz ‐145.49 ‐150.36 @ 100kHz ‐159.99 @ 100kHz @ 1MHz ‐161.83 @ 1MHz ‐151.37 @ 5MHz ‐161.61 @ 5MHz ‐152.11 Integration Bandwidth 12kHz ‐ 20MHz 179.24 SYMBO L CO NDITIO NS TYP fs P hase Jitter, RMS UNIT P ARAMETER LVP ECL @ 3 1 2 .2 0 MHz tjrms Integration Bandwidth 12kHz ‐ 20MHz 132.20 SYMBO L CO NDITIO NS TYP dBc/Hz fs UNIT LVDS @ 1 5 5 .5 2 MHz P h ase No ise Single Side Band ‐ P h ase Jitter, RMS SYMBO L LVP ECL @ 1 0 0 .0 0 MHz tjrms P hase Noise Single Side Band @ 10Hz ‐65.93 @ 10Hz ‐69.89 @ 100Hz ‐95.92 @ 100Hz ‐103.42 @ 1kHz ‐128.25 @ 10kHz ‐130.51 dBc/Hz ‐ @ 1kHz ‐130.99 @ 10kHz ‐142.69 @ 100kHz ‐142.82 @ 100kHz ‐144.46 @ 1MHz ‐142.84 @ 1MHz ‐144.49 @ 10MHz ‐143.80 @ 20MHz ‐145.13 Integration Bandwidth 12kHz ‐ 20MHz 208.52 DOC# 008‐0367‐0 Rev. B fs P hase Jitter, RMS tjrms Integration Bandwidth 12kHz ‐ 20MHz 383.70 dBc/Hz fs Page 6 of 8 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 653 Very Low Jitter LVPECL or LVDS Clock Mechanical Specifications Package Drawing Marking Information 1. ** ‐ Manufacturing Site Code. 2. D – Date Code. See Table I for codes. 3. O – Output Type; P or E = LVPECL, L or V = LVDS. 3. ST – Frequency Stability/Temperature Code. [Refer to Ordering Information] 4. V – Voltage Code; 3 = 3.3V, 2 = 2.5V. 5. xxxx – Frequency Code. 3‐digits, frequencies below 100MHz 4‐digits, frequencies 100MHz or greater [See document 016‐1454‐0, Frequency Code Tables.] CTS**D 653OSTV ● xxxx Recommended Pad Layout Notes 1. JEDEC termination code (e4). Barrier‐plating is nickel [Ni] with gold [Au] flash plate. 2. Reflow conditions per JEDEC J‐STD‐020; +260°C maximum, 20 seconds. 3. MSL = 1. Pin Assignments Pin Symbol Function 1 2 3 4 5 6 EOH or N.C. N.C. or EOH GND Output Output VCC Enable [std] or No Connect No Connect or Enable [opt] Circuit & Package Ground RF Output Complimentary RF Output Supply Voltage Table I ‐ Date Code MO NTH 2001 2002 2003 2004 YEAR 2005 2009 2006 2010 2007 2011 2008 2012 2013 2014 2015 2016 2017 2018 2019 2020 JAN FEB MAR AP R MAY JUN JUL AUG SEP O CT NO V DEC A N a n B P b p C Q c q D R d r E S e s F T f t G U g u H V h v J W j w K X k x L Y l y M Z m z DOC# 008‐0367‐0 Rev. B Page 7 of 8 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote. Model 653 Very Low Jitter LVPECL or LVDS Clock Packaging ‐ Tape and Reel Tape Drawing Reel Drawing Notes 1. Device quantity is 1k pieces per 180mm reel. 2. Complete CTS part number, frequency value and date code information must appear on reel and carton labels. DOC# 008‐0367‐0 Rev. B Page 8 of 8 ©2015 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.