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TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
TMS320C5535, 'C5534, 'C5533, 'C5532 Fixed-Point Digital Signal Processors
1 Device Overview
1.1
Features
1
• CORE:
– High-Performance, Low-Power, TMS320C55x
Fixed-Point Digital Signal Processor
• 20-, 10-ns Instruction Cycle Time
• 50-, 100-MHz Clock Rate
• One or Two Instructions Executed per Cycle
• Dual Multiply-and-Accumulate Units (Up to
200 Million Multiply-Accumulates per Second
[MMACS])
• Two Arithmetic and Logic Units (ALUs)
• Three Internal Data and Operand Read
Buses and Two Internal Data and Operand
Write Buses
• Software-Compatible with C55x Devices
• Industrial Temperature Devices Available
– 320KB of Zero-Wait State On-Chip RAM,
Composed of:
• 64KB of Dual-Access RAM (DARAM),
8 Blocks of 4K x 16-Bit
• 256KB of Single-Access RAM (SARAM), 32
Blocks of 4K x 16-Bit
– 128KB of Zero Wait-State On-Chip ROM
(4 Blocks of 16K x 16-Bit)
– Tightly Coupled FFT Hardware Accelerator
• PERIPHERAL:
– Direct Memory Access (DMA) Controller
• Four DMA with 4 Channels Each (16
Channels Total)
– Three 32-Bit General-Purpose (GP) Timers
• One Selectable as a Watchdog or GP
– Two Embedded Multimedia Card (eMMC) or
Secure Digital (SD) Interfaces
– Universal Asynchronous Receiver/Transmitter
(UART)
– Serial Port Interface (SPI) with Four Chip
Selects
– Master and Slave Inter-Integrated Circuit (I2C
Bus)
•
•
•
•
– Four Inter-IC Sound (I2S Bus) for Data
Transport
– Device USB Port with Integrated 2.0 HighSpeed PHY that Supports:
• USB 2.0 Full- and High-Speed Device
– LCD Bridge with Asynchronous Interface
– 10-Bit 4-Input Successive Approximation (SAR)
ADC
– IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible
– 32 General-Purpose I/O (GPIO) Pins
(Multiplexed with Other Device Functions)
• Configure Up to 20 GPIO Pins at the Same
Time
POWER:
– Four Core Isolated Power Supply Domains:
Analog, RTC, CPU and Peripherals, and USB
– Three I/O Isolated Power Supply Domains: RTC
I/O, USB PHY, and DVDDIO
– Three integrated LDOs (DSP_LDO, ANA_LDO,
and USB_LDO) to power the isolated domains:
DSP Core, Analog, and USB Core, respectively
– 1.05-V Core (50 MHz), 1.8-, 2.5-, 2.75-, or 3.3-V
I/Os
– 1.3-V Core (100 MHz), 1.8-, 2.5-, 2.75-, or 3.3-V
I/Os
CLOCK:
– Real-Time Clock (RTC) with Crystal Input,
Separate Clock Domain, and Separate Power
Supply
– Low-Power Software Programmable PhaseLocked Loop (PLL) Clock Generator
BOOTLOADER:
– On-Chip ROM Bootloader (RBL) to Boot From
SPI EEPROM, SPI Serial Flash or I2C EEPROM
eMMC, SD, SDHC, UART, and USB
PACKAGE:
– 144-Terminal Pb-Free Plastic BGA (Ball Grid
Array) (ZHH Suffix)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
1.2
•
•
•
Applications
Wireless Audio Devices (for example, Headsets,
Microphones, Speakerphones)
Echo Cancellation Headphones
Portable Medical Devices
1.3
www.ti.com
•
•
•
•
Voice Applications
Industrial Controls
Fingerprint Biometrics
Software-defined Radio
Description
These devices are members of TI's C5000™ fixed-point Digital Signal Processor (DSP) product family and
are designed for low-power applications.
The fixed-point DSP is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP
architecture achieves high performance and low power through increased parallelism and total focus on
power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses
dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data
reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each
with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention.
Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the
CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit
multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is
supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the
ability to optimize parallel activity and power consumption. These resources are managed in the Address
Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction
Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the
Program Unit (PU). The PU decodes the instructions, directs tasks to the AU and DU resources, and
manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution
of conditional instructions.
The general-purpose input and output functions, along with the 10-bit SAR ADC on the TMS320C5535,
provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces.
Serial media is supported through two secure digital (SD) peripherals, four Inter-IC Sound (I2S Bus)
modules, one serial port interface (SPI) with up to four chip selects, one I2C multimaster and slave
interface, and a universal asynchronous receiver/transmitter (UART) interface.
Additional peripherals include: a high-speed Universal Serial Bus (USB 2.0) device mode only (not
available on TMS320C5532), a real-time clock (RTC), three general-purpose timers with one configurable
as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.
In addition, the TMS320C5535 includes a tightly coupled FFT Hardware Accelerator. The tightly coupled
FFT Hardware Accelerator supports 8- to 1024-point (in power of 2) real and complex-valued FFTs.
Furthermore, the device includes the following three integrated LDOs to power different sections of the
device.
ANA_LDO (all devices) provides 1.3 V to the DSP PLL (VDDA_PLL), SAR, and power-management circuits
(VDDA_ANA).
2
Device Overview
Copyright © 2011–2014, Texas Instruments Incorporated
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Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532
TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
www.ti.com
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
DSP_LDO (TMS320C5535 and 'C5534) provides 1.3 V or 1.05 V to the DSP core (CVDD), selectable onthe-fly by software as long as operating frequency ranges are observed. For lowest power operation, the
programmer can shut down the internal DSP_LDO, cutting power to the DSP core (CVDD) while an
external supply provides power to the RTC (CVDDRTC and DVDDRTC). The RTC alarm interrupt or the
WAKEUP pin can re-enable the internal DSP_LDO and re-apply power to the DSP core. When DSP_LDO
comes out of reset, it is enabled to 1.3 V for the bootloader to operate. For the 50-MHz devices,
DSP_LDO must be programmed to 1.05 V to match the core voltage, CVDD, for proper operation after
reset.
USB_LDO (TMS320C5535, 'C5534, and 'C5533) provides 1.3 V to the USB core digital (USB_VDD1P3) and
PHY circuits (USB_VDDA1P3).
These devices are supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™
Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the
industry’s largest third-party network. Code Composer Studio IDE features code generation tools including
a C Compiler and Linker, RTDX™, XDS100, XDS510™, XDS560™ emulation device drivers, and
evaluation modules. The devices are also supported by the C55x DSP library which features more than 50
foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip
support libraries.
Table 1-1. Device Information
PACKAGE
BODY SIZE
TMS320C5535AZHH10
PART NUMBER
BGA MICROSTAR (144)
12.0 mm x 12.0 mm
TMS320C5535AZHHA10
BGA MICROSTAR (144)
12.0 mm x 12.0 mm
TMS320C5534AZHH10
BGA MICROSTAR (144)
12.0 mm x 12.0 mm
TMS320C5534AZHHA10
BGA MICROSTAR (144)
12.0 mm x 12.0 mm
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532
Device Overview
3
TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
1.4
www.ti.com
Functional Block Diagram
Figure 1-1 shows the functional block diagram of the devices.
DSP System
JTAG Interface
C55x DSP CPU
PLL/Clock
Generator
Power
Management
Input
Clocks
64KB DARAM
Pin
Multiplexing
128KB ROM
TMS320C5532
No SARAM
TMS320C5533
64KB SARAM
TMS320C5534
192KB SARAM
256KB SARAM
TMS320C5535
FFT Hardware
Accelerator
Switched Central Resource (SCR)
Peripherals
TMS320C5534
TMS320C5535
TMS320C5533
Interconnect
Program/Data
Storage
DMA
(x4)
eMMC/SD
SDHC
(x2)
Connectivity
I2C
SPI
UART
Display
10-Bit
SAR
ADC
LCD
Bridge
USB 2.0
PHY (HS)
[DEVICE]
Not Applicable
TMS320C5532
System
Serial Interfaces
I2S
(x4)
Application
Specific
RTC
GP Timer
(x2)
GP Timer
or WD
ANA_LDO
TMS320C5532
USB_LDO
TMS320C5533
DSP_LDO
TMS320C5535/C5534
Figure 1-1. Functional Block Diagram
4
Device Overview
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532
TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
www.ti.com
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Table of Contents
Device Overview ......................................... 1
5.5
Thermal Characteristics ............................. 54
1.1
Features .............................................. 1
5.6
Power-On Hours
1.2
Applications ........................................... 2
5.7
Timing and Switching Characteristics ............... 55
1.3
Description ............................................ 2
1.4
Functional Block Diagram ............................ 4
6.1
CPU ................................................ 118
2
3
Revision History ......................................... 6
Device Comparison ..................................... 7
6.2
Memory
6.3
Identification........................................ 144
6.4
Boot Modes ........................................ 145
4
Terminal Configuration and Functions ............ 13
1
3.1
5
6
Device Characteristics ................................ 7
7
54
Detailed Description.................................. 118
............................................
118
Device and Documentation Support .............. 149
4.1
Pin Diagram ......................................... 13
7.1
4.2
Signal Descriptions .................................. 17
7.2
4.3
Pin Multiplexing...................................... 46
7.3
Specifications ........................................... 49
7.4
5.1
Absolute Maximum Ratings ......................... 49
7.5
5.2
Recommended Operating Conditions ............... 50
7.6
5.3
Electrical Characteristics ............................ 51
7.7
5.4
Handling Ratings .................................... 54
8
....................................
....................................
Documentation Support ............................
Related Links ......................................
Community Resources.............................
Trademarks ........................................
Electrostatic Discharge Caution ...................
Glossary............................................
Device Support
149
150
151
151
151
151
151
Mechanical Packaging and Orderable
Information ............................................. 152
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532
Table of Contents
5
TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February, 2012) to Revision C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
6
Page
Added power-on information for USB_VBUS, USB_VDDA3P3, USB_VDDA1P3, and USB_VDD1P3 (LitBug
SDOCM00101620) .................................................................................................................. 28
Changed description for RSV6 to tie directly to Vss (LitBug SDOCM00101619) ........................................... 41
Changed values for ESD Stress Voltage. HBM changed to > 1000 V ....................................................... 54
Added note that CVDDRTC must always be powered by an external power source and cannot be powered by onchip LDOs (Bugzilla 2151) ......................................................................................................... 56
Changed WU_DOUT reset value to 1 (LitBug SDOCM00096670) ........................................................... 58
Added steps to Power-Supply Sequencing when USB subsystem is used (LitBug SDOCM00101620) ................ 64
Deleted unsupported EMIF pins (LitBug SDOCM00095615).................................................................. 68
Changed PLLOUT minimum to 60, maximum to 120 (LitBug SDOCM00097379) ......................................... 76
Changed SYSCLK maximum to 50 (Bugzilla 2145) ............................................................................ 76
Changed PLL_LOCKTIME to 4 ms maximum from 4 ms minimum (LitBug SDOCM00097381) ......................... 76
Changed minimum value for timing requirement for Wake-Up From IDLE (LitBug SDOCM00096476) ................. 82
Changed description of switching characteristic parameter for Wake-Up From IDLE (LitBug SDOCM00096480) .... 82
Changed timing diagram for Wake-Up From IDLE (LitBug SDOCM00096480) ............................................ 83
Added hardware requirement for RTC-Only Mode to verify the USB oscillator is disabled (LitBug
SDOCM00097368) ................................................................................................................ 104
Changed addresses for SD0 and SD1 in Peripheral I/O-Space Control Registers (LitBug SDOCM00101622) ...... 121
Added step to copy boot image sections to system memory (TIS Doc Feedback ID 5979) ............................. 146
Changed Bootloader Software Architecture (TIS Doc Feedback ID 5979) ................................................ 147
Revision History
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532
TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
www.ti.com
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
3 Device Comparison
Table 3-1 lists the important differences between the devices.
Table 3-1. Differences Between Devices
Device
Digital Core Supply
Voltage (CVDD)
1.05 V
On-chip
DARAM
On-chip
SARAM
USB
LCD
Interface
TightlyCoupled
FFT
SAR
ADC
64KB
256KB
√ (1)
√
√
√
ANA, DSP,
and USB
64KB
192KB
√
- (2)
-
-
ANA, DSP,
and USB
64KB
64KB
√
-
-
-
ANA and
USB
64KB
0KB
-
-
-
-
ANA only
1.3 V
LDO
Maximum CPU Speed
TMS320C5535A05
50 MHz
-
TMS320C5535A10
50 MHz
100 MHz
TMS320C5534A05
50 MHz
-
TMS320C5534A10
50 MHz
100 MHz
TMS320C5533A05
50 MHz
-
TMS320C5533A10
50 MHz
100 MHz
TMS320C5532A05
50 MHz
-
TMS320C5532A10
50 MHz
100 MHz
(1)
(2)
3.1
√ — Supported
- — Not supported
Device Characteristics
The following tables provide an overview of all the devices. The tables show significant features of each
device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type
with pin count. For more detailed information on the actual device part number and maximum device
operating frequency, see Section 7.1.2, Device Nomenclature.
Table 3-2. Characteristics of the C5535 Processor
HARDWARE FEATURES
TMS320C5535A05, C5535A10
Peripherals
Not all peripheral pins are
available at the same time DMA
(for more detail, see
Section 5).
Four DMA controllers each with four channels,
for a total of 16 channels
Timers
2 32-Bit General-Purpose (GP) Timers
1 Additional Timer Configurable as a 32-Bit GP Timer or a
Watchdog
UART
1 (with RTS and CTS flow control)
SPI
1 with 4 chip selects
2
I C
1 (Master or Slave)
I2S
4 (Two Channel, Full Duplex Communication)
USB 2.0 (Device only)
SD
LCD Bridge
ADC (Successive Approximation [SAR])
Real-Time Clock (RTC)
FFT Hardware Accelerator
General-Purpose Input/Output Port (GPIO)
High- and Full-Speed Device
2 SD, 256-byte read and write buffer, max 50-MHz clock and
signaling for DMA transfers
1 (8-bit or 16-bit asynchronous parallel bus)
1 (10-bit, 4 -input, 16-μs conversion time)
1 (Crystal Input, Separate Clock Domain and Power Supply)
1 (Supports 8 to 1024-point 16-bit real and complex FFT)
32 pins (with 1 Additional General-Purpose Output (XF) and 4
Special-Purpose Outputs for Use With SAR
Configure up to 20 pins simultaneously
Device Comparison
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Copyright © 2011–2014, Texas Instruments Incorporated
7
TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
www.ti.com
Table 3-2. Characteristics of the C5535 Processor (continued)
HARDWARE FEATURES
TMS320C5535A05, C5535A10
Size (Bytes)
On-Chip Memory
320 KB RAM, 128KB ROM
•
•
•
Organization
JTAG BSDL_ID
JTAGID Register
(Value is: 0x1B8F E02F)
CPU Frequency
MHz
Cycle Time
ns
Voltage
Core (V)
64KB On-Chip Dual-Access RAM (DARAM)
256KB On-Chip Single-Access RAM (SARAM)
128 KB On-Chip Single-Access ROM (SAROM)
see Figure 6-5
1.05-V Core
50 MHz
1.3-V Core
100 MHz (TMS320C5535A10 only)
1.05-V Core
20 ns
1.3-V Core
10 ns (TMS320C5535A10 only)
1.05 V – 50 MHz
1.3 V – 100 MHz (TMS320C5535A10 only)
I/O (V)
LDOs
Power Characterization
1.3 V or 1.05 V, 250 mA max current for DSP CPU (CVDD)
ANA_LDO
1.3 V, 4 mA max current to supply power to PLL (VDDA_PLL),
SAR, and power management circuits (VDDA_ANA)
USB_LDO
1.3 V, 25 mA max current to supply power to USB core digital
(USB_VDD1P3) and PHY circuits (USB_VDDA1P3)
Active @ Room Temp 25°C, 75% DMAC +
25% ADD
0.15 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Active @ Room Temp 25°C, 75% DMAC +
25% NOP
0.14 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM and SARAM in Active
Mode)
0.26 mW @ 1.05 V
0.44 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM in Retention and
SARAM in Active Mode)
0.23 mW @ 1.05 V
0.40 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM in Active Mode and
SARAM in Retention)
0.15 mW @ 1.05 V
0.28 mW @ 1.3 V
PLL Options
Software Programmable Multiplier
BGA Package
12 x 12 mm
Product Status (1)
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
(1)
8
1.8 V, 2.5 V, 2.75 V, 3.3 V
DSP_LDO
x4 to x4099 multiplier
144-Pin BGA (ZHH)
PD
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Device Comparison
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532
TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
www.ti.com
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Table 3-3. Characteristics of the C5534 Processor
HARDWARE FEATURES
TMS320C5534A05, C5534A10
Peripherals
Not all peripheral pins are
available at the same time DMA
(for more detail, see
Section 5).
Four DMA controllers each with four channels, for a total of 16
channels
Timers
2 32-Bit General-Purpose (GP) Timers
1 Additional Timer Configurable as a 32-Bit GP Timer or a
Watchdog
UART
1 (with RTS and CTS flow control)
SPI
1 with 4 chip selects
I2C
1 (Master or Slave)
I2S
4 (Two Channel, Full Duplex Communication)
USB 2.0 (Device only)
High- and Full-Speed Device
SD
2 SD, 256-byte read and write buffer, max 50-MHz clock and
signaling for DMA transfers
Real-Time Clock (RTC)
1 (Crystal Input, Separate Clock Domain and Power Supply)
General-Purpose Input/Output Port (GPIO)
Up to 20 pins (with 1 Additional General-Purpose Output (XF))
Size (Bytes)
On-Chip Memory
•
•
•
Organization
JTAG BSDL_ID
JTAGID Register
(Value is: 0x1B8F E02F)
CPU Frequency
MHz
Cycle Time
ns
Voltage
256KB RAM, 128KB ROM
see Figure 6-5
1.05-V Core
50 MHz
1.3-V Core
100 MHz (TMS320C5534A10 only)
1.05-V Core
20 ns
1.3-V Core
10 ns (TMS320C5534A10 only)
Core (V)
I/O (V)
LDOs
Power Characterization
64KB On-Chip Dual-Access RAM (DARAM)
192KB On-Chip Single-Access RAM (SARAM)
128KB On-Chip Single-Access ROM (SAROM)
1.05 V – 50 MHz
1.3 V – 100 MHz (TMS320C5534A10 only)
1.8 V, 2.5 V, 2.75 V, 3.3 V
DSP_LDO
1.3 V or 1.05 V, 250 mA max current for DSP CPU (CVDD)
ANA_LDO
1.3 V, 4 mA max current to supply power to PLL (VDDA_PLL)
and power management circuits (VDDA_ANA)
USB_LDO
1.3 V, 25 mA max current to supply power to USB core digital
(USB_VDD1P3) and PHY circuits (USB_VDDA1P3)
Active @ Room Temp 25°C, 75% DMAC +
25% ADD
0.15 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Active @ Room Temp 25°C, 75% DMAC +
25% NOP
0.14 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM and SARAM in Active
Mode)
0.26 mW @ 1.05 V
0.44 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM in Retention and
SARAM in Active Mode)
0.23 mW @ 1.05 V
0.40 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM in Active Mode and
SARAM in Retention)
0.15 mW @ 1.05 V
0.28 mW @ 1.3 V
PLL Options
Software Programmable Multiplier
BGA Package
12 x 12 mm
x4 to x4099 multiplier
144-Pin BGA (ZHH)
Device Comparison
Submit Documentation Feedback
Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532
Copyright © 2011–2014, Texas Instruments Incorporated
9
TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
www.ti.com
Table 3-3. Characteristics of the C5534 Processor (continued)
HARDWARE FEATURES
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
Product Status (1)
(1)
10
TMS320C5534A05, C5534A10
PD
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Device Comparison
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532
TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
www.ti.com
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Table 3-4. Characteristics of the C5533 Processor
HARDWARE FEATURES
TMS320C5533A05, C5533A10
Peripherals
Not all peripheral pins are
available at the same time DMA
(for more detail, see
Section 5).
Four DMA controllers each with four channels,
for a total of 16 channels
Timers
2 32-Bit General-Purpose (GP) Timers
1 Additional Timer Configurable as a 32-Bit GP Timer or a
Watchdog
UART
1 (with RTS and CTS flow control)
SPI
1 with 4 chip selects
I2C
1 (Master or Slave)
I2S
4 (Two Channel, Full Duplex Communication)
USB 2.0 (Device only)
High- and Full-Speed Device
SD
2 SD, 256-byte read and write buffer, max 50-MHz clock and
signaling for DMA transfers
Real-Time Clock (RTC)
1 (Crystal Input, Separate Clock Domain and Power Supply)
General-Purpose Input/Output Port (GPIO)
Up to 20 pins (with 1 Additional General-Purpose Output (XF))
Size (Bytes)
On-Chip Memory
•
•
•
Organization
JTAG BSDL_ID
JTAGID Register
(Value is: 0x1B8F E02F)
CPU Frequency
MHz
Cycle Time
ns
Voltage
128 KB RAM, 128KB ROM
see Figure 6-5
1.05-V Core
50 MHz
1.3-V Core
100 MHz (TMS320C5533A10 only)
1.05-V Core
20 ns
1.3-V Core
10 ns (TMS320C5533A10 only)
Core (V)
I/O (V)
LDOs
Power Characterization
1.05 V – 50 MHz
1.3 V – 100 MHz (TMS320C5533A10 only)
1.8 V, 2.5 V, 2.75 V, 3.3 V
ANA_LDO
1.3 V, 4 mA max current to supply power to PLL (VDDA_PLL)
and power management circuits (VDDA_ANA)
USB_LDO
1.3 V, 25 mA max current to supply power to USB core digital
(USB_VDD1P3) and PHY circuits (USB_VDDA1P3)
Active @ Room Temp 25°C, 75% DMAC +
25% ADD
0.15 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Active @ Room Temp 25°C, 75% DMAC +
25% NOP
0.14 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM and SARAM in Active
Mode)
0.26 mW @ 1.05 V
0.44 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM in Retention and
SARAM in Active Mode)
0.23 mW @ 1.05 V
0.40 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM in Active Mode and
SARAM in Retention)
0.15 mW @ 1.05 V
0.28 mW @ 1.3 V
PLL Options
Software Programmable Multiplier
BGA Package
12 x 12 mm
Product Status (1)
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
(1)
64 KB On-Chip Dual-Access RAM (DARAM)
64 KB On-Chip Single-Access RAM (SARAM)
128 KB On-Chip Single-Access ROM (SAROM)
x4 to x4099 multiplier
144-Pin BGA (ZHH)
PD
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Device Comparison
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Copyright © 2011–2014, Texas Instruments Incorporated
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
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Table 3-5. Characteristics of the C5532 Processor
HARDWARE FEATURES
TMS320C5532A05, C5532A10
Peripherals
Not all peripheral pins are
available at the same time DMA
(for more detail, see
Section 5).
Four DMA controllers each with four channels,
for a total of 16 channels
Timers
2 32-Bit General-Purpose (GP) Timers
1 Additional Timer Configurable as a 32-Bit GP Timer or a
Watchdog
UART
1 (with RTS and CTS flow control)
SPI
1 with 4 chip selects
I2C
1 (Master or Slave)
I2S
4 (Two Channel, Full Duplex Communication)
SD
2 SD, 256-byte read and write buffer, max 50-MHz clock and
signaling for DMA transfers
Real-Time Clock (RTC)
1 (Crystal Input, Separate Clock Domain and Power Supply)
General-Purpose Input/Output Port (GPIO)
Up to 20 pins (with 1 Additional General-Purpose Output (XF))
Size (Bytes)
On-Chip Memory
64KB RAM, 128KB ROM
•
•
Organization
JTAG BSDL_ID
JTAGID Register
(Value is: 0x1B8F E02F)
CPU Frequency
MHz
Cycle Time
ns
see Figure 6-5
1.05-V Core
50 MHz
1.3-V Core
100 MHz (TMS320C5532A10 only)
1.05-V Core
20 ns
1.3-V Core
10 ns (TMS320C5532A10 only)
Core (V)
Voltage
64KB On-Chip Dual-Access RAM (DARAM)
128KB On-Chip Single-Access ROM (SAROM)
I/O (V)
1.05 V – 50 MHz
1.3 V – 100 MHz (TMS320C5532A10 only)
1.8 V, 2.5 V, 2.75 V, 3.3 V
1.3 V, 4 mA max current for PLL (VDDA_PLL) power
management circuits (VDDA_ANA)
LDO
ANA_LDO
Power Characterization
Active @ Room Temp 25°C, 75% DMAC +
25% ADD
0.15 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Active @ Room Temp 25°C, 75% DMAC +
25% NOP
0.14 mW/MHz @ 1.05 V, 50 MHz
0.22 mW/MHz @ 1.3 V, 100 MHz
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM and SARAM in Active
Mode)
0.26 mW @ 1.05 V
0.44 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM in Retention and
SARAM in Active Mode)
0.23 mW @ 1.05 V
0.40 mW @ 1.3 V
Standby (Master Clock Disabled) @ Room
Temp 25°C (DARAM in Active Mode and
SARAM in Retention)
0.15 mW @ 1.05 V
0.28 mW @ 1.3 V
PLL Options
Software Programmable Multiplier
BGA Package
12 x 12 mm
Product Status (1)
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
(1)
12
x4 to x4099 multiplier
144-Pin BGA (ZHH)
PD
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Device Comparison
Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C5535 TMS320C5534 TMS320C5533 TMS320C5532
TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
www.ti.com
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
4 Terminal Configuration and Functions
4.1
Pin Diagram
The following figures show the bottom view of the package pin assignments.
SD0_D1/
I2S0_RX/
GP[3]
SD0_D3/
GP[5]
SD1_D1/
I2S1_RX/
GP[9]
SD0_D2/
GP[4]
SD0_CLK/
I2S0_CLK/
GP[0]
SD0_CMD/
I2S0_FS/
GP[1]
SD1_D3/
GP[11]
SD1_CMD/
I2S1_FS/
GP[7]
SD1_D0/
I2S1_DX/
GP[8]
SD1_CLK/
I2S1_CLK/
GP[6]
SD1_D2/
GP[10]
SD0_D0/
I2S0_DX/
GP[2]
USB_MXI
USB_MXO
INT0
DSP_LDO_
EN
DVDDRTC
INT1
LDOI
LDOI
DSP_LDOO
Figure 4-1. C5535 Pin Diagram
Terminal Configuration and Functions
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Copyright © 2011–2014, Texas Instruments Incorporated
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TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
www.ti.com
P
VSS
GP[14]
GP[16]
TRST
I2S2_CLK/
GP[18]/
SPI_CLK
SD0_D1/
I2S0_RX/
GP[3]
SD0_D3/
GP[5]
GP[17]
I2S2_RX/
GP[20]/
SPI_RX
SD1_D1/
I2S1_RX/
GP[9]
I2S2_DX/
GP[27]/
SPI_TX
UART_CTS/
GP[29]/
I2S3_FS
UART_RXD/
GP[30]/
I2S3_RX
N
TDO
SPI_CS2
TCK
SPI_RX
GP[13]
TMS
GP[15]
DVDDIO
CVDD
I2S2_FS/
GP[19]/
SPI_CS0
DVDDIO
UART_RTS/
GP[28]/
I2S3_CLK
SD0_D2/
GP[4]
DVDDIO
M
EMU1
SPI_CS1
DVDDIO
DVDDIO
SPI_CS3
CVDD
VSS
SD0_CLK/
I2S0_CLK/
GP[0]
CVDD
SD0_CMD/
I2S0_FS/
GP[1]
UART_TXD/
GP[31]/
I2S3_DX
SD1_D3/
GP[11]
SD1_D0/
I2S1_DX/
GP[8]
SD1_CLK/
I2S1_CLK/
GP[6]
L
SPI_CS0
EMU0
SPI_CLK
DVDDIO
VSS
VSS
SD1_CMD/
I2S1_FS/
GP[7]
SD1_D2/
GP[10]
RSV2
USB_VBUS
K
SPI_TX
TDI
VSS
VSS
CVDD
RSV1
USB_VDD1P3
J
SD0_D0/
I2S0_DX/
GP[2]
GP[12]
XF
USB_VSSA1P3
VSS
USB_DM
H
RSV10
CVDD
VSS
USB_
VDDA1P3
USB_VSSA3P3
USB_DP
G
RSV9
RSV12
CVDD
USB_VDDA3P3 USB_VDDPLL
USB_R1
F
RSV8
CVDD
VSS
E
RSV7
RSV11
VSS
VSS
D
CLK_SEL
RESET
CVDD
VSS
VSS
C
CLKIN
INT0
DVDDRTC
SCL
VSSRTC
DVDDIO
VDDA_PLL
VSS
B
INT1
VSS
VSS
CVDDRTC
CVDDRTC
VSSA_ANA
VDDA_ANA
A
VSSA_PLL
CLKOUT
RTC_CLKOUT
SDA
WAKEUP
RTC_XO
1
2
3
4
5
6
VSS
USB_VSS1P3
USB_VSSREF USB_VSSPLL USB_VDD1P3
VSS
USB_VDD1P3 USB_VDDOSC
USB_MXI
USB_VSSOSC
USB_LDOO
USB_MXO
VSS
CVDD
VSSA_ANA
BG_CAP
CVDD
VSS
DSP_LDO_
EN
LDOI
NC
ANA_LDOO
LDOI
RSV5
RSV3
RSV6
LDOI
RTC_XI
NC
NC
NC
RSV4
RSV0
DSP_LDOO
VSS
7
8
9
10
11
12
13
14
Figure 4-2. C5534 Pin Diagram
14
Terminal Configuration and Functions
Copyright © 2011–2014, Texas Instruments Incorporated
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TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
www.ti.com
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
P
VSS
GP[14]
GP[16]
TRST
I2S2_CLK/
GP[18]/
SPI_CLK
SD0_D1/
I2S0_RX/
GP[3]
SD0_D3/
GP[5]
GP[17]
I2S2_RX/
GP[20]/
SPI_RX
SD1_D1/
I2S1_RX/
GP[9]
I2S2_DX/
GP[27]/
SPI_TX
UART_CTS/
GP[29]/
I2S3_FS
UART_RXD/
GP[30]/
I2S3_RX
N
TDO
SPI_CS2
TCK
SPI_RX
GP[13]
TMS
GP[15]
DVDDIO
CVDD
I2S2_FS/
GP[19]/
SPI_CS0
DVDDIO
UART_RTS/
GP[28]/
I2S3_CLK
SD0_D2/
GP[4]
DVDDIO
M
EMU1
SPI_CS1
DVDDIO
DVDDIO
SPI_CS3
CVDD
VSS
SD0_CLK/
I2S0_CLK/
GP[0]
CVDD
SD0_CMD/
I2S0_FS/
GP[1]
UART_TXD/
GP[31]/
I2S3_DX
SD1_D3/
GP[11]
SD1_D0/
I2S1_DX/
GP[8]
SD1_CLK/
I2S1_CLK/
GP[6]
L
SPI_CS0
EMU0
SPI_CLK
DVDDIO
VSS
VSS
SD1_CMD/
I2S1_FS/
GP[7]
SD1_D2/
GP[10]
RSV2
USB_VBUS
K
SPI_TX
TDI
VSS
VSS
CVDD
RSV1
USB_VDD1P3
J
SD0_D0/
I2S0_DX/
GP[2]
GP[12]
XF
USB_VSSA1P3
VSS
USB_DM
H
RSV10
CVDD
VSS
USB_
VDDA1P3
USB_VSSA3P3
USB_DP
G
RSV9
RSV12
CVDD
USB_VDDA3P3 USB_VDDPLL
USB_R1
F
RSV8
CVDD
VSS
E
RSV7
RSV11
VSS
VSS
D
CLK_SEL
RESET
CVDD
VSS
VSS
C
CLKIN
INT0
DVDDRTC
SCL
VSSRTC
VSS
DVDDIO
VDDA_PLL
VSS
VSSA_ANA
VSS
CVDD
BG_CAP
CVDD
USB_VDD1P3 USB_VDDOSC
USB_MXI
USB_VSSOSC
USB_LDOO
USB_MXO
VSS
DSP_LDO_
LDOI
B
INT1
VSS
VSS
CVDDRTC
CVDDRTC
VSSA_ANA
VDDA_ANA
NC
ANA_LDOO
LDOI
RSV5
RSV3
A
VSSA_PLL
CLKOUT
RTC_CLKOUT
SDA
WAKEUP
RTC_XO
RTC_XI
NC
NC
NC
RSV4
RSV0
1
2
3
4
5
6
7
8
9
10
11
12
(2)
USB_VSS1P3
USB_VSSREF USB_VSSPLL USB_VDD1P3
EN
(1)
VSS
(1)
LDOI
RSV6
DSP_LDOO
(2)
13
VSS
14
DSP_LDOO is not supported on the TMS320C5533. An external power supply is used to provide power to CVDD, DSP_LDO_EN
must be tied to LDOI, and DSP_LDOO must be left unconnected. The RESET pin must be asserted appropriately for device
initialization after power up.
DSP_LDOO is not supported on the TMS320C5533. For proper device operation, this pin must be left connected. DSP_LDOO can
be enabled to provide a regulated 1.3- or 1.05-V output only to the internal POR to support the RTC-only mode. For more
information, see Section 5.7.11.1, RTC Only Mode.
Figure 4-3. C5533 Pin Diagram
Terminal Configuration and Functions
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www.ti.com
P
VSS
GP[14]
GP[16]
TRST
I2S2_CLK/
GP[18]/
SPI_CLK
SD0_D1/
I2S0_RX/
GP[3]
SD0_D3/
GP[5]
GP[17]
I2S2_RX/
GP[20]/
SPI_RX
SD1_D1/
I2S1_RX/
GP[9]
I2S2_DX/
GP[27]/
SPI_TX
UART_CTS/
GP[29]/
I2S3_FS
UART_RXD/
GP[30]/
I2S3_RX
N
TDO
SPI_CS2
TCK
SPI_RX
GP[13]
TMS
GP[15]
DVDDIO
CVDD
I2S2_FS/
GP[19]/
SPI_CS0
DVDDIO
UART_RTS/
GP[28]/
I2S3_CLK
SD0_D2/
GP[4]
DVDDIO
M
EMU1
SPI_CS1
DVDDIO
DVDDIO
SPI_CS3
CVDD
VSS
SD0_CLK/
I2S0_CLK/
GP[0]
CVDD
SD0_CMD/
I2S0_FS/
GP[1]
UART_TXD/
GP[31]/
I2S3_DX
SD1_D3/
GP[11]
SD1_D0/
I2S1_DX/
GP[8]
SD1_CLK/
I2S1_CLK/
GP[6]
L
SPI_CS0
EMU0
SPI_CLK
DVDDIO
VSS
VSS
SD1_CMD/
I2S1_FS/
GP[7]
SD1_D2/
GP[10]
RSV2
USB_VBUS
K
SPI_TX
TDI
VSS
VSS
CVDD
RSV1
USB_VDD1P3
J
SD0_D0/
I2S0_DX/
GP[2]
GP[12]
XF
USB_VSSA1P3
VSS
USB_DM
H
RSV10
CVDD
VSS
USB_
VDDA1P3
USB_VSSA3P3
USB_DP
G
RSV9
RSV12
CVDD
USB_VDDA3P3 USB_VDDPLL
USB_R1
F
RSV8
CVDD
VSS
E
RSV7
RSV11
VSS
VSS
D
CLK_SEL
RESET
CVDD
VSS
VSS
USB_VSS1P3
USB_VSSREF USB_VSSPLL USB_VDD1P3
VSS
VSS
VSS
CVDD
USB_VDD1P3 USB_VDDOSC
USB_MXI
USB_VSSOSC
USB_MXO
USB_
(1)
LDOO
CLKIN
C
INT0
DVDDRTC
SCL
VSSRTC
DVDDIO
VDDA_PLL
VSS
VSSA_ANA
BG_CAP
CVDD
VSS
DSP_LDO_
EN
B
INT1
VSS
VSS
CVDDRTC
CVDDRTC
VSSA_ANA
VDDA_ANA
NC
ANA_LDOO
LDOI
RSV5
RSV3
A
VSSA_PLL
CLKOUT
RTC_CLKOUT
SDA
WAKEUP
RTC_XO
RTC_XI
NC
NC
NC
RSV4
RSV0
(2)
RSV6
1
(3)
2
3
4
5
6
7
8
9
10
11
12
LDOI
DSP_
(3)
LDOO
(1)
(2)
LDOI
13
VSS
14
USB_LDOO is not supported on the TMS320C5532. For proper device operation, this pin must be left unconnected.
DSP_LDOO is not supported on the TMS320C5532. An external power supply is used to provide power to CVDD, DSP_LDO_EN
must be tied to LDOI, and DSP_LDOO must be left unconnected. The RESET pin must be asserted appropriately for device
initialization after power up.
DSP_LDOO is not supported on the TMS320C5532. For proper device operation, this pin must be left connected. DSP_LDOO can
be enabled to provide a regulated 1.3- or 1.05-V output only to the internal POR to support the RTC-only mode. For more
information, see Section 5.7.11.1, RTC Only Mode.
Shaded pins are not supported on this device. To ensure proper device operation, these pins must be hooked up
properly. See Table 4-9, Unsupported USB 2.0 Signal Descriptions.
Figure 4-4. C5532 Pin Diagram
16
Terminal Configuration and Functions
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www.ti.com
4.2
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Signal Descriptions
The signal descriptions tables (Table 4-1 through Table 4-18) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors or bus-holders, and a functional pin description. For more
information on pin multiplexing, see Section 4.3, Pin Multiplexing.
For proper device operation, external pullup and pulldown resistors may be required on some pins.
Section 5.7.17.1.1, Pullup and Pulldown Resistors discusses situations where external pullup and
pulldown resistors are required.
Terminal Configuration and Functions
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4.2.1
www.ti.com
Oscillator and PLL
Table 4-1. Oscillator and PLL Signal Descriptions
SIGNAL
NAME
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION
DSP clock output signal. For debug purposes only, the CLKOUT pin can be used
to tap different clocks within the system clock generator. The SRC bits in the
CLKOUT Control Source Register (CCSSR) can be used to specify the CLKOUT
pin source. Additionally, the slew rate of the CLKOUT pin can be controlled by the
Output Slew Rate Control Register (OSRCR) [1C16h].
CLKOUT
A2
O/Z
–
DVDDIO
BH
The CLKOUT pin is enabled and disabled through the CLKOFF bit in the CPU
ST3_55 register. When disabled, the CLKOUT pin is placed in high-impedance
(Hi-Z). At reset the CLKOUT pin is enabled until the beginning of the boot
sequence, when the on-chip bootloader sets CLKOFF = 1 and the CLKOUT pin is
disabled (Hi-Z). For more information on the ST3_55 register, see the
TMS320C55x 3.0 CPU Reference Guide (literature number: SWPU073).
Note: This pin may consume static power if configured as Hi-Z and not externally
pulled low or high. Prevent current drain by externally terminating the pin.
Input clock. This signal is used to input an external clock when the 32-kHz on-chip
oscillator is not used as the DSP clock (pin CLK_SEL = 1). For boot purposes, the
CLKIN frequency is assumed to be either 11.2896, 12, or 12.288 MHz.
The CLK_SEL pin (D1) selects between the 32-kHz crystal clock or CLKIN.
CLKIN
C1
I
–
DVDDIO
BH
When the CLK_SEL pin is low, this pin must be tied to ground (VSS). When
CLK_SEL is high, this pin must be driven by an external clock source.
If CLK_SEL is high, this pin is used as the reference clock for the clock generator.
During bootup, the bootloader bypasses the PLL and assumes the CLKIN
frequency is one of the following frequencies: 11.2896-, 12-, or 12.288-MHz. In
addition, the bootloader sets the SPI clock rate at 500 kHz and the I2C clock rate
at 400 kHz .
Clock input select. This pin selects between the 32-kHz crystal clock or CLKIN.
CLK_SEL
D1
I
–
DVDDIO
BH
0 = 32-kHz on-chip oscillator drives the RTC timer and the system clock generator
while CLKIN is ignored.
1 = CLKIN drives the system clock generator and the 32-kHz on-chip oscillator
drives only the RTC timer.
This pin is not allowed to change during device operation; it must be tied high or
low at the board.
(1)
(2)
(3)
(4)
18
VDDA_PLL
C7
PWR
1.3-V Analog PLL power supply for the system clock generator (PLLOUT ≤ 120
see Section 5.2, MHz).
ROC
This signal can be powered from the ANA_LDOO pin.
VSSA_PLL
A1
GND
see Section 5.2,
Analog PLL ground for the system clock generator.
ROC
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
Terminal Configuration and Functions
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4.2.2
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Real-Time Clock (RTC)
Table 4-2. RTC Signal Descriptions
SIGNAL
NAME
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION
Real-time clock oscillator output. This pin operates at the RTC core voltage,
CVDDRTC, and supports a 32.768-kHz crystal.
RTC_XO
A6
I/O/Z
–
CVDDRTC
DVDDRTC
If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to
CVDDRTC and RTC_XO to ground (VSS). A voltage must still be applied to CVDDRTC
by an external power source (see Section 5.2, Recommended Operating
Conditions). None of the on-chip LDOs can be used to power CVDDRTC.
Note: When RTC oscillator is disabled, the RTC registers (I/O address range
1900h – 197Fh) are not accessible.
Real-time clock oscillator input.
–
RTC_XI
A7
I
CVDDRTC
DVDDRTC
If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to
CVDDRTC and RTC_XO to ground (VSS). A voltage must still be applied to CVDDRTC
by an external power source (see Section 5.2, Recommended Operating
Conditions). None of the on-chip LDOs can be used to power CVDDRTC.
Note: When RTC oscillator is disabled, the RTC registers (I/O address range
1900h – 197Fh) are not accessible.
RTC_CLKOUT
A3
O/Z
WAKEUP
A5
I/O/Z
(1)
(2)
(3)
(4)
–
DVDDRTC
–
DVDDRTC
Real-time clock output pin. This pin operates at DVDDRTC voltage. The
RTC_CLKOUT pin is enabled and disabled through the RTCCLKOUTEN bit in the
RTC Power Management Register (RTCPMGT). At reset, the RTC_CLKOUT pin is
disabled (high-impedance [Hi-Z]).
The pin is used to WAKEUP the core from idle condition. This pin defaults to an
input at CVDDRTC powerup, but can also be configured as an active-low open-drain
output signal to wakeup an external device from an RTC alarm.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
Terminal Configuration and Functions
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
4.2.3
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RESET, Interrupts, and JTAG
Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions
SIGNAL
NAME
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION
RESET
External Flag Output. XF is used for signaling other processors in multiprocessor
configurations or XF can be used as a fast general-purpose output pin.
XF
J3
O/Z
–
DVDDIO
BH
XF is set high by the BSET XF instruction and XF is set low by the BCLR XF
instruction or by writing to bit 13 of the ST1_55 register. For more information on the
ST1_55 register, see the TMS320C55x 3.0 CPU Reference Guide (literature
number: SWPU073).
For XF pin behavior at reset, see Section 5.7.3.2, Pin Behavior at Reset.
Note: This pin may consume static power if configured as Hi-Z and not externally
pulled low or high. Prevent current drain by externally terminating the pin. XF pin is
ONLY in the Hi-Z state when doing boundary scan. Therefore, external termination
is probably not required for most applications.
RESET
D2
I
IPU
DVDDIO
BH
Device reset. RESET causes the DSP to terminate execution and loads the program
counter with the contents of the reset vector. When RESET is brought to a high
level, the reset vector in ROM at FFFF00h forces the program execution to branch
to the location of the on-chip ROM bootloader.
RESET affects the various registers and status bits.
The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register
but will be forced ON when RESET is asserted.
JTAG
[For more detailed information on emulation header design guidelines, see the XDS560 Emulator Technical Reference (literature number:
SPRU589).]
IEEE standard 1149.1 test mode select. This serial control input is clocked into the
TAP controller on the rising edge of TCK.
TMS
N6
I
IPU
DVDDIO
BH
If the emulation header is located greater than 6 inches from the device, TMS must
be buffered. In this case, the input buffer for TMS needs a pullup resistor connected
to DVDDIO to hold the signal at a known value when the emulator is not connected. A
resistor value of 4.7 kΩ or greater is suggested. For board design guidelines related
to the emulation header, see the XDS560 Emulator Technical Reference (literature
number: SPRU589).
The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
IEEE standard 1149.1 test data output. The contents of the selected register
(instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the
high-impedance (Hi-Z) state except when the scanning of data is in progress.
TDO
N1
O/Z
–
DVDDIO
BH
For board design guidelines related to the emulation header, see the XDS560
Emulator Technical Reference (literature number: SPRU589).
If the emulation header is located greater than 6 inches from the device, TDO must
be buffered.
Note: This pin may consume static power if configured as Hi-Z and not externally
pulled low or high. Prevent current drain by externally terminating the pin. TDO pin
will be in Hi-Z whenever not doing emulation and boundary scan, so an external
pullup is highly recommended.
(1)
(2)
(3)
(4)
20
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
Terminal Configuration and Functions
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions (continued)
SIGNAL
NAME
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION
IEEE standard 1149.1 test data input. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDI
K2
I
IPU
DVDDIO
BH
If the emulation header is located greater than 6 inches from the device, TDI must
be buffered. In this case, the input buffer for TDI needs a pullup resistor connected
to DVDDIO to hold this signal at a known value when the emulator is not connected.
A resistor value of 4.7 kΩ or greater is suggested.
The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a
50% duty cycle. The changes on input signals TMS and TDI are clocked into the
TAP controller, instruction register, or selected test data register on the rising edge
of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK.
TCK
N3
I
IPU
DVDDIO
BH
If the emulation header is located greater than 6 inches from the device, TCK must
be buffered.
For board design guidelines related to the emulation header, see the XDS560
Emulator Technical Reference (literature number: SPRU589).
The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
TRST
P4
I
IPD
DVDDIO
BH
IEEE standard 1149.1 reset signal for test and emulation logic. TRST, when high,
allows the IEEE standard 1149.1 scan and emulation logic to take control of the
operations of the device. If TRST is not connected or is driven low, the device
operates in its functional mode, and the IEEE standard 1149.1 signals are ignored.
The device will not operate properly if this reset pin is never asserted low.
For board design guidelines related to the emulation header, see the XDS560
Emulator Technical Reference (literature number: SPRU589).
It is recommended that an external pulldown resistor be used in addition to the IPD - especially if there is a long trace to an emulation header.
Emulator 1 pin. EMU1 is used as an interrupt to or from the emulator system and is
defined as input/output by way of the emulation logic.
EMU1
M1
I/O/Z
IPU
DVDDIO
BH
For board design guidelines related to the emulation header, see the XDS560
Emulator Technical Reference (literature number: SPRU589).
An external pullup to DVDDIO is required to provide a signal rise time of less than 10
μsec. A 4.7-kΩ resistor is suggested for most applications.
For board design guidelines related to the emulation header, see the XDS560
Emulator Technical Reference (literature number: SPRU589).
The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
EMU0
L2
I/O/Z
IPU
DVDDIO
BH
Emulator 0 pin. When TRST is driven low and then high, the state of the EMU0 pin
is latched and used to connect the JTAG pins (TCK, TMS, TDI, TDO) to either the
IEEE1149.1 Boundary-Scan TAP (when the latched value of EMU0 = 0) or to the
DSP Emulation TAP (when the latched value of EMU0 = 1). Once TRST is high,
EMU0 is used as an interrupt to or from the emulator system and is defined as
input/output by way of the emulation logic.
An external pullup to DVDDIO is required to provide a signal rise time of less than 10
μsec. A 4.7-kΩ resistor is suggested for most applications.
For board design guidelines related to the emulation header, see the XDS560
Emulator Technical Reference (literature number: SPRU589).
The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register.
EXTERNAL INTERRUPTS
INT1
B1
I
IPU
DVDDIO
BH
External interrupt inputs (INT1 and INT0). These pins are maskable via their specific
Interrupt Mask Register (IMR1, IMR0) and the interrupt mode bit. The pins can be
polled and reset by their specific Interrupt Flag Register (IFR1, IFR0).
INT0
C2
I
IPU
DVDDIO
BH
The IPU resistor on these pins can be enabled or disabled via the PDINHIBR2
register.
Terminal Configuration and Functions
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4.2.4
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Inter-Integrated Circuit (I2C)
Table 4-4. I2C Signal Descriptions
SIGNAL
NAME
NO.
TYPE
(1) (2)
OTHER (3)
This pin is the I2C clock output. Per the I2C standard, an external pullup is required
on this pin.
This pin is the I2C bidirectional data signal. Per the I2C standard, an external pullup
is required on this pin.
(4)
DESCRIPTION
I2C
(1)
(2)
(3)
(4)
22
SCL
C4
I/O/Z
DVDDIO
BH
SDA
A4
I/O/Z
DVDDIO
BH
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
Terminal Configuration and Functions
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4.2.5
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Inter-IC Sound (I2S)
Table 4-5. I2S0 – I2S3 Signal Descriptions
SIGNAL
NAME (5)
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION (5)
Interface 0 (I2S0)
This pin is multiplexed between SD0, I2S0, and GPIO.
SD0_D0/
I2S0_DX/
GP[2]
J1
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S0 transmit data output I2S0_DX.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD0, I2S0, and GPIO.
SD0_CLK/
I2S0_CLK/
GP[0]
M8
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S0 clock input/output I2S0_CLK.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD0, I2S0, and GPIO.
SD0_D1/
I2S0_RX/
GP[3]
P6
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S0 receive data input I2S0_RX.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD0, I2S0, and GPIO.
SD0_CMD/
I2S0_FS/
GP[1]
M10
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S0 frame synchronization input/output I2S0_FS.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
Interface 1 (I2S1)
This pin is multiplexed between SD1, I2S1, and GPIO.
SD1_D0/
I2S1_DX/
GP[8]
M13
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S1 transmit data output I2S1_DX.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD1, I2S1, and GPIO.
SD1_CLK/
I2S1_CLK/
GP[6]
M14
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S1 clock input/output I2S1_CLK.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD1, I2S1, and GPIO.
SD1_D1/
I2S1_RX/
GP[9]
P10
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S1 receive data input I2S1_RX.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD1, I2S2, and GPIO.
SD1_CMD/
I2S1_FS/
GP[7]
(1)
(2)
(3)
(4)
(5)
L11
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S1 frame synchronization input/output I2S1_FS.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
LCD Bridge applies only to TMS320C5535.
Terminal Configuration and Functions
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Table 4-5. I2S0 – I2S3 Signal Descriptions (continued)
SIGNAL
NAME (5)
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION (5)
Interface 2 (I2S2)
LCD_D[11]/
I2S2_DX/
GP[27]/
SPI_TX
LCD_D[8]/
I2S2_CLK/
GP[18]/
SPI_CLK
LCD_D[10]/
I2S2_RX/
GP[20]/
SPI_RX
LCD_D[9]/
I2S2_FS/
GP[19]/
SPI_CS0
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
P11
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S2 transmit data output I2S2_DX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
P5
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S2 clock input/output I2S2_CLK.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
P9
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S2 receive data input I2S2_RX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2 and GPIO.
N10
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S2 frame synchronization input/output I2S2_FS.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
Interface 3 (I2S3)
LCD_D[15]/
UART_TXD/
GP[31]/
I2S3_DX
LCD_D[12]/
UART_RTS/
GP[28]/
I2S3_CLK
LCD_D[14]/
UART_RXD/
GP[30]/
I2S3_RX
LCD_D[13]/
UART_CTS/
GP[29]/
I2S3_FS
24
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
M11
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S3 transmit data output I2S3_DX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
N12
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S3 clock input/output I2S3_CLK.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
P13
I/O/Z
IPD
DVDDIO
BH
For I2S, it is I2S3 receive data input I2S3_RX.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
P12
I/O/Z
IPD
DVDDIO
BH
Terminal Configuration and Functions
For I2S, it is I2S3 frame synchronization input/output I2S3_FS.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
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4.2.6
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Serial Peripheral Interface (SPI)
Table 4-6. SPI Signal Descriptions
SIGNAL
NAME (5)
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION (5)
Serial Port Interface (SPI)
This pin is multiplexed between LCD Bridge and SPI.
LCD_CS0_E0/
SPI_CS0
L1
I/O/Z
DVDDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS0.
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
LCD_D[9]/
I2S2_FS/
GP[19]/
SPI_CS0
N10
I/O/Z
IPD
DVDDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS0.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and SPI.
LCD_CS1_E1/
SPI_CS1
M2
I/O/Z
DVDDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS1.
This pin is multiplexed between LCD Bridge and SPI.
LCD_RW_WRB/
SPI_CS2
N2
I/O/Z
DVDDIO
BH
LCD_RS/
SPI_CS3
M5
I/O/Z
DVDDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS2.
This pin is multiplexed between LCD Bridge and SPI.
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI chip select SPI_CS3.
This pin is multiplexed between LCD Bridge and SPI.
LCD_EN_RDB/
SPI_CLK
L3
O/Z
DVDDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is clock output SPI_CLK.
Note: This pin may consume static power if configured as Hi-Z and not externally
pulled low or high. Prevent current drain by externally terminating the pin.
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
LCD_D[8]/
I2S2_CLK/
GP[18]/
SPI_CLK
P5
I/O/Z
IPD
DVDDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is clock output SPI_CLK.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and SPI.
LCD_D[1]/
SPI_TX
K1
I/O/Z
DVDDIO
BH
I/O/Z
IPD
DVDDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI transmit data output.
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
LCD_D[11]/
I2S2_DX/
GP[27]/
SPI_TX
P11
Mux control via the PPMODE bits in the EBSR.
For SPI, this pin is SPI transmit data output.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and SPI.
LCD_D[0]/
SPI_RX
(1)
(2)
(3)
(4)
(5)
N4
I/O/Z
DVDDIO
BH
Mux control via the PPMODE bits in the EBSR.
For SPI this pin is SPI receive data input.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
LCD Bridge applies to only TMS320C5535.
Terminal Configuration and Functions
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Table 4-6. SPI Signal Descriptions (continued)
SIGNAL
NAME (5)
NO.
TYPE
(1) (2)
OTHER (3)
I/O/Z
IPD
DVDDIO
BH
(4)
DESCRIPTION (5)
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
LCD_D[10]/
I2S2_RX/
GP[20]/
SPI_RX
P9
Mux control via the PPMODE bits in the EBSR.
For SPI this pin is SPI receive data input.
The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.
26
Terminal Configuration and Functions
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4.2.7
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Universal Asynchronous Receiver/Transmitter (UART)
Table 4-7. UART Signal Descriptions
SIGNAL
NAME (5)
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION (5)
UART
LCD_D[14]/
UART_RXD/
GP[30]/
I2S3_RX
LCD_D[15]/
UART_TXD/
GP[31]/
I2S3_DX
LCD_D[13]/
UART_CTS/
GP[29]/
I2S3_FS
LCD_D[12]/
UART_RTS/
GP[28]/
I2S3_CLK
(1)
(2)
(3)
(4)
(5)
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
P13
I/O/Z
IPD
DVDDIO
BH
When used by UART, it is the receive data input UART_RXD.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
M11
I/O/Z
IPD
DVDDIO
BH
In UART mode, it is the transmit data output UART_TXD.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
P12
I/O/Z
IPD
DVDDIO
BH
In UART mode, it is the clear to send input UART_CTS.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
N12
I/O/Z
IPD
DVDDIO
BH
In UART mode, it is the ready to send output UART_RTS.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
LCD Bridge applies only to TMS320C5535.
Terminal Configuration and Functions
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4.2.8
www.ti.com
Universal Serial Bus (USB) 2.0
Table 4-8. USB 2.0 Signal Descriptions — Not Used On C5532
SIGNAL
NAME
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION
USB 2.0
12-MHz crystal oscillator input.
When the USB peripheral is not used, USB_MXI must be connected to ground
(VSS).
USB_MXI
E14
I
USB_VDDOSC
When using an external 12-MHz oscillator, the external oscillator clock signal must
be connected to the USB_MXI pin and the amplitude of the oscillator clock signal
must meet the VIH requirement (see Section 5.2, Recommended Operating
Conditions). The USB_MXO remains unconnected and the USB_VSSOSC signal is
connected to board ground (VSS).
12-MHz crystal oscillator output.
When the USB peripheral is not used, USB_MXO must be left unconnected.
USB_MXO
D14
O/Z
USB_VDDOSC
USB_VDDOSC
E13
S
see
Section 5.2,
ROC
When using an external 12-MHz oscillator, the external oscillator clock signal must
be connected to the USB_MXI pin and the amplitude of the oscillator clock signal
must meet the VIH requirement (see Section 5.2, Recommended Operating
Conditions). The USB_MXO remains unconnected and the USB_VSSOSC signal is
connected to board ground (VSS).
3.3-V power supply for USB oscillator.
When the USB peripheral is not used, USB_VDDOSC must be connected to ground
(VSS).
Ground for USB oscillator.
USB_VSSOSC
D12
S
see
Section 5.2,
ROC
When the USB peripheral is not used, USB_VSSOSC must be connected to ground
(VSS).
When using an external 12-MHz oscillator, the external oscillator clock signal must
be connected to the USB_MXI pin and the amplitude of the oscillator clock signal
must meet the VIH requirement (see Section 5.2, Recommended Operating
Conditions). The USB_MXO remains unconnected and the USB_VSSOSC signal is
connected to board ground (VSS).
USB power detect. 5-V input that signifies that VBUS is connected.
USB_VBUS
L14
A I/O
see
Section 5.2,
ROC
USB_DP
H14
A I/O
USB_VDDA3P3
USB_DM
J14
A I/O
USB_VDDA3P3
USB_R1
G14
A I/O
USB_VDDA3P3
This signal must be powered on in the order listed in Section 5.7.2.4, Power-Supply
Sequencing.
When the USB peripheral is not used, the USB_VBUS signal must be connected to
ground (VSS).
USB bi-directional Data Differential signal pair [positive and negative].
When the USB peripheral is not used, the USB_DP and USB_DM signals should
both be tied to ground (VSS).
External resistor connect. Reference current output. This must be connected via a
10-kΩ ±1% resistor to USB_VSSREF and be placed as close to the device as
possible.
When the USB peripheral is not used, the USB_R1 signal must be connected via a
10-kΩ resistor to ground (VSS).
USB_VSSREF
(1)
(2)
(3)
(4)
28
F12
GND
see
Section 5.2,
ROC
Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to
USB_R1.
When the USB peripheral is not used, the USB_VSSREF signal must be connected
directly to ground (Vss).
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
Terminal Configuration and Functions
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Table 4-8. USB 2.0 Signal Descriptions — Not Used On C5532 (continued)
SIGNAL
NAME
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION
Analog 3.3 V power supply for USB PHY.
USB_VDDA3P3
USB_VSSA3P3
G12
H13
S
GND
see
Section 5.2,
ROC
see
Section 5.2,
ROC
This signal must be powered on in the order listed in Section 5.7.2.4, Power-Supply
Sequencing.
When the USB peripheral is not used, the USB_VDDA3P3 signal must be connected
to ground (VSS).
Analog ground for USB PHY.
Analog 1.3 V power supply for USB PHY. [For high-speed sensitive analog circuits]
USB_VDDA1P3
USB_VSSA1P3
H12
J12
S
GND
see
Section 5.2,
ROC
see
Section 5.2,
ROC
This signal must be powered on in the order listed in Section 5.7.2.4, Power-Supply
Sequencing.
When the USB peripheral is not used, the USB_VDDA1P3 signal must be connected
to ground (VSS).
Analog ground for USB PHY [For high speed sensitive analog circuits].
1.3-V digital core power supply for USB PHY.
K13,
E12,
F14
S
USB_VSS1P3
K14
GND
see
Section 5.2,
ROC
USB_VDDPLL
G13
S
see
Section 5.2,
ROC
USB_VSSPLL
F13
GND
see
Section 5.2,
ROC
USB_VDD1P3
see
Section 5.2,
ROC
This signal must be powered on in the order listed in Section 5.7.2.4, Power-Supply
Sequencing.
When the USB peripheral is not used, the USB_VDD1P3 signal must be connected to
ground (VSS).
Digital core ground for USB PHY. Analog ground for USB PHY [For high-speed
sensitive analog circuits].
3.3 V USB Analog PLL power supply.
When the USB peripheral is not used, the USB_VDDPLL signal must be connected to
ground (VSS).
USB Analog PLL ground.
Terminal Configuration and Functions
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Table 4-9. Unsupported USB 2.0 Signal Descriptions — TMS320C5532 Only
SIGNAL
NAME
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION
USB 2.0
(1)
(2)
(3)
(4)
30
USB_MXI
E14
I
-
When the USB peripheral is not used, USB_MXI must be connected to ground
(VSS).
USB_MXO
D14
O/Z
-
When the USB peripheral is not used, USB_MXO must be left unconnected.
USB_VDDOSC
E13
S
-
When the USB peripheral is not used, USB_VDDOSC must be connected to ground
(VSS).
USB_VSSOSC
D12
S
-
The USB_MXO remains unconnected and the USB_VSSOSC signal is connected to
board ground (VSS).
USB_VBUS
L14
A I/O
-
When the USB peripheral is not used, the USB_VBUS signal must be connected to
ground (VSS).
USB_DP
H14
A I/O
-
USB_DM
J14
A I/O
-
When the USB peripheral is not used, the USB_DP and USB_DM signals should
both be tied to ground (VSS).
USB_R1
G14
A I/O
-
When the USB peripheral is not used, the USB_R1 signal must be connected via a
10-kΩ resistor to ground (Vss).
USB_VSSREF
F12
GND
-
When the USB peripheral is not used, the USB_VSSREF signal must be connected
directly to ground (Vss).
USB_VDDA3P3
G12
S
-
When the USB peripheral is not used, the USB_VDDA3P3 signal must be connected
to ground (VSS).
USB_VSSA3P3
H13
GND
-
When the USB peripheral is not used, USB_VSSA3P3 must be conntected to ground
(VSS).
USB_VDDA1P3
H12
S
-
When the USB peripheral is not used, the USB_VDDA1P3 signal must be connected
to ground (VSS).
USB_VSSA1P3
J12
GND
-
When the USB peripheral is not used, USBVSSA1P3 must be connected to ground
(VSS).
USB_VDD1P3
K13,
E12,
F14
S
-
When the USB peripheral is not used, the USB_VDD1P3 signal must be connected to
ground (VSS).
USB_VSS1P3
K14
GND
-
When the USB peripheral is not used, USB_VSS1P3 must be connected to ground
(VSS).
USB_VDDPLL
G13
S
-
When the USB peripheral is not used, the USB_VDDPLL signal must be connected to
ground (VSS).
USB_VSSPLL
F13
GND
-
When the USB peripheral is not used, USB_VSSPLL must be connected to ground
(VSS).
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
Terminal Configuration and Functions
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4.2.9
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
LCD Bridge
Table 4-10. LCD Bridge Signal Descriptions — C5535 Only
SIGNAL
NAME
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION
This pin is multiplexed between LCD Bridge and SPI.
LCD_EN_RDB/
SPI_CLK
L3
O/Z
DVDDIO
BH
For LCD Bridge, this pin is either LCD Bridge read and write enable (MPU68 mode)
or read strobe (MPU80 mode).
Mux control via the PPMODE bits in the EBSR.
Note: This pin may consume static power if configured as Hi-Z and not externally
pulled low or high. Prevent current drain by externally terminating the pin.
This pin is multiplexed between LCD Bridge and SPI.
LCD_CS0_E0/
SPI_CS0
L1
I/O/Z
DVDDIO
BH
For LCD Bridge, this pin is either LCD Bridge chip select 0 (MPU68 and MPU80
modes) or enable 0 (HD44780 mode).
Mux control via the PPMODE bits in the EBSR.
This pin is multiplexed between LCD Bridge and SPI.
LCD_CS1_E1/
SPI_CS1
M2
I/O/Z
DVDDIO
BH
For LCD Bridge, this pin is either LCD Bridge chip select 1 (MPU68 and MPU80
modes) or enable 1 (HD44780 mode).
Mux control via the PPMODE bits in the EBSR.
This pin is multiplexed between LCD Bridge and SPI.
LCD_RW_WRB/
SPI_CS2
N2
I/O/Z
DVDDIO
BH
For LCD, this pin is either LCD Bridge read and write select (HD44780 and MPU68
modes) or write strobe (MPU80 mode).
Mux control via the PPMODE bits in the EBSR.
This pin is multiplexed between LCD Bridge and SPI.
LCD_RS/
SPI_CS3
M5
I/O/Z
DVDDIO
BH
For LCD, this pin is the LCD Bridge address set-up.
Mux control via the PPMODE bits in the EBSR.
LCD_D[15]/
UART_TXD/
GP[31]/
I2S3_DX
LCD_D[14]/
UART_RXD/
GP[30]/
I2S3_RX
LCD_D[13]/
UART_CTS/
GP[29]/
I2S3_FS
LCD_D[12]/
UART_RTS/
GP[28]/
I2S3_CLK
(1)
(2)
(3)
(4)
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
M11
I/O/Z
IPD
DVDDIO
BH
For LCD Bridge, it is LCD data pin 15.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
P13
I/O/Z
IPD
DVDDIO
BH
For LCD Bridge, it is LCD data pin 14.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
P12
I/O/Z
IPD
DVDDIO
BH
For LCD Bridge, it is LCD data pin 13.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, and GPIO.
N12
I/O/Z
IPD
DVDDIO
BH
For LCD Bridge, it is LCD data pin 12.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
Terminal Configuration and Functions
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Table 4-10. LCD Bridge Signal Descriptions — C5535 Only (continued)
SIGNAL
NAME
LCD_D[11]/
I2S2_DX/
GP[27]/
SPI_TX
LCD_D[10]/
I2S2_RX/
GP[20]/
SPI_RX
LCD_D[9]/
I2S2_FS/
GP[19]/
SPI_CS0
LCD_D[8]/
I2S2_CLK
GP[18]/
SPI_CLK
NO.
TYPE
(1) (2)
OTHER (3)
I/O/Z
IPD
DVDDIO
BH
(4)
DESCRIPTION
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
P11
For LCD Bridge, it is LCD data pin 11.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
P9
I/O/Z
IPD
DVDDIO
BH
For LCD Bridge, it is LCD data pin 10.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
N10
I/O/Z
IPD
DVDDIO
BH
For LCD Bridge, it is LCD data pin 9.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
P5
I/O/Z
IPD
DVDDIO
BH
For LCD Bridge, it is LCD data pin 8.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[7]/
GP[17]
P8
I/O/Z
IPD
DVDDIO
BH
For LCD Bridge, it is LCD data pin 7.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[6]/
GP[16]
P3
I/O/Z
IPD
DVDDIO
BH
For LCD Bridge, it is LCD data pin 6.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[5]/
GP[15]
N7
I/O/Z
IPD
DVDDIO
BH
For LCD Bridge, it is LCD data pin 5.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[4]/
GP[14]
P2
I/O/Z
IPD
DVDDIO
BH
For LCD Bridge, it is LCD data pin 4.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[3]/
GP[13]
N5
I/O/Z
IPD
DVDDIO
BH
For LCD Bridge, it is LCD data pin 3.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[2]/
GP[12]
J2
I/O/Z
IPD
DVDDIO
BH
For LCD Bridge, it is LCD data pin 2.
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and SPI.
LCD_D[1]/
SPI_TX
K1
I/O/Z
DVDDIO
BH
For LCD Bridge, it is LCD data pin 1.
Mux control via the PPMODE bits in the EBSR.
This pin is multiplexed between LCD Bridge and SPI.
LCD_D[0]/
SPI_RX
N4
I/O/Z
DVDDIO
BH
For LCD Bridge, it is LCD data pin 0.
Mux control via the PPMODE bits in the EBSR.
32
Terminal Configuration and Functions
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
4.2.10 Secure Digital (SD)
4.2.10.1 SD1 Signal Descriptions
Table 4-11. SD1 Signal Descriptions
SIGNAL
NAME
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION
SD
This pin is multiplexed between SD1, I2S1, and GPIO.
SD1_CLK/
I2S1_CLK/
GP[6]
M14
I/O/Z
IPD
DVDDIO
BH
For SD, this is the SD1 data clock output SD1_CLK.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD1, I2S1, and GPIO.
SD1_CMD/
I2S1_FS/
GP[7]
L11
SD1_D3/
GP[11]
M12
SD1_D2/
GP[10]
(1)
(2)
(3)
(4)
L12
SD1_D1/
I2S1_RX/
GP[9]
P10
SD1_D0/
I2S1_DX/
GP[8]
M13
I/O/Z
IPD
DVDDIO
BH
I/O/Z
IPD
DVDDIO
BH
I/O/Z
IPD
DVDDIO
BH
I/O/Z
IPD
DVDDIO
BH
I/O/Z
IPD
DVDDIO
BH
For SD, this is the SD1 command I/O output SD1_CMD.
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
The SD1_D3 and SD1_D2 pins are multiplexed between SD1 and GPIO.
The SD1_D1 and SD1_D0 pins are multiplexed between SD1, I2S1, and GPIO.
In SD mode, all these pins are the SD1 nibble wide bi-directional data bus.
Mux control via the SP1MODE bits in the EBSR.
The IPD resistor on these pins can be enabled or disabled via the PDINHIBR1
register.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
Terminal Configuration and Functions
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4.2.10.2 SD0 Signal Descriptions
Table 4-12. SD0 Signal Descriptions
SIGNAL
NAME
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION
SD
This pin is multiplexed between SD0, I2S0, and GPIO.
SD0_CLK/
I2S0_CLK/
GP[0]
M8
I/O/Z
IPD
DVDDIO
BH
For SD, this is the SD0 data clock output SD0_CLK.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD0, I2S0, and GPIO.
SD0_CMD/
I2S0_FS/
GP[1]
M10
SD0_D3/
GP[5]
P7
SD0_D2/
GP[4]
SD0_D1/
I2S0_RX/
GP[3]
SD0_D0/
I2S0_DX/
GP[2]
(1)
(2)
(3)
(4)
34
N13
P6
J1
I/O/Z
IPD
DVDDIO
BH
I/O/Z
IPD
DVDDIO
BH
I/O/Z
IPD
DVDDIO
BH
I/O/Z
IPD
DVDDIO
BH
I/O/Z
IPD
DVDDIO
BH
For SD, this is the SD0 command I/O output SD0_CMD.
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
The SD0_D3 and SD0_D2 pins are multiplexed between SD0 and GPIO.
The SD0_D1 and SD0_D0 pins are multiplexed between SD0, I2S0, and GPIO.
In SD mode, these pins are the SD0 nibble wide bi-directional data bus.
Mux control via the SP0MODE bits in the EBSR.
The IPD resistor on these pins can be enabled or disabled via the PDINHIBR1
register.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
Terminal Configuration and Functions
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4.2.11 Successive Approximation (SAR) Analog-to-Digital Converter (ADC)
Table 4-13. 10-Bit SAR ADC Signal Descriptions — C5535 Only
SIGNAL
NAME
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION
SAR ADC
GPAIN0
A8
I/O
VDDA_ANA
GPAIN0: General -Purpose Output and Analog Input pin 0. This pin is demuxed
internally into ADC Channels 0, 1, and 2. GPAIN0 can also be used as a generalpurpose open-drain output. This pin is unique among the GPAIN pins in that it is the
only pin that is 3.6 V-tolerant to support measuring a battery voltage. GPAIN0 can
accommodate input voltages from 0 V to 3.6 V; although, the ADC is unable to
accept signals greater than VDDA_ANA without clamping. ADC Channel 1 is capable
of switching in an internal resistor divider that has a divide ratio of approximately 1/8.
GPAIN1: General -Purpose Output and Analog Input pin 1. This pin is connected to
ADC Channel 3. GPAIN1 can be used as a general-purpose output if certain
requirements are met (see the following note). GPAIN1 can accommodate input
voltages from 0 V to VDDA_ANA.
GPAIN1
GPAIN2
GPAIN3
(1)
(2)
(3)
(4)
B8
A9
A10
I/O
I/O
I/O
VDDA_ANA
VDDA_ANA
VDDA_ANA
Note: If the ANA_LDO is used to supply power to VDDA_ANA, this pin must not be
used as a general-purpose output (driving high) since the max current capability
(see the ISD parameter in Section 5.3, Electrical Characteristics) of the ANA_LDO
can be exceeded. Doing so may result in the on-chip power-on reset (POR)
resetting the chip.
GPAIN2: General -Purpose Output and Analog Input pin 2. This pin is connected to
ADC Channel 4. GPAIN2 can be used as a general-purpose output if certain
requirements are met (see the following note). GPAIN2 can accommodate input
voltages from 0 V to VDDA_ANA.
Note: If the ANA_LDO is used to supply power to VDDA_ANA, this pin must not be
used as a general-purpose output (driving high) since the max current capability
(see the ISD parameter in Section 5.3, Electrical Characteristics) of the ANA_LDO
can be exceeded. Doing so may result in the on-chip POR resetting the chip.
GPAIN3: General -Purpose Output and Analog Input pin 3. This pin is connected to
ADC Channel 5. GPAIN3 can be used as a general-purpose output if certain
requirements are met (see the following note). GPAIN3 can accommodate input
voltages from 0 V to VDDA_ANA.
Note: If the ANA_LDO is used to supply power to VDDA_ANA, this pin must not be
used as a general-purpose output (driving high) since the max current capability
(see the ISD parameter in Section 5.3, Electrical Characteristics) of the ANA_LDO
can be exceeded. Doing so may result in the on-chip POR resetting the chip.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
Terminal Configuration and Functions
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4.2.12 General-Purpose Input/Output (GPIO)
Table 4-14. GPIO Signal Descriptions
SIGNAL
NAME (5)
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION (5)
General-Purpose Input/Output
External Flag Output. XF is used for signaling other processors in multiprocessor
configurations or XF can be used as a fast general-purpose output pin.
XF
J3
O/Z
–
DVDDIO
BH
XF is set high by the BSET XF instruction and XF is set low by the BCLR XF
instruction or by writing to bit 13 of the ST1_55 register. For more information on the
ST1_55 register, see the TMS320C55x 3.0 CPU Reference Guide (literature
number: SWPU073).
For XF pin behavior at reset, see Section 5.7.3.2, Pin Behavior at Reset.
Note: This pin may consume static power if configured as Hi-Z and not externally
pulled low or high. Prevent current drain by externally terminating the pin. XF pin is
ONLY in the Hi-Z state when doing boundary scan. Therefore, external termination
is probably not required for most applications.
This pin is multiplexed between SD0, I2S0, and GPIO.
SD0_CLK/
I2S0_CLK/
GP[0]
M8
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 0 (GP[0]).
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD0, I2S0, and GPIO.
SD0_CMD/
I2S0_FS/
GP[1]
M10
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 1 (GP[1]).
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD0, I2S0, and GPIO.
SD0_D0/
I2S0_DX/
GP[2]
J1
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 2 (GP[2]).
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD0, I2S0, and GPIO.
SD0_D1/
I2S0_RX/
GP[3]
P6
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 3 (GP[3]).
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD0 and GPIO.
SD0_D2/
GP[4]
N13
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 4 (GP[4]).
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD0 and GPIO.
(1)
(2)
(3)
(4)
(5)
36
SD0_D3/
GP[5]
P7
SD1_CLK/
I2S1_CLK/
GP[6]
M14
I/O/Z
I/O/Z
IPD
DVDDIO
BH
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 5 (GP[5]).
Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD1, I2S1, and GPIO.
For GPIO, it is general-purpose input/output pin 6 (GP[6]).
Mux control via the SP1MODE bits in the EBSR.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
LCD Bridge applies to only TMS320C5535.
Terminal Configuration and Functions
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Table 4-14. GPIO Signal Descriptions (continued)
SIGNAL
NAME (5)
NO.
TYPE
(1) (2)
OTHER (3)
I/O/Z
IPD
DVDDIO
BH
(4)
DESCRIPTION (5)
This pin is multiplexed between SD1, I2S1, and GPIO.
SD1_CMD/
I2S1_FS/
GP[7]
L11
For GPIO, it is general-purpose input/output pin 7 (GP[7]).
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD1, I2S1, and GPIO.
SD1_D0/
I2S1_DX/
GP[8]
M13
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 8 (GP[8]).
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD1, I2S1, and GPIO.
SD1_D1/
I2S1_RX/
GP[9]
P10
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 9 (GP[9]).
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD1 and GPIO.
SD1_D2/
GP[10]
L12
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 10 (GP[10]).
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between SD1 and GPIO.
SD1_D3/
GP[11]
M12
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 11 (GP[11]).
Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR1 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[2]/
GP[12]
J2
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 12 (GP[12]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[3]/
GP[13]
N5
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 13 (GP[13]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[4]/
GP[14]
P2
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 14 (GP[14]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[5]/
GP[15]
N7
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 15 (GP[15]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[6]/
GP[16]
P3
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 16 (GP[16]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge and GPIO.
LCD_D[7]/
GP[17]
P8
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 17 (GP[17]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
Terminal Configuration and Functions
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Table 4-14. GPIO Signal Descriptions (continued)
SIGNAL
NAME (5)
LCD_D[8]/
I2S2_CLK/
GP[18]/
SPI_CLK
LCD_D[9]/
I2S2_FS/
GP[19]/
SPI_CS0
LCD_D[10]/
I2S2_RX/
GP[20]/
SPI_RX
LCD_D[11]/
I2S2_DX/
GP[27]/
SPI_TX
LCD_D[12]/
UART_RTS/
GP[28]/
I2S3_CLK
LCD_D[13]/
UART_CTS/
GP[29]/
I2S3_FS
LCD_D[14]/
UART_RXD/
GP[30]/
I2S3_RX
LCD_D[15]/
UART_TXD/
GP[31]/
I2S3_DX
38
NO.
TYPE
(1) (2)
OTHER (3)
I/O/Z
IPD
DVDDIO
BH
(4)
DESCRIPTION (5)
This pin is multiplexed between LCD Bridge and GPIO.
P5
For GPIO, it is general-purpose input/output pin 18 (GP[18]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, and GPIO.
N10
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 19 (GP[19]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, GPIO and SPI.
P9
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 20 (GP[20]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.
P11
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 27 (GP[27]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
N12
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 28 (GP[28]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
P12
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 29 (GP[29]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
P13
I/O/Z
IPD
DVDDIO
BH
For GPIO, it is general-purpose input/output pin 30 (GP[30]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.
M11
I/O/Z
IPD
DVDDIO
BH
Terminal Configuration and Functions
For GPIO, it is general-purpose input/output pin 31 (GP[31]).
Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be
enabled or disabled via the PDINHIBR3 register.
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4.2.13 Regulators and Power Management
Table 4-15. Regulators and Power Management Signal Descriptions
SIGNAL
NAME
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION
Regulators
DSP_LDO output. When enabled, this output provides a regulated 1.3- or 1.05-V
output and up to 250 mA of current (see the ISD parameter in Section 5.3, Electrical
Characteristics). The DSP_LDO is intended to supply current to the digital core
circuits only (CVDD) and not external devices. For proper device operation, the
external decoupling capacitor of this pin must be 5µF ~ 10µF. For more detailed
information, see Section 5.7.2.7, Power-Supply Decoupling.
DSP_LDOO (5)
When disabled, this pin is in the high-impedance (Hi-Z) state.
A13
S
When DSP_LDO comes out of reset, it is enabled to 1.3 V for the bootloader to
operate. For the 50 -MHz devices, DSP_LDO must be programmed to 1.05 V to
match the core voltage, CVDD, for proper operation after reset.
Note: DSP_LDO is not supported on TMS320C5533 and C5532, so the
DSP_LDOO pin must be left unconnected. DSP_LDO can be enabled to provide a
regulated 1.3 V or 1.05 V output to only the internal POR to support the RTC only
mode (see Section 5.7.11.1, RTC Only Mode). DSP_LDOO must never be used to
provide power to the CPU Core (CVDD) on these devices.
B14,
C14,
B10
LDOI
LDO inputs. For proper device operation, LDOI must always be powered. The LDOI
pins must be connected to the same power supply source with a voltage range of
1.8 V to 3.6 V. These pins supply power to the internal LDOs, the bandgap
reference generator circuits, and serve as the I/O supply for some input pins.
S
DSP_LDO enable input. This signal is not intended to be dynamically switched.
0 = DSP_LDO is enabled. The internal DSP LDO is enabled to regulate power on
the DSP_LDOO pin at either 1.3 V or 1.05 V, according to the DSP_LDO_V bit in
the LDOCNTL register (see Figure 5-4). At power-on-reset, the internal POR
monitors the DSP_LDOO pin voltage and generates the internal POWERGOOD
signal when the DSP_LDO voltage is above a minimum threshold voltage. The
internal device reset is generated by the AND of POWERGOOD and the RESET
pin.
Note: For the 50 -MHz devices, DSP_LDO must be programmed to 1.05 V to match
the core voltage, CVDD, for proper operation after reset.
DSP_LDO_EN
(5)
C13
I
–
LDOI
1 = DSP_LDO is disabled and the DSP_LDOO pin is in a high-impedance (Hi-Z)
state. The internal voltage monitoring on the DSP_LDOO is bypassed and the
internal POWERGOOD signal is immediately set high. The RESET pin (D2) will act
as the sole reset source for the device. If an external power supply is used to
provide power to CVDD, then DSP_LDO_EN must be tied to LDOI, DSP_LDOO
must be left unconnected, and the RESET pin must be asserted appropriately for
device initialization after power up.
Note: To pull-up this pin, connect it to the same supply as the LDOI pins.
Note: DSP_LDO is not supported on the TMS320C5533 and C5532. An external
power supply is used to provide power to CVDD, DSP_LDO_EN must be tied to
LDOI, and DSP_LDOO must be left unconnected. The RESET pin must be asserted
appropriately for device initialization after power up.
(1)
(2)
(3)
(4)
(5)
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
Applies to only TMS320C5535 and TMS320C5534.
Terminal Configuration and Functions
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Table 4-15. Regulators and Power Management Signal Descriptions (continued)
SIGNAL
NAME
USB_LDOO
TYPE
NO.
D13
(1) (2)
OTHER (3)
S
(4)
DESCRIPTION
USB_LDO output. This output provides a regulated 1.3 V output and up to 25 mA of
current (see the ISD parameter in Section 5.3, Electrical Characteristics). For proper
device operation, this pin must be connected to a 1 μF ~ 2 μF decoupling capacitor
to VSS. For more detailed information, see Section 5.7.2.7, Power-Supply
Decoupling. This LDO is intended to supply power to the USB_ VDD1P3,
USB_VDDA1P3 pins and not external devices.
Note: USB_LDO is not supported on TMS320C5532 . For proper device operation,
this pin must be left unconnected on these devices.
ANA_LDO output. This output provides a regulated 1.3 V output and up to 4 mA of
current (see the ISD parameter in Section 5.3, Electrical Characteristics).
ANA_LDOO
B9
S
For proper device operation, this pin must be connected to an ~ 1.0 μF decoupling
capacitor to VSS. For more detailed information, see Section 5.7.2.7, Power-Supply
Decoupling. This LDO is intended to supply power to the VDDA_ANA and VDDA_PLL
pins and not external devices.
Bandgap reference filter signal.
For proper device operation, this pin needs to be bypassed with a 0.1 μF capacitor
to analog ground (VSSA_ANA).
BG_CAP
C10
A I/O
BG_CAP provides a settling time of 200 ms that must elapse before executing
bootloader code. The settling time is used by Timer0.
The BG_CAP external capacitor provides filtering for stable reference voltages and
currents generated by the bandgap circuit. The bandgap produces the references for
use by the System PLL, SAR, and POR circuits.
40
Terminal Configuration and Functions
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4.2.14 Reserved and No Connects
Table 4-16. Reserved and No Connects Signal Descriptions
SIGNAL
TYPE
(1) (2)
OTHER (3)
(4)
DESCRIPTION
NAME
NO.
RSV0
A12
I
RSV1
K12
PWR
RSV2
L13
PWR
RSV3
B12
I
-
Reserved. For proper device operation, this pin must be tied directly to VSS.
RSV4
A11
I
-
Reserved. For proper device operation, this pin must be tied directly to VSS.
RSV5
B11
I
-
Reserved. For proper device operation, this pin must be tied directly to VSS.
RSV6
B13
I
-
Reserved. For proper device operation, this pin must be directly tied to VSS.
RSV7
E1
I
Reserved. (Leave unconnected, do not connect to power or ground).
RSV8
F1
I
Reserved. (Leave unconnected, do not connect to power or ground).
Reserved
(1)
(2)
(3)
(4)
-
Reserved. For proper device operation, this pin must be tied directly to VSS.
Reserved. For proper device operation, this pin must be tied directly to CVDD.
Reserved. For proper device operation, this pin must be tied directly to CVDD.
RSV9
G1
I
Reserved. (Leave unconnected, do not connect to power or ground).
RSV10
H1
I
Reserved. (Leave unconnected, do not connect to power or ground).
RSV11
E2
I
Reserved. (Leave unconnected, do not connect to power or ground).
RSV12
G2
I
Reserved. (Leave unconnected, do not connect to power or ground).
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
Terminal Configuration and Functions
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4.2.15 Supply Voltage
Table 4-17. Supply Voltage Signal Descriptions
SIGNAL
NAME (5)
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION (5)
SUPPLY VOLTAGES
F2
H2
CVDD
D3
G3
1.05-V Digital Core supply voltage (50 MHz)
PWR
1.3-V Digital Core supply voltage (100 MHz)
M6
M9
N9
C11
D11
K11
M3
DVDDIO
L4
1.8-V, 2.5-V, 2.75-V, or 3.3-V I/O power supply for non-RTC I/Os
The DVDDIO must always be powered for proper operation.
PWR
M4
C6
N8
N11
N14
1.05-V thru 1.3-V RTC digital core and RTC oscillator power supply.
CVDDRTC
B5
Note: The CVDDRTC must always be powered even though RTC is not used.
PWR
Note: The CVDDRTC cannot be powered by any of the on-chip LDOs and must be
externally powered.
B4
DVDDRTC
C3
PWR
VDDA_PLL
C7
PWR
1.8-V, 2.5-V, 2.75-V, or 3.3-V I/O power supply for RTC_CLOCKOUT and WAKEUP
pins .
Note: The DVDDRTC can be tied to ground (VSS) when the RTC_CLKOUT and
WAKEUP pins are not permanently used. In this case, the WAKEUP pin must be
configured as an output by software (see Table 5-1).
see
Section 5.2,
ROC
1.3-V Analog PLL power supply for the system clock generator (PLLOUT ≤ 120
MHz).
This signal can be powered from the ANA_LDOO pin.
G13
S
see
Section 5.2,
ROC
3.3 V USB Analog PLL power supply.
USB_VDDPLL
E12
S
see
Section 5.2,
ROC
1.3-V digital core power supply for USB PHY.
USB_VDD1P3
H12
S
see
Section 5.2,
ROC
Analog 1.3 V power supply for USB PHY. [For high-speed sensitive analog circuits]
USB_VDDA1P3
(1)
(2)
(3)
(4)
(5)
42
When the USB peripheral is not used, the USB_VDDPLL signal must be connected
to ground (VSS).
When the USB peripheral is not used, the USB_VDD1P3 signal must be connected
to ground (VSS).
When the USB peripheral is not used, the USB_VDDA1P3 signal must be connected
to ground (VSS).
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
USB signal does not apply to TMS320C5532.
Terminal Configuration and Functions
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Table 4-17. Supply Voltage Signal Descriptions (continued)
SIGNAL
TYPE
(1) (2)
OTHER (3)
(4)
DESCRIPTION (5)
NAME (5)
NO.
G12
S
see
Section 5.2,
ROC
Analog 3.3 V power supply for USB PHY.
USB_VDDA3P3
E13
S
see
Section 5.2,
ROC
3.3-V power supply for USB oscillator.
USB_VDDOSC
VDDA_ANA
B7
PWR
When the USB peripheral is not used, the USB_VDDA3P3 signal must be connected
to ground (VSS).
When the USB peripheral is not used , USB_VDDOSC must be connected to ground
(VSS).
1.3-V supply for power management and 10-bit SAR ADC
This signal can be powered from the ANA_LDOO pin.
Terminal Configuration and Functions
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4.2.16 Ground
Table 4-18. Ground Signal Descriptions
SIGNAL
NAME (5)
TYPE
NO.
(1) (2)
OTHER (3)
(4)
DESCRIPTION (5)
P1
B2
B3
E3
F3
H3
K3
VSS
D4
E4
GND
Ground pins
K4
D5
L5
M7
C8
D10
L10
E11
C12
J13
A14
P14
(1)
(2)
(3)
(4)
(5)
44
VSSRTC
C5
GND
see
Section 5.2,
ROC
Ground for RTC oscillator. When using a 32.768-kHz crystal, this pin is a local
ground for the crystal and must not be connected to the board ground (See
Figure 5-11 and Figure 5-12). When not using RTC and the crystal is not populated
on the board, this pin is connected to the board ground.
VSSA_PLL
A1
GND
see
Section 5.2,
ROC
Analog PLL ground for the system clock generator.
USB_VSSPLL
F13
GND
see
Section 5.2,
ROC
USB Analog PLL ground.
USB_VSS1P3
K14
GND
see
Section 5.2,
ROC
Digital core ground for USB PHY. Analog ground for USB PHY [For high speed
sensitive analog circuits].
USB_VSSA1P3
J12
GND
see
Section 5.2,
ROC
Analog ground for USB PHY [For high speed sensitive analog circuits].
USB_VSSA3P3
H13
GND
see
Section 5.2,
ROC
Analog ground for USB PHY.
USB_VSSOSC
D12
S
see
Section 5.2,
ROC
Ground for USB oscillator.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder
Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to
float. When configured as input or high-impedance state, and not driven to a known state, they may cause an excessive IO-supply
current. If this is the case, enable IPD and IPU, if applicable, or externally terminate the pins.
IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where
external pullup and pulldown resistors are required, see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
Specifies the operating I/O supply voltage for each signal
USB signal does not apply to TMS320C5532.
Terminal Configuration and Functions
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Table 4-18. Ground Signal Descriptions (continued)
SIGNAL
NAME (5)
USB_VSSREF
VSSA_ANA
NO.
F12
B6
C9
TYPE
OTHER (3)
GND
see
Section 5.2,
ROC
(1) (2)
0
(4)
DESCRIPTION (5)
Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to
USB_R1.
When the USB peripheral is not used, the USB_VSSREF signal must be connected
directly to ground (Vss).
Ground pins for power management (POR and Bandgap circuits) and 10-bit SAR
ADC
Terminal Configuration and Functions
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4.3
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Pin Multiplexing
Extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the
smallest possible package. The external bus selection register (EBSR) controls all the pin multiplexing
functions on the device.
This section discusses how to program the external bus selection register (EBSR) to select the desired
peripheral functions and pin muxing. See the individual pin mux sections for pin muxing details for a
specific muxed pin. After changing any of the pin mux control registers, it will be necessary to reset the
peripherals that are affected.
4.3.1
LCD Controller, SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] Pin Multiplexing
[EBSR.PPMODE Bits] — C5535 Only
The LCD Controller, SPI, UART, I2S2, I2S3, and GPIO signal muxing is determined by the value of the
PPMODE bit fields in the External Bus Selection Register (EBSR) register. For more details on the actual
pin functions, see Table 4-19 .
46
Terminal Configuration and Functions
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Table 4-19. LCD Controller (1), SPI, UART, I2S2, I2S3, and GP[31:27, 20:12] Pin Multiplexing
PDINHIBR3
REGISTER
BIT
FIELDS (2)
EBSR PPMODE BITS
PIN NAME
LCD_EN_RDB/SPI_CLK
MODE 0
MODE 1
MODE 2
MODE 3
MODE 4
MODE 5
MODE 6
000
(Reset default)
001
010
011
100
101
110
LCD_EN_RDB
SPI_CLK
LCD_EN_RDB
LCD_EN_RDB
LCD_EN_RDB
LCD_EN_RDB
SPI_CLK
LCD_D[0]/SPI_RX
LCD_D[0]
SPI_RX
LCD_D[0]
LCD_D[0]
LCD_D[0]
LCD_D[0]
SPI_RX
LCD_D[1]/SPI_TX
LCD_D[1]
SPI_TX
LCD_D[1]
LCD_D[1]
LCD_D[1]
LCD_D[1]
SPI_TX
P2PD
LCD_D[2]/GP[12]
LCD_D[2]
GP[12]
LCD_D[2]
LCD_D[2]
LCD_D[2]
LCD_D[2]
GP[12]
P3PD
LCD_D[3]/GP[13]
LCD_D[3]
GP[13]
LCD_D[3]
LCD_D[3]
LCD_D[3]
LCD_D[3]
GP[13]
P4PD
LCD_D[4]/GP[14]
LCD_D[4]
GP[14]
LCD_D[4]
LCD_D[4]
LCD_D[4]
LCD_D[4]
GP[14]
P5PD
LCD_D[5]/GP[15]
LCD_D[5]
GP[15]
LCD_D[5]
LCD_D[5]
LCD_D[5]
LCD_D[5]
GP[15]
P6PD
LCD_D[6]/GP[16]
LCD_D[6]
GP[16]
LCD_D[6]
LCD_D[6]
LCD_D[6]
LCD_D[6]
GP[16]
P7PD
LCD_D[7]/GP[17]
LCD_D[7]
GP[17]
LCD_D[7]
LCD_D[7]
LCD_D[7]
LCD_D[7]
GP[17]
P8PD
LCD_D[8]/I2S2_CLK/GP[18]/SPI_CLK
LCD_D[8]
I2S2_CLK
GP[18]
SPI_CLK
I2S2_CLK
SPI_CLK
I2S2_CLK
P9PD
LCD_D[9]/I2S2_FS/GP[19]/SPI_CS0
LCD_D[9]
I2S2_FS
GP[19]
SPI_CS0
I2S2_FS
SPI_CS0
I2S2_FS
P10PD
LCD_D[10]/I2S2_RX/GP[20]/SPI_RX
LCD_D[10]
I2S2_RX
GP[20]
SPI_RX
I2S2_RX
SPI_RX
I2S2_RX
P11PD
LCD_D[11]/I2S2_DX/GP[27]/SPI_TX
LCD_D[11]
I2S2_DX
GP[27]
SPI_TX
I2S2_DX
SPI_TX
I2S2_DX
P12PD
LCD_D[12]/UART_RTS/GP[28]/I2S3_CLK
LCD_D[12]
UART_RTS
GP[28]
I2S3_CLK
UART_RTS
UART_RTS
I2S3_CLK
P13PD
LCD_D[13]/UART_CTS/GP[29]/I2S3_FS
LCD_D[13]
UART_CTS
GP[29]
I2S3_FS
UART_CTS
UART_CTS
I2S3_FS
P14PD
LCD_D[14]/UART_RXD/GP[30]/I2S3_RX
LCD_D[14]
UART_RXD
GP[30]
I2S3_RX
UART_RXD
UART_RXD
I2S3_RX
P15PD
LCD_D[15]/UART_TXD/GP[31]/I2S3_DX
LCD_D[15]
UART_TXD
GP[31]
I2S3_DX
UART_TXD
UART_TXD
I2S3_DX
LCD_CS0_E0/SPI_CS0
LCD_CS0_E0
SPI_CS0
LCD_CS0_E0
LCD_CS0_E0
LCD_CS0_E0
LCD_CS0_E0
SPI_CS0
LCD_CS1_E1/SPI_CS1
LCD_CS1_E1
SPI_CS1
LCD_CS1_E1
LCD_CS1_E1
LCD_CS1_E1
LCD_CS1_E1
SPI_CS1
LCD_RW_WRB
SPI_CS2
LCD_RW_WRB
LCD_RW_WRB
LCD_RW_WRB
LCD_RW_WRB
SPI_CS2
LCD_RS
SPI_CS3
LCD_RS
LCD_RS
LCD_RS
LCD_RS
SPI_CS3
LCD_RW_WRB/SPI_CS2
LCD_RS/SPI_CS3
(1)
LCD Controller is supported on only TMS320C5535. For TMS320C5534, C5533, and C5532, the LCD Controller clock gate control bit in PCGCR2 must be disabled for a lower operating
power. For a description of disabling the bit, see TMS320C5535/34/33/32 Ultra-Low Power DSP Technical Reference Manual (literature number SPRUH87).
(2)
The pin names with PDINHIBR3 register bit field references can have the pulldown resistor enabled or disabled via this register.
Terminal Configuration and Functions
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4.3.2
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SD1, I2S1, and GP[11:6] Pin Multiplexing [EBSR.SP1MODE Bits]
The SD1, I2S1, and GPIO signal muxing is determined by the value of the SP1MODE bit fields in the
External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see
Table 4-20.
Table 4-20. SD1, I2S1, and GP[11:6] Pin Multiplexing
EBSR SP1MODE BITS
PDINHIBR1
REGISTER
BIT FIELDS (1)
(1)
PIN NAME
MODE 0
MODE 1
MODE 2
00
(Reset default)
01
10
S10PD
SD1_CLK/I2S1_CLK/GP[6]
SD1_CLK
I2S1_CLK
GP[6]
S11PD
SD1_CMD/I2S1_FS/GP[7]
SD1_CMD
I2S1_FS
GP[7]
S12PD
SD1_D0/I2S1_DX/GP[8]
SD1_D0
I2S1_DX
GP[8]
S13PD
SD1_D1/I2S1_RX/GP[9]
SD1_D1
I2S1_RX
GP[9]
S14PD
SD1_D2/GP[10]
SD1_D2
GP[10]
GP[10]
S15PD
SD1_D3/GP[11]
SD1_D3
GP[11]
GP[11]
The pin names with PDINHIBR1 register bit field references can have the pulldown register enabled or disabled via this register.
4.3.3
SD0, I2S0, and GP[5:0] Pin Multiplexing [EBSR.SP0MODE Bits]
The SD0, I2S0, and GPIO signal muxing is determined by the value of the SP0MODE bit fields in the
External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see
Table 4-21.
Table 4-21. SD0, I2S0, and GP[5:0] Pin Multiplexing
EBSR SP0MODE BITS
PDINHIBR1
REGISTER
BIT FIELDS (1)
(1)
48
PIN NAME
MODE 0
MODE 1
MODE 2
00
(Reset default)
01
10
I2S0_CLK
GP[0]
S00PD
SD0_CLK/I2S0_CLK/GP[0]
SD0_CLK
S01PD
SD0_CMD/I2S0_FS/GP[1]
SD0_CMD
I2S0_FS
GP[1]
S02PD
SD0_D0/I2S0_DX/GP[2]
SD0_D0
I2S0_DX
GP[2]
S03PD
SD0_D1/I2S0_RX/GP[3]
SD0_D1
I2S0_RX
GP[3]
S04PD
SD0_D2/GP[4]
SD0_D2
GP[4]
GP[4]
S05PD
SD0_D3/GP[5]
SD0_D3
GP[5]
GP[5]
The pin names with PDINHIBR1 register bit field references can have the pulldown register enabled or disabled via this register.
Terminal Configuration and Functions
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
5 Specifications
For the device maximum operating frequency, see Section 7.1.2, Device Nomenclature.
5.1
Absolute Maximum Ratings
Over Operating Case Temperature Range (Unless Otherwise Noted) (1)
Supply voltage ranges:
Input and Output voltage ranges:
Digital Core (CVDD, CVDDRTC , USB_VDD1P3 ) (2)
–0.5 V to 1.7 V
I/O, 1.8 V, 2.5 V, 2.75 V, 3.3 V (DVDDIO, DVDDRTC) 3.3 V
USB supplies USB PHY (USB_VDDOSC, USB_VDDPLL,
USB_VDDA3P3) (2)
–0.5 V to 4.2 V
LDOI
–0.5 V to 4.2 V
Analog, 1.3 V (VDDA_PLL, USB_VDDA1P3, VDDA_ANA) (2)
–0.5 V to 1.7 V
VI I/O, All pins with DVDDIO or USB_VDDOSC or USB_VDDPLL
or USB_VDDA3P3 as supply source
–0.5 V to 4.2 V
VO I/O, All pins with DVDDIO or USB_VDDOSC or
USB_VDDPLLor USB_VDDA3P3 as supply source
–0.5 V to 4.2 V
RTC_XI and RTC_XO
–0.5 V to 1.7 V
VI and VO, GPAIN[0]
–0.5 V to 4.2 V
VI and VO, GPAIN[3:1]
–0.5 V to 1.7 V
VO, BG_CAP
–0.5 V to 1.7 V
USB_VBUS Input
ANA_LDOO, DSP_LDOO, and USB_LDOO
Operating case temperature ranges, Tc:
(1)
(2)
(3)
-0.5 V to 5.5 V
(3)
Commercial Temperature (default)
–0.5 V to 1.7 V
-10°C to 70°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS.
DSP_LDOO on TMS320C5533 and C5532 and USB_LDOO on TMS320C5532 are not supported and must be left unconnected.
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49
TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
5.2
www.ti.com
Recommended Operating Conditions
CVDD
Core Supplies
I/O Supplies
GND
Supply voltage, Digital Core
MIN
NOM
MAX
UNIT
50 MHz
0.998
1.05
1.15
V
100 MHz
1.24
1.3
1.43
V
1.43
V
CVDDRTC
Supply voltage, RTC and RTC OSC
USB_VDD1P3
Supply voltage, Digital USB
1.24
1.3
1.43
V
USB_VDDA1P3
Supply voltage, 1.3 V Analog USB
1.24
1.3
1.43
V
VDDA_ANA
Supply voltage, 1.3 V SAR and Pwr Mgmt
1.24
1.3
1.43
V
VDDA_PLL
Supply voltage, System PLL
1.24
1.3
1.43
V
USB_VDDPLL
Supply voltage, 3.3 V USB PLL
2.97
3.3
3.63
V
Supply voltage, I/O, 3.3 V
2.97
3.3
3.63
V
Supply voltage, I/O, 2.75 V
2.48
2.75
3.02
V
Supply voltage, I/O, 2.5 V
2.25
2.5
2.75
V
DVDDIO
DVDDRTC
32.768 kHz
0.998
Supply voltage, I/O, 1.8 V
1.65
1.8
1.98
V
USB_VDDOSC
Supply voltage, I/O, 3.3 V USB OSC
2.97
3.3
3.63
V
USB_VDDA3P3
Supply voltage, I/O, 3.3 V Analog USB PHY
2.97
3.3
3.63
V
LDOI
Supply voltage, Analog Pwr Mgmt and LDO Inputs
3.6
V
VSS
Supply ground, Digital I/O
VSSRTC
Supply ground, RTC
USB_VSSOSC
Supply ground, USB OSC
USB_VSSPLL
Supply ground, USB PLL
USB_VSSA3P3
Supply ground, 3.3 V Analog USB PHY
0
V
USB_VSSA1P3
Supply ground, USB 1.3 V Analog USB PHY
USB_VSSREF
Supply ground, USB Reference Current
VSSA_PLL
Supply ground, System PLL
USB_VSS1P3
Supply ground, 1.3 V Digital USB PHY
VSSA_ANA
Supply ground, SAR and Pwr Mgmt
1.8
0
0
VIH
(1)
High-level input voltage, 3.3, 2.75, 2.5, 1.8 V I/O (except
GPAIN[3:0 ] pins) (2)
0.7 * DVDD
DVDD + 0.3
V
VIL
(1)
Low-level input voltage, 3.3, 2.75, 2.5, 1.8 V I/O (except
GPAIN[3:0 ] pins) (2)
-0.3
0.3 * DVDD
V
Input voltage, GPAIN0 pin (3)
-0.3
3.6
V
Input voltage, GPAIN[3:1] pins
-0.3
VDDA_ANA + 0.3
V
-10
70
°C
VIN
Tc
Operating case temperature
Default
(Commercial)
FSYSCLK
DSP Operating Frequency (SYSCLK)
1.05 V
0
50
MHz
1.3 V
0
100
MHz
(1)
(2)
(3)
50
DVDD refers to the pin I/O supply voltage. To determine the I/O supply voltage for each pin, see Section 4.2, Signal Descriptions.
The I2C pin SDA and SCL do not feature fail-safe I/O buffers. These pin could potentially draw current when the DVDDIO is powered
down. Due to the fact that different voltage devices can be connected to I2C bus and the I2C inputs are LVCMOS, the level of logic 0
(low) and logic 1 (high) are not fixed and depend on DVDDIO.
The GNDON bit in the SARPINCTRL register must be set to "1" before SAR channels 0, 1, or 2 are enabled via the CHSEL bit in the
SARCTRL register, when VIN greater than VDDA_ANA.
Specifications
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5.3
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Electrical Characteristics
Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)
PARAMETER
VOH
VOL
VLDO
IIHPD
(6) (7)
(6) (7)
IIH/
IIL (7)
IOH
(7)
(8)
MAX
High speed: USB_DN and
USB_DP (2)
360
440
UNIT
V
mV
High-level output voltage, 3.3,
2.75, 2.5, 1.8 V I/O (except
GPAIN[3:0 ] pins)
IO = IOH
0.8 * DVDD
V
High-level output voltage,
GPAIN[3:1] pins
IO = IOH
0.8 * VDDA_ANA
V
Full speed: USB_DN and
USB_DP (2)
0.0
0.3
V
High speed: USB_DN and
USB_DP (2)
–10
10
mV
Low-level output voltage, 3.3,
2.75, 2.5, 1.8V I/O (except I2C
and GPAIN[3:0 ] pins)
IO = IOL
Low-level output voltage, I2C
pins (3)
VDD > 2 V, IO L = 3 mA
Low-level output voltage,
GPAIN[3:0 ] pins
IO = IOL
0
0.2 * DVDD
V
0.4
V
0.2 * VDDA_ANA
V
DVDD = 3.3 V
162
mV
DVDD = 2.5 V
141
mV
DVDD = 1.8 V
122
mV
USB_LDOO voltage
1.24
1.3
1.43
V
ANA_LDOO voltage
1.24
1.3
1.43
V
DSP_LDO_V bit in the LDOCNTL register = 1
1.24
1.3
1.43
V
DSP_LDO_V bit in the LDOCNTL register = 0
0.998
1.05
1.15
DSP_LDO shutdown current (5)
LDOI = VMIN
ANA_LDO shutdown current (5)
USB_LDO shutdown current (5)
Input current [DC] (except
WAKEUP, I2C and GPAIN[3:0 ]
pins)
Input current [DC] (except
WAKEUP, I2C and GPAIN[3:0 ]
pins)
V
250
mA
LDOI = VMIN
4
mA
LDOI = VMIN
25
Input only pin, internal pulldown or pullup disabled
-5
mA
+5
μA
DVDD = 3.3 V with internal pullup enabled
(8)
-59 to
-161
μA
DVDD = 2.5 V with internal pullup enabled
(8)
-31 to -93
μA
DVDD = 1.8 V with internal pullup enabled (8)
-14 to -44
Input only pin, internal pulldown or pullup disabled
-5
μA
+5
μA
DVDD = 3.3 V with internal pulldown enabled (8)
52 to 158
μA
DVDD = 2.5 V with internal pulldown enabled (8)
27 to 83
μA
DVDD = 1.8 V with internal pulldown enabled (8)
11 to 35
μA
VI = VSS to DVDD with internal pullups and
pulldowns disabled.
-5
All Pins (except USB, CLKOUT, and GPAIN[3:0 ]
pins)
-4
mA
DVDD = 3.3 V
-6
mA
DVDD = 1.8 V
-4
mA
High-level output current [DC]
CLKOUT pin
(1)
(2)
(3)
(4)
(5)
(6)
TYP
USB_VDDA3P3
Input current [DC], ALL pins
(7)
MIN
2.8
DSP_LDOO voltage
ISD
(1)
Full speed: USB_DN and
USB_DP (2)
Input hysteresis (4)
VHYS
IILPU
TEST CONDITIONS
+5
μA
For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
The USB I/Os adhere to the Universal Bus Specification Revision 2.0 (USB2.0 spec).
VDD is the voltage to which the I2C bus pullup resistors are connected.
Applies to all input pins except WAKEUP, I2C pins, GPAIN[3:0 ], RTC_XI, and USB_MXI.
ISD is the amount of current the LDO is ensured to deliver before shutting down to protect itself.
II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
When CVDD power is "ON", the pin bus-holders are disabled. For more detailed information, see Section 5.7.2.5, Digital I/O Behavior
When Core Power (CVDD) is Down.
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
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TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
www.ti.com
Electrical Characteristics (continued)
Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
mA
(GPAIN0 is open-drain DV = V
DDA_ANA = 1.3
and cannot drive high) V, DD
Internal Regulator (9)
-100
μA
All Pins (except USB, CLKOUT, and GPAIN[3:0 ])
(7)
Low-level output current [DC]
CLKOUT pin
GPAIN[3:0 ]
IOZ
(10)
I/O Off-state output current
+4
mA
DVDD = 3.3 V
+6
mA
DVDD = 1.8 V
+4
mA
DVDD = VDDA_ANA = 1.3
V, external regulator
+4
mA
DVDD = VDDA_ANA = 1.3
V, internal regulator (9)
+4
mA
μA
All Pins (except USB and GPAIN[3:0 ])
-10
+10
GPAIN[3:0 ] pins
-10
+10
μA
2.2
mA
1.6
mA
1.4
mA
0.72
mA
Supply voltage, I/O, 3.3 V
IOLBH
(11)
Bus Holder pull low current when
Supply voltage, I/O, 2.75 V
CVDD is powered "OFF"
Supply voltage, I/O, 2.5 V
Supply voltage, I/O, 1.8 V
IOHBH
(11)
Bus Holder pull high current
when CVDD is powered "OFF"
UNIT
-4
GPAIN[3:1] pins
IOL
MAX
DVDD = VDDA_ANA = 1.3
V,
External Regulator (9)
Supply voltage, I/O, 3.3 V
-1.3
mA
Supply voltage, I/O, 2.75 V
-0.97
mA
Supply voltage, I/O, 2.5 V
-0.83
mA
Supply voltage, I/O, 1.8 V
-0.46
mA
(9)
When the ANA_LDO supplies VDDA_ANA, it is not recommended to use the GPAIN[3:1] signals for general-purpose outputs (driving
high). The ISD parameter of the ANA_LDO is too low to drive any realistic load on the GPAIN[3:1] pins while also supplying the PLL
through VDDA_PLL and the SAR through VDDA_ANA .
(10) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
(11) This parameter specifies the maximum strength of the Bus Holder and is needed to calculate the minimum strength of external pull-ups
and pull-downs.
52
Specifications
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Electrical Characteristics (continued)
Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
Active, CVDD = 1.3 V, DSP clock = 100 MHz,
Clock source = RTC on-chip Oscillator
0.22
mW/MHz
0.15
mW/MHz
0.22
mW/MHz
0.14
mW/MHz
0.44
mW
0.26
mW
0.40
mW
0.23
mW
0.28
mW
0.15
mW
0.7
mA
Room Temp (25 °C), 75% DMAC + 25% ADD
(typical sine wave data switching)
Active, CVDD = 1.05 V, DSP clock = 50 MHz,
Clock source = RTC on-chip Oscillator
Room Temp (25 °C), 75% DMAC + 25% ADD
(typical data switching)
Active, CVDD = 1.3 V, DSP clock = 100 MHz,
Clock source = RTC on-chip Oscillator
Room Temp (25 °C), 75% DMAC + 25% NOP
(typical sine wave data switching)
Active, CVDD = 1.05 V, DSP clock = 50 MHz,
Clock source = RTC on-chip Oscillator
Room Temp (25 °C), 75% DMAC + 25% NOP
(typical data switching)
Standby, CVDD = 1.3 V, Master clock disabled,
Clock source = RTC on-chip Oscillator
P
Core (CVDD) supply power
Room Temp (25 °C), DARAM and SARAM in
active mode
Standby, CVDD = 1.05 V, Master clock disabled,
Clock source = RTC on-chip Oscillator
Room Temp (25 °C), DARAM and SARAM in
active mode
Standby, CVDD = 1.3 V, Master clock disabled,
Clock source = RTC on-chip Oscillator
Room Temp (25 °C), DARAM in retention and
SARAM in active mode
Standby, CVDD = 1.05 V, Master clock disabled,
Clock source = RTC on-chip Oscillator
Room Temp (25 °C), DARAM in retention and
SARAM in active mode
Standby, CVDD = 1.3 V, Master clock disabled,
Clock source = RTC on-chip Oscillator
Room Temp (25 °C), DARAM in active mode and
SARAM in retention
Standby, CVDD = 1.05 V, Master clock disabled,
Clock source = RTC on-chip Oscillator
Room Temp (25 °C), DARAM in active mode and
SARAM in retention
I
Analog PLL (VDDA_PLL) supply
current
SAR Analog (VDDA_ANA) supply
current
VDDA_PLL = 1.3 V
Room Temp (25 °C), Phase detector = 170 kHz,
VCO = 100 MHz
VDDA_ANA = 1.3 V, SAR clock = 2 MHz, Temp
1
mA
(70 °C)
CI
Input capacitance
4
pF
Co
Output capacitance
4
pF
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Specifications
53
TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
5.4
Handling Ratings
MIN
MAX
UNIT
–65
150
ºC
Human Body Model (HBM) (2)
0
> 1000
V
Charged Device Model (CDM) (3)
0
> 250
V
Storage temperature
range, Tstg
(default)
ESD Stress Voltage (1)
(1)
(2)
(3)
www.ti.com
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by electrostatic discharges into the device.
Level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe
manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary precautions
are taken. Pins listed as 1000 V may actually have higher performance.
Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe
manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.
Section 5.5 shows the thermal resistance characteristics for the PBGA–ZHH mechanical package.
5.5
Thermal Characteristics
°C/W (1)
AIR FLOW (m/s) (2)
N/A
RTJC
Junction-to-case
1S0P
12.53
RTJB
Junction-to-board
2S2P
38
N/A
RTJA
Junction-to-free air
2S2P
50
0.00
PsiJT
Junction-to-package top
2S2P
0.49
0.00
PsiJB
Junction-to-board
2S2P
37.4
0.00
(1)
(2)
5.6
These measurements were conducted in a JEDEC-defined 1S0P/2S2P system and will change based on environment as well as
application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method
Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded
Surface Mount Packages.
m/s = meters per second
Power-On Hours
Over Operating Case Temperature Range (Unless Otherwise Noted)
Device Operating Life
Power-On Hours (POH)
(1)
54
(1)
DSP Operating Frequency
(SYSCLK ) ≤100 MHz
<70 °C
100,000 POH
This information is provided solely for your convenience and does not extend or modify the warranty provided under TI’s standard terms
and conditions for TI semiconductor products.
Specifications
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5.7
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Timing and Switching Characteristics
5.7.1
Parameter Information
Tester Pin Electronics
42 Ω
3.5 nH
Transmission Line
Z0 = 50 Ω
(see Note)
4.0 pF
1.85 pF
Data Sheet Timing Reference Point
Output
Under
Test
Device Pin
(see Note)
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 5-1. 3.3-V Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
5.7.1.1
1.8-V, 2.5-V, 2.75-V, and 3.3-V Signal Transition Levels
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL
MAX and VOH MIN for output clocks.
Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
Figure 5-2. Rise and Fall Transition Time Voltage Reference Levels
5.7.1.2
3.3-V Signal Transition Rates
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
5.7.1.3
Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routing. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing or decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report (literature number SPRA839). If needed, external logic hardware such as
buffers may be used to compensate any timing differences.
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55
TMS320C5535, TMS320C5534, TMS320C5533, TMS320C5532
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
5.7.2
www.ti.com
Power Supplies
5.7.2.1
Power Considerations for C5535 and C5534
The device provides several means of managing power consumption.
To
•
•
•
•
•
•
•
•
minimize power consumption, the device divides its circuits into nine main isolated supply domains:
LDOI (LDOs and Bandgap Power Supply)
Analog POR, SAR, and PLL (VDDA_ANA and VDDA_PLL) (2)
RTC Core (CVDDRTC)
Note: CVDDRTC must always be powered by an external power source and none of the on-chip LDOs
can be used to power CVDDRTC.
Digital Core (CVDD)
USB Core (USB_ VDD1P3 and USB_VDDA1P3)
USB PHY and USB PLL (USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL)
RTC I/O (DVDDRTC)
Rest of the I/O (DVDDIO)
5.7.2.1.1 LDO Configuration
The device includes Low-Dropout Regulators (LDOs) which can be used to regulate the power supplies of
the analog PLL and SAR ADC and Power Management (ANA_LDO), Digital Core (DSP_LDO), and USB
Core (USB_LDO).
These LDOs are controlled by a combination of pin configuration and register settings. For more detailed
information see the following sections.
5.7.2.1.1.1 LDO Inputs
The LDOI pins (B10, B14, C14) provide power to the internal Analog LDO, DSP LDO, USB LDO, the
bandgap reference generator, and some I/O input pins, and can range from 1.8 V to 3.6 V. The bandgap
provides accurate voltage and current references to the POR, LDOs, PLL, and SAR ; therefore, for proper
device operation, power must always be applied to the LDOI pins even if the LDO outputs are not used.
5.7.2.1.1.2 LDO Outputs
The ANA_LDOO pin (B9) is the output of the internal ANA_LDO and can provide regulated 1.3 V power of
up to 4 mA. The ANA_LDOO pin is intended to be connected, on the board, to the VDDA_ANA and VDDA_PLL
pins to provide a regulated 1.3 V to the 10-bit SAR ADC, Power Management Circuits and System PLL.
VDDA_ANA and VDDA_PLL may be powered by this LDO output, which is recommended, to take advantage of
the device's power management techniques, or by an external power supply. The ANA_LDO cannot be
disabled individually (see Section 5.7.2.1.1.3, LDO Control).
The DSP_LDOO pin (A13) is the output of the internal DSP_LDO and provides software-selectable
regulated 1.3 V or regulated 1.05 V power of up to 250 mA. The DSP_LDOO pin is intended to be
connected, on the board, to the CVDD pins. In this configuration, the DSP_LDO_EN pin must be tied to the
board VSS, thus enabling the DSP_LDO. Optionally, the CVDD pins may be powered by an external power
supply; in this configuration the DSP_LDO_EN pin must be tied (high) to LDOI, disabling DSP_LDO. The
DSP_LDO_EN also affects how reset is generated to the chip (for more details, see the DSP_LDO_EN
pin description in Table 4-15, Regulators and Power Management Signal Descriptions). When the
DSP_LDO is disabled, its output pin is in a high-impedance state. Note: DSP_LDO_EN is not intended to
be changed dynamically.
When DSP_LDO comes out of reset, it is enabled to 1.3 V for the bootloader to operate. For the 50-MHz
devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CVDD, for proper operation
after reset.
(2)
56
SAR applies to only TMS320C5535.
Specifications
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
The USB_LDOO pin (D13 ) is the output of the internal USB_LDO and provides regulated 1.3 V, softwareswitchable (on and off) power of up to 25 mA. The USB_LDOO pin is intended to be connected, on the
board, to the USB_VDD1P3 and USB_VDDA1P3 pins to provide power to portions of the USB. Optionally, the
USB_VDD1P3 and USB_VDDA1P3 may be powered by an external power supply and the USB_LDO can be
left disabled. When the USB_LDO is disabled, its output pin is in a high-impedance state.
5.7.2.1.1.3 LDO Control
All LDOs can be simultaneously disabled via software by writing to either the BG_PD bit or the LDO_PD
bit in the RTCPMGT register (see Figure 5-3). When the LDOs are disabled via this mechanism, the only
way to re-enable them is by asserting the WAKEUP signal pin (which must also have been previously
enabled to allow wakeup), or by a previously enabled and configured RTC alarm, or by cycling power to
the CVDDRTC pin.
ANA_LDO: The ANA_LDO is only disabled by the BG_PD and the LDO_PD mechanism described above.
Otherwise, it is always enabled.
DSP_LDO: The DSP_LDO can be statically disabled by the DSP_LDO_EN pin as described in
Section 5.7.2.1.1.2, LDO Outputs. The DSP_LDO can be also dynamically disabled via the BG_PD and
the LDO_PD mechanism described above. The DSP_LDO can change its output voltage dynamically by
software via the DSP_LDO_V bit in the LDOCNTL register (see Figure 5-4). The DSP_LDO output voltage
is set to 1.3 V at reset.
For the 50 -MHz devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CVDD, for
proper operation after reset.
USB_LDO: The USB_LDO can be independently and dynamically enabled or disabled by software via the
USB_LDO_EN bit in the LDOCNTL register (see Figure 5-4). The USB _LDO is disabled at reset.
Table 5-3 shows the ON and OFF control of each LDO and its register control bit configurations.
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Figure 5-3. RTC Power Management Register (RTCPMGT) [1930h]
15
14
13
12
11
10
9
8
4
WU_DOUT
3
WU_DIR
2
BG_PD
1
LDO_PD
R/W-1
R/W-0
R/W-0
R/W-0
0
RTCCLKOUTE
N
R/W-0
Reserved
R-0
7
6
Reserved
5
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-1. RTCPMGT Register Bit Descriptions
BIT
NAME
15:5
RESERVED
Reserved. Read-only, writes have no effect.
4
WU_DOUT
Wakeup output, active low, open-drain.
0 = WAKEUP pin driven low.
1 = WAKEUP pin is in high-impedance (Hi-Z).
3
WU_DIR
DESCRIPTION
Wakeup pin direction control.
0 = WAKEUP pin configured as a input.
1 = WAKEUP pin configured as a output.
Note: When the WAKEUP pin is configured as an input, it is active high. When the WAKEUP pin is
configured as an output, is an open-drain that is active low and must be externally pulled-up via a
10-kΩ resistor to DVDDRTC. WU_DIR must be configured as an input to allow the WAKEUP pin to
wake the device up from idle modes.
Bandgap, on-chip LDOs, and the analog POR power down bit.
This bit shuts down the on-chip LDOs (ANA_LDO, DSP_LDO, and USB_LDO), the Analog POR,
and Bandgap reference. BG_PD and LDO_PD are only intended to be used when the internal
LDOs supply power to the chip. If the internal LDOs are bypassed and not used then the BG_PD
and LDO_PD power down mechanisms should not be used since POR gets powered down and the
POWERGOOD signal is not generated properly.
2
BG_PD
After this bit is asserted, the on-chip LDOs, Analog POR, and the Bandgap reference can be reenabled by the WAKEUP pin (high) or the RTC alarm interrupt. The Bandgap circuit will take about
100 msec to charge the external 0.1 μF capacitor via the internal 326-kΩ resistor.
0 = On-chip LDOs, Analog POR, and Bandgap reference are enabled.
1 = On-chip LDOs, Analog POR, and Bandgap reference are disabled (shutdown).
On-chip LDOs and Analog POR power down bit.
1
LDO_PD
This bit shuts down the on-chip LDOs (ANA_LDO, DSP_LDO, and USB_LDO) and the Analog
POR. BG_PD and LDO_PD are only intended to be used when the internal LDOs supply power to
the chip. If the internal LDOs are bypassed and not used then the BG_PD and LDO_PD power
down mechanisms should not be used since POR gets powered down and the POWERGOOD
signal is not generated properly.
After this bit is asserted, the on-chip LDOs and Analog POR can be re-enabled by the WAKEUP
pin (high) or the RTC alarm interrupt. This bit keeps the Bandgap reference turned on to allow a
faster wake-up time with the expense power consumption of the Bandgap reference.
0 = On-chip LDOs and Analog POR are enabled.
1 = On-chip LDOs and Analog POR are disabled (shutdown).
Clockout output enable bit.
0
RTCCLKOUTEN
0 = Clock output disabled.
1 = Clock output enabled.
58
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Figure 5-4. LDO Control Register (LDOCNTL) [7004h]
15
14
13
12
11
10
9
8
3
2
1
DSP_LDO_V
R/W-0
0
USB_LDO_EN
R/W-0
Reserved
R-0
7
6
5
4
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-2. LDOCNTL Register Bit Descriptions
BIT
NAME
15:2
Reserved
DESCRIPTION
Reserved. Read-only, writes have no effect.
DSP_LDO voltage select bit.
0 = DSP_LDOO is regulated to 1.3 V.
1
DSP_LDO_V
1 = DSP_LDOO is regulated to 1.05 V
Note: For the 50 -MHz devices, DSP_LDO must be programmed to 1.05 V to match the core
voltage, CVDD, for proper operation after reset.
USB_LDO enable bit.
0
USB_LDO_EN
0 = USB_LDO output is disabled. USB_LDOO pin is placed in high-impedance (Hi-Z) state.
1 = USB_LDO output is enabled. USB_LDOO is regulated to 1.3 V.
Table 5-3. LDO Controls Matrix
RTCPMGT Register
(1930h)
LDOCNTL Register
(7004h)
BG_PD Bit
LDO_PD Bit
USB_LDO_EN Bit
DSP_LDO_EN
(Pin C13 )
ANA_LDO
DSP_LDO
USB_LDO
1
Don't Care
Don't Care
Don't Care
OFF
OFF
OFF
Don't Care
1
Don't Care
Don't Care
OFF
OFF
OFF
0
0
0
Low
ON
ON
OFF
0
0
0
High
ON
OFF
OFF
0
0
1
Low
ON
ON
ON
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
5.7.2.2
www.ti.com
Power Considerations for C5533
The device provides several means of managing power consumption.
To
•
•
•
•
•
•
•
•
minimize power consumption, the device divides its circuits into nine main isolated supply domains:
LDOI (LDOs and Bandgap Power Supply)
Analog POR and PLL (VDDA_ANA and VDDA_PLL)
RTC Core (CVDDRTC)
Digital Core (CVDD)
USB Core (USB_ VDD1P3 and USB_VDDA1P3)
USB PHY and USB PLL (USB_VDDOSC, USB_VDDA3P3, and USB_VDDPLL)
RTC I/O (DVDDRTC)
Rest of the I/O (DVDDIO)
5.7.2.2.1 LDO Configuration
The device includes two Low-Dropout Regulators (LDOs) which can be used to regulate the power
supplies of the analog PLL and Power Management (ANA_LDO) and USB Core (USB_LDO).
These LDOs are controlled by a combination of pin configuration and register settings. For more detailed
information see the following sections.
5.7.2.2.1.1 LDO Inputs
The LDOI pins (B10, B14, C14) provide power to the internal Analog and USB LDOs, the bandgap
reference generator, and some I/O input pins, and can range from 1.8 V to 3.6 V. The bandgap provides
accurate voltage and current references to the POR, LDOs, and PLL; therefore, for proper device
operation, power must always be applied to the LDOI pins even if the LDO outputs are not used.
5.7.2.2.1.2 LDO Outputs
The ANA_LDOO pin (B9) is the output of the internal ANA_LDO and can provide regulated 1.3 V power of
up to 4 mA. The ANA_LDOO pin is intended to be connected, on the board, to the VDDA_ANA and VDDA_PLL
pins to provide a regulated 1.3 V to the Power Management Circuits and System PLL. VDDA_ANA and
VDDA_PLL may be powered by this LDO output, which is recommended, to take advantage of the device's
power management techniques, or by an external power supply. The ANA_LDO cannot be disabled
individually (see Section 5.7.2.1.1.3, LDO Control).
The USB_LDOO pin (D13) is the output of the internal USB_LDO and provides regulated 1.3 V, softwareswitchable (on and off) power of up to 25 mA. The USB_LDOO pin is intended to be connected, on the
board, to the USB_VDD1P3 and USB_VDDA1P3 pins to provide power to portions of the USB. Optionally, the
USB_VDD1P3 and USB_VDDA1P3 may be powered by an external power supply and the USB_LDO can be
left disabled. When the USB_LDO is disabled, its output pin is in a high-impedance state.
5.7.2.2.1.3 LDO Control
Both LDOs can be simultaneously disabled via software by writing to either the BG_PD bit or the LDO_PD
bit in the RTCPMGT register (see Figure 5-3). When the LDOs are disabled via this mechanism, the only
way to re-enable them is by asserting the WAKEUP signal pin (which must also have been previously
enabled to allow wakeup), or by a previously enabled and configured RTC alarm, or by cycling power to
the CVDDRTC pin.
ANA_LDO: The ANA_LDO is only disabled by the BG_PD and the LDO_PD mechanism described above.
Otherwise, it is always enabled.
USB_LDO: The USB_LDO can be independently and dynamically enabled or disabled by software via the
USB_LDO_EN bit in the LDOCNTL register (see Figure 5-4). The USB _LDO is disabled at reset.
Table 5-3 shows the ON and OFF control of each LDO and its register control bit configurations.
60
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Figure 5-5. RTC Power Management Register (RTCPMGT) [1930h]
15
14
13
12
11
10
9
8
4
WU_DOUT
3
WU_DIR
2
BG_PD
1
LDO_PD
R/W-1
R/W-0
R/W-0
R/W-0
0
RTCCLKOUTE
N
R/W-0
Reserved
R-0
7
6
Reserved
5
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-4. RTCPMGT Register Bit Descriptions
BIT
NAME
15:5
RESERVED
Reserved. Read-only, writes have no effect.
4
WU_DOUT
Wakeup output, active low, open-drain.
0 = WAKEUP pin driven low.
1 = WAKEUP pin is in high-impedance (Hi-Z).
3
2
WU_DIR
BG_PD
DESCRIPTION
Wakeup pin direction control.
0 = WAKEUP pin configured as a input.
1 = WAKEUP pin configured as a output.
Note: When the WAKEUP pin is configured as an input, it is active high. When the WAKEUP pin is
configured as an output, is an open-drain that is active low and must be externally pulled-up via a
10-kΩ resistor to DVDDRTC. WU_DIR must be configured as an input to allow the WAKEUP pin to
wake the device up from idle modes.
Bandgap, on-chip LDOs, and the analog POR power down bit.
This bit shuts down the on-chip LDOs (ANA_LDO and USB_LDO), the Analog POR, and Bandgap
reference. BG_PD and LDO_PD are only intended to be used when the internal LDOs supply
power to the chip. If the internal LDOs are bypassed and not used then the BG_PD and LDO_PD
power down mechanisms should not be used since POR gets powered down and the
POWERGOOD signal is not generated properly.
After this bit is asserted, the on-chip LDOs, Analog POR, and the Bandgap reference can be reenabled by the WAKEUP pin (high) or the RTC alarm interrupt. The Bandgap circuit will take about
100 msec to charge the external 0.1 uF capacitor via the internal 326-kΩ resistor.
0 = On-chip LDOs, Analog POR, and Bandgap reference are enabled.
1 = On-chip LDOs, Analog POR, and Bandgap reference are disabled (shutdown).
1
LDO_PD
On-chip LDOs and Analog POR power down bit.
This bit shuts down the on-chip LDOs (ANA_LDO and USB_LDO) and the Analog POR. BG_PD
and LDO_PD are only intended to be used when the internal LDOs supply power to the chip. If the
internal LDOs are bypassed and not used then the BG_PD and LDO_PD power down mechanisms
should not be used since POR gets powered down and the POWERGOOD signal is not generated
properly.
After this bit is asserted, the on-chip LDOs and Analog POR can be re-enabled by the WAKEUP
pin (high) or the RTC alarm interrupt. This bit keeps the Bandgap reference turned on to allow a
faster wake-up time with the expense power consumption of the Bandgap reference.
0 = On-chip LDOs and Analog POR are enabled.
1 = On-chip LDOs and Analog POR are disabled (shutdown).
0
RTCCLKOUTEN
Clockout output enable bit.
0 = Clock output disabled.
1 = Clock output enabled.
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Figure 5-6. LDO Control Register (LDOCNTL) [7004h]
15
14
13
12
11
10
9
8
3
2
1
0
USB_LDO_EN
R/W-0
Reserved
R-0
7
6
5
4
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-5. LDOCNTL Register Bit Descriptions
BIT
NAME
15:1
RESERVED
0
USB_LDO_EN
DESCRIPTION
Reserved. Read-only. Writes have no effect.
USB_LDO enable bit.
0 = USB_LDO output is disabled. USB_LDOO pin is placed in high-impedance (Hi-Z) state.
1 = USB_LDO output is enabled. USB_LDOO is regulated to 1.3 V.
Table 5-6. LDO Controls Matrix
RTCPMGT Register
(1930h)
62
LDOCNTL Register
(7004h)
BG_PD Bit
LDO_PD Bit
USB_LDO_EN Bit
DSP_LDO_EN
(Pin C13)
ANA_LDO
USB_LDO
1
Don't Care
Don't Care
High
OFF
OFF
Don't Care
1
Don't Care
High
OFF
OFF
0
0
0
High
ON
OFF
0
0
0
High
ON
OFF
0
0
1
High
ON
ON
Specifications
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5.7.2.3
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Power Considerations for C5532
The device provides several means of managing power consumption.
To
•
•
•
•
•
•
minimize power consumption, the device divides its circuits into nine main isolated supply domains:
LDOI (ANA_LDO and Bandgap Power Supply)
Analog POR and PLL (VDDA_ANA and VDDA_PLL)
RTC Core (CVDDRTC)
Digital Core (CVDD)
RTC I/O (DVDDRTC)
Rest of the I/O (DVDDIO)
5.7.2.3.1 LDO Configuration
The device includes one Low-Dropout Regulators (LDO) which can be used to regulate the power
supplies of the analog PLL.
5.7.2.3.2 LDO Inputs
The LDOI pins (B10, B14, C14) provide power to the internal Analog LDO, the bandgap reference
generator, and some I/O input pins, and can range from 1.8 V to 3.6 V. The bandgap provides accurate
voltage and current references to the LDO PLL; therefore, for proper device operation, power must always
be applied to the LDOI pins even if the LDO output is not used.
5.7.2.3.3 LDO Outputs
The ANA_LDOO pin (B9) is the output of the internal ANA_LDO and can provide regulated 1.3 V power of
up to 4 mA. The ANA_LDOO pin is intended to be connected, on the board, to the VDDA_ANA and
VDDA_PLL pins to provide a regulated 1.3 V to the System PLL. VDDA_ANA and VDDA_PLL may be
powered by this LDO output. However, when VDDA_PLL requires 1.4 V, VDDA_PLL must be powered
externally and ANA_LDO output can provide a regulated 1.3 V, but only to VDDA_ANA, not both.
NOTE
The DSP_LDOO is not supported on TMS320C5532. However, DSP_LDO can be enabled to
support the RTC only mode (see Section 5.7.11.1, RTC Only Mode, for details). Otherwise,
DSP_LDO must be disabled on this device and the DSP_LDO output pin must be left
unconnected. The USB_LDOO is not supported on this device, so the USB_LDO must be
left disabled. USB_LDO is disabled at reset, so it does not require any action to disable the
USB_LDO. When the USB_LDO is disabled, the USB_LDOO pin is in a high-impedance (HiZ) state and must be left unconnected.
5.7.2.4
Power-Supply Sequencing
NOTE
The external reset signal on the RESET pin must be held low until all of the power supplies
reach their operating voltage conditions.
The device includes four core voltage-level supplies (CVDD, CVDDRTC, USB_VDD1P3, USB_VDDA1P3 ), and
four I/O supplies (DVDDIO, DVDDRTC, USB_VDDOSC, and USB_VDDA3P3).
Some TI power-supply devices include features that facilitate power sequencing—for example, Auto-Track
and Slow-Start and Enable features. For more information regarding TI's power management products
and suggested devices to power TI DSPs, visit www.ti.com/processorpower.
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The device does not require a specific power-up sequence. However, if the DSP_LDO is disabled
(DSP_LDO_EN = high) and an external regulator supplies power to the CPU Core (CVDD), the external
reset signal (RESET) must be held asserted until all of the supply voltages reach their valid operating
ranges.
The I/O design allows either the core supplies (CVDD, CVDDRTC , USB_VDD1P3, USB_VDDA1P3 ) or the I/O
supplies (DVDDIO, DVDDRTC , USB_VDDOSC, and USB_VDDA3P3 ) to be powered up for an indefinite period of
time while the other supply is not powered if the following constraints are met:
1. All maximum ratings and recommended operating conditions are satisfied.
2. All warnings about exposure to maximum rated and recommended conditions, particularly junction
temperature are satisfied. These apply to power transitions as well as normal operation.
3. Bus contention while core supplies are powered must be limited to 100 hours over the projected
lifetime of the device.
4. Bus contention while core supplies are powered down does not violate the absolute maximum ratings.
If the USB subsystem is used, the subsystem must be powered up in the following sequence:
1. USB_VDDA1P3 and USB_VDD1P3
2. USB_VDDA3P3
3. USB_VBUS
If the USB subsystem is not used, the following can be powered off:
• USB Core
– USB_VDD1P3
– USB_VDDA1P3
• USB PHY and I/O Level Supplies
– USB_VDDOSC
– USB_VDDA3P3
– USB_VDDPLL
A supply bus is powered up when the voltage is within the recommended operating range. The supply bus
is powered down when the voltage is below that range, either stable or while in transition.
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5.7.2.5
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Digital I/O Behavior When Core Power (CVDD) is Down
With some exceptions (listed below), all digital I/O pins on the device have special features to allow
powering down of the Digital Core Domain (CVDD) without causing I/O contentions or floating inputs at the
pins (see Figure 5-7). The device asserts the internal signal called HHV high when power has been
removed from the Digital Core Domain (CVDD). Asserting the internal HHV signal causes the following
conditions to occur in any order:
• All output pin strong drivers to go to the high-impedance (Hi-Z) state
• Weak bus holders to be enabled to hold the pin at a valid high or low
• The internal pullups or pulldowns (IPUs and IPDs) on the I/O pins will be disabled
The exception pins that do not have this special feature are:
• Pins driven by the CVDDRTC Power Domain [This power domain is "Always On"; therefore, the pins
driven by CVDDRTC do not need these special features]:
– RTC_XI, RTC_XO, RTC_CLKOUT, and WAKEUP
• USB Pins:
– USB_DP, USB_DM, USB_R1, USB_VBUS, USB_MXI, and USB_MXO
• Pins for the Analog Block:
– GPAIN[3:0 ], DSP_LDO_EN and BG_CAP
DVDD
Y
PAD
A
GZ
hhvgz
HHV
OR
HHV
PI
hhvpi
OR
HHV
Figure 5-7. Bus Holder I/O Circuit
NOTE
Figure 5-7 shows both a pullup and pulldown but pins have only one, not both.
PI = Pullup and pulldown Inhibit
GZ = Output Enable (active low)
HHV = Described in Section 5.7.2.5
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
5.7.2.6
www.ti.com
Power-Supply Design Considerations
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the device, the PC board should include separate power planes for core, I/O,
VDDA_ANA and VDDA_PLL (which can share the same PCB power plane), and ground; all bypassed with
high–quality low–ESL and ESR capacitors.
5.7.2.7
Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place capacitors (caps) as close as
possible to the device. These caps need to be no more than 1.25 cm maximum distance from the device
power pins to be effective. Physically smaller caps, such as 0402, are better but need to be evaluated
from a yield and manufacturing point-of-view. Parasitic inductance limits the effectiveness of the
decoupling capacitors, therefore physically smaller capacitors must be used while maintaining the largest
available capacitance value.
Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order
of 10 μF) should be furthest away, but still as close as possible. Large caps for each supply should be
placed outside of the BGA footprint.
As with the selection of any component, verification of capacitor availability over the product's production
lifetime must be considered.
The recommended decoupling capacitance for the DSP core supplies should be 1 μF in parallel with 0.01μF capacitor per supply pin.
5.7.2.8
LDO Input Decoupling
The LDO inputs should follow the same decoupling guidelines as other power-supply pins above.
5.7.2.9
LDO Output Decoupling
The LDO circuits implement a voltage feedback control system which has been designed to optimize gain
and stability tradeoffs. As such, there are design assumptions for the amount of capacitance on the LDO
outputs. For proper device operation, the following external decoupling capacitors must be used when the
on-chip LDOs are enabled:
• ANA_LDOO– 1μF
• DSP_LDOO – 5μF ~ 10μF
• USB_LDOO – 1μF ~ 2μF
66
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5.7.3
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Reset
The device has two main types of reset: hardware reset and software reset.
Hardware reset is responsible for initializing all key states of the device. The hardware reset occurs
whenever the RESET pin is asserted or when the internal power-on-reset (POR) circuit deasserts an
internal signal called POWERGOOD. The device's internal POR is a voltage comparator that monitors the
DSP_LDOO pin voltage and generates the internal POWERGOOD signal when the DSP_LDO is enabled
externally by the DSP_LDO_EN pin. POWERGOOD is asserted when the DSP_LDOO voltage is above a
minimum threshold voltage provided by the bandgap. When the DSP_LDO is disabled (DSP_LDO_EN is
high), the internal voltage comparator becomes inactive, and the POWERGOOD signal logic level is
immediately set high. The RESET pin and the POWERGOOD signal are internally combined with a logical
AND gate to produce an (active low) hardware reset (see Figure 5-8, Power-On Reset Timing
Requirements and Figure 5-9, Reset Timing Requirements).
There are two types of software reset: the CPU's software reset instruction and the software control of the
peripheral reset signals. For more information on the CPU's software reset instruction, see the
TMS320C55x CPU 3.0 CPU Reference Guide (literature number: SWPU073). In all the device
documentation, all references to "reset" refer to hardware reset. Any references to software reset will
explicitly state software reset.
The device RTC has one additional type of reset, a power-on-reset (POR) for the registers in the RTC
core. This POR monitors the voltage of CVDDRTC and resets the RTC registers when power is first applied
to the RTC core.
5.7.3.1
Power-On Reset (POR) Circuits
The device includes two power-on reset (POR) circuits, one for the RTC (RTC POR) and another for the
rest of the chip (MAIN POR).
5.7.3.1.1 RTC Power-On Reset (POR)
The RTC POR ensures that the flip-flops in the CVDDRTC power domain have an initial state upon
powerup. In particular, the RTCNOPWR register is reset by this POR and is used to indicate that the RTC
time registers need to be initialized with the current time and date when power is first applied.
5.7.3.1.2 Main Power-On Reset (POR)
The device includes an analog power-on reset (POR) circuit that keeps the DSP in reset until specific
voltages have reached predetermined levels. When the DSP_LDO is enabled externally by the
DSP_LDO_EN pin, the output of the POR circuit, POWERGOOD, is held low until the following conditions
are satisfied:
• LDOI is powered and the bandgap is active for at least approximately 8 ms
• VDD_ANA is powered for at least approximately 4 ms
• DSP_LDOO is above a threshold of approximately 950 mV
Note: The POR comparator has hysteresis, so the threshold voltage becomes approximately 850 mV after
POWERGOOD signal is set high.
Once these conditions are met, the internal POWERGOOD signal is set high. The POWERGOOD signal
is internally combined with the RESET pin signal, via an AND-gate, to produce the DSP subsystem's
global reset. This global reset is the hardware reset for the whole chip, except the RTC. When the global
reset is deasserted (high), the boot sequence starts. For more detailed information on the boot sequence,
see Section 6.4.1, Boot Sequence.
When the DSP_LDO is disabled (DSP_LDO_EN pin = 1), the voltage monitoring on the DSP_LDOO pin is
de-activated and the POWERGOOD signal is immediately set high. The RESET pin will be the sole
source of hardware reset.
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5.7.3.1.3 Reset Pin (RESET)
The device can receive an external reset signal on the RESET pin. As specified above in
Section 5.7.3.1.2, Main Power-On Reset, the RESET pin is combined with the internal POWERGOOD
signal, that is generated by the MAIN POR, via an AND-gate. The output of the AND gate provides the
hardware reset to the chip. The RESET pin may be tied high and the MAIN POR can provide the
hardware reset in case DSP_LDO is enabled (DSP_LDO_EN = 0), but an external hardware reset must
be provided via the RESET pin when the DSP_LDO is disabled (DSP_LDO_EN = 1).
Once the hardware reset is applied, the system clock generator is enabled and the DSP starts the boot
sequence. For more information on the boot sequence, see Section 6.4.1, Boot Sequence.
5.7.3.2
Pin Behavior at Reset
During normal operation, pins are controlled by the respective peripheral selected in the External Bus
Selection Register (EBSR) register. During power-on reset and reset, the behavior of the output pins
changes and is categorized as follows:
68
•
High Group: LCD_RS/SPI_CS3
•
Low Group: LCD_EN_RDB/SPI_CLK, SD0_CLK/I2S0_CLK/GP[0], SD1_CLK/I2S1_CLK/GP[6]
•
Z Group: EMU[1:0], SCL, SDA, LCD_D[0]/SPI_RX, LCD_D[1]/SPI_TX,
LCD_D[10]/I2S2_RX/GP[20]/SPI_RX, LCD_D[11]/I2S2_DX/GP[27]/SPI_TX,
LCD_D[12]/UART_RTS/GP[28]/I2S3_CLK, LCD_D[13]/UART_CTS/GP[29]/I2S3_FS,
LCD_D[14]/UART_RXD/GP[30]/I2S3_RX, LCD_D[15]/UART_TXD/GP[31]/I2S3_DX,
LCD_D[2]/GP[12], LCD_D[3]/GP[13], LCD_D[4]/GP[14], LCD_D[5]/GP[15], LCD_D[6]/GP[16],
LCD_D[7]/GP[17], LCD_D[8]/I2S2_CLK/GP[18]/SPI_CLK, LCD_D[9] I2S2_FS/GP[19]/SPI_CS0,
RTC_CLKOUT, SD0_CMD/I2S0_FS/GP[1], SD0_D0/I2S0_DX/GP[2], SD0_D1/I2S0_RX/GP[3],
SD0_D2/GP[4], SD0_D3/GP[5], SD1_CMD/I2S1_FS/GP[7], SD1_D0/I2S1_DX/GP[8],
SD1_D1/I2S1_RX/GP[9], SD1_D2/GP[10], SD1_D3/GP[11], TDO, WAKEUP
•
CLKOUT Group: CLKOUT , LCD_CS1_E1/SPI_CS1
•
SYNCH 0→1 Group: LCD_CS0_E0/SPI_CS0, LCD_RW_WRB/SPI_CS2
•
SYNCH x→1 Group: XF
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5.7.3.3
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Reset Electrical Data and Timing
Table 5-7. Timing Requirements for Reset (1) (see Figure 5-8 and Figure 5-9)
CVDD = 1.05 V
NO.
1
(1)
MIN
tw(RSTL)
Pulse duration, RESET low
CVDD = 1.3 V
MAX
3P
MIN
MAX
3P
UNIT
ns
P = 1/SYSCLK clock frequency in ns. For example, if SYSCLK = 12 MHz, use P = 83.3 ns. In IDLE3 mode the system clock generator
is bypassed and the SYSCLK frequency is equal to either CLKIN or the RTC clock frequency depending on CLK_SEL.
POWERGOOD
(Internal)
RESET
POWERGOOD and RESET
(Internal)
LOW Group
HIGH Group
Z Group
SYNCH X® 1
Group
SYNCH 0® 1
Group
Valid Clock
CLKOUT
65526 + 38 clocks if CLK_SEL = 1,
32 + 38 clocks if CLK_SEL = 0
Figure 5-8. Power-On Reset Timing Requirements
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POWERGOOD
(Internal)
RESET
tw(RSTL)
POWERGOOD and RESET
(Internal)
LOW Group
HIGH Group
Z Group
SYNCH X ® 1
Group
SYNCH 0 ® 1
Group
Valid Clock
CLKOUT
65526 + 38 clocks if CLK_SEL = 1,
32 + 38 clocks if CLK_SEL = 0
Figure 5-9. Reset Timing Requirements
70
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5.7.3.4
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Configurations at Reset
Some device configurations are determined at reset. The following subsections give more details.
5.7.3.4.1 Device and Peripheral Configurations at Device Reset
Table 5-8 summarizes the device boot and configuration pins that are required to be statically tied high,
tied low, or remain unconnected during device operation. For proper device operation, a device reset must
be initiated after changing any of these pin functions.
Table 5-8. Default Functions Affected by Device Configuration Pins
CONFIGURATION PINS
SIGNAL NO.
IPU and IPD
DSP_LDO_EN
C13
–
FUNCTIONAL DESCRIPTION
DSP_LDO enable input.
This signal is not intended to be dynamically switched.
0 = DSP_LDO is enabled. The internal DSP LDO is enabled to
regulate power on the DSP_LDOO pin at either 1.3 V or 1.05 V
according to the DSP_LDO_V bit in the LDOCNTL register, see
Figure 5-4). At power-on-reset, the internal POR monitors the
DSP_LDOO pin voltage and generates the internal
POWERGOOD signal when the DSP_LDO voltage is above a
minimum threshold voltage. The internal device reset is
generated by the AND of POWERGOOD and the RESET pin.
Note: For the 50-MHz devices, DSP_LDO must be
programmed to 1.05 V to match the core voltage, CVDD, for
proper operation after reset.
1 = DSP_LDO is disabled and the DSP_LDOO pin is in a highimpedance (Hi-Z) state. The internal voltage monitoring on the
DSP_LDOO is bypassed and the internal POWERGOOD signal
is immediately set high. The RESET pin will act as the sole
reset source for the device. If an external power supply is used
to provide power to CVDD, then DSP_LDO_EN must be tied to
LDOI, DSP_LDOO must be left unconnected, and the RESET
pin must be asserted appropriately for device initialization after
powerup.
Note: To pullup this pin, connect it to the same supply as LDOI
pins.
CLK_SEL
D1
–
Clock input select.
0 = 32-kHz on-chip oscillator drives the RTC timer and the
system clock generator. CLKIN is ignored.
1 = CLKIN drives the system clock generator and the 32-kHz
on-chip oscillator drives only the RTC timer.
This pin is not allowed to change during device operation; it
must be tied to DVDDIO or GND at the board.
For proper device operation, external pullup and pulldown resistors may be required on these device
configuration pins. For discussion on situations where external pullup and pulldown resistors are required,
see Section 5.7.17.1.1, Pullup and Pulldown Resistors.
This device also has RESERVED pins that need to be configured correctly for proper device operation
(statically tied high, tied low, or remain unconnected at all times). For more details on these pins, see
Table 4-16, Reserved and No Connects Signal Descriptions.
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5.7.3.5
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Configurations After Reset
The following sections provide details on configuring the device after reset. Multiplexed pin functions are
selected by software after reset. For more details on multiplexed pin function control, see Section 4.3, Pin
Multiplexing.
5.7.3.5.1 External Bus Selection Register (EBSR)
The External Bus Selection Register (EBSR) determines the mapping of the LCD controller, I2S2, I2S3,
UART, SPI, and GPIO signals to 21 signals of the external parallel port pins. The EBSR also determines
the mapping of the I2S or SD ports to serial port 1 pins and serial port 2 pins. The EBSR register is
located at port address 1C00h. Once the bit fields of this register are changed, the routing of the signals
takes place on the next CPU clock cycle.
Before modifying the values of the external bus selection register, you must clock gate all affected
peripherals through the Peripheral Clock Gating Control Register. After the external bus selection register
has been modified, you must reset the peripherals before using them through the Peripheral Software
Reset Counter Register.
Figure 5-10. External Bus Selection Register (EBSR) [1C00h]
15
Reserved
R-0
14
7
Reserved
R-0
6
13
PPMODE
R/W-000
12
5
4
11
10
9
SP1MODE
R/W-00
3
Reserved
R-0
8
SP0MODE
R/W-00
2
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-9. EBSR Register Bit Descriptions
BIT
NAME
15
RESERVED
DESCRIPTION
Reserved. Read-only, writes have no effect.
Parallel Port Mode Control Bits. These bits control the pin multiplexing of the LCD Controller, SPI,
UART, I2S2, I2S3, and GP[31:27, 20:18] pins on the parallel port.
For more details, see Table 4-19, LCD Controller, SPI, UART, I2S2, I2S3, and GP[31:27, 20:18] Pin
Multiplexing.
000 = Mode 0 (16-bit LCD Controller). All 21 signals of the LCD Bridge module are routed to the 21
external signals of the parallel port.
001 = Mode 1 (SPI, GPIO, UART, and I2S2). 7 signals of the SPI module, 6 GPIO signals, 4
signals of the UART module and 4 signals of the I2S2 module are routed to the 21 external signals
of the parallel port.
010 = Mode 2 (8-bit LCD Controller and GPIO). 8 bits of pixel data of the LCD Controller module
and 8 GPIO are routed to the 21 external signals of the parallel port.
14:12
PPMODE
011 = Mode 3 (8-bit LCD Controller, SPI and I2S3). 8 bits of pixel data of the LCD Controller
module, 4 signals of the SPI module and 4 signals of the I2S3 module are routed to the 21 external
signals of the parallel port.
100 = Mode 4 (8-bit LCD Controller, I2S2 and UART). 8 bits of pixel data of the LCD Controller
module, 4 signals of the I2S2 module and 4 signals of the UART module are routed to the 21
external signals of the parallel port.
101 = Mode 5 (8-bit LCD Controller, SPI and UART). 8 bits of pixel data of the LCD Controller
module, 4 signals of the SPI module and 4 signals of the UART module are routed to the 21
external signals of the parallel port.
110 = Mode 6 (SPI, I2S2, I2S3, and GPIO). 7 signals of the SPI module, 4 signals of the I2S2
module, 4 signals of the I2S3 module, and 6 GPIO are routed to the 21 external signals of the
parallel port.
111 = Reserved.
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Table 5-9. EBSR Register Bit Descriptions (continued)
BIT
NAME
DESCRIPTION
Serial Port 1 Mode Control Bits. The bits control the pin multiplexing of the SD1, I2S1, and GPIO
pins on serial port 1.
For more details, see Table 4-20, SD1, I2S1, and GP[11:6] Pin Multiplexing.
00 = Mode 0 (SD1). All 6 signals of the SD1 module are routed to the 6 external signals of the
serial port 1.
11:10
SP1MODE
01 = Mode 1 (I2S1 and GP[11:10]). 4 signals of the I2S1 module and 2 GP[11:10] signals are
routed to the 6 external signals of the serial port 1.
10 = Mode 2 (GP[11:6]). 6 GPIO signals (GP[11:6]) are routed to the 6 external signals of the serial
port 1.
11 = Reserved.
Serial Port 0 Mode Control Bits. The bits control the pin multiplexing of the SD0, I2S0, and GPIO
pins on serial port 0.
For more details, see Section 4.3.3, SD0, I2S0, and GP[5:0] Pin Multiplexing.
00 = Mode 0 (SD0). All 6 signals of the SD0 module are routed to the 6 external signals of the
serial port 0.
9:8
SP0MODE
01 = Mode 1 (I2S0 and GP[5:0]). 4 signals of the I2S0 module and 2 GP[5:4] signals are routed to
the 6 external signals of the serial port 0.
10 = Mode 2 (GP[5:0]). 6 GPIO signals (GP[5:0]) are routed to the 6 external signals of the serial
port 0.
11 = Reserved.
7
RESERVED
Reserved. Read-only, writes have no effect.
6
RESERVED
Reserved. Read-only, writes have no effect.
5
RESERVED
Reserved
4
RESERVED
Reserved
3
RESERVED
Reserved
2
RESERVED
Reserved
1
RESERVED
Reserved
0
RESERVED
Reserved
5.7.3.5.2 LDO Control Register [7004h]
When the DSP_LDO is enabled by the DSP_LDO_EN pin [C13], by default, the DSP_LDOO voltage is set
to 1.3 V. The DSP_LDOO voltage can be programmed to be either 1.05 V or 1.3 V via the DSP_LDO_V
bit (bit 1) in the LDO Control Register (LDOCNTL).
For the 50-MHz devices, DSP_LDO must be programmed to 1.05 V to match the core voltage, CVDD, for
proper operation after reset.
At reset, the USB_LDO is turned off. The USB_LDO can be enabled via the USBLDOEN bit (bit 0) in the
LDOCNTL register.
For more detailed information on the LDOs, see Section 5.7.2.1.1 LDO Configuration.
5.7.3.5.3 USB System Control Registers (USBSCR) [1C32h]
After reset, by default, the CPU performs 16-bit accesses to the USB register and data space. To perform
8-bit accesses to the USB data space, the user must set the BYTEMODE bits to 01b for the "high byte" or
10b for the "low byte" in the USB System Control Register (USBSCR).
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5.7.3.5.4 Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2) [1C02h and 1C03h]
After hardware reset, the DSP executes the on-chip bootloader from ROM. As the bootloader executes, it
selectively enables the clock of the peripheral being queried for a valid boot. If a valid boot source is not
found, the bootloader disables the clock to that peripheral and moves on to the next peripheral in the boot
order. After the boot process is complete, all of the peripheral clocks will be off and all domains in the ICR,
except for the CPU domain, will be idled (this includes the MPORT and HWA). The user must enable the
clocks to the peripherals and CPU ports that are going to be used. The peripheral clock gating control
registers (PCGCR1 and PCGCR2) are used to enable and disable the peripheral clocks.
5.7.3.5.5 Pullup and Pulldown Inhibit Registers (PDINHIBR1, 2, and 3) [1C17h, 1C18h, and 1C19h]
Each internal pullup and pulldown (IPU and IPD) resistor on the device DSP, except for the IPD on TRST,
can be individually controlled through the IPU and IPD registers (PDINHIBR1 [1C17h] , PDINHIBR2
[1C18h], and PDINHIBR3 [1C19h]). To minimize power consumption, internal pullup or pulldown resistors
must be disabled in the presence of an external pullup or pulldown resistor or external driver.
Section 5.7.17.1.1, Pullup and Pulldown Resistors, describes other situations in which an pullup and
pulldown resistors are required.
When CVDD is powered down, pullup and pulldown resistors will be forced disabled and an internal busholder will be enabled. For more detailed information, see Section 5.7.2.5, Digital I/O Behavior When Core
Power (CVDD) is Down.
5.7.3.5.6 Output Slew Rate Control Register (OSRCR) [1C16h]
To provide the lowest power consumption setting, the DSP has configurable slew rate control on the
CLKOUT output pin. The output slew rate control register (OSRCR) is used to set a subset of the device
I/O pins, namely the CLKOUT pin, to either fast or slow slew rate. The slew rate feature is implemented by
staging or delaying turn-on times of the parallel p-channel drive transistors and parallel n-channel drive
transistors of the output buffer. In the slow slew rate configuration, the delay is longer, but ultimately the
same number of parallel transistors are used to drive the output high or low. Thus, the drive strength is
ultimately the same. The slower slew rate control can be used for power savings and has the greatest
effect at lower DVDDIO voltages.
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5.7.4
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Clock Specifications
5.7.4.1
Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
5.7.4.2
Clock Considerations
The system clock, which is used by the CPU and most of the DSP peripherals, is controlled by the system
clock generator. The system clock generator features a software-programmable PLL multiplier and several
dividers. The clock generator accepts an input reference clock from the CLKIN pin or the output clock of
the 32.768-kHz real-time clock (RTC) oscillator. The selection of the input reference clock is based on the
state of the CLK_SEL pin. The CLK_SEL pin is required to be statically tied high or low and cannot
change dynamically after reset.
In addition, the DSP requires a reference clock for USB applications. The USB reference clock is
generated using a dedicated on-chip oscillator with a 12-MHz external crystal connected to the USB_MXI
and USB_MXO pins.
The USB reference clock is not required if the USB peripheral is not being used. To completely disable the
USB oscillator, connect the USB_MXI pin to ground (VSS) and leave the USB_MXO pin unconnected. The
USB oscillator power pins (USB_VDDOSC and USB_VSSOSC) should also be connected to ground.
The RTC oscillator generates a clock when a 32.768-kHz crystal is connected to the RTC_XI and
RTC_XO pins. The 32.768-kHz crystal can be disabled if CLKIN is used as the clock source for the DSP.
However, when the RTC oscillator is disabled, the RTC peripheral will not operate and the RTC registers
(I/O address range 1900h – 197Fh) will not be accessible. This includes the RTC power management
register (RTCPMGT) which controls the RTCLKOUT and WAKEUP pins. To disable the RTC oscillator,
connect the RTC_XI pin to CVDDRTC and the RTC_XO pin to ground.
For more information on crystal specifications for the RTC oscillator and the USB oscillator, see
Section 5.7.4.3.3, External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins.
5.7.4.2.1 Clock Configurations After Device Reset
After reset, the on-chip bootloader programs the system clock generator based on the input clock selected
via the CLK_SEL pin.
If CLK_SEL = 0, the bootloader programs the system clock generator and sets the system clock to 12.288
MHz (multiply the 32.768-kHz RTC oscillator clock by 375).
If CLK_SEL = 1, the bootloader bypasses the system clock generator altogether and the system clock is
driven by the CLKIN pin. In this case, the CLKIN frequency is expected to be 11.2896 MHz, 12.000 MHz,
or 12.288 MHz. The bootloader sets the system PLL to 60 MHz and the SPI module clock to 15 MHz.
While the bootloader tries to boot from the USB, the clock generator will be programmed to output
approximately 36 MHz.
5.7.4.2.1.1 Device Clock Frequency
After the boot process is complete, the user is allowed to re-program the system clock generator to bring
the device up to the desired clock frequency and the desired peripheral clock state (clock gating or not).
The user must adhere to various clock requirements when programming the system clock generator. For
more information, see Section 5.7.4.3, Clock PLLs.
Note: The on-chip bootloader allows for DSP registers to be configured during the boot process. However,
this feature must not be used to change the output frequency of the system clock generator during the
boot process. The bootloader also uses Timer0 to calculate the settling time of BG_CAP until executing
bootloader code. The bootloader register modification feature must not modify the Timer0 registers.
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5.7.4.2.1.2 Peripheral Clock State
The clock and reset state of each of peripheral is controlled through a set of system registers. The
peripheral clock gating control registers (PCGCR1 and PCGCR2) are used to enable and disable
peripheral clocks. The peripheral software reset counter register (PSRCR) and the peripheral reset control
register (PRCR) are used to assert and de-assert peripheral reset signals.
At hardware reset, all of the peripheral clocks are off to conserve power. After hardware reset, the DSP
boots via the bootloader code in ROM. During the boot process, the bootloader queries each peripheral to
determine if it can boot from that peripheral. In other words, it reads each peripheral searching for a valid
boot image file. At that time, the individual peripheral clocks will be enabled for the query and then
disabled again when the bootloader is finished with the peripheral. By the time the bootloader releases
control to the user code, all peripheral clocks will be off and all domains in the ICR, except the CPU
domain, will be idled.
5.7.4.2.1.3 USB Oscillator Control
The USB oscillator is controlled through the USB system control register (USBSCR). To enable the
oscillator, the USBOSCDIS and USBOSCBIASDIS bits must be cleared to 0. The user must wait until the
USB oscillator stabilizes before proceeding with the USB configuration. The USB oscillator stabilization
time is typically 100 μs, with a 10 ms maximum (Note: the startup time is highly dependent on the ESR
and capacitive load on the crystal).
5.7.4.3
PLLs
The device DSP uses a software-programmable PLL to generate frequencies required by the CPU, DMA,
and peripherals. The reference clock for the PLL is taken from either the CLKIN pin or the RTC on-chip
oscillator (as specified through the CLK_SEL pin).
5.7.4.3.1 PLL Device-Specific Information
Table 5-10. PLL Clock Frequency Ranges
CLOCK SIGNAL NAME
CVDD = 1.05 V
VDDA_PLL = 1.3 V
MIN
MAX
MIN
11.2896
12
12.288
CLKIN (1)
RTC Clock
PLLIN
32.768
11.2896
12
12.288
MHz
32.768
kHz
170
kHz
120
60
120
MHz
50
0.032768
100
MHz
4
ms
170
PLLOUT
60
SYSCLK
0.032768
PLL_LOCKTIME
UNIT
MAX
32.768
32.768
(1)
CVDD = 1.3 V
VDDA_PLL = 1.3 V
4
These CLKIN values are used when the CLK_SEL pin = 1.
The PLL has lock time requirements that must be followed. The PLL lock time is the amount of time
needed for the PLL to complete its phase-locking sequence. After the maximum PLL_LOCKTIME has
passed, the PLL is locked and ready to use.
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5.7.4.3.2
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Clock PLL Considerations With External Clock Sources
If the CLKIN pin is used to provide the reference clock to the PLL, to minimize the clock jitter a single
clean power supply should power both the device and the external clock oscillator circuit. The minimum
CLKIN rise and fall times should also be observed. For the input clock timing requirements, see
Section 5.7.4.4, Input and Output Clocks Electrical Data and Timing.
Rise and fall times, duty cycles (high and low pulse durations), and the load capacitance of the external
clock source must meet the device requirements in this data manual (see Section 5.3, Electrical
Characteristics, and Section 5.7.4.4, Input and Output Clocks Electrical Data and Timing.
5.7.4.3.3 External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins
The device DSP includes two options to provide an external clock input to the system clock generator:
• Use the on-chip real-time clock (RTC) oscillator with an external 32.768-kHz crystal connected to the
RTC_XI and RTC_XO pins.
• Use an external 11.2896-, 12.0-, or 12.288-MHz LVCMOS clock input fed into the CLKIN pin that
operates at the same voltage as the DVDDIO supply (1.8-, 2.5-, 2.75-, or 3.3-V).
The CLK_SEL pin determines which input is used as the clock source for the system clock generator. For
more details, see Section 5.7.3.4.1, Device and Peripheral Configurations at Device Reset. The crystal for
the RTC oscillator is not required if CLKIN is used as the system reference clock; however, the RTC must
still be powered by an external power source. None of the on-chip LDOs can power CVDDRTC. The RTC
registers starting at I/O address 1900h will not be accessible without an RTC clock. This includes the RTC
Power Management Register which provides control to the on-chip LDOs and WAKEUP and
RTC_CLKOUT pins. Section 5.7.4.3.3.1, Real-Time Clock (RTC) On-Chip Oscillator With External Crystal
provides more details on using the RTC on-chip oscillator with an external crystal. Section 5.7.4.3.3.2,
CLKIN Pin With LVCMOS-Compatible Clock Input provides details on using an external LVCMOScompatible clock input fed into the CLKIN pin.
Additionally, the USB requires a reference clock generated using a dedicated on-chip oscillator with a 12MHz external crystal connected to the USB_MXI and USB_MXO pins. The USB reference clock is not
required if the USB peripheral is not being used. Section 5.7.4.3.3.3, USB On-Chip Oscillator With
External Crystal provides details on using the USB on-chip oscillator with an external crystal.
5.7.4.3.3.1 Real-Time Clock (RTC) On-Chip Oscillator With External Crystal
The on-chip oscillator requires an external 32.768-kHz crystal connected across the RTC_XI and RTC_XO
pins, along with two load capacitors, as shown in Figure 5-11. The external crystal load capacitors must
be connected only to the RTC oscillator ground pin (VSSRTC). Do not connect to board ground (VSS).
Position the VSS lead on the board between RTC_XI and RTC_XO as a shield to reduce direct
capacitance between RTC_XI and RTC_XO leads on the board. The CVDDRTC pin can be connected to the
same power supply as CVDD , or may be connected to a different supply that meets the recommended
operating conditions (see Section 5.2, Recommended Operating Conditions), if desired. However, the
CVDDRTC pin must not be supplied by any on-chip LDOs.
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RTC_XI
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RTC_XO
VSSRTC
VSS
CVDDRTC
CVDD
Crystal
32.768 kHz
C1
C2
0.998-1.43 V
1.05/1.3 V
Figure 5-11. 32.768-kHz RTC Oscillator
The crystal should be in fundamental-mode function, and parallel resonant, with a maximum effective
series resistance (ESR) specified in Table 5-11. The load capacitors, C1 and C2, are the total capacitance
of the circuit board and components, excluding the IC and crystal. The load capacitors values are usually
approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal
manufacturer's datasheet and should be chosen such that the equation is satisfied.
CL =
C1 C2
(C1 + C2 )
All discrete components used to implement the oscillator circuit must be placed as close as possible to the
associated oscillator pins (RTC_XI and RTC_XO) and to the VSSRTC pin.
Table 5-11. Input Requirements for Crystal on the 32.768-kHz RTC Oscillator
PARAMETER
MIN
Start-up time (from power up until oscillating at stable frequency of 32.768-kHz) (1)
0.2
Oscillation frequency
NOM
MAX
2
32.768
UNIT
sec
kHz
ESR
100
Maximum shunt capacitance
1.6
pF
Maximum crystal drive
1.0
μW
(1)
kΩ
The startup time is highly dependent on the ESR and the capacitive load of the crystal.
5.7.4.3.3.2 CLKIN Pin With LVCMOS-Compatible Clock Input (Optional)
Note: If CLKIN is not used, the pin must be tied low.
A LVCMOS-compatible clock input of a frequency less than 24 MHz can be fed into the CLKIN pin for use
by the DSP system clock generator. The external connections are shown in Figure 5-12 and Figure 5-13.
The bootloader assumes that the CLKIN pin is connected to the LVCMOS-compatible clock source with a
frequency of 11.2896-, 12.0-, or 12.288-MHz. These frequencies were selected to support boot mode
peripheral speeds of 500 kHz for SPI and 400 kHz for I2C and UART. These clock frequencies are
achieved by dividing the CLKIN value by 25 for SPI and by 32 for I2C and UART. If a faster external clock
is input, then these boot modes will run at faster clock speeds. If the system design utilizes faster
peripherals or these boot modes are not used, CLKIN values higher than 12.288 MHz can be used. Note:
The CLKIN pin operates at the same voltage as the DVDDIO supply (1.8-, 2.5-, 2.75-, or 3.3-V).
In this configuration the RTC oscillator can be optionally disabled by connecting RTC_XI to CVDDRTC and
RTC_XO to ground (VSS). However, when the RTC oscillator is disabled the RTC registers starting at I/O
address 1900h will not be accessible. This includes the RTC Power Management Register which provides
control to the on-chip LDOs and WAKEUP and RTC_CLKOUT pins. Note: The RTC core must still be
powered by an external power source even if the RTC oscillator is disabled. None of the on-chip LDOs
can power CVDDRTC.
78
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
For more details on the RTC on-chip oscillator, see Section 5.7.4.3.3.1, Real-Time Clock (RTC) On-Chip
Oscillator With External Crystal.
CLKIN
RTC_XI
RTC_XO
VSSRTC
CVDDRTC
VSS
CVDD
Crystal
32.768 kHz
C1
C2
1.05/1.3 V
0.998-1.43 V
Figure 5-12. LVCMOS-Compatible Clock Input With RTC Oscillator Enabled
CLKIN
RTC_XI
CVDDRTC
RTC_XO
VSS
VSSRTC
CVDD
1.05/1.3 V
0.998-1.43 V
Figure 5-13. LVCMOS-Compatible Clock Input With RTC Oscillator Disabled
5.7.4.3.3.3 USB On-Chip Oscillator With External Crystal (Optional)
When using the USB, the USB on-chip oscillator requires an external 12-MHz crystal connected across
the USB_MXI and USB_MXO pins, along with two load capacitors, as shown in Figure 5-14. The external
crystal load capacitors must be connected only to the USB oscillator ground pin (USB_VSSOSC). Do not
connect to board ground (VSS). The USB_VDDOSC pin can be connected to the same power supply as
USB_VDDA3P3.
The USB on-chip oscillator can be permanently disabled, via tie-offs, if the USB peripheral is not being
used. To permanently disable the USB oscillator, connect the USB_MXI pin to ground (VSS) and leave the
USB_MXO pin unconnected. The USB oscillator power pins (USB_VDDOSC and USB_VSSOSC) should also
be connected to ground, as shown in Figure 5-15.
When using an external 12-MHz oscillator, the external oscillator clock signal must be connected to the
USB_MXI pin and the amplitude of the oscillator clock signal must meet the VIH requirement (see
Section 5.2, Recommended Operating Conditions). The USB_MXO remains unconnected and the
USB_VSSOSC signal is connected to board ground (VSS).
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USB_MXI
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USB_MXO
USB_VSSOSC
USB_VDDOSC
VSS
USB_VDDA3P3
Crystal
12 MHz
C1
C2
3.3 V
3.3 V
Figure 5-14. 12-MHz USB Oscillator
USB_MXI
USB_MXO
USB_VSSOSC
USB_VDDOSC
VSS
USB_VDDA3P3
Figure 5-15. Connections when USB Oscillator is Permanently Disabled
The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective
series resistance (ESR) specified in Table 5-12. The load capacitors, C1 and C2 are the total capacitance
of the circuit board and components, excluding the IC and crystal. The load capacitor value is usually
approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal
manufacturer's data sheet and should be chosen such that the equation below is satisfied. All discrete
components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (USB_MXI and USB_MXO) and to the USB_VSSOSC pin.
CL =
C1 C2
(C1 + C2 )
Table 5-12. Input Requirements for Crystal on the 12-MHz USB Oscillator
PARAMETER
MIN
Start-up time (from power up until oscillating at stable frequency of 12 MHz) (1)
Oscillation frequency
NOM
MAX
0.100
10
12
ESR
Frequency stability
(2)
Maximum shunt capacitance
Maximum crystal drive
(1)
(2)
80
UNIT
ms
MHz
100
Ω
±100
ppm
5
pF
330
μW
The startup time is highly dependent on the ESR and the capacitive load of the crystal.
If the USB is used, a 12-MHz, ±100-ppm crystal is recommended.
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5.7.4.4
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Input and Output Clocks Electrical Data and Timing
Table 5-13. Timing Requirements for CLKIN (1)
(2)
(see Figure 5-16)
CVDD = 1.05 V
NO.
MIN
CVDD = 1.3 V
NOM
MAX
MIN
NOM
88.577,
83.333,
or
81.380
Cycle time, external clock driven on
CLKIN
MAX
UNIT
88.577,
83.333,
or
81.380
1
tc(CLKIN)
2
tw(CLKINH) Pulse width, CLKIN high
0.466 *
tc(CLKIN)
0.466 *
tc(CLKIN)
ns
3
tw(CLKINL) Pulse width, CLKIN low
0.466 *
tc(CLKIN)
0.466 *
tc(CLKIN)
ns
4
(1)
tt(CLKIN)
Transition time, CLKIN
4
ns
4
ns
The CLKIN frequency and PLL multiply factor must be chosen such that the resulting clock frequency is within the specific range for
CPU operating frequency.
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2)
1
4
1
2
CLKIN
3
4
Figure 5-16. CLKIN Timing
Table 5-14. Switching Characteristics Over Recommended Operating Conditions for CLKOUT (1)
(see Figure 5-17)
NO.
1
(1)
(2)
(3)
CVDD = 1.05 V
VDDA_PLL = 1.3 V
PARAMETER
tc(CLKOUT)
Cycle time, CLKOUT
2
tw(CLKOUTH)
Pulse duration, CLKOUT high
3
tw(CLKOUTL)
Pulse duration, CLKOUT low
MIN
MAX
P
20
tt(CLKOUTR)
Transition time (rise), CLKOUT
5
tt(CLKOUTF)
Transition time (fall), CLKOUT (3)
UNIT
MIN
MAX
P
10
0.466 *
0.466 *
tc(CLKOUT)
tc(CLKOUT)
0.466 *
tc(CLKOUT)
0.466 *
tc(CLKOUT)
(3)
4
CVDD = 1.3 V
VDDA_PLL = 1.3 V
(2)
ns
ns
ns
5
5
ns
5
5
ns
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
P = 1/SYSCLK clock frequency in nanoseconds (ns). For example, when SYSCLK frequency is 100 MHz, use P = 10 ns.
Transition time is measured with the slew rate set to FAST and DVDDIO = 1.65 V. (For more detailed information, see the
Section 5.7.3.5.6, Output Slew Rate Control Register (OSRCR) [1C16h].).
2
5
1
CLKOUT
3
4
Figure 5-17. CLKOUT Timing
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Wake-up Events, Interrupts, and XF
The device has a number of interrupts to service the needs of its peripherals. The interrupts can be
selectively enabled or disabled.
5.7.4.5.1 Interrupts Electrical Data and Timing
Table 5-15. Timing Requirements for Interrupts (1) (see Figure 5-18)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
MIN
(1)
UNIT
MAX
1
tw(INTH)
Pulse duration, interrupt high CPU active
2P
ns
2
tw(INTL)
Pulse duration, interrupt low CPU active
2P
ns
P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns. For example, when the
CPU core is clocked at 120 MHz, use P = 8.3 ns.
1
INTx
2
Figure 5-18. External Interrupt Timings
5.7.4.5.2 Wake Up From IDLE Electrical Data and Timing
Table 5-16. Timing Requirements for Wake-Up From IDLE (see Figure 5-19)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
MIN
1
tw(WKPL)
Pulse duration, WAKEUP or INTx low, SYSCLKDIS = 1
UNIT
MAX
30.5
µs
Table 5-17. Switching Characteristics Over Recommended Operating Conditions For Wake-Up From
IDLE (1) (2) (3) (4) (see Figure 5-19)
NO.
CVDD = 1.05 V
CVDD = 1.3 V
PARAMETER
MIN
2
td(WKEVTH-C
KLGEN)
82
UNIT
MAX
IDLE3 Mode with SYSCLKDIS = 1,
WAKEUP or INTx event, CLK_SEL =
1
D
ns
Delay time, WAKEUP pulse complete to
IDLE3 Mode with SYSCLKDIS = 1,
CPU active
WAKEUP or INTx event, CLK_SEL =
0
C
ns
3P
ns
IDLE2 Mode; INTx event
(1)
(2)
(3)
(4)
TYP
D = 1/ External Clock Frequency (CLKIN).
C = 1/RTCCLK= 30.5 μs. RTCCLK is the clock output of the 32.768-kHz RTC oscillator.
P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
Assumes the internal LDOs are used with a 0.1 μF bandgap capacitor.
Specifications
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2
CLKOUT
1
WAKEUP
INTx
A.
B.
C.
D.
INT[1:0] can only be used as a wake-up event for IDLE3 and IDLE2 modes.
RTC interrupt (internal signal) can be used as wake-up event for IDLE3 and IDLE2 modes.
Any unmasked interrupt can be used to exit the IDLE2 mode.
CLKOUT reflects either the CPU clock, SAR, USB PHY, or PLL clock dependent on the setting of the CLKOUT Clock
Source Register. For this diagram, CLKOUT refers to the CPU clock.
Figure 5-19. Wake-Up From IDLE Timings
5.7.4.5.3 XF Electrical Data and Timing
Table 5-18. Switching Characteristics Over Recommended Operating Conditions For XF (1)
(see Figure 5-20)
NO.
1
(1)
(2)
CVDD = 1.05 V
CVDD = 1.3 V
PARAMETER
td(XF)
(2)
Delay time, CLKOUT high to XF high
MIN
MAX
0
10.2
UNIT
ns
P = 1/SYSCLK clock frequency in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
C = 1/RTCCLK= 30.5 μs. RTCCLK is the clock output of the 32.768-kHz RTC oscillator.
(A)
CLKOUT
1
XF
A.
CLKOUT reflects either the CPU clock, SAR,USB PHY, or PLL clock dependent on the setting of the CLOCKOUT
Clock Source Register. For this diagram, CLKOUT refers to the CPU clock.
Figure 5-20. XF Timings
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5.7.5
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Direct Memory Access (DMA) Controller
The DMA controller is used to move data among internal memory, external memory, and peripherals
without intervention from the CPU and in the background of CPU operation.
The DSP includes a total of four DMA controllers. Aside from the DSP resources they can access, all four
DMA controllers are identical.
The DMA controller has the following features:
• Operation that is independent of the CPU.
• Four channels, which allow the DMA controller to keep track of the context of four independent block
transfers.
• Event synchronization. DMA transfers in each channel can be made dependent on the occurrence of
selected events.
• An interrupt for each channel. Each channel can send an interrupt to the CPU on completion of the
programmed transfer.
• Ping-Pong mode allows the DMA controller to keep track of double buffering context without CPU
intervention.
• A dedicated clock idle domain. The four device DMA controllers can be put into a low-power state by
independently turning off their input clocks.
5.7.5.1
DMA Channel Synchronization Events
The DMA controllers allow activity in their channels to be synchronized to selected events. The DSP
supports 20 separate synchronization events and each channel can be tied to separate sync events
independent of the other channels. Synchronization events are selected by programming the CHnEVT
field in the DMAn channel event source registers (DMAnCESR1 and DMAnCESR2).
84
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5.7.6
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
General-Purpose Input/Output
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, you can write to an internal register to control the state driven on the
output pin. When configured as an input, you can detect the state of the input by reading the state of the
internal register. The GPIO can also be used to send interrupts to the CPU.
The GPIO peripheral supports the following:
• 32 GPIO pins plus 1 general-purpose output (XF) and 4 Special-Purpose Outputs for Use With SAR —
TMS320C5535 Only
– Configure up to 20 GPIO pins simultaneously
• Each GPIO pin has internal pulldowns (IPDs) which can be individually disabled
• Each GPIO pin can be configured to generate edge detected interrupts to the CPU on either the rising
or falling edge
The device GPIO pin functions are multiplexed with various other signals. For more detailed information
on what signals are multiplexed with the GPIO and how to configure them, see Section 4.2, Signal
Descriptions and Section 4.3, Pin Multiplexing of this document.
5.7.6.1
GPIO Peripheral Input/Output Electrical Data and Timing
Table 5-19. Timing Requirements for GPIO Inputs (1) (see Figure 5-21)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
MIN
1
tw(ACTIVE)
2
(1)
(2)
2C (1)
Pulse duration, GPIO input and external interrupt pulse active
tw(INACTIVE)
Pulse duration, GPIO input and external interrupt pulse inactive
C
UNIT
MAX
(2)
ns
(1) (2)
ns
The pulse width given is sufficient to get latched into the GPIO_IFR register and to generate an interrupt. However, if a user wants to
have the device recognize the GPIO changes through software polling of the GPIO Data In (GPIO_DIN) register, the GPIO duration
must be extended to allow the device enough time to access the GPIO register through the internal bus.
C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns.
Table 5-20. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 5-21)
NO.
CVDD = 1.05 V
CVDD = 1.3 V
PARAMETER
MIN
(1)
(2)
UNIT
MAX
3
tw(GPOH)
Pulse duration, GP[x] output high
3C (1)
(2)
ns
4
tw(GPOL)
Pulse duration, GP[x] output low
3C (1)
(2)
ns
This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns.
2
GP[x] Input
(With IOINTEDGy = 0)
1
2
GP[x] Input
(With IOINTEDGy = 1)
1
4
3
GP[x] Output
Figure 5-21. GPIO Port Timing
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GPIO Peripheral Input Latency Electrical Data and Timing
Table 5-21. Timing Requirements for GPIO Input Latency (1)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
MIN
1
(1)
86
tL(GPI)
Latency, GP[x] input
UNIT
MAX
Polling GPIO_DIN register
5
cyc
Polling GPIO_IFR register
7
cyc
Interrupt Detection
8
cyc
The pulse width given is sufficient to generate a CPU interrupt. However, if a user wants to have the device recognize the GP[x] input
changes through software polling of the GPIO register, the GP[x] input duration must be extended to allow device enough time to access
the GPIO register through the internal bus.
Specifications
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5.7.7
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
General-Purpose Timers
The device has three 32-bit software programmable timers. Each timer can be used as a general- purpose
(GP) timer. Timer2 can be configured as either a GP or a Watchdog (WD) or both. General-purpose timers
are typically used to provide interrupts to the CPU to schedule periodic tasks or a delayed task. A
watchdog timer is used to reset the CPU in case it gets into an infinite loop. The GP timers are 32-bit
timers with a 13-bit prescaler that can divide the CPU clock and uses this scaled value as a reference
clock. These timers can be used to generate periodic interrupts. The watchdog timer is a 16-bit counter
with a 16-bit prescaler used to provide a recovery mechanism for the device in the event of a fault
condition, such as a non-exiting code loop.
The device timers support the following:
• 32-bit Programmable Countdown Timer
• 13-bit Prescaler Divider
• Timer Modes:
– 32-bit General-Purpose Timer
– 32-bit Watchdog Timer (Timer2 only)
• Auto Reload Option
• Generates Single Interrupt to CPU (The interrupt is individually latched to determine which timer
triggered the interrupt.)
• Generates Active Low Pulse to the Hardware Reset (Watchdog only)
• Interrupt can be used for DMA Event
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Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module provides an interface between the device and other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit and receive 2 to 8-bit data to and from the DSP
through the I2C module. The I2C port does not support CBUS compatible devices.
The I2C port supports the following features:
• Compatible with Philips I2C Specification Revision 2.1 (January 2000)
• Data Transfer Rate from 10 kbps to 400 kbps (Philips Fast-Mode Rate)
• Noise Filter to Remove Noise 50 ns or Less
• Seven- and Ten-Bit Device Addressing Modes
• Master (Transmit and Receive) and Slave (Transmit and Receive) Functionality
• One Read DMA Event and One Write DMA Event, which can be used by the DMA Controller
• One Interrupt that can be used by the CPU
• Slew-Rate Limited Open-Drain Output Buffers
The I2C module clock must be in the range from 6.7 MHz to 13.3 MHz. This is necessary for proper
operation of the I2C module. With the I2C module clock in this range, the noise filters on the SDA and
SCL pins suppress noise that has a duration of 50 ns or shorter. The I2C module clock is derived from the
DSP clock divided by a programmable prescaler.
88
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5.7.8.1
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
I2C Electrical Data and Timing
Table 5-22. Timing Requirements for I2C Timings (1) (see Figure 5-22)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
STANDARD
MODE
MIN
1
(1)
(2)
(3)
(4)
(5)
(6)
UNIT
FAST MODE
MAX
MIN
MAX
tc(SCL)
Cycle time, SCL
10
2.5
µs
2
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
0.6
µs
3
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a START and a
repeated START condition)
4
0.6
µs
4
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
5
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
(2)
6
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
250
7
th(SDA-SCLL)
Hold time, SDA valid after SCL low
0 (3)
0 (3)
8
tw(SDAH)
Pulse duration, SDA high between STOP and START
conditions
4.7
1.3
9
tr(SDA)
Rise time, SDA (5)
1000 20 + 0.1Cb
(6)
300
ns
10
tr(SCL)
Rise time, SCL
(5)
1000 20 + 0.1Cb
(6)
300
ns
11
tf(SDA)
Fall time, SDA (5)
300 20 + 0.1Cb
(6)
300
ns
12
tf(SCL)
(5)
300 20 + 0.1Cb
(6)
13
tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition)
14
tw(SP)
15
(6)
Cb
Fall time, SCL
100
4
ns
0.9 (4)
µs
300
0.6
Pulse duration, spike (must be suppressed)
ns
µs
0
Capacitive load for each bus line
µs
400
50
ns
400
pF
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down. Also these pins are not 3.6 V-tolerant (their VIH cannot go above DVDDIO + 0.3 V).
A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
The rise and fall times are measured at 30% and 70% of DVDDIO. The fall time is only slightly influenced by the external bus load (Cb)
and external pullup resistor. However, the rise time (tr) is mainly determined by the bus load capacitance and the value of the pullup
resistor. The pullup resistor must be selected to meet the I2C rise and fall time values specified.
Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
11
9
SDA
6
8
14
4
13
5
10
SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 5-22. I2C Receive Timings
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Table 5-23. Switching Characteristics for I2C Timings (1) (see Figure 5-23)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
PARAMETER
STANDARD
MODE
MIN
(1)
(2)
UNIT
FAST MODE
MAX
MIN
MAX
16
tc(SCL)
Cycle time, SCL
10
2.5
µs
17
td(SCLH-SDAL)
Delay time, SCL high to SDA low (for a repeated START
condition)
4.7
0.6
µs
18
td(SDAL-SCLL)
Delay time, SDA low to SCL low (for a START and a
repeated START condition)
4
0.6
µs
19
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
µs
20
tw(SCLH)
Pulse duration, SCL high
4
0.6
µs
21
td(SDAV-SCLH)
Delay time, SDA valid to SCL high
250
100
ns
22
tv(SCLL-SDAV)
Valid time, SDA valid after SCL low
0
0
23
tw(SDAH)
Pulse duration, SDA high between STOP and START
conditions
4.7
1.3
24
tr(SDA)
Rise time, SDA (2)
25
tr(SCL)
Rise time, SCL
(2)
26
tf(SDA)
Fall time, SDA (2)
27
tf(SCL)
Fall time, SCL (2)
28
td(SCLH-SDAH)
Delay time, SCL high to SDA high (for STOP condition)
29
Cp
Capacitance for each I2C pin
0.9
µs
µs
1000 20 + 0.1Cb
(1)
300
ns
1000 20 + 0.1Cb
(1)
300
ns
300 20 + 0.1Cb
(1)
300
ns
300 20 + 0.1Cb
(1)
300
ns
10
pF
4
0.6
10
µs
Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
The rise and fall times are measured at 30% and 70% of DVDDIO. The fall time is only slightly influenced by the external bus load (Cb)
and external pullup resistor. However, the rise time (tr) is mainly determined by the bus load capacitance and the value of the pullup
resistor. The pullup resistor must be selected to meet the I2C rise and fall time values specified.
26
24
SDA
21
23
19
28
20
25
SCL
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 5-23. I2C Transmit Timings
90
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5.7.9
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Inter-IC Sound (I2S)
The device I2S peripherals allow serial transfer of full-duplex streaming data, usually audio data, between
the device and an external I2S peripheral device such as an audio codec.
The device supports 4 independent dual-channel I2S peripherals, each with the following features:
• Full-duplex (transmit and receive) dual-channel communication
• Double buffered data registers that allow for continuous data streaming
• I2S/Left-justified and DSP data format with a data delay of 1 or 2 bits
• Data word-lengths of 8, 10, 12, 14, 16, 18, 20, 24, or 32 bits
• Ability to sign-extend received data samples for easy use in signal processing algorithms
• Programmable polarity for both frame synchronization and bit clocks
• Stereo (in I2S/Left-justified or DSP data formats) or mono (in DSP data format) mode
• Detection of over-run, under-run, and frame-sync error conditions
5.7.9.1
I2S Electrical Data and Timing
Table 5-24. Timing Requirements for I2S [I/O = 3.3 V, 2.75 V, and 2.5 V] (1) (see Figure 5-24)
MASTER
CVDD = 1.05
V
NO.
MIN
CVDD = 1.3 V
MIN
CVDD = 1.05 V
MA
X
MIN
MIN
UNIT
MA
X
2P (1)
(2)
40 or 2P (1)
(2)
ns
40 or
2P (1) (2)
Pulse duration, I2S_CLK high
20
20
20
20
ns
Pulse duration, I2S_CLK low
20
20
20
20
ns
tsu(RXV-CLKH)
Setup time, I2S_RX valid before I2S
CLK high (CLKPOL = 0)
5
5
5
5
ns
tsu(RXV-CLKL)
Setup time, I2S_RX valid before
I2S_CLK low (CLKPOL = 1)
5
5
5
5
ns
th(CLKH-RXV)
Hold time, I2S_RX valid after
I2S_CLK high (CLKPOL = 0)
3
3
3
3
ns
th(CLKL-RXV)
Hold time, I2S_RX valid after
I2S_CLK low (CLKPOL = 1)
3
3
3
3
ns
tsu(FSV-CLKH)
Setup time, I2S_FS valid before
I2S_CLK high (CLKPOL = 0)
–
–
15
15
ns
tsu(FSV-CLKL)
Setup time, I2S_FS valid before
I2S_CLK low (CLKPOL = 1)
–
–
15
15
ns
th(CLKH-FSV)
Hold time, I2S_FS valid after
I2S_CLK high (CLKPOL = 0)
–
–
tw(CLKH) +
0.6 (3)
tw(CLKH) +
0.6 (3)
ns
th(CLKL-FSV)
Hold time, I2S_FS valid after
I2S_CLK low (CLKPOL = 1)
–
–
tw(CLKL) +
0.6 (3)
tw(CLKL) +
0.6 (3)
ns
tc(CLK)
Cycle time, I2S_CLK
2
tw(CLKH)
3
tw(CLKL)
8
9
10
40 or
MA
X
CVDD = 1.3 V
40 or
2P (1) (2)
1
7
(1)
(2)
(3)
MA
X
SLAVE
P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
Use whichever value is greater.
In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK).
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Table 5-25. Timing Requirements for I2S
[I/O = 1.8 V] (1) (see Figure 5-24)
MASTER
NO.
CVDD = 1.05 V
MIN
SLAVE
CVDD = 1.3 V
MAX
MIN
CVDD = 1.05 V
MAX
MIN
CVDD = 1.3 V
MAX
MIN
UNIT
MAX
50 or
2P (1)
40 or
2P (1)
(2)
50 or
2P (1) (2)
40 or
2P (1) (2)
ns
1
tc(CLK)
Cycle time, I2S_CLK
2
tw(CLKH)
Pulse duration, I2S_CLK high
25
20
25
20
ns
3
tw(CLKL)
Pulse duration, I2S_CLK low
25
20
25
20
ns
tsu(RXV-CLKH)
Setup time, I2S_RX valid before
I2S CLK high (CLKPOL = 0)
5
5
5
5
ns
tsu(RXV-CLKL)
Setup time, I2S_RX valid before
I2S_CLK low (CLKPOL = 1)
5
5
5
5
ns
th(CLKH-RXV)
Hold time, I2S_RX valid after
I2S_CLK high (CLKPOL = 0)
3
3
3
3
ns
th(CLKL-RXV)
Hold time, I2S_RX valid after
I2S_CLK low (CLKPOL = 1)
3
3
3
3
ns
tsu(FSV-CLKH)
Setup time, I2S_FS valid before
I2S_CLK high (CLKPOL = 0)
–
–
15
15
ns
tsu(FSV-CLKL)
Setup time, I2S_FS valid before
I2S_CLK low (CLKPOL = 1)
–
–
15
15
ns
th(CLKH-FSV)
Hold time, I2S_FS valid after
I2S_CLK high (CLKPOL = 0)
–
–
tw(CLKH) +
0.6 (3)
tw(CLKH) +
0.6 (3)
ns
th(CLKL-FSV)
Hold time, I2S_FS valid after
I2S_CLK low (CLKPOL = 1)
–
–
tw(CLKL) +
0.6 (3)
tw(CLKL) +
0.6 (3)
ns
7
8
9
10
(1)
(2)
(3)
(2)
P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
Use whichever value is greater.
In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK).
Table 5-26. Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 3.3 V, 2.75 V, or 2.5 V] (see Figure 5-24)
MASTER
NO.
PARAMETER
CVDD = 1.05
V
MIN
1
2
3
4
MAX
MIN
MAX
MIN
MAX
40 or
2P (1)
40 or
2P (1)
40 or
2P (1)
40 or
2P (1)
ns
tw(CLKH)
Pulse duration, I2S_CLK high (CLKPOL = 0)
20
20
20
20
ns
tw(CLKL)
Pulse duration, I2S_CLK low (CLKPOL = 1)
20
20
20
20
ns
tw(CLKL)
Pulse duration, I2S_CLK low (CLKPOL = 0)
20
20
20
20
ns
tw(CLKH)
Pulse duration, I2S_CLK high (CLKPOL = 1)
20
20
20
20
ns
tdmax(CLKL-
Output Delay time, I2S_CLK low to I2S_DX valid
(CLKPOL = 0)
0
15
0
14
0
15
0
15
ns
Output Delay time, I2S_CLK high to I2S_DX
valid (CLKPOL = 1)
0
15
0
14
0
15
0
15
ns
Delay time, I2S_CLK low to I2S_FS valid
(CLKPOL = 0)
-1.1
14
-1.1
14
–
–
ns
Delay time, I2S_CLK high to I2S_FS valid
(CLKPOL = 1)
-1.1
14
-1.1
14
–
–
ns
DXV)
tdmax(CLKH-
FSV)
tdmax(CLKHFSV)
92
MIN
CVDD = 1.3 V UNIT
Cycle time, I2S_CLK
tdmax(CLKL-
(1)
(2)
CVDD = 1.3 V
tc(CLK)
DXV)
5
MAX
SLAVE
CVDD = 1.05
V
(2)
(2)
(2)
(2)
P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
Use whichever value is greater.
Specifications
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Table 5-27. Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 1.8 V] (see Figure 5-24)
MASTER
NO.
CVDD = 1.05
V
PARAMETER
MIN
1
2
3
4
MIN
MAX
MIN
MAX
CVDD = 1.3 V UNIT
MIN
MAX
50 or
2P (1)
40 or
2P (1)
50 or
2P (1)
40 or
2P (1)
ns
Cycle time, I2S_CLK
tw(CLKH)
Pulse duration, I2S_CLK high (CLKPOL = 0)
25
20
25
20
ns
tw(CLKL)
Pulse duration, I2S_CLK low (CLKPOL = 1)
25
20
25
20
ns
tw(CLKL)
Pulse duration, I2S_CLK low (CLKPOL = 0)
25
20
25
20
ns
tw(CLKH)
Pulse duration, I2S_CLK high (CLKPOL = 1)
25
20
25
20
ns
tdmax(CLKL-
Output Delay time, I2S_CLK low to I2S_DX valid
(CLKPOL = 0)
0
19
0
14
0
19
0
16.5
ns
Output Delay time, I2S_CLK high to I2S_DX
valid (CLKPOL = 1)
0
19
0
14
0
19
0
16.5
ns
Delay time, I2S_CLK low to I2S_FS valid
(CLKPOL = 0)
-1.1
14
-1.1
14
–
–
ns
Delay time, I2S_CLK high to I2S_FS valid
(CLKPOL = 1)
-1.1
14
-1.1
14
–
–
ns
DXV)
tdmax(CLKHtdmax(CLKLFSV)
tdmax(CLKHFSV)
(1)
(2)
CVDD = 1.3 V
tc(CLK)
DXV)
5
MAX
SLAVE
CVDD = 1.05
V
(2)
(2)
(2)
(2)
P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
Use whichever value is greater.
1
3
2
I2S_CLK
(CLKPOL = 0)
I2S_CLK
(CLKPOL = 1)
5
I2S_FS
(Output, MODE = 1)
9
10
7
8
I2S_FS
(Input, MODE = 0)
4
I2S_DX
I2S_RX
Figure 5-24. I2S Input and Output Timings
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5.7.10 Liquid Crystal Display Controller (LCDC) — C5535 Only
The device includes a LCD Interface Display Driver (LIDD) controller.
The LIDD Controller supports the asynchronous LCD interface and has the following features:
• Provides full-timing programmability of control signals and output data
Note: Raster mode is not supported on this device.
The LCD controller is responsible for generating the correct external timing. The DMA engine provides a
constant flow of data from the frame buffer to the external LCD panel via the LIDD controller. In addition,
CPU access is provided to read and write registers.
Because the LCD Controller is supported on only TMS320C5535, the LCD Controller clock gate control bit
in PCGCR2 must be disabled for a lower operating power on TMS320C5534, C5533, and C5532. For
more information, see TMS320C5535/34/33/32 Ultra-Low Power DSP Technical Reference Manual
(literature number SPRUH87).
94
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
5.7.10.1 LCDC Electrical Data and Timing
Table 5-28. Timing Requirements for LCD LIDD Mode (1) (see Figure 5-25 through Figure 5-32)
CVDD = 1.05 V
NO.
MIN
CVDD = 1.3 V
MAX
MIN
MAX
UNIT
16
tsu(LCD_D-CLK)
Setup time, LCD_D[15:0] valid
before LCD_CLK rising edge
27
42
ns
17
th(CLK-LCD_D)
Hold time, LCD_D[15:0] valid after
LCD_CLK rising edge
0
0
ns
(1)
Over operating free-air temperature range (unless otherwise noted)
Table 5-29. Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode (see
Figure 5-25 through Figure 5-32)
NO.
PARAMETER
4
td(LCD_D_V)
Delay time, LCD_CLK rising edge
to LCD_D[15:0] valid (write)
5
td(LCD_D_I)
Delay time, LCD_CLK rising edge
to LCD_D[15:0] invalid (write)
6
td(LCD_E_A)
Delay time, LCD_CLK rising edge
to LCD_CSx_Ex low
7
td(LCD_E_I)
Delay time, LCD_CLKrising edge
to LCD_CSx_Ex high
8
td(LCD_A_A)
Delay time, LCD_CLKrising edge
to LCD_RS low
9
td(LCD_A_I)
Delay time, LCD_CLK rising edge
to LCD_RS high
10
td(LCD_W_A)
Delay time, LCD_CLK rising edge
to LCD_RW_WRB low
11
td(LCD_W_I)
Delay time, LCD_CLK rising edge
to LCD_RW_WRB high
12
td(LCD_STRB_A)
Delay time, LCD_CLK rising edge
to LCD_EN_RDB high
13
td(LCD_STRB_I)
Delay time, LCD_CLK rising edge
to LCD_EN_RDB low
14
td(LCD_D_Z)
Delay time, LCD_CLK rising edge
to LCD_D[15:0] in 3-state
15
td(Z_LCD_D)
Delay time, LCD_CLK rising edge
to LCD_D[15:0] valid from 3-state
CVDD = 1.05 V
MIN
CVDD = 1.3 V
MAX
MIN
5
-6
7
-6
5
-6
-6
-6
-6
-6
-6
-6
-6
-6
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ns
ns
ns
7
Copyright © 2011–2014, Texas Instruments Incorporated
ns
ns
7
5
ns
ns
7
5
ns
ns
7
5
UNIT
ns
7
5
-6
MAX
ns
ns
Specifications
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W_SU
(0 to 31)
LCD_CLK
[Internal]
www.ti.com
CS_DELAY
(0 to 3)
W_STROBE
(1 to 63)
R_SU
(0 to 31)
R_HOLD
(1 to 15)
W_HOLD
(1 to 15)
4
CS_DELAY
(0 to 3)
R_STROBE
(1 to 63)
5
14
17
16
LCD_D[15:0]
15
Write Data
Data[7:0]
Read Status
8
9
LCD_RS
RS
10
11
LCD_RW_WRB
R/W
12
12
13
13
E0
E1
LCD_CSx_Ex
Figure 5-25. Character Display HD44780 Write
W_HOLD
(1–15)
R_SU
(0–31)
R_STROBE
R_HOLD
CS_DELAY
(1–63)
(1–5)
(0-3)
(0–31)
W_SU
17
15
4
W_STROBE
CS_DELAY
(1–63)
(0 - 3)
LCD_CLK
[Internal]
14
16
LCD_D[7:0]
5
Data[7:0]
Write Instruction
Read
Data
8
9
RS
LCD_RS
10
11
LCD_RW_WRB
R/W
12
12
13
LCD_CSx_Ex
13
E0
E1
Figure 5-26. Character Display HD44780 Read
96
Specifications
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W_HOLD
(1-15)
W_HOLD
(1-15)
W_SU
(0-31)
W_STROBE
(1-63)
CS_DELAY
W_SU
(0-3)
(0-31)
W_STROBE
CS_DELAY
(0-3)
(1-63)
LCD_CLK
[Internal]
4
LCD_D[15:0]
LCD_CSx_Ex
(async mode)
5
5
4
Write Address
Write Data
7
6
Data[15:0]
6
7
CS0
CS1
9
8
RS
LCD_RS
10
11
11
10
R/W
LCD_RW_WRB
12
13
12
13
EN
LCD_EN_RDB
Figure 5-27. Micro-Interface Graphic Display 6800 Write
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W_HOLD
(1-15)
W_SU
(0-31)
W_STROBE
R_SU
(0-31)
CS_DELAY
(1-63)
R_STROBE
(1-63
(0-3)
R_HOLD
CS_DELAY
(1-15)
(0-3)
17
15
LCD_CLK
[Internal]
5
4
LCD_D[15:0]
14
16
Write Address
Data[15:0]
6
7
Read
Data
6
LCD_CSx_Ex
(Async Mode)
7
CS0
CS1
9
8
LCD_RS
RS
10
11
LCD_RW_WRB
R/W
12
13
12
13
LCD_EN_RDB
EN
Figure 5-28. Micro-Interface Graphic Display 6800 Read
98
Specifications
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R_SU
(0-31)
R_SU
(0-31)
R_STROBE R_HOLD CS_DELAY
(1-63)
(1-15)
(0-3)
16
17
15
R_STROBE R_HOLD CS_DELAY
(1-63)
(1-15)
(0-3)
17
15
LCD_CLK
[Internal]
14
16
14
LCD_D[15:0]
LCD_CSx_Ex
(Async Mode)
Data[15:0]
Read
Data
6
7
Read
Status
6
7
CS0
CS1
8
9
LCD_RS
RS
LCD_RW_WRB
R/W
12
13
12
13
EN
LCD_EN_RDB
Figure 5-29. Micro-Interface Graphic Display 6800 Status
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W_HOLD
(1-15)
W_HOLD
(1-15)
W_SU
W_STROBE
CS_DELAY
W_SU
(0-31)
(1-63)
(0-3)
(0-31)
W_STROBE
CS_DELAY
(1-63)
(0 - 3)
LCD_CLK
[Internal]
4
LCD_D[15:0]
LCD_CSx_Ex
(Async Mode)
5
4
Write Address
5
DATA[15:0]
Write Data
7
6
6
7
CS0
CS1
8
9
LCD_RS
RS
10
11
10
11
LCD_RW_WRB
WRB
LCD_EN_RDB
RDB
Figure 5-30. Micro-Interface Graphic Display 8080 Write
100
Specifications
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
W_HOLD
(1-15)
W_SU
(0-31)
W_STROBE
R_SU
(0-31)
CS_DELAY
(1-63)
R_STROBE
(0-3)
R_HOLD
CS_DELAY
(1-63)
(1-15)
(0-3)
16
17
15
LCD_CLK
[Internal]
4
LCD_D[15:0]
5
14
Data[15:0]
Write Address
6
7
LCD_CSx_Ex
(async mode)
6
Read
Data
7
CS0
CS1
9
8
LCD_RS
RS
10
11
WRB
LCD_RW_WRB
12
13
RDB
LCD_EN_RDB
Figure 5-31. Micro-Interface Graphic Display 8080 Read
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R_SU
(0-31)
R_SU
(0-31)
R_STROBE
(1-63)
R_HOLD
(1-15)
CS_DELAY
R_STROBE R_HOLD
(0-3)
(1-63)
(1-15)
16
17
CS_DELAY
(0-3)
LCD_CLK
[Internal]
14
16
17
15
14
15
Data[15:0]
LCD_D[15:0]
Read Data
Read Status
7
6
6
7
LCD_CSx_Ex
CS0
CS1
8
9
LCD_RS
RS
LCD_RW_WRB
WRB
12
13
12
13
RDB
LCD_PCLK
Figure 5-32. Micro-Interface Graphic Display 8080 Status
102
Specifications
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
5.7.11 Real-Time Clock (RTC)
The device includes a Real-Time Clock (RTC) with its own separated power supply and isolation circuits.
The separate supply and isolation circuits allow the RTC to run with the least possible power consumption,
called RTC-only mode. The RTC-only mode requires CVDDRTC, LDOI, and DVDDRTC power domains to be
powered, but other power domains can be shut off. See Section 5.7.11.1, RTC-Only Mode for details. All
RTC registers are preserved (except for RTC Control and RTC Update Registers) and the counter
continues to operate when the device is powered off.
The RTC also has the capability to wake up the device from idle states via alarms, periodic interrupts, or
an external WAKEUP input. Additionally, the RTC is able to output an alarm or periodic interrupt on the
WAKEUP pin to cause external power management to re-enable power to the DSP Core and I/O. Note:
The RTC Core (CVDDRTC) must be properly powered by an external power source even though RTC is not
used. None of the on-chip LDOs can power CVDDRTC.
The device RTC provides the following features:
• 100-year calendar up to year 2099.
• Counts seconds, minutes, hours, day of the week, date, month, and year with leap year compensation
• Millisecond time correction
• Binary-coded-decimal (BCD) representation of time, calendar, and alarm
• 24-hour clock mode
• Second, minute, hour, day, or week alarm interrupt
• Periodic interrupt: every millisecond, second, minute, hour, or day
• Alarm interrupt: precise time of day
• Single interrupt to the DSP CPU
• 32.768-kHz crystal oscillator with frequency calibration
Control of the RTC is maintained through a set of I/O memory mapped registers (see Table 6-15). Note
that any write to these registers will be synchronized to the RTC 32.768-kHz clock; thus, the CPU must
run at least 3X faster than the RTC. Writes to these registers will not be evident until the next two 32.768kHz clock cycles later. Furthermore, if the RTC Oscillator is disabled, no RTC register can be written to.
The RTC has its own power-on-reset (POR) circuit which resets the registers in the RTC core domain
when power is first applied to the CVDDRTC power pin. The RTC flops are not reset by the device's RESET
pin nor the digital core's POR (powergood signal).
The scratch registers in the RTC can be used to take advantage of this unique reset domain to keep track
of when the DSP boots and whether the RTC time registers have already been initialized to the current
clock time or whether the software needs to go into a routine to prompt the user to set the time and date.
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5.7.11.1 RTC-Only Mode
The lowest power consumption can be achieved by using RTC-only mode. There are hardware and
software requirements to use RTC-only mode.
Hardware Requirements:
• The DSP_LDO_EN pin must be tied to GND or pulled down to GND.
• The RTC Core (CVDDRTC), RTC I/O (DVDDRTC), and LDO inputs (LDOI) must be always powered.
CVDDRTC must be powered using an external power source.
• VDDA_ANA is recommended to be powered from the ANA_LDOO pin. (In case VDDA_ANA has to be
powered externally, then VDDA_ANA must be always powered, too.)
• All other power domains can be totally shut down when using RTC-only mode.
– Verify the USB oscillator is disabled according to the workaround described in
TMS320C5535/34/33/32 Fixed-Point DSP Silicon Errata (Silicon Revision 2.2) (literature number
SPRZ373).
• A high pulse for a minimum of one RTC clock period (30.5 µs) to the WAKEUP pin is required to wake
up the device from the RTC only mode.
Power Down Sequence:
1. CPU must set the LDO_PD bit or the BG_PD bit in the RTCPMGT register (See Figure 5-3). Once the
LDO_PD bit or the BG_PD bit is set to 1, the DSP_LDOO will be internally shut off and it will cause the
internal POR holds the internal POWERGOOD signal low, which creates isolation for RTC.
2. All of the device power domains can be shut down except RTC Core (CVDDRTC), RTC I/O (DVDDRTC),
and LDO inputs (LDOI).
Wake-Up Sequence:
1. When waking up the device, all power domains must be turned back on before or upon applying a
pulse to WAKEUP.
2. A pulse (≥ 30.5 µs) must be applied to the WAKEUP pin (active high). When the WAKEUP pin is
asserted, the voltage on the DSP_LDOO pin will start ramping up and it is monitored by the internal
POR. Until the voltage reaches to the threshold level, the internal POR will hold the internal
POWERGOOD signal low, which provides isolation to RTC during transition period. Once the voltage
reaches to the threshold level, the internal POR asserts the internal POWERGOOD signal (logic level
high) and it resets reset of the system and disables RTC isolation and enables CPU to communicate
with RTC.
104
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
5.7.12 SAR ADC (10-Bit) — C5535 Only
The device includes a 10-bit SAR ADC using a switched capacitor architecture which converts an analog
input signal to a digital value at a maximum rate of 62.5-k samples per second (ksps) for use by the DSP.
This SAR module supports six channels that are connected to four general purpose analog pins (GPAIN
[3:0 ]) which can be used as general purpose outputs.
The device SAR supports the following features:
• Up to 62.5 ksps (2-MHz clock with 32 cycles per conversion)
• Single conversion and continuous back-to-back conversion modes
• Interrupt driven or polling conversion or DMA event generation
• Internal configurable bandgap reference voltages of 1 V or 0.8 V; or external Vref of VDDA_ANA
• One 3.6-V Tolerant analog input (GPAIN0) with internal voltage division for conversion of battery
voltage
• Software controlled power down
• Individually configurable general-purpose digital outputs
5.7.12.1 SAR ADC Electrical Data and Timing
Table 5-30. Switching Characteristics Over Recommended Operating Conditions for ADC Characteristics
NO.
PARAMETER
CVDD = 1.3 V
CVDD = 1.05 V
MIN
1
tC(SCLC)
Cycle time, ADC internal conversion clock
3
td(CONV)
Delay time, ADC conversion time
4
SDNL
Static differential non-linearity error (DNL measured for 9 bits)
5
SINL
Static integral non-linearity error
6
Zset
Zero-scale offset error (INL measured for 9 bits)
7
Fset
Full-scale offset error
8
Analog input impedance
9
Signal-to-noise ratio
TYP
UNIT
MAX
2
32tC(SCLC)
±0.6
LSB
2
LSB
2
LSB
1
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ns
LSB
±1
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MHz
MΩ
54
dB
Specifications
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5.7.13 Secure Digital (SD)
The device includes two SD controllers which are compliant with Secure Digital Part 1 Physical Layer
Specification V2.0 and Secure Digital Input Output (SDIO) V2.0 and eMMC V4.3 specifications. The SD
card controller supports these industry standards and assumes the reader is familiar with these standards.
Each SD controller in the device has the following features:
• Embedded Multimedia Card and Secure Digital (eMMC, SD, HCSD, and HSSD) protocol support
• Programmable clock frequency
• 512-bit read and write FIFO to lower system overhead
• Slave DMA transfer capability
The SD card controller transfers data between the CPU and DMA controller on one side and the SD card
on the other side. The CPU and DMA controller can read and write the data in the card by accessing the
registers in the SD controller.
The SD controller on this device, does not support the SPI mode of operation.
106
Specifications
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
5.7.13.1 SD Electrical Data and Timing
Table 5-31. Timing Requirements for SD (see Figure 5-33 and Figure 5-36)
NO
.
CVDD = 1.3 V
CVDD = 1.05 V
FAST MODE
STD MODE
MIN
MAX
MIN
UNIT
MAX
1
tsu(CMDV-CLKH)
Setup time, SDx_CMD data input valid before SDx_CLK high
3
3
ns
2
th(CLKH-CMDV)
Hold time, SDx_CMD data input valid after SDx_CLK high
3
3
ns
3
tsu(DATV-CLKH)
Setup time, SD_Dx data input valid before SDx_CLK high
3
3
ns
4
th(CLKH-DATV)
Hold time, SD_Dx data input valid after SDx_CLK high
3
3
ns
Table 5-32. Switching Characteristics Over Recommended Operating Conditions for SD Output (1) (see
Figure 5-33 and Figure 5-36)
NO
.
PARAMETER
CVDD = 1.3 V
CVDD = 1.05 V
FAST MODE
STD MODE
UNIT
MIN
MAX
MIN
MAX
7
f(CLK)
Operating frequency, SDx_CLK
0
50 (2)
0
25 (2)
MHz
8
f(CLK_ID)
Identification mode frequency, SDx_CLK
0
400
0
400
kHz
9
tw(CLKL)
Pulse width, SDx_CLK low
7
10
tw(CLKH)
Pulse width, SDx_CLK high
7
11
tr(CLK)
Rise time, SDx_CLK
3
3
ns
12
tf(CLK)
Fall time, SDx_CLK
3
3
ns
13
td(MDCLKL-CMDIV)
Delay time, SDx_CLK low to SD_CMD data output invalid
14
td(MDCLKL-CMDV)
Delay time, SDx_CLK low to SD_CMD data output valid
15
td(MDCLKL-DATIV)
Delay time, SDx_CLK low to SD_Dx data output invalid
td(MDCLKL-DATV)
Delay time, SDx_CLK low to SD_Dx data output valid
16
(1)
(2)
10
ns
10
-4
ns
-4.1
ns
4
5.1
-4
-4.1
ns
ns
4
5.1
ns
For SD, the parametric values are measured at DVDDIO = 3.3 V and 2.75 V.
Use this value or SYS_CLK/2 whichever is smaller.
7
9
10
SDx_CLK
13
14
VALID
SDx_CMD
Figure 5-33. SD Host Command Write Timing
9
10
7
SDx_CLK
4
4
3
SDx_Dx
3
Start
D0
D1
Dx
End
Figure 5-34. SD Card Response Timing
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9
7
10
SDx_CLK
1
2
SDx_CMD
START
XMIT
Valid
Valid
Valid
END
Figure 5-35. SD Host Write Timing
7
9
10
SDx_CLK
15
16
SDx_DAT
VALID
Figure 5-36. SD Data Write Timing
108
Specifications
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5.7.14 Serial Port Interface (SPI)
The device serial port interface (SPI) is a high-speed synchronous serial input/output port that allows a
serial bit stream of programmed length (1 to 32 bits) to be shifted into and out of the device at a
programmed bit-transfer rate. The SPI supports multi-chip operation of up to four SPI slave devices. The
SPI can operate as a master device only, slave mode is not supported. Note: The SPI is not supported by
the device DMA controller, so DMA cannot be used in transferring data between the SPI and the on-chip
RAM.
The SPI is normally used for communication between the DSP and external peripherals. Typical
applications include an interface to external I/O or peripheral expansion via devices such as shift registers,
display drivers, SPI EEPROMs, and analog-to-digital converters.
The SPI has the following features:
• Programmable divider for serial data clock generation
• Four pin interface (SPI_CLK, SPI_CSn, SPI_RX, and SPI_TX)
• Programmable data length (1 to 32 bits)
• 4 external chip select signals
• Programmable transfer or frame size (1 to 4096 characters)
• Optional interrupt generation on character completion
• Programmable SPI_CSn to SPI_TX delay from 0 to 3 SPI_CLK cycles
• Programmable signal polarities
• Programmable active clock edge
• Internal loopback mode for testing
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5.7.14.1 SPI Electrical Data and Timing
Table 5-33. Timing Requirements for SPI Inputs (see Figure 5-37 through Figure 5-40)
CVDD = 1.05 V
NO.
MIN
Pulse duration, SPI_CLK high
30
19
ns
Pulse duration, SPI_CLK low
30
19
ns
Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 0
16.1
13.9
ns
Setup time, SPI_RX valid before SPI_CLK low, SPI Mode 1
16.1
13.9
ns
Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 2
16.1
13.9
ns
Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 3
5
tw(SCLKH)
6
tw(SCLKL)
(1)
(2)
th(SCLK-SRXV)
UNIT
ns
Cycle time, SPI_CLK
8
MAX
40 or
4P (1) (2)
tC(SCLK)
tsu(SRXV-SCLK)
MIN
66.4 or
4P (1) (2)
4
7
CVDD = 1.3 V
MAX
16.1
13.9
ns
Hold time, SPI_RX valid after SPI_CLK high, SPI Mode 0
0
0
ns
Hold time, SPI_RX valid after SPI_CLK low, SPI Mode 1
0
0
ns
Hold time, SPI_RX valid after SPI_CLK low, SPI Mode 2
0
0
ns
Hold time, SPI_RX valid after SPI_CLK high, SPI Mode 3
0
0
ns
P = SYSCLK period in ns. For example, when the CPU core is clocked at 100 MHz, use P = 10 ns.
Use whichever value is greater.
Table 5-34. Switching Characteristics Over Recommended Operating Conditions for SPI Outputs
(see Figure 5-37 through Figure 5-40)
NO.
1
CVDD = 1.05 V
PARAMETER
td(SCLK-STXV)
UNIT
MAX
MIN
MAX
Delay time, SPI_CLK low to SPI_TX valid, SPI
Mode 0
-4.2
8.9
-4.9
5.3
ns
Delay time, SPI_CLK high to SPI_TX valid, SPI
Mode 1
-4.2
8.9
-4.9
5.3
ns
Delay time, SPI_CLK high to SPI_TX valid, SPI
Mode 2
-4.2
8.9
-4.9
5.3
ns
Delay time, SPI_CLK low to SPI_TX valid, SPI
Mode 3
-4.2
8.9
-4.9
5.3
ns
tC - 8 + D (1)
ns
2
td(SPICS-SCLK)
Delay time, SPI_CS active to SPI_CLK active
3
toh(SCLKI-SPICSI)
Output hold time, SPI_CS inactive to SPI_CLK
inactive
(1)
CVDD = 1.3 V
MIN
tC - 8 + D (1)
0.5tC - 2.2
0.5tC - 2.2
ns
D is the programable data delay in ns. Data delay can be programmed to 0, 1, 2, or 3 SPICLK clock cycles.
4
6
5
SPI_CLK
1
SPI_TX
B0
SPI_RX
B1
B0
2
B1
7
Bn-2
Bn-1
Bn-2
Bn-1
8
3
SPI_CS
A.
B.
Character length is programmable between 1 and 32 bits; 8-bit character length shown.
Polarity of SPI_CSn is configurable, active-low polarity is shown.
Figure 5-37. SPI Mode 0 Transfer (CKPn = 0, CKPHn = 0)
110
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4
6
5
SPI_CLK
1
B0
SPI_TX
B1
SPI_RX
7
2
B1
Bn-2
Bn-1
B1
Bn-2
Bn-1
8
3
SPI_CS
A.
B.
Character length is programmable between 1 and 32 bits; 8-bit character length shown.
Polarity of SPI_CSn is configurable, active-low polarity is shown.
Figure 5-38. SPI Mode 1 Transfer (CKPn = 0, CKPHn = 1)
4
5
6
SPI_CLK
1
SPI_TX
SPI_RX
B0
B1
B0
B1
Bn-2
Bn-1
Bn-2
7
2
Bn-1
3
8
SPI_CS
A.
B.
Character length is programmable between 1 and 32 bits; 8-bit character length shown.
Polarity of SPI_CSn is configurable, active-low polarity is shown.
Figure 5-39. SPI Mode 2 Transfer (CKPn = 1, CKPHn = 0)
4
5
6
SPI_CLK
1
B0
SPI_TX
B0
SPI_RX
SPI_CS
A.
B.
2
7
B1
Bn-2
Bn-1
B1
Bn-2
Bn-1
8
3
Character length is programmable between 1 and 32 bits; 8-bit character length shown.
Polarity of SPI_CSn is configurable, active-low polarity is shown.
Figure 5-40. SPI Mode 3 Transfer (CKPn = 1, CKPHn = 1)
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5.7.15 Universal Asynchronous Receiver/Transmitter (UART)
The UART performs serial-to-parallel conversions on data received from an external peripheral device and
parallel-to-serial conversions on data transmitted to an external peripheral device via a serial bus.
The device has one UART peripheral with the following features:
• Programmable baud rates (frequency pre-scale values from 1 to 65535)
• Fully programmable serial interface characteristics:
– 5, 6, 7, or 8-bit characters
– Even, odd, or no PARITY bit generation and detection
– 1, 1.5, or 2 STOP bit generation
• 16-byte depth transmitter and receiver FIFOs:
– The UART can be operated with or without the FIFOs
– 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
• DMA signaling capability for both received and transmitted data
• CPU interrupt capability for both received and transmitted data
• False START bit detection
• Line break generation and detection
• Internal diagnostic capabilities:
– Loopback controls for communications link fault isolation
– Break, parity, overrun, and framing error simulation
• Programmable autoflow control using CTS and RTS signals
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5.7.15.1 UART Electrical Data and Timing [Receive and Transmit]
Table 5-35. Timing Requirements for UART Receive (1)
(2)
(see Figure 5-41)
CVDD = 1.05 V
NO.
CVDD = 1.3 V
MIN
MAX
MIN
MAX
UNIT
4
tw(URXDB)
Pulse duration, receive data bit (UART_RXD) [15/30 pF]
U - 3.5
U+3
U - 3.5
U+3
ns
5
tw(URXSB)
Pulse duration, receive start bit [15/30 pF]
U - 3.5
U+3
U - 3.5
U+3
ns
(1)
(2)
U = UART baud time = 1/programmed baud rate.
Based on a maximum CPU frequency of 50 MHz.
Table 5-36. Switching Characteristics Over Recommended Operating Conditions for UART Transmit (1)
(see Figure 5-41)
NO.
(1)
(2)
CVDD = 1.05 V
PARAMETER
MIN
MAX
1
f(baud)
Maximum programmable bit rate
2
tw(UTXDB)
Pulse duration, transmit data bit (UART_TXD) [15/30 pF]
U - 3.5
U+4
3
tw(UTXSB)
Pulse duration, transmit start bit [15/30 pF]
U - 3.5
U+4
CVDD = 1.3V
MIN
MAX
3.75
(2)
UNIT
6.25
MHz
U - 3.5
U+4
ns
U - 3.5
U+4
ns
U = UART baud time = 1/programmed baud rate.
Based on a maximum CPU frequency of 50 MHz.
3
2
UART_TXD
Start
Bit
Data Bits
5
4
UART_RXD
Start
Bit
Data Bits
Figure 5-41. UART Transmit and Receive Timing
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5.7.16 Universal Serial Bus (USB) 2.0 Controller — Does Not Apply to C5532
The device USB2.0 peripheral supports the following features:
• USB2.0 peripheral at speeds high-speed (480Mb/s) and full-speed (12Mb/s)
• All transfer modes (control, bulk, interrupt, and isochronous asynchronous mode)
• 4 Transmit (TX) and 4 Receive (RX) Endpoints in addition to Control Endpoint 0
• FIFO RAM
– 4K endpoint
– Programmable size
• Integrated USB2.0 High Speed PHY
• RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
The USB2.0 peripheral on this device, does not support:
• Host Mode (Peripheral and Device Modes supported only)
• On-Chip Charge Pump
• On-the-Go (OTG) Mode
5.7.16.1 USB 2.0 Electrical Data and Timing
Table 5-37. Switching Characteristics Over Recommended Operating Conditions for USB 2.0 (see
Figure 5-42)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
1
PARAMETER
tr(D)
FULL SPEED
12 Mbps
Rise time, USB_DP and USB_DM signals (2)
(2)
HIGH SPEED
480 Mbps (1)
MIN
MAX
MIN
4
20
0.5
UNIT
MAX
ns
2
tf(D)
Fall time, USB_DP and USB_DM signals
4
20
0.5
3
trfM
Rise and Fall time, matching (3)
90
111
–
–
%
4
VCRS
Output signal cross-over voltage (2)
1.3
2
–
–
V
160
175
–
–
ns
(4)
7
tw(EOPT)
Pulse duration, EOP transmitter
8
tw(EOPR)
Pulse duration, EOP receiver (4)
9
t(DRATE)
Data Rate
10
ZDRV
Driver Output Resistance
40.5
11
ZINP
Receiver Input Impedance
100k
(1)
(2)
(3)
(4)
82
ns
–
12
49.5
ns
480
Mb/s
40.5
49.5
Ω
-
-
Ω
For more detailed information, see the Universal Serial Bus Specification, Revision 2.0, Chapter 7.
Full Speed and High Speed CL = 50 pF
tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
Must accept as valid EOP
USB_DM
VCRS
USB_DP
tper - tjr
90% VOH
10% VOL
tr
tf
Figure 5-42. USB2.0 Integrated Transceiver Interface Timing
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5.7.17 Emulation and Debug
5.7.17.1 Debugging Considerations
5.7.17.1.1 Pullup and Pulldown Resistors
Proper board design should ensure that input pins to the device DSP always be at a valid logic level and
not floating. This may be achieved via pullup and pulldown resistors. The DSP features internal pullup
(IPU) and internal pulldown (IPD) resistors on many pins, including all GPIO pins, to eliminate the need,
unless otherwise noted, for external pullup and pulldown resistors.
An external pullup and pulldown resistor may need to be used in the following situations:
• Configuration Pins: An external pullup and pulldown resistor is recommended to set the desired value
or state (see the configuration pins listed in Table 5-8, Default Functions Affected by Device
Configuration Pins). Note that some configuration pins must be connected directly to ground or to a
specific supply voltage.
• Other Input Pins: If the IPU and IPD does not match the desired value or state, use an external pullup
and pulldown resistor to pull the signal to the opposite rail.
For the configuration pins (listed in Table 5-8, Default Functions Affected by Device Configuration Pins), if
they are both routed out and high-impedance state (not driven), it is strongly recommended that an
external pullup and pulldown resistor be implemented. In addition, applying external pullup and pulldown
resistors on the configuration pins adds convenience to the user in debugging and flexibility in switching
operating modes.
When an external pullup or pulldown resistor is used on a pin, the pin’s internal pullup or pulldown resistor
must be disabled through the Pullup and Pulldown Inhibit Registers (PDINHIBR1, 2, and 3) [1C17h,
1C18h, and 1C19h, respectively] to minimize power consumption.
Tips for choosing an external pullup and pulldown resistor:
• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown (IPU and IPD) resistors.
• Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
• Select a pullup and pulldown resistor with the largest possible value; but, which can still ensure that the
net will reach the target pulled value when maximum current from all devices on the net is flowing
through the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup and pulldown resistors on the net.
• For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
• Remember to include tolerances when selecting the resistor value.
• For pullup resistors, also remember to include tolerances on the DVDDIO rail.
For most systems, a 1-kΩ resistor can be used to oppose the IPU and IPD while meeting the above
criteria. Users should confirm this resistor value is correct for their specific application.
For most systems, a 20-kΩ resistor can be used to compliment the IPU and IPD on the configuration pins
while meeting the above criteria. Users should confirm this resistor value is correct for their specific
application.
For more detailed information on input current (II), and the low- and high-level input voltages (VIL and VIH)
for the device DSP, see Section 5.3, Electrical Characteristics.
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For the internal pullup and pulldown resistors for all device pins, see the peripheral and system-specific
signal descriptions table in this document.
5.7.17.1.2 Bus Holders
The device has special I/O bus-holder structures to ensure pins are not left floating when CVDD power is
removed while I/O power is applied. When CVDD is "ON", the bus-holders are disabled and the internal
pullups or pulldowns, if applicable, function normally. But when CVDD is "OFF" and the I/O supply is "ON",
the bus-holders become enabled and any applicable internal pullups and pulldowns are disabled.
The bus-holders are weak drivers on the pin and, for as long as CVDD is "OFF" and I/O power is "ON",
they hold the last state on the pin. If an external device is strongly driving the device I/O pin to the
opposite state then the bus-holder will flip state to match the external driver and DC current will stop.
This bus-holder feature prevents unnecessary power consumption when CVDD is "OFF" and I/O supply is
"ON". For example, current caused by undriven pins (input buffer oscillation) or DC current flowing through
pullups or pulldowns.
If external pullup or pulldown resistors are implemented, then care must be taken that those pullup and
pulldown resistors can exceed the internal bus-holder's max current and thereby cause the bus-holder to
flip state to match the state of the external pullup or pulldown. Otherwise, DC current will flow
unnecessarily. When CVDD power is applied, the bus holders are disabled (for further details on bus
holders, see Section 5.7.2.5, Digital I/O Behavior When Core Power (CVDD) is Down).
5.7.17.1.3 CLKOUT Pin
For debug purposes only, the DSP includes a CLKOUT pin which can be used to tap different clocks
within the clock generator. The SRC bits of the CLKOUT Control Source Register (CCSSR) can be used
to specify the source for the CLKOUT pin.
Note: The bootloader disables the CLKOUT pin via CLKOFF bit in the ST3_55 CPU register.
For more information on the ST3_55 CPU register, see the TMS320C55x 3.0 CPU Reference Guide
(literature number: SWPU073).
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5.7.18 IEEE 1149.1 JTAG
The JTAG interface is used for Boundary-Scan testing and emulation of the device.
TRST should only to be deasserted when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality.
The device includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be
asserted upon power up and the device's internal emulation logic will always be properly initialized. An
external pulldown is also recommended to ensure proper device operation when an emulation or boundary
scan JTAG controller is not connected to the JTAG pins. JTAG controllers from Texas Instruments actively
drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use
of a pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the device
after powerup and externally drive TRST high before attempting any emulation or boundary scan
operations. The device will not operate properly if TRST is not asserted low during powerup.
5.7.18.1 JTAG Test_port Electrical Data and Timing
Table 5-38. Timing Requirements for JTAG Test Port (see Figure 5-43)
CVDD = 1.05 V
CVDD = 1.3 V
NO.
MIN
UNIT
MAX
2
tc(TCK)
Cycle time, TCK
60
ns
3
tw(TCKH)
Pulse duration, TCK high
24
ns
4
tw(TCKL)
Pulse duration, TCK low
24
ns
5
tsu(TDIV-TCKH)
Setup time, TDI valid before TCK high
10
ns
6
tsu(TMSV-TCKH)
Setup time, TMS valid before TCK high
6
ns
7
th(TCKH-TDIV)
Hold time, TDI valid after TCK high
5
ns
8
th(TCKH-TDIV)
Hold time, TMS valid after TCK high
4
ns
Table 5-39. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 5-43)
NO.
CVDD = 1.05 V
CVDD = 1.3 V
PARAMETER
MIN
1
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
UNIT
MAX
30.5
ns
2
3
4
TCK
1
1
TDO
7
5
TDI
8
6
TMS
Figure 5-43. JTAG Test-Port Timing
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6 Detailed Description
6.1
CPU
The fixed-point digital signal processors (DSP) are based on the C55x CPU 3.3 generation processor
core. The C55x DSP architecture achieves high performance and low power through increased parallelism
and total focus on power savings. The CPU supports an internal bus structure that is composed of one
program bus, three data read buses (one 32-bit data read bus and two 16-bit data read buses), two 16-bit
data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the
ability to perform up to four data reads and two data writes in a single cycle. Each DMA controller can
perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit
multiplication in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an
additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize
parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data
Unit (DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The
Instruction Unit (IU) performs 32-bit program fetches from internal or external memory, stores them in a
128-byte Instruction Buffer Queue, and queues instructions for the Program Unit (PU). The Program Unit
decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline.
Predictive branching capability avoids pipeline flushes on execution of conditional instruction calls.
For more detailed information on the CPU, see the TMS320C55x CPU 3.0 CPU Reference Guide
(literature number SWPU073).
6.2
Memory
6.2.1
Internal Memory
6.2.1.1
On-Chip Dual-Access RAM (DARAM)
The DARAM is located in the byte address range 000000h − 00FFFFh and is composed of eight blocks of
4K words each (see Table 6-1). Each DARAM block can perform two accesses per cycle (two reads, two
writes, or a read and a write). The DARAM can be accessed by the internal program, data, or DMA buses.
Table 6-1. DARAM Blocks
(1)
118
CPU
BYTE ADDRESS RANGE
DMA CONTROLLER
BYTE ADDRESS RANGE
MEMORY BLOCK
000000h – 001FFFh
0001 0000h – 0001 1FFFh
DARAM 0 (1)
002000h – 003FFFh
0001 2000h – 0001 3FFFh
DARAM 1
004000h – 005FFFh
0001 4000h – 0001 5FFFh
DARAM 2
006000h – 007FFFh
0001 6000h – 0001 7FFFh
DARAM 3
008000h – 009FFFh
0001 8000h – 0001 9FFFh
DARAM 4
00A000h – 00BFFFh
0001 A000h – 0001 BFFFh
DARAM 5
00C000h – 00DFFFh
0001 C000h – 0001 DFFFh
DARAM 6
00E000h – 00FFFFh
0001 E000h – 0001 FFFFh
DARAM 7
The first 192 bytes are reserved for memory-mapped registers (MMRs). See Section 6.2.2, Memory
Map Summary.
Detailed Description
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6.2.1.2
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On-Chip Read-Only Memory (ROM)
The zero-wait-state ROM is located at the byte address range FE0000h – FFFFFFh. The ROM is
composed of four 16K-word blocks, for a total of 128K bytes of ROM. The ROM address space can be
mapped by software to the internal ROM.
The standard device includes a bootloader program resident in the ROM.
When the MPNMC bit field of the ST3 status register is cleared (by default), the byte address range
FE0000h – FFFFFFh is reserved for the on-chip ROM. When the MPNMC bit field of the ST3 status
register is set through software, the on-chip ROM is disabled and not present in the memory map, and
byte address range FE0000h – FFFFFFh is unmapped. A hardware reset always clears the MPNMC bit,
so it is not possible to disable the ROM at reset. However, the software reset instruction does not affect
the MPNMC bit. The ROM can be accessed by the program and data buses. Each on-chip ROM block is
a one cycle per word access memory.
6.2.1.3
On-Chip Single-Access RAM (SARAM)
Section 6.2.1.3.1 explains the SARAM blocks for the C5535. Section 6.2.1.3.2 explains the SARAM blocks
for the C5534. Section 6.2.1.3.3 explains the SARAM blocks for the C5533. The C5532 has no SARAM
blocks.
6.2.1.3.1 SARAM for C5535
The SARAM is located at the byte address range 010000h – 04FFFFh and is composed of 32 blocks of
4K words each (see Table 6-2). Each SARAM block can perform one access per cycle (one read or one
write). SARAM can be accessed by the internal program, data, or DMA buses.
SARAM is also accessed by the USB and LCD DMA buses.
Table 6-2. SARAM Blocks for C5535
CPU
BYTE ADDRESS RANGE
DMA and USB CONTROLLER
BYTE ADDRESS RANGE
MEMORY BLOCK
010000h − 011FFFh
0009 0000h – 0009 1FFFh
SARAM 0
012000h − 013FFFh
0009 2000h – 0009 3FFFh
SARAM 1
014000h − 015FFFh
0009 4000h – 0009 5FFFh
SARAM 2
016000h − 017FFFh
0009 6000h – 0009 7FFFh
SARAM 3
018000h − 019FFFh
0009 8000h – 0009 9FFFh
SARAM 4
01A000h − 01BFFFh
0009 A000h – 0009 BFFFh
SARAM 5
01C000h − 01DFFFh
0009 C000h – 0009 DFFFh
SARAM 6
01E000h − 01FFFFh
0009 E000h – 0009 FFFFh
SARAM 7
020000h − 021FFFh
000A 0000h – 000A 1FFFh
SARAM 8
022000h − 023FFFh
000A 2000h – 000A 3FFFh
SARAM 9
024000h − 025FFFh
000A 4000h – 000A 5FFFh
SARAM 10
026000h − 027FFFh
000A 6000h – 000A 7FFFh
SARAM 11
028000h − 029FFFh
000A 8000h – 000A 9FFFh
SARAM 12
02A000h − 02BFFFh
000A A000h – 000A BFFFh
SARAM 13
02C000h − 02DFFFh
000A C000h – 000A DFFFh
SARAM 14
02E000h − 02FFFFh
000A E000h – 000A FFFFh
SARAM 15
030000h − 031FFFh
000B 0000h – 000B 1FFFh
SARAM 16
032000h − 033FFFh
000B 2000h – 000B 3FFFh
SARAM 17
034000h − 035FFFh
000B 4000h – 000B 5FFFh
SARAM 18
036000h − 037FFFh
000B 6000h – 000B 7FFFh
SARAM 19
038000h − 039FFFh
000B 8000h – 000B 9FFFh
SARAM 20
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Table 6-2. SARAM Blocks for C5535 (continued)
CPU
BYTE ADDRESS RANGE
(1)
DMA and USB CONTROLLER
BYTE ADDRESS RANGE
MEMORY BLOCK
03A000h − 03BFFFh
000B A000h – 000B BFFFh
SARAM 21
03C000h − 03DFFFh
000B C000h – 000B DFFFh
SARAM 22
03E000h − 03FFFFh
000B E000h – 000B FFFFh
SARAM 23
040000h – 041FFFh
000C 0000h – 000C 1FFFh
SARAM 24
042000h – 043FFFh
000C 2000h – 000C 3FFFh
SARAM 25
044000h – 045FFFh
000C 4000h – 000C 5FFFh
SARAM 26
046000h – 047FFFh
000C 6000h – 000C 7FFFh
SARAM 27
048000h – 049FFFh
000C 8000h – 000C 9FFFh
SARAM 28
04A000h – 04BFFFh
000C A000h – 000C BFFFh
SARAM 29
04C000h – 04DFFFh
000C C000h – 000C DFFFh
SARAM 30
04E000h – 04FFFFh
000C E000h – 000C FFFFh
SARAM 31 (1)
SARAM31 (byte address range: 0x4E000 – 0x4EFFF) is reserved for the bootloader. After the boot
process is complete, this memory space can be used.
6.2.1.3.2 SARAM for C5534
The SARAM is located at the byte address range 010000h – 03FFFFh and is composed of 24 blocks of
4K words each (see Table 6-3). Each SARAM block can perform one access per cycle (one read or one
write). SARAM can be accessed by the internal program, data, or DMA buses. SARAM is also accessed
by the USB bus.
Table 6-3. SARAM Blocks for C5534
120
CPU
BYTE ADDRESS RANGE
DMA and USB CONTROLLER
BYTE ADDRESS RANGE
MEMORY BLOCK
010000h − 011FFFh
0009 0000h – 0009 1FFFh
SARAM 0
012000h − 013FFFh
0009 2000h – 0009 3FFFh
SARAM 1
014000h − 015FFFh
0009 4000h – 0009 5FFFh
SARAM 2
016000h − 017FFFh
0009 6000h – 0009 7FFFh
SARAM 3
018000h − 019FFFh
0009 8000h – 0009 9FFFh
SARAM 4
01A000h − 01BFFFh
0009 A000h – 0009 BFFFh
SARAM 5
01C000h − 01DFFFh
0009 C000h – 0009 DFFFh
SARAM 6
01E000h − 01FFFFh
0009 E000h – 0009 FFFFh
SARAM 7
020000h − 021FFFh
000A 0000h – 000A 1FFFh
SARAM 8
022000h − 023FFFh
000A 2000h – 000A 3FFFh
SARAM 9
024000h − 025FFFh
000A 4000h – 000A 5FFFh
SARAM 10
026000h − 027FFFh
000A 6000h – 000A 7FFFh
SARAM 11
028000h − 029FFFh
000A 8000h – 000A 9FFFh
SARAM 12
02A000h − 02BFFFh
000A A000h – 000A BFFFh
SARAM 13
02C000h − 02DFFFh
000A C000h – 000A DFFFh
SARAM 14
02E000h − 02FFFFh
000A E000h – 000A FFFFh
SARAM 15
030000h − 031FFFh
000B 0000h – 000B 1FFFh
SARAM 16
032000h − 033FFFh
000B 2000h – 000B 3FFFh
SARAM 17
034000h − 035FFFh
000B 4000h – 000B 5FFFh
SARAM 18
036000h − 037FFFh
000B 6000h – 000B 7FFFh
SARAM 19
038000h − 039FFFh
000B 8000h – 000B 9FFFh
SARAM 20
03A000h − 03BFFFh
000B A000h – 000B BFFFh
SARAM 21
03C000h − 03DFFFh
000B C000h – 000B DFFFh
SARAM 22
Detailed Description
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Table 6-3. SARAM Blocks for C5534 (continued)
CPU
BYTE ADDRESS RANGE
DMA and USB CONTROLLER
BYTE ADDRESS RANGE
MEMORY BLOCK
03E000h − 03FFFFh
000B E000h – 000B FFFFh
SARAM 23
6.2.1.3.3 SARAM for C5533
The SARAM is located at the byte address range 010000h – 01FFFFh and is composed of 8 blocks of 4K
words each (see Table 6-4). Each SARAM block can perform one access per cycle (one read or one
write). SARAM can be accessed by the internal program, data, or DMA buses. SARAM is also accessed
by the USB bus.
Table 6-4. SARAM Blocks for C5533
6.2.1.4
CPU
BYTE ADDRESS RANGE
DMA and USB CONTROLLER
BYTE ADDRESS RANGE
MEMORY BLOCK
010000h − 011FFFh
0009 0000h – 0009 1FFFh
SARAM 0
012000h − 013FFFh
0009 2000h – 0009 3FFFh
SARAM 1
014000h − 015FFFh
0009 4000h – 0009 5FFFh
SARAM 2
016000h − 017FFFh
0009 6000h – 0009 7FFFh
SARAM 3
018000h − 019FFFh
0009 8000h – 0009 9FFFh
SARAM 4
01A000h − 01BFFFh
0009 A000h – 0009 BFFFh
SARAM 5
01C000h − 01DFFFh
0009 C000h – 0009 DFFFh
SARAM 6
01E000h − 01FFFFh
0009 E000h – 0009 FFFFh
SARAM 7
I/O Memory
Each device includes a 64K byte I/O space for the memory-mapped registers of the DSP peripherals and
system registers used for idle control, status monitoring and system configuration. I/O space is separate
from program and memory space and is accessed with separate instruction opcodes or via the DMAs.
Table 6-5, Table 6-6 and Table 6-7 list the memory-mapped registers of each device. Note that not all
addresses in the 64K byte I/O space are used; these addresses must be treated as reserved and not
accessed by the CPU nor DMA. For the expanded tables of each peripheral, see , Peripheral Information
and Electrical Specifications of this document.
Some DMA controllers have access to the I/O-Space memory-mapped registers of the following
peripherals registers: I2C, UART, I2S, SD, USB, and SAR ADC.
Before accessing any peripheral memory-mapped register, make sure the peripheral being accessed is
not held in reset via the Peripheral Reset Control Register (PRCR) and its internal clock is enabled via the
Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2).
Table 6-5. Peripheral I/O-Space Control Registers for C5535
WORD ADDRESS
PERIPHERAL
0x0000 – 0x0004
Idle Control
0x0005 – 0x000D through 0x0803 – 0x0BFF
Reserved
0x0C00 – 0x0C7F
DMA0
0x0C80 – 0x0CFF
Reserved
0x0D00 – 0x0D7F
DMA1
0x0D80 – 0x0DFF
Reserved
0x0E00 – 0x0E7F
DMA2
0x0E80 – 0x0EFF
Reserved
Detailed Description
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Table 6-5. Peripheral I/O-Space Control Registers for C5535 (continued)
WORD ADDRESS
PERIPHERAL
0x0F00 – 0x0F7F
DMA3
0x0F80 – 0x17FF
Reserved
0x1800 – 0x181F
Timer0
0x1820 – 0x183F
Reserved
0x1840 – 0x185F
Timer1
0x1860 – 0x187F
Reserved
0x1880 – 0x189F
Timer2
0x1900 – 0x197F
RTC
0x1980 – 0x19FF
Reserved
0x1A00 – 0x1A6C
I2C
0x1A6D – 0x1AFF
Reserved
0x1B00 – 0x1B1F
UART
0x1B80 – 0x1BFF
Reserved
0x1C00 – 0x1CFF
System Control
0x1D00 – 0x1FFF through 0x2600 – 0x27FF
Reserved
0x2800 – 0x2840
I2S0
0x2900 – 0x2940
I2S1
0x2A00 – 0x2A40
I2S2
0x2B00 – 0x2B40
I2S3
0x2C41 – 0x2DFF
Reserved
0x2E00 – 0x2E40
LCD
0x2E41 – 0x2FFF
Reserved
0x3000 – 0x300F
SPI
0x3010 – 0x39FF
Reserved
0x3A00 – 0x3A7F
SD0
0x3A80 – 0x3AFF
Reserved
0x3B00 – 0x3B7F
SD1
0x3B80 – 0x6FFF
Reserved
0x7000 – 0x70FF
SAR and Analog Control Registers
0x7100 – 0x7FFF
Reserved
0x8000 – 0xFFFF
USB
Table 6-6. Peripheral I/O-Space Control Registers for C5534 and C5533
122
WORD ADDRESS
PERIPHERAL
0x0000 – 0x0004
Idle Control
0x0005 – 0x000D through 0x0803 – 0x0BFF
Reserved
0x0C00 – 0x0C7F
DMA0
0x0C80 – 0x0CFF
Reserved
0x0D00 – 0x0D7F
DMA1
0x0D80 – 0x0DFF
Reserved
0x0E00 – 0x0E7F
DMA2
0x0E80 – 0x0EFF
Reserved
0x0F00 – 0x0F7F
DMA3
0x0F80 – 0x0FFF
Reserved
0x1000 – 0x10DD
Reserved
0x10EE – 0x10FF through 0x1300 – 0x17FF
Reserved
Detailed Description
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Table 6-6. Peripheral I/O-Space Control Registers for C5534 and C5533
(continued)
WORD ADDRESS
PERIPHERAL
0x1800 – 0x181F
Timer0
0x1820 – 0x183F
Reserved
0x1840 – 0x185F
Timer1
0x1860 – 0x187F
Reserved
0x1880 – 0x189F
Timer2
0x1900 – 0x197F
RTC
0x1980 – 0x19FF
Reserved
0x1A00 – 0x1A6C
I2C
0x1A6D – 0x1AFF
Reserved
0x1B00 – 0x1B1F
UART
0x1B80 – 0x1BFF
Reserved
0x1C00 – 0x1CFF
System Control
0x1D00 – 0x1FFF through 0x2600 – 0x27FF
Reserved
0x2800 – 0x2840
I2S0
0x2900 – 0x2940
I2S1
0x2A00 – 0x2A40
I2S2
0x2B00 – 0x2B40
I2S3
0x2C41 – 0x2FFF
Reserved
0x3000 – 0x300F
SPI
0x3010 – 0x39FF
Reserved
0x3A00 – 0x3A7F
SD0
0x3A80 – 0x3AFF
Reserved
0x3B00 – 0x3B7F
SD1
0x3B80 – 0x7FFF
Reserved
0x8000 – 0xFFFF
USB
Table 6-7. Peripheral I/O-Space Control Registers for C5532
WORD ADDRESS
PERIPHERAL
0x0000 – 0x0004
Idle Control
0x0005 – 0x000D through 0x0803 – 0x0BFF
Reserved
0x0C00 – 0x0C7F
DMA0
0x0C80 – 0x0CFF
Reserved
0x0D00 – 0x0D7F
DMA1
0x0D80 – 0x0DFF
Reserved
0x0E00 – 0x0E7F
DMA2
0x0E80 – 0x0EFF
Reserved
0x0F00 – 0x0F7F
DMA3
0x0F80 – 0x0FFF
Reserved
0x1000 – 0x10DD
Reserved
0x10EE – 0x10FF through 0x1300 – 0x17FF
Reserved
0x1800 – 0x181F
Timer0
0x1820 – 0x183F
Reserved
0x1840 – 0x185F
Timer1
0x1860 – 0x187F
Reserved
0x1880 – 0x189F
Timer2
Detailed Description
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Table 6-7. Peripheral I/O-Space Control Registers for C5532 (continued)
124
WORD ADDRESS
PERIPHERAL
0x1900 – 0x197F
RTC
0x1980 – 0x19FF
Reserved
0x1A00 – 0x1A6C
I2C
0x1A6D – 0x1AFF
Reserved
0x1B00 – 0x1B1F
UART
0x1B80 – 0x1BFF
Reserved
0x1C00 – 0x1CFF
System Control
0x1D00 – 0x1FFF through 0x2600 – 0x27FF
Reserved
0x2800 – 0x2840
I2S0
0x2900 – 0x2940
I2S1
0x2A00 – 0x2A40
I2S2
0x2B00 – 0x2B40
I2S3
0x2C41 – 0x2DFF through 0x2E41 - 0x2FFF
Reserved
0x3000 – 0x300F
SPI
0x3010 – 0x39FF
Reserved
Detailed Description
0x3A00 – 0x3A7F
SD0
0x3A80 – 0x3AFF
Reserved
0x3B00 – 0x3B7F
SD1
0x3B80 – 0xFFFF
Reserved
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6.2.2
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Memory Map
The on-chip, dual-access RAM allows two accesses to a given block during the same cycle. There are 8
blocks of 8K bytes of dual-access RAM. The on-chip, single-access RAM allows one access to a given
block per cycle. In addition, there are 32 blocks of 8K bytes of single-access RAM.
The DSP memory is accessible by different master modules within the DSP, including the C55x CPU and
the four DMA controllers, LCD, and USB's CDMA (see Figure 6-1).
CPU BYTE
DMA/USB/LCD
ADDRESS(A)
BYTE ADDRESS(A)
000000h
0001 0000h
0000C0h
0001 00C0h
MEMORY BLOCKS
MMR (Reserved)
DARAM
010000h
(B)
(C)
64K Minus 192 Bytes
0009 0000h
SARAM
050000h
BLOCK SIZE
256K Bytes
0100 0000h
Reserved
FE0000h
050E 0000h
ROM
(if MPNMC=0)
FFFFFFh
A.
Reserved
(if MPNMC=1)
Unmapped (if MPNMC=1)
128K Bytes ROM (if MPNMC=0)
050F FFFFh
The USB and LCD controllers do not have access to DARAM.
Figure 6-1. C5535 Memory Map Summary
Detailed Description
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CPU BYTE
DMA/USB
ADDRESS(A)
BYTE ADDRESS(A)
000000h
0001 0000h
0000C0h
0001 00C0h
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MEMORY BLOCKS
MMR (Reserved)
DARAM
010000h
(B)
(C)
64K Minus 192 Bytes
0009 0000h
SARAM
040000h
BLOCK SIZE
192K Bytes
000C 0000h
Reserved
FE0000h
050E 0000h
ROM
(if MPNMC=0)
FFFFFFh
A.
B.
C.
Reserved
(if MPNMC=1)
Unmapped (if MPNMC=1)
128K Bytes ROM (if MPNMC=0)
050F FFFFh
Address shown represents the first byte address in each block.
The first 192 bytes are reserved for memory-mapped registers (MMRs).
The USB controller does not have access to DARAM.
Figure 6-2. C5534 Memory Map Summary
126
Detailed Description
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CPU BYTE
DMA/USB
ADDRESS(A)
BYTE ADDRESS(A)
000000h
0001 0000h
0000C0h
0001 00C0h
MEMORY BLOCKS
MMR (Reserved)
DARAM
010000h
(B)
(C)
64K Minus 192 Bytes
0009 0000h
SARAM
020000h
BLOCK SIZE
64K Bytes
000A 0000h
Reserved
FE0000h
050E 0000h
ROM
(if MPNMC=0)
FFFFFFh
A.
B.
C.
Reserved
(if MPNMC=1)
Unmapped (if MPNMC=1)
128K Bytes ROM (if MPNMC=0)
050F FFFFh
Address shown represents the first byte address in each block.
The first 192 bytes are reserved for memory-mapped registers (MMRs).
The USB controller does not have access to DARAM.
Figure 6-3. C5533 Memory Map Summary
Detailed Description
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CPU BYTE
DMA
ADDRESS(A)
BYTE ADDRESS(A)
000000h
0001 0000h
0000C0h
0001 00C0h
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MEMORY BLOCKS
MMR (Reserved)
(B)
DARAM
010000h
BLOCK SIZE
64K Minus 192 Bytes
0009 0000h
Reserved
FE0000h
050E 0000h
ROM
(if MPNMC=0)
FFFFFFh
A.
B.
Reserved
(if MPNMC=1)
Unmapped (if MPNMC=1)
128K Bytes ROM (if MPNMC=0)
050F FFFFh
Address shown represents the first byte address in each block.
The first 192 bytes are reserved for memory-mapped registers (MMRs).
Figure 6-4. C5532 Memory Map Summary
128
Detailed Description
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6.2.3
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Register Map
6.2.3.1
General-Purpose Input/Output Peripheral Register Descriptions
The external parallel port interface includes a 16-bit general purpose I/O that can be individually
programmed as input or output with interrupt capability. Control of the general purpose I/O is maintained
through a set of I/O memory-mapped registers shown in Table 6-8.
Table 6-8. GPIO Registers
HEX ADDRESS
RANGE
ACRONYM
1C06h
IODIR1
GPIO Direction Register 1
1C07h
IODIR2
GPIO Direction Register 2
1C08h
IOINDATA1
GPIO Data In Register 1
GPIO Data In Register 2
REGISTER NAME
1C09h
IOINDATA2
1C0Ah
IODATAOUT1
GPIO Data Out Register 1
1C0Bh
IODATAOUT2
GPIO Data Out Register 2
1C0Ch
IOINTEDG1
GPIO Interrupt Edge Trigger Enable Register 1
1C0Dh
IOINTEDG2
GPIO Interrupt Edge Trigger Enable Register 2
1C0Eh
IOINTEN1
GPIO Interrupt Enable Register 1
1C0Fh
IOINTEN2
GPIO Interrupt Enable Register 2
1C10h
IOINTFLG1
GPIO Interrupt Flag Register 1
1C11h
IOINTFLG2
GPIO Interrupt Flag Register 2
Detailed Description
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I2C Peripheral Register Descriptions
Table 6-9 shows the Inter-Integrated Circuit (I2C) registers.
Table 6-9. Inter-Integrated Circuit (I2C) Registers
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
1A00h
ICOAR
I2C Own Address Register
1A04h
ICIMR
I2C Interrupt Mask Register
1A08h
ICSTR
I2C Interrupt Status Register
1A0Ch
ICCLKL
I2C Clock Low-Time Divider Register
1A10h
ICCLKH
I2C Clock High-Time Divider Register
1A14h
ICCNT
I2C Data Count Register
1A18h
ICDRR
I2C Data Receive Register
1A1Ch
ICSAR
I2C Slave Address Register
1A20h
ICDXR
I2C Data Transmit Register
1A24h
ICMDR
I2C Mode Register
1A28h
ICIVR
I2C Interrupt Vector Register
1A2Ch
ICEMDR
I2C Extended Mode Register
1A30h
ICPSC
I2C Prescaler Register
1A34h
ICPID1
I2C Peripheral Identification Register 1
1A38h
ICPID2
I2C Peripheral Identification Register 2
6.2.3.3
I2S Peripheral Register Descriptions
Table 6-10 through Table 6-13 show the I2S0 through I2S3 registers.
Table 6-10. I2S0 Registers
HEX ADDRESS
RANGE
130
ACRONYM
REGISTER NAME
2800h
I2S0SCTRL
I2S0 Serializer Control Register
2804h
I2S0SRATE
I2S0 Sample Rate Generator Register
2808h
I2S0TXLT0
I2S0 Transmit Left Data 0 Register
2809h
I2S0TXLT1
I2S0 Transmit Left Data 1 Register
280Ch
I2S0TXRT0
I2S0 Transmit Right Data 0 Register
280Dh
I2S0TXRT1
I2S0 Transmit Right Data 1 Register
2810h
I2S0INTFL
I2S0 Interrupt Flag Register
2814h
I2S0INTMASK
I2S0 Interrupt Mask Register
2828h
I2S0RXLT0
I2S0 Receive Left Data 0 Register
2829h
I2S0RXLT1
I2S0 Receive Left Data 1 Register
282Ch
I2S0RXRT0
I2S0 Receive Right Data 0 Register
282Dh
I2S0RXRT1
I2S0 Receive Right Data 1 Register
Detailed Description
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Table 6-11. I2S1 Registers
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
2900h
I2S1SCTRL
I2S1 Serializer Control Register
2904h
I2S1SRATE
I2S1 Sample Rate Generator Register
2908h
I2S1TXLT0
I2S1 Transmit Left Data 0 Register
2909h
I2S1TXLT1
I2S1 Transmit Left Data 1 Register
290Ch
I2S1TXRT0
I2S1 Transmit Right Data 0 Register
290Dh
I2S1TXRT1
I2S1 Transmit Right Data 1 Register
2910h
I2S1INTFL
I2S1 Interrupt Flag Register
2914h
I2S1INTMASK
I2S1 Interrupt Mask Register
2928h
I2S1RXLT0
I2S1 Receive Left Data 0 Register
2929h
I2S1RXLT1
I2S1 Receive Left Data 1 Register
292Ch
I2S1RXRT0
I2S1 Receive Right Data 0 Register
292Dh
I2S1RXRT1
I2S1 Receive Right Data 1 Register
Table 6-12. I2S2 Registers
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
2A00h
I2S2SCTRL
I2S2 Serializer Control Register
2A04h
I2S2SRATE
I2S2 Sample Rate Generator Register
2A08h
I2S2TXLT0
I2S2 Transmit Left Data 0 Register
2A09h
I2S2TXLT1
I2S2 Transmit Left Data 1 Register
2A0Ch
I2S2TXRT0
I2S2 Transmit Right Data 0 Register
2A0Dh
I2S2TXRT1
I2S2 Transmit Right Data 1 Register
2A10h
I2S2INTFL
I2S2 Interrupt Flag Register
2A14h
I2S2INTMASK
I2S2 Interrupt Mask Register
2A28h
I2S2RXLT0
I2S2 Receive Left Data 0 Register
2A29h
I2S2RXLT1
I2S2 Receive Left Data 1 Register
2A2Ch
I2S2RXRT0
I2S2 Receive Right Data 0 Register
2A2Dh
I2S2RXRT1
I2S2 Receive Right Data 1 Register
Table 6-13. I2S3 Registers
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
2B00h
I2S3SCTRL
I2S3 Serializer Control Register
2B04h
I2S3SRATE
I2S3 Sample Rate Generator Register
2B08h
I2S3TXLT0
I2S3 Transmit Left Data 0 Register
2B09h
I2S3TXLT1
I2S3 Transmit Left Data 1 Register
2B0Ch
I2S3TXRT0
I2S3 Transmit Right Data 0 Register
2B0Dh
I2S3TXRT1
I2S3 Transmit Right Data 1 Register
2B10h
I2S3INTFL
I2S3 Interrupt Flag Register
2B14h
I2S3INTMASK
I2S3 Interrupt Mask Register
2B28h
I2S3RXLT0
I2S3 Receive Left Data 0 Register
2B29h
I2S3RXLT1
I2S3 Receive Left Data 1 Register
2B2Ch
I2S3RXRT0
I2S3 Receive Right Data 0 Register
2B2Dh
I2S3RXRT1
I2S3 Receive Right Data 1 Register
Detailed Description
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LCDC Peripheral Register Descriptions
Table 6-14 shows the LCDC peripheral registers.
Table 6-14. LCD Controller Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
2E00h
LCDREVMIN
LCD Minor Revision Register
2E01h
LCDREVMAJ
LCD Major Revision Register
2E04h
LCDCR
LCD Control Register
2E08h
LCDSR
LCD Status Register
2E0Ch
LCDLIDDCR
2E10h
LCDLIDDCS0CONFIG0
LCD LIDD CS0 Configuration Register 0
2E11h
LCDLIDDCS0CONFIG1
LCD LIDD CS0 Configuration Register 1
2E14h
LCDLIDDCS0ADDR
LCD LIDD CS0 Address Read and Write Register
2E18h
LCDLIDDCS0DATA
LCD LIDD CS0 Data Read and Write Register
2E1Ch
LCDLIDDCS1CONFIG0
LCD LIDD CS1 Configuration Register 0
2E1Dh
LCDLIDDCS1CONFIG1
LCD LIDD CS1 Configuration Register 1
2E20h
LCDLIDDCS1ADDR
LCD LIDD CS1 Address Read and Write Register
LCD LIDD CS1 Data Read and Write Register
LCD LIDD Control Register
2E24h
LCDLIDDCS1DATA
2E28h – 2E3Ah
—
2E40h
LCDDMACR
2E44h
LCDDMAFB0BAR0
LCD DMA Frame Buffer 0 Base Address Register 0
2E45h
LCDDMAFB0BAR1
LCD DMA Frame Buffer 0 Base Address Register 1
2E48h
LCDDMAFB0CAR0
LCD DMA Frame Buffer 0 Ceiling Address Register 0
2E49h
LCDDMAFB0CAR1
LCD DMA Frame Buffer 0 Ceiling Address Register 1
2E4Ch
LCDDMAFB1BAR0
LCD DMA Frame Buffer 1 Base Address Register 0
2E4Dh
LCDDMAFB1BAR1
LCD DMA Frame Buffer 1 Base Address Register 1
2E50h
LCDDMAFB1CAR0
LCD DMA Frame Buffer 1 Ceiling Address Register 0
2E51h
LCDDMAFB1CAR1
LCD DMA Frame Buffer 1 Ceiling Address Register 1
132
Detailed Description
Reserved
LCD DMA Control Register
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6.2.3.5
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
RTC Peripheral Register Descriptions
Table 6-15 shows the RTC registers.
Table 6-15. Real-Time Clock (RTC) Registers
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
1900h
RTCINTEN
1901h
RTCUPDATE
RTC Interrupt Enable Register
RTC Update Register
1904h
RTCMIL
Milliseconds Register
1905h
RTCMILA
Milliseconds Alarm Register
1908h
RTCSEC
Seconds Register
1909h
RTCSECA
190Ch
RTCMIN
Seconds Alarm Register
190Dh
RTCMINA
Minutes Alarm Register
1910h
RTCHOUR
Hours Register
1911h
RTCHOURA
1914h
RTCDAY
1915h
RTCDAYA
Minutes Register
Hours Alarm Register
Days Register
Days Alarm Register
1918h
RTCMONTH
1919h
RTCMONTHA
Months Register
191Ch
RTCYEAR
191Dh
RTCYEARA
1920h
RTCINTFL
1921h
RTCNOPWR
RTC Lost Power Status Register
1924h
RTCINTREG
RTC Interrupt Register
Months Alarm Register
Years Register
Years Alarm Register
RTC Interrupt Flag Register
1928h
RTCDRIFT
192Ch
RTCOSC
1930h
RTCPMGT
RTC Power Management Register
1960h
RTCSCR1
RTC LSW Scratch Register 1
1961h
RTCSCR2
RTC MSW Scratch Register 2
1964h
RTCSCR3
RTC LSW Scratch Register 3
1965h
RTCSCR4
RTC MSW Scratch Register 4
6.2.3.6
RTC Compensation Register
RTC Oscillator Register
SAR ADC Peripheral Register Descriptions
Table 6-16 shows the SAR ADC peripheral registers.
Note: SAR ADC applies only to C5535.
Table 6-16. SAR Analog Control Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
7012h
SARCTRL
SAR A/D Control Register
7014h
SARDATA
SAR A/D Data Register
7016h
SARCLKCTRL
SAR A/D Clock Control Register
7018h
SARPINCTRL
SAR A/D Reference and Pin Control Register
701Ah
SARGPOCTRL
SAR A/D GPO Control Register
Detailed Description
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SD Peripheral Register Descriptions
Table 6-17 and Table 6-18 shows the SD registers. The SD0 registers start at address 3A00h and the
SD1 registers start at address 3B00h.
Table 6-17. SD0 Registers
HEX ADDRESS
RANGE
ACRONYM
3A00h
SDCTL
SD Control Register
3A04h
SDCLK
SD Memory Clock Control Register
3A08h
SDST0
SD Status Register 0
3A0Ch
SDST1
SD Status Register 1
3A10h
SDIM
3A14h
SDTOR
SD Response Time-Out Register
3A18h
SDTOD
SD Data Read Time-Out Register
3A1Ch
SDBLEN
SD Block Length Register
3A20h
SDNBLK
SD Number of Blocks Register
3A24h
SDNBLC
SD Number of Blocks Counter Register
3A28h
SDDRR1
SD Data Receive 1 Register
3A29h
SDDRR2
SD Data Receive 2 Register
3A2Ch
SDDXR1
SD Data Transmit 1 Register
3A2Dh
SDDXR2
SD Data Transmit 2 Register
3A30h
SDCMD
SD Command Register
3A34h
SDARGHL
SD Argument Register
3A38h
SDRSP0
SD Response Register 0
3A39h
SDRSP1
SD Response Register 1
3A3Ch
SDRSP2
SD Response Register 2
3A3Dh
SDRSP3
SD Response Register 3
3A40h
SDRSP4
SD Response Register 4
3A41h
SDRSP5
SD Response Register 5
3A44h
SDRSP6
SD Response Register 6
3A45h
SDRSP7
SD Response Register 7
3A48h
SDDRSP
SD Data Response Register
SD Command Index Register
3A50h
SDCIDX
3A64h – 3A70h
–
3A74h
SDFIFOCTL
134
REGISTER NAME
Detailed Description
SD Interrupt Mask Register
Reserved
SD FIFO Control Register
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Table 6-18. SD1 Registers
HEX ADDRESS
RANGE
ACRONYM
REGISTER NAME
3B00h
SDCTL
SD Control Register
3B04h
SDCLK
SD Memory Clock Control Register
3B08h
SDST0
SD Status Register 0
3B0Ch
SDST1
SD Status Register 1
3B10h
SDIM
3B14h
SDTOR
SD Response Time-Out Register
3B18h
SDTOD
SD Data Read Time-Out Register
3B1Ch
SDBLEN
SD Block Length Register
3B20h
SDNBLK
SD Number of Blocks Register
3B24h
SDNBLC
SD Number of Blocks Counter Register
3B28h
SDDRR1
SD Data Receive 1 Register
3B29h
SDDRR2
SD Data Receive 2 Register
3B2Ch
SDDXR1
SD Data Transmit 1 Register
3B2Dh
SDDXR2
SD Data Transmit 2 Register
3B30h
SDCMD
SD Command Register
3B34h
SDARGHL
SD Argument Register
3B38h
SDRSP0
SD Response Register 0
3B39h
SDRSP1
SD Response Register 1
3B3Ch
SDRSP2
SD Response Register 2
3B3Dh
SDRSP3
SD Response Register 3
3B40h
SDRSP4
SD Response Register 4
3B41h
SDRSP5
SD Response Register 5
3B44h
SDRSP6
SD Response Register 6
3B45h
SDRSP7
SD Response Register 7
3B48h
SDDRSP
SD Data Response Register
3B50h
SDCIDX
SD Command Index Register
3B74h
SDFIFOCTL
6.2.3.8
SD Interrupt Mask Register
SD FIFO Control Register
SPI Peripheral Register Descriptions
Table 6-19 shows the SPI registers.
Table 6-19. SPI Module Registers
CPU WORD
ADDRESS
ACRONYM
3000h
SPICDR
Clock Divider Register
3001h
SPICCR
Clock Control Register
3002h
SPIDCR1
Device Configuration Register 1
3003h
SPIDCR2
Device Configuration Register 2
3004h
SPICMD1
Command Register 1
3005h
SPICMD2
Command Register 2
3006h
SPISTAT1
Status Register 1
3007h
SPISTAT2
Status Register 2
3008h
SPIDAT1
Data Register 1
3009h
SPIDAT2
Data Register 2
REGISTER NAME
Detailed Description
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System Registers
The system registers are used to configure the device and monitor its status. Brief descriptions of the
various system registers are shown in Table 6-20.
Table 6-20. Idle Control, Status, and System Registers
CPU WORD
ADDRESS
136
ACRONYM
0001h
ICR
Idle Control Register
0002h
ISTR
Idle Status Register
1C00h
EBSR
1C02h
PCGCR1
Peripheral Clock Gating Control Register 1
1C03h
PCGCR2
Peripheral Clock Gating Control Register 2
1C04h
PSRCR
Peripheral Software Reset Counter Register
1C05h
PRCR
Peripheral Reset Control Register
1C14h
TIAFR
Timer Interrupt Aggregation Flag Register
See Section 5.7.3.5.1 of this
document.
External Bus Selection Register
1C16h
ODSCR
1C17h
PDINHIBR1
Pulldown Inhibit Register 1
1C18h
PDINHIBR2
Pulldown Inhibit Register 2
Output Drive Strength Control Register
Pulldown Inhibit Register 3
1C19h
PDINHIBR3
1C1Ah
DMA0CESR1
DMA0 Channel Event Source Register 1
1C1Bh
DMA0CESR2
DMA0 Channel Event Source Register 2
1C1Ch
DMA1CESR1
DMA1 Channel Event Source Register 1
1C1Dh
DMA1CESR2
DMA1 Channel Event Source Register 2
1C28h
RAMSLPMDCNTLR1
RAM Sleep Mode Control Register 1
1C2Ah
RAMSLPMDCNTLR2
RAM Sleep Mode Control Register 2
1C2Bh
RAMSLPMDCNTLR3
RAM Sleep Mode Control Register 3
1C2Ch
RAMSLPMDCNTLR4
RAM Sleep Mode Control Register 4
1C2Dh
RAMSLPMDCNTLR5
RAM Sleep Mode Control Register 5
1C30h
DMAIFR
DMA Interrupt Flag Aggregation Register
1C31h
DMAIER
DMA Interrupt Enable Register
1C32h
USBSCR
1C36h
DMA2CESR1
DMA2 Channel Event Source Register 1
1C37h
DMA2CESR2
DMA2 Channel Event Source Register 2
1C38h
DMA3CESR1
DMA3 Channel Event Source Register 1
DMA3 Channel Event Source Register 2
Does not apply to
TMS320C5532.
USB System Control Register
1C39h
DMA3CESR2
1C3Ah
CLKSTOP
1C40h
DIEIDR0
Die ID Register 0
1C41h
DIEIDR1
Die ID Register 1
1C42h
DIEIDR2
Die ID Register 2
1C43h
DIEIDR3
Die ID Register 3
1C44h
DIEIDR4
Die ID Register 4
1C45h
DIEIDR5
Die ID Register 5
1C46h
DIEIDR6
Die ID Register 6
1C47h
DIEIDR7
Die ID Register 7
7004h
LDOCNTL
Detailed Description
COMMENTS
Register Description
Peripheral Clock Stop Request and Acknowledge Register
LDO Control Register
see Section 5.7.2.1.1.3 of
this document.
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6.2.3.10 Timers Peripheral Register Descriptions
Table 6-21 through Table 6-24 show the timer and watchdog registers.
Table 6-21. Watchdog Timer Registers (Timer2 only)
CPU WORD
ADDRESS
ACRONYM
1880h
WDKCKLK
1882h
WDKICK
Watchdog Kick Register
1884h
WDSVLR
Watchdog Start Value Lock Register
1886h
WDSVR
Watchdog Start Value Register
1888h
WDENLOK
Watchdog Enable Lock Register
188Ah
WDEN
188Ch
WDPSLR
188Eh
WDPS
REGISTER DESCRIPTION
Watchdog Kick Lock Register
Watchdog Enable Register
Watchdog Prescale Lock Register
Watchdog Prescale Register
Table 6-22. General-Purpose Timer 0 Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
1810h
TCR
Timer 0 Control Register
1812h
TIMPRD1
Timer 0 Period Register 1
1813h
TIMPRD2
Timer 0 Period Register 2
1814h
TIMCNT1
Timer 0 Counter Register 1
1815h
TIMCNT2
Timer 0 Counter Register 2
Table 6-23. General-Purpose Timer 1 Registers
CPU WORD
ADDRESS
ACRONYM
1850h
TCR
Timer 1 Control Register
1852h
TIMPRD1
Timer 1 Period Register 1
1853h
TIMPRD2
Timer 1 Period Register 2
1854h
TIMCNT1
Timer 1 Counter Register 1
1855h
TIMCNT2
Timer 1 Counter Register 2
REGISTER DESCRIPTION
Table 6-24. General-Purpose Timer 2 Registers
CPU WORD
ADDRESS
ACRONYM
REGISTER DESCRIPTION
1890h
TCR
Timer 2 Control Register
1892h
TIMPRD1
Timer 2 Period Register 1
1893h
TIMPRD2
Timer 2 Period Register 2
1894h
TIMCNT1
Timer 2 Counter Register 1
1895h
TIMCNT2
Timer 2 Counter Register 2
Detailed Description
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6.2.3.11 UART Peripheral Register Descriptions
Table 6-25 shows the UART registers.
Table 6-25. UART Registers
HEX ADDRESS
RANGE
ACRONYM
1B00h
RBR
Receiver Buffer Register (read only)
1B00h
THR
Transmitter Holding Register (write only)
1B02h
IER
Interrupt Enable Register
1B04h
IIR
Interrupt Identification Register (read only)
1B04h
FCR
FIFO Control Register (write only)
1B06h
LCR
Line Control Register
1B08h
MCR
Modem Control Register
1B0Ah
LSR
Line Status Register
1B0Ch
MSR
Modem Status Register
1B0Eh
SCR
Scratch Register
1B10h
DLL
Divisor LSB Latch
1B12h
DLH
Divisor MSB Latch
1B18h
PWREMU_MGMT
138
Detailed Description
REGISTER NAME
Power and Emulation Management Register
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6.2.3.12 USB2.0 Peripheral Register Descriptions
Table 6-26 lists of the USB2.0 peripheral registers.
Note: USB does not apply to C5532.
Table 6-26. Universal Serial Bus (USB) Registers (1)
(1)
CPU WORD
ADDRESS
ACRONYM
8000h
REVID1
Revision Identification Register 1
8001h
REVID2
Revision Identification Register 2
8004h
CTRLR
Control Register
8008h
STATR
Status Register
800Ch
EMUR
Emulation Register
8010h
MODER1
Mode Register 1
8011h
MODER2
Mode Register 2
REGISTER DESCRIPTION
8014h
AUTOREQ
8018h
SRPFIXTIME1
Auto Request Register
SRP Fix Time Register 1
8019h
SRPFIXTIME2
SRP Fix Time Register 2
801Ch
TEARDOWN1
Teardown Register 1
801Dh
TEARDOWN2
Teardown Register 2
8020h
INTSRCR1
USB Interrupt Source Register 1
8021h
INTSRCR2
USB Interrupt Source Register 2
8024h
INTSETR1
USB Interrupt Source Set Register 1
8025h
INTSETR2
USB Interrupt Source Set Register 2
8028h
INTCLRR1
USB Interrupt Source Clear Register 1
8029h
INTCLRR2
USB Interrupt Source Clear Register 2
802Ch
INTMSKR1
USB Interrupt Mask Register 1
802Dh
INTMSKR2
USB Interrupt Mask Register 2
8030h
INTMSKSETR1
USB Interrupt Mask Set Register 1
8031h
INTMSKSETR2
USB Interrupt Mask Set Register 2
8034h
INTMSKCLRR1
USB Interrupt Mask Clear Register 1
8035h
INTMSKCLRR2
USB Interrupt Mask Clear Register 2
8038h
INTMASKEDR1
USB Interrupt Source Masked Register 1
8039h
INTMASKEDR2
USB Interrupt Source Masked Register 2
803Ch
EOIR
8040h
INTVECTR1
USB Interrupt Vector Register 1
8041h
INTVECTR2
USB Interrupt Vector Register 2
8050h
GREP1SZR1
Generic RNDIS EP1Size Register 1
8051h
GREP1SZR2
Generic RNDIS EP1Size Register 2
8054h
GREP2SZR1
Generic RNDIS EP2 Size Register 1
8055h
GREP2SZR2
Generic RNDIS EP2 Size Register 2
8058h
GREP3SZR1
Generic RNDIS EP3 Size Register 1
USB End of Interrupt Register
8059h
GREP3SZR2
Generic RNDIS EP3 Size Register 2
805Ch
GREP4SZR1
Generic RNDIS EP4 Size Register 1
805Dh
GREP4SZR2
Generic RNDIS EP4 Size Register 2
Before reading or writing to the USB registers, be sure to set the BYTEMODE bits to "00b" in the USB system control register to enable
word accesses to the USB registers.
Detailed Description
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Table 6-26. Universal Serial Bus (USB) Registers(1) (continued)
CPU WORD
ADDRESS
ACRONYM
8401h
FADDR_POWER
8402h
INTRTX
Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
8405h
INTRRX
Interrupt Register for Receive Endpoints 1 to 4
8406h
INTRTXE
Interrupt enable register for INTRTX
8409h
INTRRXE
Interrupt Enable Register for INTRRX
840Ah
INTRUSB_INTRUSBE
840Dh
FRAME
REGISTER DESCRIPTION
Common USB Registers
840Eh
INDEX_TESTMODE
Function Address Register, Power Management Register
Interrupt Register for Common USB Interrupts, Interrupt Enable Register
Frame Number Register
Index Register for Selecting the Endpoint Status and Control Registers, Register to
Enable the USB 2.0 Test Modes
USB Indexed Registers
8411h
8412h
TXMAXP_INDX
PERI_CSR0_INDX
Control Status Register for Endpoint 0 in Peripheral Mode. (Index register set to
select Endpoint 0)
PERI_TXCSR_INDX
Control Status Register for Peripheral Transmit Endpoint. (Index register set to select
Endpoints 1-4)
RXMAXP_INDX
Maximum Packet Size for Peripheral and Host Receive Endpoint. (Index register set
to select Endpoints 1-4)
PERI_RXCSR_INDX
Control Status Register for Peripheral Receive Endpoint. (Index register set to select
Endpoints 1-4)
COUNT0_INDX
Number of Received Bytes in Endpoint 0 FIFO. (Index register set to select Endpoint
0)
8415h
8416h
Maximum Packet Size for Peripheral and Host Transmit Endpoint. (Index register set
to select Endpoints 1-4)
8419h
RXCOUNT_INDX
Number of Bytes in Host Receive Endpoint FIFO. (Index register set to select
Endpoints 1- 4)
841Ah
-
Reserved
841Dh
-
Reserved
841Eh
CONFIGDATA_INDC
(Upper byte of 841Eh)
8421h
FIFO0R1
Transmit and Receive FIFO Register 1 for Endpoint 0
8422h
FIFO0R2
Transmit and Receive FIFO Register 2 for Endpoint 0
8425h
FIFO1R1
Transmit and Receive FIFO Register 1 for Endpoint 1
8426h
FIFO1R2
Transmit and Receive FIFO Register 2 for Endpoint 1
8429h
FIFO2R1
Transmit and Receive FIFO Register 1 for Endpoint 2
Returns details of core configuration. (index register set to select Endpoint 0)
USB FIFO Registers
842Ah
FIFO2R2
Transmit and Receive FIFO Register 2 for Endpoint 2
842Dh
FIFO3R1
Transmit and Receive FIFO Register 1 for Endpoint 3
842Eh
FIFO3R2
Transmit and Receive FIFO Register 2 for Endpoint 3
8431h
FIFO4R1
Transmit and Receive FIFO Register 1 for Endpoint 4
8432h
FIFO4R2
Transmit and Receive FIFO Register 2 for Endpoint 4
Dynamic FIFO Control Registers
8461h
8462h
140
DEVCTL
TXFIFOSZ_RXFIFOSZ
Device Control Register
Transmit Endpoint FIFO Size, Receive Endpoint FIFO Size (Index register set to
select Endpoints 1-4)
8465h
TXFIFOADDR
Transmit Endpoint FIFO Address (Index register set to select Endpoints 1-4)
8466h
RXFIFOADDR
Receive Endpoint FIFO Address (Index register set to select Endpoints 1-4)
846Dh
-
Detailed Description
Reserved
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Table 6-26. Universal Serial Bus (USB) Registers(1) (continued)
CPU WORD
ADDRESS
ACRONYM
8501h
-
8502h
PERI_CSR0
8505h
-
Reserved
8506h
-
Reserved
8509h
COUNT0
850Ah
-
Reserved
850Dh
-
Reserved
850Eh
CONFIGDATA
(Upper byte of 850Eh)
8511h
TXMAXP
8512h
PERI_TXCSR
REGISTER DESCRIPTION
Control and Status Register for Endpoint 0
Reserved
Control Status Register for Peripheral Endpoint 0
Number of Received Bytes in Endpoint 0 FIFO
Returns details of core configuration.
Control and Status Register for Endpoint 1
Maximum Packet Size for Peripheral and Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
8515h
RXMAXP
8516h
PERI_RXCSR
Maximum Packet Size for Peripheral and Host Receive Endpoint
8519h
RXCOUNT
851Ah
-
Reserved
851Dh
-
Reserved
851Eh
-
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Number of Bytes in the Receiving Endpoint's FIFO
Reserved
Control and Status Register for Endpoint 2
8521h
TXMAXP
8522h
PERI_TXCSR
Maximum Packet Size for Peripheral and Host Transmit Endpoint
8525h
RXMAXP
8526h
PERI_RXCSR
8529h
RXCOUNT
852Ah
-
Reserved
852Dh
-
Reserved
852Eh
-
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Maximum Packet Size for Peripheral and Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Number of Bytes in Host Receive endpoint FIFO
Reserved
Control and Status Register for Endpoint 3
8531h
TXMAXP
8532h
PERI_TXCSR
8535h
RXMAXP
8536h
PERI_RXCSR
Maximum Packet Size for Peripheral and Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Maximum Packet Size for Peripheral and Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
8539h
RXCOUNT
853Ah
-
Number of Bytes in Host Receive endpoint FIFO
Reserved
853Dh
-
Reserved
853Eh
-
Reserved
8541h
TXMAXP
8542h
PERI_TXCSR
Control and Status Register for Endpoint 4
8545h
RXMAXP
8546h
PERI_RXCSR
8549h
RXCOUNT
Maximum Packet Size for Peripheral and Host Transmit Endpoint
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)
Maximum Packet Size for Peripheral and Host Receive Endpoint
Control Status Register for Peripheral Receive Endpoint (peripheral mode)
Number of Bytes in Host Receive endpoint FIFO
854Ah
-
Reserved
854Dh
-
Reserved
854Eh
-
Reserved
Detailed Description
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Table 6-26. Universal Serial Bus (USB) Registers(1) (continued)
CPU WORD
ADDRESS
ACRONYM
9000h
-
Reserved
9001h
-
Reserved
REGISTER DESCRIPTION
CPPI DMA (CMDA) Registers
9004h
TDFDQ
9008h
DMAEMU
9800h
TXGCR1[0]
Transmit Channel 0 Global Configuration Register 1
9801h
TXGCR2[0]
Transmit Channel 0 Global Configuration Register 2
9808h
RXGCR1[0]
Receive Channel 0 Global Configuration Register 1
9809h
RXGCR2[0]
Receive Channel 0 Global Configuration Register 2
980Ch
RXHPCR1A[0]
Receive Channel 0 Host Packet Configuration Register 1 A
980Dh
RXHPCR2A[0]
Receive Channel 0 Host Packet Configuration Register 2 A
9810h
RXHPCR1B[0]
Receive Channel 0 Host Packet Configuration Register 1 B
9811h
RXHPCR2B[0]
Receive Channel 0 Host Packet Configuration Register 2 B
9820h
TXGCR1[1]
Transmit Channel 1 Global Configuration Register 1
9821h
TXGCR2[1]
Transmit Channel 1 Global Configuration Register 2
9828h
RXGCR1[1]
Receive Channel 1 Global Configuration Register 1
9829h
RXGCR2[1]
Receive Channel 1 Global Configuration Register 2
982Ch
RXHPCR1A[1]
Receive Channel 1 Host Packet Configuration Register 1 A
982Dh
RXHPCR2A[1]
Receive Channel 1 Host Packet Configuration Register 2 A
9830h
RXHPCR1B[1]
Receive Channel 1 Host Packet Configuration Register 1 B
9831h
RXHPCR2B[1]
Receive Channel 1 Host Packet Configuration Register 2 B
9840h
TXGCR1[2]
Transmit Channel 2 Global Configuration Register 1
9841h
TXGCR2[2]
Transmit Channel 2 Global Configuration Register 2
9848h
RXGCR1[2]
Receive Channel 2 Global Configuration Register 1
9849h
RXGCR2[2]
Receive Channel 2 Global Configuration Register 2
984Ch
RXHPCR1A[2]
Receive Channel 2 Host Packet Configuration Register 1 A
984Dh
RXHPCR2A[2]
Receive Channel 2 Host Packet Configuration Register 2 A
9850h
RXHPCR1B[2]
Receive Channel 2 Host Packet Configuration Register 1 B
9851h
RXHPCR2B[2]
Receive Channel 2 Host Packet Configuration Register 2 B
9860h
TXGCR1[3]
Transmit Channel 3 Global Configuration Register 1
9861h
TXGCR2[3]
Transmit Channel 3 Global Configuration Register 2
9868h
RXGCR1[3]
Receive Channel 3 Global Configuration Register 1
9869h
RXGCR2[3]
Receive Channel 3 Global Configuration Register 2
986Ch
RXHPCR1A[3]
Receive Channel 3 Host Packet Configuration Register 1 A
986Dh
RXHPCR2A[3]
Receive Channel 3 Host Packet Configuration Register 2 A
9870h
RXHPCR1B[3]
Receive Channel 3 Host Packet Configuration Register 1 B
9871h
RXHPCR2B[3]
Receive Channel 3 Host Packet Configuration Register 2 B
A000h
DMA_SCHED_CTRL1
CDMA Scheduler Control Register 1
A001h
DMA_SCHED_CTRL2
CDMA Scheduler Control Register 1
A800h + 4 × N
ENTRYLSW[N]
CDMA Scheduler Table Word N Registers LSW (N = 0 to 63)
A801h + 4 × N
ENTRYMSW[N]
CDMA Scheduler Table Word N Registers MSW (N = 0 to 63)
142
Detailed Description
CDMA Teardown Free Descriptor Queue Control Register
CDMA Emulation Control Register
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Table 6-26. Universal Serial Bus (USB) Registers(1) (continued)
CPU WORD
ADDRESS
ACRONYM
C000h
-
Reserved
C001h
-
Reserved
C008h
DIVERSION1
Queue Manager Queue Diversion Register 1
C009h
DIVERSION2
Queue Manager Queue Diversion Register 2
C020h
FDBSC0
Queue Manager Free Descriptor and Buffer Starvation Count Register 0
C021h
FDBSC1
Queue Manager Free Descriptor and Buffer Starvation Count Register 1
C024h
FDBSC2
Queue Manager Free Descriptor and Buffer Starvation Count Register 2
C025h
FDBSC3
Queue Manager Free Descriptor and Buffer Starvation Count Register 3
C028h
FDBSC4
Queue Manager Free Descriptor and Buffer Starvation Count Register 4
REGISTER DESCRIPTION
Queue Manager (QMGR) Registers
C029h
FDBSC5
Queue Manager Free Descriptor and Buffer Starvation Count Register 5
C02Ch
FDBSC6
Queue Manager Free Descriptor and Buffer Starvation Count Register 6
C02Dh
FDBSC7
Queue Manager Free Descriptor and Buffer Starvation Count Register 7
C080h
LRAM0BASE1
Queue Manager Linking RAM Region 0 Base Address Register 1
C081h
LRAM0BASE2
Queue Manager Linking RAM Region 0 Base Address Register 2
C084h
LRAM0SIZE
C085h
-
C088h
LRAM1BASE1
Queue Manager Linking RAM Region 1 Base Address Register 1
C089h
LRAM1BASE2
Queue Manager Linking RAM Region 1 Base Address Register 2
C090h
PEND0
Queue Manager Queue Pending 0
C091h
PEND1
Queue Manager Queue Pending 1
C094h
PEND2
Queue Manager Queue Pending 2
C095h
PEND3
Queue Manager Queue Pending 3
C098h
PEND4
Queue Manager Queue Pending 4
C099h
PEND5
Queue Manager Queue Pending 5
D000h + 16 × R
QMEMRBASE1[R]
Queue Manager Memory Region R Base Address Register 1 (R = 0 to 15)
D001h + 16 × R
QMEMRBASE2[R]
Queue Manager Memory Region R Base Address Register 2 (R = 0 to 15)
D004h + 16 × R
QMEMRCTRL1[R]
Queue Manager Memory Region R Control Register (R = 0 to 15)
D005h + 16 × R
QMEMRCTRL2[R]
Queue Manager Memory Region R Control Register (R = 0 to 15)
E000h + 16 × N
CTRL1A
Queue Manager Queue N Control Register 1A (N = 0 to 63)
E001h + 16 × N
CTRL2A
Queue Manager Queue N Control Register 2A (N = 0 to 63)
E004h + 16 × N
CTRL1B
Queue Manager Queue N Control Register 1B (N = 0 to 63)
E005h + 16 × N
CTRL2B
Queue Manager Queue N Control Register 2B (N = 0 to 63)
E008h + 16 × N
CTRL1C
Queue Manager Queue N Control Register 1C (N = 0 to 63)
E009h + 16 × N
CTRL2C
Queue Manager Queue N Control Register 2C (N = 0 to 63)
E00Ch + 16 × N
CTRL1D
Queue Manager Queue N Control Register 1D (N = 0 to 63)
E00Dh + 16 × N
CTRL2D
Queue Manager Queue N Control Register 2D (N = 0 to 63)
E800h + 16 × N
QSTAT1A
Queue Manager Queue N Status Register 1A (N = 0 to 63)
E801h + 16 × N
QSTAT2A
Queue Manager Queue N Status Register 2A (N = 0 to 63)
E804h + 16 × N
QSTAT1B
Queue Manager Queue N Status Register 1B (N = 0 to 63)
E805h + 16 × N
QSTAT2B
Queue Manager Queue N Status Register 2B (N = 0 to 63)
E808h + 16 × N
QSTAT1C
Queue Manager Queue N Status Register 1C (N = 0 to 63)
E809h + 16 × N
QSTAT1C
Queue Manager Queue N Status Register 2C (N = 0 to 63)
Queue Manager Linking RAM Region 0 Size Register
Reserved
Detailed Description
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6.3
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Identification
6.3.1
JTAG Identification
Table 6-27. JTAG ID Register
HEX ADDRESS RANGE
ACRONYM
N/A
JTAGID
REGISTER NAME
COMMENTS
Read-only. Provides 32-bit
JTAG ID of the device.
JTAG Identification Register
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. The
register hex value for the device is: 0x1B8F E02F. For the actual register bit names and their associated
bit field descriptions, see Figure 6-5 and Table 6-28.
31-28
27-12
11-1
0
VARIANT (4-Bit)
PART NUMBER (16-Bit)
MANUFACTURER (11-Bit)
LSB
R-0001
R-1011 1000 1111 1110
R-0000 0010 111
R-1
LEGEND: R = Read, W = Write, n = value at reset
Figure 6-5. JTAG ID Register Description — 0x1B8F E02F
Table 6-28. JTAG ID Register Selection Bit Descriptions
144
BIT
NAME
31:28
VARIANT
27:12
PART NUMBER
11:1
MANUFACTURER
0
LSB
Detailed Description
DESCRIPTION
Variant (4-Bit) value: 0001.
Part Number (16-Bit) value: 1011 1000 1111 1110.
Manufacturer (11-Bit) value: 0000 0010 111.
LSB. This bit is read as a "1".
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6.4
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Boot Modes
The DSP supports the following boot modes in the following device order: SPI 16-bit EEPROM, SPI 24-bit
Flash, I2C EEPROM, and eMMC boot partition, eMMC, SD, or SDHC card. The boot mode is determined
by checking for a valid boot signature on each supported boot device. The first boot device with a valid
boot signature will be used to load and execute the user code. If none of the supported boot devices have
a valid boot signature, the bootloader goes into an endless loop checking the UART or USB boot mode
and the device must be reset to search for another valid boot image in the supported boot modes.
Note: For detailed information on eMMC boot partition, eMMC, SD, or SDHC and UART or USB boot
modes, contact your local sales representative.
6.4.1
Invocation Sequence
The boot sequence is a process by which the device's on-chip memory is loaded with program and data
sections from an external image file (in flash memory, for example). The boot sequence also allows,
optionally, for some of the device's internal registers to be programmed with predetermined values. The
boot sequence is started automatically after each device reset. For more details on device reset, see
Section 5.7.3, Reset.
There are several methods by which the memory and register initialization can take place. Each of these
methods is referred to as a boot mode. At reset, the device cycles through different boot modes until an
image is found with a valid boot signature. The on-chip bootloader allows the DSP registers to be
configured during the boot process, if the optional register configuration section is present in the boot
image (see Figure 6-6). For more information on the boot modes supported, see Section 6.4, Boot Modes.
The device bootloader follows the following steps as shown in Figure 6-6
1. Immediately after reset, the CPU fetches the reset vector from 0xFFFF00. MP or MC is 0 by default, so
0xFFFF00 is mapped to internal ROM. The PLL is in bypass mode.
2. Set CLKOUT slew rate control to slow slew rate.
3. Idle all peripherals, MPORT and HWA.
4. If CLK_SEL = 0, the bootloader powers up the PLL and sets its output frequency to 12.288 MHz (with
a 375x multiplier using VP = 749, VS = 0, input divider disabled, output divide-by-8 enabled, and output
divider enabled with VO = 0). If CLK_SEL = 1, the bootloader keeps the PLL bypassed. Enable Timer0
to count the settling time of BG_CAP.
5. Apply manufacturing trim to the bandgap references.
6. Disable CLKOUT.
7. Test for 16-bit and 24-bit SPI EEPROM boot on SPI_CS[0] with a 500-kHz clock rate and set to
Parallel Port Mode on the External Bus Selection Register to 5, then set to 6:
(a) Check the first 2 bytes read from boot table for a boot signature match using 16-bit address mode.
(b) If the boot signature is not valid, read the first 2 bytes again using 24-bit address mode.
(c) If the boot signature is not valid from either case (16-bit and 24-bit address modes), go to step 8.
(d) Set Register Configuration, if present in boot image.
(e) Attempt SPI Serial Memory boot, go to step 12.
8. Test for I2C EEPROM boot with a 7-bit slave address 0x50 and 400-kHz clock rate.
(a) Check the first 2 bytes read from boot table for a boot signature match.
(b) If the boot signature is not valid, go to step 9.
(c) Set Register Configuration, if present in boot image.
(d) Attempt I2C EEPROM boot, go to step 12.
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9. Test for eMMC partitions, eMMC, SD0 boot:
– For an eMMC, SD, or SDHC card, the card must be formatted to FAT16 or FAT32. The boot image
file must be renamed to "bootimg.bin" and copied to the foot directory of the formatted card.
– If an eMMC boot partition is desired (for only eMMC 4.3 and up), then the boot image file must be
programmed to one of the two boot partitions (1 or 2) on the eMMC card. PARTITION_CONFIG in
the EXT_CSD must be set accordingly.
– If the boot signature is found, attempt eMMC, SD, or SDHC boot and go to step 12.
If boot signature is not found, go to step 10.
10. Set the PLL output to approximately 36 MHz. If CLK_SEL = 1, CLKIN multiplied by 3x. If CLK_SEL =
0, CLKIN is multiplied by 1125x. Re-enable TIMER0 to start counting the settling time of BG_CAP due
to the PLL change.
11. Test for UART or USB boot:
– The USB internal LDO will be enabled and the device is configured to accept a boot image on EP1
OUT.
– UART will be set to 57600 baud, 8 bit, 1 stop bit, CTS or RTS auto flow control, and odd parity will
be enabled to accept a boot image from the UART transmitter.
– The device will poll UART and USB in turns. If a valid boot signature is detected on either device, a
boot image will attempt to download on that device. Go to step 12.
If a valid signature is not detected, return to the start of this step.
12. Copy the boot image sections to system memory.
13. Ensure a minimum of 200 ms has elapsed before proceeding to execute the bootloaded code.
14. Jump to the entry point specified in the boot image.
146
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
CLK SEL = 1
?
No
Setup PLL to
x375
Yes
Internal Configuration
SPI Boot
?
Yes
No
Yes
I2C Boot
?
No
eMMC/SD0
Boot
?
Yes
Set Register
Configuration
(1)
UART/USB
?
Boot
No
Yes
Copy Boot
Image Sections
to System
Memory
Start Timer0 to Count
200 ms
Has Timer0
Counter Expired
?
No
Yes
Jump to Stored
Execution Point
(1)
USB is not supported on TMS320C5532.
Figure 6-6. Bootloader Software Architecture
Detailed Description
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6.4.2
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Boot Configuration
After reset, the on-chip bootloader programs the system clock generator based on the input clock selected
via the CLK_SEL pin. If CLK_SEL = 0, the bootloader programs the system clock generator and sets the
system clock to 12.288 MHz (multiply the 32.768-kHz RTC oscillator clock by 375). If CLK_SEL = 1, the
bootloader bypasses the system clock generator altogether and the system clock is driven by the CLKIN
pin.
Note:
• When CLK_SEL =1, the CLKIN frequency is expected to be 11.2896 MHz, 12.0 MHz, or 12.288 MHz.
• The on-chip bootloader allows for DSP registers to be configured during the boot process. However,
this feature must not be used to change the output frequency of the system clock generator during the
boot process. Timer0 is also used by the bootloader to allow for 200 ms of BG_CAP settling time. The
bootloader register modification feature must not modify the PLL or Timer0 registers.
After hardware reset, the DSP boots via the bootloader code in ROM. During the boot process, the
bootloader queries each peripheral to determine if it can boot from that peripheral. At that time, the
individual peripheral clocks will be enabled for the query and then disabled when the bootloader is finished
with the peripheral. By the time the bootloader releases control to the user code, all peripheral clocks will
be "off" and all domains in the ICR, except the CPU domain, will be idled.
6.4.3
DSP Resources Used By the Bootloader
The bootloader uses SARAM block 31 for the storing of temporary data. This block of memory is reserved
during the boot process. However, after the boot process is complete, it can be used by the user
application.
148
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SPRS737C – AUGUST 2011 – REVISED APRIL 2014
7 Device and Documentation Support
7.1
7.1.1
Device Support
Development Support
TI offers an extensive line of development tools for the TMS320C55x DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules. The tool's support documentation is electronically
available within the Code Composer Studio Integrated Development Environment (IDE).
The following products support development of TMS320C55x fixed-point DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE): Version 4.2.4 or later
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™ Version 5.33 or later), which provides the
basic run-time target software needed to support any DSP application.
Hardware Development Tools:
Extended Development System ( XDS™) Emulator
For a complete listing of development-support tools for the TMS320C55x DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.
7.1.2
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (for example, TMS320C5535AZHHA10). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX and TMDX) through fully qualified
production devices and tools (TMS and TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device's electrical
specifications.
TMP
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
TMS
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Device and Documentation Support
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Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZHH), and the temperature range (for example, "Blank" is the commercial
temperature range).
The following figure provides a legend for reading the complete device name for any DSP platform
member.
TMS 320
C
5535
A
ZHH
A
10
PREFIX
TMX = Experimental device
TMS = Qualified device
DEVICE MAXIMUM OPERATING FREQUENCY
10 = 50 MHz at 1.05 V, 100 MHz at 1.3 V
DEVICE FAMILY
320 = TMS320™ DSP family
TEMPERATURE RANGE
Blank = –10° C to 70° C, Commercial Temperature
A = –40° C to 85° C, Industrial Temperature
TECHNOLOGY
C = Dual-supply CMOS
DEVICE
C55x™ DSP: 5535A10, 5535A05
5534A10, 5534A05
5533A10, 5533A05
5532A10, 5532A05
A.
PACKAGE TYPE
ZHH = 144-pin plastic BGA, with Pb-Free
soldered balls [Green]
SILICON REVISION
Revision 2.2
For actual device part numbers (P/Ns) and ordering information, see the TI website (http://www.ti.com)
Figure 7-1. Device Nomenclature
7.2
7.2.1
Documentation Support
Related Documentation
The following documents describe the DSP. To access the documents, click the literature number (e.g.,
SPRUH87) or wiki link.
The current documentation that describes the DSP, related peripherals, and other technical collateral, is
available in the product folder at www.ti.com.
150
SPRUH87
TMS320C5535/34/33/32 Ultra-Low Power DSP Technical Reference Manual. Collection of
documents providing detailed information on the device including system control, FFT
implementation, and memory access. Detailed information on the device as well as a
functional description of the peripherals supported is also included.
SPRZ373
TMS320C5535/34/33/32 Fixed-Point Digital Signal Processor Silicon Revision 2.2
Silicon Errata. Describes the known exceptions to the functional specifications for this
device.
SPRABL7
Using the TMS320C5535/34/33/32 Bootloader. Describes features of the on-chip ROM for
this device, as well as descriptions of how to interface with possible boot devices and
generating a boot image to store on an external device.
SWPU073
TMS320C55x DSP v3.x CPU Reference Guide. Describes more detailed information on the
C55x CPU.
Wiki
C5505/15/35 Schematic Checklist. Describes recommendations for the device applicable to
unused pins, clocking, power, reset, and peripherals. Description also includes critical
connections, DDR2 routing checklist, and debug considerations, and more.
Device and Documentation Support
Copyright © 2011–2014, Texas Instruments Incorporated
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7.3
SPRS737C – AUGUST 2011 – REVISED APRIL 2014
Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TMS320C5535
Click here
Click here
Click here
Click here
Click here
TMS320C5534
Click here
Click here
Click here
Click here
Click here
TMS320C5533
Click here
Click here
Click here
Click here
Click here
TMS320C5532
Click here
Click here
Click here
Click here
Click here
7.4
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
7.5
Trademarks
C5000, eXpressDSP, Code Composer Studio, DSP/BIOS, RTDX, XDS510, XDS560, XDS, E2E are
trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
7.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.7
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
Device and Documentation Support
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8 Mechanical Packaging and Orderable Information
The following packaging information and addendum reflect the most current data available for the
designated device. This data is subject to change without notice and without revision of this document.
152
Mechanical Packaging and Orderable Information
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TMS320C5532AZHH05
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-10 to 70
32AZHH05
TMS320C55
TMS320C5532AZHH10
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-10 to 70
32AZHH10
TMS320C55
TMS320C5532AZHHA05
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
32AZHHA05
TMS320C55
TMS320C5532AZHHA10
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
32AZHHA10
TMS320C55
TMS320C5533AZHH05
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-10 to 70
33AZHH05
TMS320C55
TMS320C5533AZHH10
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-10 to 70
33AZHH10
TMS320C55
TMS320C5533AZHHA05
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
33AZHHA05
TMS320C55
TMS320C5533AZHHA10
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
33AZHHA10
TMS320C55
TMS320C5534AZHH05
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-10 to 70
34AZHH05
TMS320C55
TMS320C5534AZHH10
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-10 to 70
34AZHH10
TMS320C55
TMS320C5534AZHHA05
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
34AZHHA05
TMS320C55
TMS320C5534AZHHA10
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
34AZHHA10
TMS320C55
TMS320C5535AZHH05
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-10 to 70
35AZHH05
TMS320C55
TMS320C5535AZHH10
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-10 to 70
35AZHH10
TMS320C55
TMS320C5535AZHHA05
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
35AZHHA05
TMS320C55
TMS320C5535AZHHA10
ACTIVE
BGA
MICROSTAR
ZHH
144
160
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
35AZHHA10
TMS320C55
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2013
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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