PIC12F519 Memory Programming

PIC12F519
PIC12F519 Memory Programming Specification
This document includes the
programming specifications for the
following devices:
1.1
The PIC12F519 requires one power supply for VDD
(5.0V) and one for VPP (12.5V).
• PIC12F519
1.0
1.2
PROGRAMMING THE
PIC12F519
VDD
1
RB5/OSC1/CLKIN
2
RB4/OSC2
3
RB3/MCLR/VPP
4
8
VSS
7
RB0/ICSPDAT
6
RB1/ICSPCLK
5
RB2/T0CKI
PIC12F519 8-PIN PDIP, SOIC, AND MSOP DIAGRAM
VDD
RB5/OSC1/CLKIN
RB4/OSC2
RB3/MCLR/VPP
TABLE 1-1:
PIC12F519
PIC12F519 8-PIN 2X3 DFN DIAGRAM
1
2
3
4
PIC12F519
FIGURE 1-2:
Program/Verify Mode
The Program/Verify mode for the PIC12F519 allows
programming of user program memory, user ID
locations, backup OSCCAL location and the
Configuration Word.
The PIC12F519 is programmed using a serial method.
The Serial mode will allow the PIC12F519 to be
programmed while in the user’s system. This allows for
increased design flexibility. This programming
specification applies to the PIC12F519 devices in all
packages.
FIGURE 1-1:
Hardware Requirements
8
7
6
5
Vss
RB0/ICSPDAT
RB1/ICSPCLK
RB2/T0CKI
PIN DESCRIPTIONS DURING PROGRAMMING
During Programming
Pin Name
Function
Pin Type
Pin Description
RB1
ICSPCLK
I
RB0
ICSPDAT
I/O
Data input/output – Schmitt Trigger input
Programming Power
Clock input – Schmitt Trigger input
Program/Verify mode
P(1)
VDD
VDD
P
Power Supply
VSS
VSS
P
Ground
MCLR/VPP/RB3
Legend: I = Input, O = Output, P = Power
Note 1: In the PIC12F519, the programming high voltage is internally generated. To activate the Program/Verify
mode, high voltage of IIHH current capability (see Table 6-1) needs to be applied to the MCLR input.
 2011 Microchip Technology Inc.
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DS41316C-page 1
PIC12F519
2.0
MEMORY MAPPING
The Program Memory map of the PIC12F519 device is
shown in Figure 2-1. In Program/Verify mode, the
Program Memory extends from 0x000 to 0x7FF.
Data Memory
Space
User Memory
Space
FIGURE 2-1:
MEMORY MAP
On-chip User
Program
Memory (Page 0)
On-chip User
Program
Memory (Page 1)
Reset Vector
1FFh
200h
3FEh
3FFh
400h
Flash Data Memory
User ID Locations
Backup OSCCAL
Locations
Configuration Memory
Space
000h
43Fh
440h
443h
444h
447h
448h
through 0x443. The Configuration Word is physically
located at 0x7FF, and the backup OSCCAL locations
extend from 0x444 through 0x447.
2.3.1
USER ID LOCATIONS
A user may store identification information (ID) in four
user ID locations. The user ID locations are mapped in
[0x440:0x443]. It is recommended that users use only
the four Least Significant bits (LSb) of each user ID
location and program the upper 8 bits as ‘1’s. The user
ID locations read out normally, even after code protection is enabled. It is recommended that user ID location
is written as ‘1111 1111 bbbb’ where ‘bbbb’ is user
ID information.
2.3.2
CONFIGURATION WORD
The Configuration Word is physically located at 0x7FF.
It is only available upon Program mode entry. Once an
Increment Address command is issued, the Configuration Word is no longer accessible, regardless of the
address of the program counter.
Note:
By convention, the Configuration Word is
stored at the logical address location of
0xFFF within the hex file generated for the
PIC12F519. This logical address location
may not reflect the actual physical
address for the part itself. It is the responsibility of the programming software to
retrieve the Configuration Word from the
logical address within the hex file and
granulate the address to the proper physical location when programming.
Reserved
49Fh
4A0h
Unimplemented
7FEh
Configuration Word
7FFh
2.3.3
2.1
User Memory
The user memory space is the on-chip user program
memory. As shown in Figure 2-1, it extends from 0x000
to 0x3FF and partitions into pages, including Reset
vector at address 0x3FF. Note that the PC will
increment from (0x000-0x3FF) then to 0x400, (not to
0x000).
2.2
Data Memory
2.3
The backup OSCCAL locations 0x444-0x447 are the
locations where the OSCCAL values are stored during
testing of the INTOSC. This location is not erased during a standard Bulk Erase, but is erased if the PC is
moved into configuration memory prior to invoking a
Bulk Erase. If this value is erased, it is the user’s
responsibility to rewrite it back to this location for future
use.
2.4
The data memory space is the Flash data memory
block and is located at addresses PC = 400h-43Fh. All
program mode commands that work on the normal
Flash memory work on the Flash data memory block.
This includes Bulk Erase, Load and Read data
commands.
Configuration Memory
BACKUP OSCCAL VALUE
Oscillator Calibration Bits
The oscillator Calibration bits are stored at the Reset
vector as the operand of a MOVLW instruction. Programming interfaces must allow users to program the Calibration bits themselves for custom trimming of the
INTOSC. Capability for programming the Calibration
bits when programming the entire memory array must
also be maintained for backwards compatibility.
The configuration memory space extends from 0x440
to 0x7FF. Locations from 0x448 through 0x49F are
reserved. The user ID locations extend from 0x440
DS41316C-page 2
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PIC12F519
3.0
COMMANDS AND
ALGORITHMS
3.1
Program/Verify Mode
3.1.2
The Program/Verify mode is entered by holding pins
ICSPCLK and ICSPDAT low while raising the VDD pin
from VIL to VDD. Then raise VPP from VIL to VIHH. Once
in this mode, the user program memory and configuration memory can be accessed and programmed in
serial fashion. Clock and data are Schmitt Trigger input
in this mode.
The sequence that enters the device into the
Programming/Verify mode places all other logic into the
Reset state (the MCLR pin was initially at VIL). This
means that all I/Os are in the Reset state (highimpedance inputs).
3.1.1
PROGRAMMING
The programming sequence loads a word, programs,
verifies and finally increments the PC.
Program/Verify mode entry will set the address to
0x7FF. The Increment Address command will
increment the PC. The available commands are shown
in Table 3-1.
FIGURE 3-1:
ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
TPPDP
SERIAL PROGRAM/VERIFY
OPERATION
The RB1 pin is used as a clock input pin, and the RB0
pin is used for entering command bits and data input/
output during serial operation. To input a command, the
clock pin (RB1) is cycled 6 times. Each command bit is
latched on the falling edge of the clock with the Least
Significant bit (LSb) of the command being input first.
The data on pin RB0 is required to have a minimum
setup and hold time of 100 ns with respect to the falling
edge of the clock. Commands that have data associated with them (Read and Load) are specified to have
a minimum delay of 1 µs between the command and
the data. After this delay the clock pin is cycled 16 times
with the first cycle being a Start bit and the last cycle
being a Stop bit. Data is also input and output LSb first,
with data input being latched on the falling edge of the
clock and data output being driven on the rising edge of
the clock. Therefore, during a Read operation the LSb
will be transmitted onto pin RB0 on the rising edge of
the second cycle, and during a Load operation the LSb
will be latched on the falling edge of the second cycle.
A minimum 1 µs delay is also specified between consecutive commands; except the “End Programming”
command which requires a 100 µs delay. Because this
is a 12-bit core, the two MSbs of the data word are
ignored. The commands that are available are
described in Table 3-1.
THLD0
VPP
VDD
RB0
(ICSPDAT)
RB1
(ICSPCLK)
TABLE 3-1:
COMMAND MAPPING LOAD DATA
Mapping
(MSb ... LSb)
Hex
Value
Load Data
xx0010
2
start_bit, data (14), stop_bit
Read Data
xx0100
4
start_bit, data (14), stop_bit
Increment Address
xx0110
6
Begin Programming
xx1000
8
End Programming
xx1110
E
Bulk Erase Program Memory
xx1001
9
Command
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Data
DS41316C-page 3
PIC12F519
3.1.2.1
Load Data
two MSbs of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 3-2.
After receiving this command, the device will clock in
14 bits as a “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
FIGURE 3-2:
LOAD DATA COMMAND (PROGRAM/VERIFY)
1
RB1
(ICSPCLK)
RB0
(ICSPDAT)
3.1.2.2
2
3
1
0
4
5
0
0
TSET1
THLD1
x
6
TDLY2
2
4
5
16
15
MSb stp_bit
LSb
strt_bit
x
3
TSET1
-+THLD1
TDLY1
edge and it will revert back to Input mode (high-impedance) after the 16th rising edge. Because this is a 12bit core, the two MSbs will read as ‘1’. A timing diagram
of this command is shown in Figure 3-3.
Read Data
After receiving this command, the chip will transmit
data bits out of the memory currently accessed starting
with the second rising edge of the clock input. The RB0
pin will go into Output mode on the second rising clock
FIGURE 3-3:
1
READ DATA FROM PROGRAM MEMORY COMMAND
TDLY2
1
RB1
(ICSPCLK)
2
3
4
5
1
0
1
6
2
3
4
5
15
16
TDLY3
RB0
(ICSPDAT)
1
0
0
x
x
strt_bit
TDLY1
TSET1
MSb stp_bit
LSb
THLD1
Input
DS41316C-page 4
Output
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Input
 2011 Microchip Technology Inc.
PIC12F519
3.1.2.3
Increment Address
The PC is incremented when this command is
received.
FIGURE 3-4:
INCREMENT ADDRESS COMMAND (SERIAL PROGRAM/VERIFY)
VIHH
MCLR/VPP
TDLY2
1
2
0
1
3
4
5
6
0
X
X
1 µs min.
Next Command
1
2
RB1
(ICSPCLK)
RB0
(ICSPDAT)
1
TSET1
THLD1
}
}
100 ns
min.
Reset
3.1.2.4
Begin Programming
the appropriate memory (User Program Memory, Flash
Data Memory or Test Program Memory) will begin after
this command is received and decoded.
A Load command (Load Data) must be given before
every Begin Programming command. Programming of
FIGURE 3-5:
BEGIN PROGRAMMING COMMAND
VIHH
MCLR/VPP
TPROG
1
2
0
0
3
4
5
6
1
X
X
Next Command
1
2
RB1
(ICSPCLK)
RB0
(ICSPDAT)
0
TSET1
THLD1
}
}
100 ns
min.
Reset
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DS41316C-page 5
PIC12F519
3.1.2.5
End Programming
After receiving this command, the chip stops
programming the memory (User Program Memory,
Flash Data Memory or Test Program Memory) it was
programming at the time.
FIGURE 3-6:
END PROGRAMMING COMMAND
VIHH
MCLR/VPP
TDIS
1
2
3
0
1
4
5
6
1
X
X
1 µs min.
Next Command
1
2
RB1
(ICSPCLK)
RB0
(ICSPDAT)
1
TSET1
THLD1
}
}
100 ns
min.
Reset
3.1.2.6
Bulk Erase Program Memory
After this command is performed, the specific section of
Program Memory and Configuration Word is erased.
See Table 3-2 for details.
Note 1: A fully erased part will read ‘1’s in every
Program Memory location.
2: The oscillator Calibration bits are erased
if a Bulk Erase is invoked. They must be
read and saved prior to erasing the
device and restored during the programming operation. Oscillator Calibration bits
are stored at the Reset vector as the
operand of a MOVLW instruction.
FIGURE 3-7:
BULK ERASE PROGRAM MEMORY COMMAND
VIHH
MCLR/VPP
TERA
1
2
3
1
0
4
5
6
1
X
X
Next Command
1
2
RB1
(ICSPCLK)
RB0
(ICSPDAT)
0
TSET1
THLD1
}
}
100 ns
min.
Reset
DS41316C-page 6
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PIC12F519
TABLE 3-2:
BULK ERASE MEMORY PORTIONS
Config.
Word
(Fuses)
User Program
Memory Erased
Flash Data Memory
Erased
User ID Memory
Erased
Configuration Word
(Fuses)
Yes
Yes
CPDF = 0 – Yes
CPDF = 1 – No
No
000h-3FFh
(User Memory)
Yes
Yes
CPDF = 0 – Yes
CPDF = 1 – No
No
400h-43Fh
(Data Memory)
No
No
CPDF = 0 – No
CPDF = 1 – Yes
No
440h-447h
(Configuration Memory)
No
No
No
Yes
PC
Note:
Yes = erase
No = unchanged
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DS41316C-page 7
PIC12F519
FIGURE 3-8:
READING AND TEMPORARY SAVING OF THE OSCCAL CALIBRATION BITS
Start
Enter Programming
Mode
Increment
Address
No
PC =
0x3FF?
Yes
Read Calibration
Bits and Save in
Computer/Programmer
Temp. Memory
Increment
Address
No
PC =
0x444?
Yes
Read Backup OSCCAL
Calibration Bits
and Save in
Computer/Programmer
Temp. Memory
Exit Programming Mode
Done
DS41316C-page 8
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PIC12F519
FIGURE 3-9:
RESTORING/PROGRAMMING THE OSCCAL CALIBRATION BITS
Start
Enter Programming
Mode
Increment
Address
No
PC =
0x3FF?
Yes
Read Calibration
Bits from
Computer/Programmer
Temp. Memory
Write Calibration Bits
back as the operand
of a MOVLW instruction
to 0x3FF
Increment
Address
No
PC =
0x444?
Yes
Read Backup OSCCAL
Calibration Bits from
Computer/Programmer
Temp. Memory
Write Backup OSCCAL
Bits back to 0x444
Exit Programming Mode
Done
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DS41316C-page 9
PIC12F519
FIGURE 3-10:
PROGRAM FLOWCHART – USER MEMORY
Start
Enter Programming
Mode
PC = 0x7FF
(Config Word)
Increment
Address
PROGRAM CYCLE
Load Data
for
Program Memory
One Word
Program Cycle
Begin
Programming
Command
(Externally timed)
Read Data
from
Program Memory
Wait TPROG
No
Data Correct?
Report
Programming
Failure
End
Programming
Yes
Increment
Address
Command
No
All Programming
Locations
Done?
Wait TDIS
Yes
Exit Programming
Mode
Done
DS41316C-page 10
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PIC12F519
FIGURE 3-11:
PROGRAM FLOWCHART – FLASH DATA MEMORY
Start
Enter Programming
Mode
PC = 0x7FF
(Config Word)
Increment
Address
No
PC = 0x400?
PROGRAM CYCLE
Load Data
for
Program Memory
Yes
One Word
Program Cycle
Begin
Programming
Command
(Externally timed)
Read Data
from
Program Memory
Wait TPROG
No
Data Correct?
Report
Programming
Failure
End
Programming
Yes
Increment
Address
Command
No
All Programming
Locations
Done?
Wait TDIS
Yes
Exit Programming
Mode
Done
 2011 Microchip Technology Inc.
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DS41316C-page 11
PIC12F519
FIGURE 3-12:
PROGRAM FLOWCHART – CONFIGURATION MEMORY
Start
Enter Programming
Mode
PC = 0x7FF
(Config Word)
Load Data Command
Programs Configuration Word
One-Word
Programming
Cycle
(see Figure 3-10)
Read Data Command
Data
Correct?
No
Report
Programming
Failure
Yes
Increment Address
Command
No
Address =
0x440?
Yes
Load Data
Command
Programs User IDs
One-Word
Programming
Cycle
(see Figure 3-10)
Read Data Command
Data
Correct?
No
Report
Programming
Failure
Yes
Increment Address
Command
No
Address =
0x444?
Yes
Exit Programming Mode
Done
DS41316C-page 12
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PIC12F519
FIGURE 3-13:
PROGRAM FLOWCHART – ERASE PROGRAM MEMORY, CONFIGURATION
WORD
Start
Bulk Erase Device
Read and save
OSCCAL bits
(Figure 3-8)
Wait TERA
Exit Programming
Mode
Enter
Program/Verify mode
PC = 0x7FF
(Config Word)
Restore OSCCAL bits
(Figure 3-9)
Done
Note:
Flash Data Memory block will also be erased if CPDF = 0 (see Table 3-2 for more information).
FIGURE 3-14:
PROGRAM FLOWCHART – ERASE FLASH DATA MEMORY
Start
Bulk Erase Device
Read and save
OSCCAL bits
(Figure 3-8)
Wait TERA
Enter
Program/Verify mode
PC = 0x7FF
(Config. Word)
Exit Programming
Mode
Restore OSCCAL bits
(Figure 3-9)
Increment Address
Done
No
PC =
0x400?
Yes
Note 1:
This operation requires that CPDF = 1.
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DS41316C-page 13
PIC12F519
FIGURE 3-15:
PROGRAM FLOWCHART – ERASE USER ID
Read and save
OSCCAL bits
(Figure 3-8)
Start
Enter
Program/Verify mode
PC = 0x7FF
(Config. Word)
Increment
PC
No
PC = 0x440?
(First User ID)
Yes
Bulk Erase Device
Wait TERA
Exit Programming Mode
Restore OSCCAL bits
(Figure 3-9)
Done
DS41316C-page 14
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PIC12F519
FIGURE 3-16:
PROGRAM FLOWCHART – HIGH-LEVEL FULL DEVICE PROGRAM
Start
Read OSCCAL bits
Bulk Erase
User Memory
Bulk Erase
Data Memory
Bulk Erase
ID/OSCCAL
Program
User Memory
Program
Data Memory
Program
Configuration Memory
Restore
OSCCAL bits
Done
 2011 Microchip Technology Inc.
Advance Information
DS41316C-page 15
PIC12F519
FIGURE 3-17:
PROGRAM FLOWCHART – HIGH-LEVEL FULL DEVICE ERASE
Start
Read OSCCAL bits
Bulk Erase
User Memory
Bulk Erase
Data Memory
Bulk Erase
ID/OSCCAL
Restore
OSCCAL bits
Done
DS41316C-page 16
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PIC12F519
4.0
CONFIGURATION WORD
See Register 4-1 below for details.
The implemented Configuration bits can be
programmed at their default values, or they are not
programmed.
REGISTER 4-1:
U-1
—
bit 11
U-1
—
CONFIGURATION WORD
U-1
—
Legend:
R = Readable bit
-n = Value at POR
U-1
—
U-1
—
R/P-1
CPDF
R/P-1
R/P-1
IOSCFS MCLRE
P
P == Programmable
Programmable
W = Writable bit
‘1’ = Bit is set
R/P-1
CP
R/P-1
WDTE
R/P-1
FOSC1
R/P-1
FOSC0
bit 0
x = Bit is unknown
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
bit 11-7
Unimplemented: Read as ‘1’
bit 6
CPDF: Code Protection bit – Flash Data Memory
1 = Code protection off
0 = Code protection on
bit 5
IOSCFS: Internal Oscillator Frequency Select bit
1 = 8 MHz INTOSC speed
0 = 4 MHz INTOSC speed
bit 4
MCLRE: Master Clear Enable bit
1 = RB3/MCLR pin functions as MCLR
0 = RB3/MCLR pin functions as RB3, MCLR internally tied to VDD
bit 3
CP: Code Protection bit – User Program Memory
1 = Code protection off
0 = Code protection on
bit 2
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
00 = LP oscillator with 18 ms DRT
01 = XT oscillator with 18 ms DRT
10 = INTRC with 1 ms DRT(1)
11 = EXTRC with 1 ms DRT(1)
Note 1: It is the responsibility of the application designer to ensure the use of the 1 ms DRT will result in acceptable
operation. Refer to Electrical Specifications for VDD rise time and stability requirements for this mode of
operation.
 2011 Microchip Technology Inc.
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DS41316C-page 17
PIC12F519
5.0
CODE PROTECTION
For the PIC12F519, once code protection is enabled,
all Program Memory locations 0x40-0x3FE, read all
‘0’s. Program Memory locations 0x000-0x03F and
0x3FF are always unprotected. The user ID locations,
backup OSCCAL location and the Configuration Word
read out in an unprotected fashion. It is possible to program the user ID locations, backup OSCCAL location
and the Configuration Word after code-protect is
enabled.
Note:
To allow portability of code, the programmer is required to read the Configuration
Word and user ID locations from the hex
file when loading the hex file. If Configuration Word information was not present in
the hex file, then a simple warning
message may be issued. Similarly, while
saving a hex file, Configuration Word and
user ID information must be included. An
option to not include this information may
be provided.
The code protection of the Flash data memory is
dependant on the CPDF bit. If the CPDF bit is set, only
the Flash data memory block is code-protected. See
Table 3-2 for erase conditions involving the CPDF bit.
5.1
Disabling Code Protection
It is recommended that the following procedure be
performed before any other programming is attempted.
It is also possible to turn code protection off using this
procedure. However, all data within the program
memory will be erased when this procedure is executed, and thus, the security of the code is not
compromised. See Table 3-2 for more information on
Flash data memory.
To disable code-protect:
a)
b)
c)
Microchip Technology Incorporated feels
strongly that this feature is important for
the benefit of the end customer.
Enter Program mode
Execute Bulk Erase
command (001001).
Wait TERA
Program
Memory
5.2
Checksum Computation
5.2.1
CHECKSUM
Checksum is calculated by reading the contents of the
PIC12F519 memory locations and adding up the
opcodes up to the maximum user addressable location.
Any Carry bits exceeding 16 bits are neglected. Finally,
the Configuration Word (appropriately masked) is
added to the checksum. The checksum computation
for the PIC12F519 is shown in Table 5-1.
The checksum is calculated by summing the following:
• The contents of all program memory locations
• The Configuration Word, appropriately masked
• Masked user ID locations (when applicable)
The Least Significant 16 bits of this sum is the
checksum.
The following table describes how to calculate the
checksum for each PIC12F519.
Note:
TABLE 5-1:
Device
PIC12F519
Legend:
Note 1:
The
checksum
calculation
differs
depending on the code-protect setting.
The Configuration Word and user ID
locations can always be read regardless
of the code-protect settings.
CHECKSUM COMPUTATIONS(1)
Code-Protect
Checksum*
Blank
Value
0x723 at 0
and Max.
Address
OFF
SUM[0x000:0x3FE] + CFGW & 0x07F
0xEC80
0xDAC8
ON
SUM[0x00:0x3F] + (CFGW & 0x07F | 0x64) + SUM_ID
0xECB7
0xD223
CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = User ID locations masked by 0xF then made into a 16-bit value with ID0 as the Most Significant nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID2 = 0x3, ID3 = 0x4, then SUM_ID = 0x1234.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
Checksum shown assumes that SUM_ID contains the unprotected checksum.
DS41316C-page 18
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PIC12F519
6.0
PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 6-1:
AC/DC TIMING REQUIREMENTS
AC TARGETS
Sym.
Characteristics
Min.
Typ.
Max.
Units
VIHH
VPP high voltage on MCLR for Program/Verify
mode entry
12.5
—
13.5
V
VIHL
Voltage on MCLR to be in Normal mode
VSS
—
VDD + 1.0
V
TVHHR
MCLR rise time (VSS to VHH) for Test mode
entry
—
—
1.0
s
VIH1
Clock (RB1) and Data (RB0) input high level
0.85*VDD
—
VIL1
Clock (RB1) and Data (RB0) input low level
—
—
0.15*VDD
V
VDDOK
Minimum VDD to perform Bulk Erase
4.5
4.0
5.5
V
VPROG
High voltage on MCLR for programming
12.5
13.0
13.5
V
IDDPROG
IDD level for programming operations,
program memory
—
—
1.8
mA
IDDERA
IDD level for Bulk Erase operations, program
memory
—
—
1.8
mA
IPP
MCLR pin current during Program/Verify
mode
—
—
0.4
mA
TPROG
Programming time
1000
—
2000
s
TPPDP
Hold time after VPP
5
—
—
s
THLD0
ISPCLK, ISPDATA hold time after MCLR
(Program/Verify mode selection pattern setup
time)
5
—
—
s
Conditions
General
V
Serial Program/Verify
TSET1
Data in setup time before clock
100
—
—
ns
THLD1
Data in hold time after clock
100
—
—
ns
TDLY1
Data input not driven to next clock input (delay
required between command/data or
command/command)
1.0
—
—
s
TDLY2
Delay between clock to clock of next
command or data
1.0
—
—
s
TDLY3
Clock to data out valid (during Read Data)
80
—
—
ns
TERA
Bulk Erase Time
4
—
10
ms
Total time to perform both stages
of Bulk Erase and
accept the next
command.
TDIS
High Voltage Discharge Time
100
—
—
s
Time to discharge
high voltage.
 2011 Microchip Technology Inc.
Advance Information
DS41316C-page 19
PIC12F519
NOTES:
DS41316C-page 20
Advance Information
 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-204-6
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2011 Microchip Technology Inc.
Advance Information
DS41316C-page 21
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
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Technical Support:
http://www.microchip.com/
support
Web Address:
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DS41316C-page 22
Italy - Milan
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Advance Information
05/02/11
 2011 Microchip Technology Inc.