CPU and ALU - PICmicro Mid-Range MCU Family

M
Section 5. CPU and ALU
HIGHLIGHTS
This section of the manual contains the following major topics:
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
Introduction ....................................................................................................................5-2
General Instruction Format ............................................................................................5-4
Central Processing Unit (CPU) ......................................................................................5-4
Instruction Clock ............................................................................................................5-4
Arithmetic Logical Unit (ALU).........................................................................................5-5
STATUS Register ...........................................................................................................5-6
OPTION_REG Register .................................................................................................5-8
PCON Register ..............................................................................................................5-9
Design Tips ..................................................................................................................5-10
Related Application Notes............................................................................................5-11
Revision History ...........................................................................................................5-12
5
CPU and ALU
 1997 Microchip Technology Inc.
DS31005A page 5-1
PICmicro MID-RANGE MCU FAMILY
5.1
Introduction
The Central Processing Unit (CPU) is responsible for using the information in the program memory (instructions) to control the operation of the device. Many of these instructions operate on
data memory. To operate on data memory, the Arithmetic Logical Unit (ALU) is required. In addition to performing arithmetical and logical operations, the ALU controls status bits (which are
found in the STATUS register). The result of some instructions force status bits to a value depending on the state of the result.
The machine codes that the CPU recognizes are show in Table 5-1 (as well as the instruction
mnemonics that the MPASM uses to generate these codes).
DS31005A-page 5-2
 1997 Microchip Technology Inc.
Section 5. CPU and ALU
Table 5-1:
Mid-Range MCU Instruction Set
Mnemonic,
Operands
14-Bit Instruction Word
Description
Cycles
MSb
LSb
Status
Bits
Notes
Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS
1,2
C,DC,Z
ffff
0111 dfff
00
1
Add W and f
f, d
ADDWF
1,2
Z
ffff
0101 dfff
00
1
AND W with f
f, d
ANDWF
2
Z
ffff
0001 lfff
00
1
Clear f
f
CLRF
Z
xxxx
0001 0xxx
00
1
Clear W
CLRW
1,2
Z
ffff
1001 dfff
00
1
Complement f
f, d
COMF
1,2
Z
ffff
0011 dfff
00
1
Decrement f
f, d
DECF
1,2,3
ffff
1011 dfff
00
1(2)
Decrement f, Skip if 0
f, d
DECFSZ
1,2
Z
ffff
1010 dfff
00
1
Increment f
f, d
INCF
1,2,3
ffff
1111 dfff
00
1(2)
Increment f, Skip if 0
f, d
INCFSZ
1,2
Z
ffff
0100 dfff
00
1
Inclusive OR W with f
f, d
IORWF
1,2
Z
ffff
1000 dfff
00
1
Move f
f, d
MOVF
ffff
0000 lfff
00
1
Move W to f
f
MOVWF
0000
0000 0xx0
00
1
No Operation
NOP
1,2
C
ffff
1101 dfff
00
1
Rotate Left f through Carry
f, d
RLF
1,2
C
ffff
1100 dfff
00
1
Rotate Right f through Carry
f, d
RRF
1,2
C,DC,Z
ffff
0010 dfff
00
1
Subtract W from f
f, d
SUBWF
1,2
ffff
1110 dfff
00
1
Swap nibbles in f
f, d
SWAPF
1,2
Z
ffff
0110 dfff
00
1
Exclusive OR W with f
f, d
XORWF
BIT-ORIENTED FILE REGISTER OPERATIONS
ffff
1,2
00bb bfff
1
01
Bit Clear f
f, b
BCF
ffff
1,2
01bb bfff
1
01
Bit Set f
f, b
BSF
3
10bb bfff- ffff
1 (2)
01
Bit Test f, Skip if Clear
f, b
BTFSC
ffff
3
11bb bfff
1 (2)
01
Bit Test f, Skip if Set
f, b
BTFSS
LITERAL AND CONTROL OPERATIONS
C,DC,Z
kkkk
111x kkkk
11
1
Add literal and W
k
ADDLW
Z
kkkk
1001 kkkk
11
1
AND literal with W
k
ANDLW
kkkk
0kkk kkkk
10
2
Call subroutine
k
CALL
TO,PD
0100
0000 0110
00
1
Clear Watchdog Timer
CLRWDT
kkkk
1kkk kkkk
10
2
Go to address
k
GOTO
kkkk
1000 kkkk
11
1
Inclusive OR literal with W
k
IORLW
Z
kkkk
00xx kkkk
11
1
Move literal to W
k
MOVLW
1001
0000 0000
00
2
Return from interrupt
RETFIE
kkkk
01xx kkkk
11
2
Return with literal in W
k
RETLW
1000
0000 0000
00
2
Return from Subroutine
RETURN
0011
0000 0110
00
1
Go into standby mode
SLEEP
TO,PD
kkkk
110x kkkk
11
1
Subtract W from literal
k
SUBLW
C,DC,Z
kkkk
1010 kkkk
11
1
Exclusive OR literal with W
k
XORLW
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared if assigned to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
5
CPU and ALU
 1997 Microchip Technology Inc.
DS31005A-page 5-3
PICmicro MID-RANGE MCU FAMILY
5.2
General Instruction Format
The Mid-Range MCU instructions can be broken down into four general formats as shown in
Figure 5-1. As can be seen the opcode for the instruction varies from 3-bits to 6-bits. This variable
opcode size is what allows 35 instructions to be implemented.
Figure 5-1: General Format for Instructions
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
0
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
OPCODE
0
k = 8-bit immediate value
k (literal)
CALL and GOTO instructions only
13
11
10
0
OPCODE
5.3
k = 11-bit immediate value
k (literal)
Central Processing Unit (CPU)
The CPU can be thought of as the “brains” of the device. It is responsible for fetching the correct
instruction for execution, decoding that instruction, and then executing that instruction.
The CPU sometimes works in conjunction with the ALU to complete the execution of the instruction (in arithmetic and logical operations).
The CPU controls the program memory address bus, the data memory address bus, and
accesses to the stack.
5.4
Instruction Clock
Each instruction cycle (TCY) is comprised of four Q cycles (Q1-Q4). The Q cycle time is the same
as the device oscillator cycle time (TOSC). The Q cycles provide the timing/designation for the
Decode, Read, Process Data, Write, etc., of each instruction cycle. The following diagram shows
the relationship of the Q cycles to the instruction cycle.
The four Q cycles that make up an instruction cycle (TCY) can be generalized as:
Q1:
Instruction Decode Cycle or forced No operation
Q2:
Instruction Read Data Cycle or No operation
Q3:
Process the Data
Q4:
Instruction Write Data Cycle or No operation
Each instruction will show a detailed Q cycle operation for the instruction.
Figure 5-2: Q Cycle Activity
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Tosc
TCY1
DS31005A-page 5-4
TCY2
TCY3
 1997 Microchip Technology Inc.
Section 5. CPU and ALU
5.5
Arithmetic Logical Unit (ALU)
PICmicro MCUs contain an 8-bit ALU and an 8-bit working register. The ALU is a general purpose arithmetic and logical unit. It performs arithmetic and Boolean functions between the data
in the working register and any register file.
Figure 5-3: Operation of the ALU and W Register
8-bit literal
(from instruction word)
8
W Register
8
8-bit register value
8 (from direct or indirect
address of instruction)
8
ALU
Register
File
Special
Function
Registers
(SFR’s)
and
General
Purpose
RAM
(GPR)
8
d bit, or from instruction
d = '0' or
Literal Instructions
d = '1'
The ALU is 8-bits wide and is capable of addition, subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand
instructions, typically one operand is the working register (W register). The other operand is a file
register or an immediate constant. In single operand instructions, the operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU operations. It is not an addressable register.
Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit
Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow bit
and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for
examples.
5
CPU and ALU
 1997 Microchip Technology Inc.
DS31005A-page 5-5
PICmicro MID-RANGE MCU FAMILY
5.6
STATUS Register
The STATUS register, shown in Figure 5-1, contains the arithmetic status of the ALU, the RESET
status and the bank select bits for data memory. Since the selection of the Data Memory banks
is controlled by this register, it is required to be present in every bank. Also, this register is in the
same relative position (offset) in each bank (see Figure 6-5: “Register File Map” in the “Memory Organization” section).
The STATUS register can be the destination for any instruction, as with any other register. If the
STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write
to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than intended.
For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the
STATUS register as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to
alter the STATUS register because these instructions do not affect the Z, C or DC bits from the
STATUS register. For other instructions, not affecting any status bits, see Table 5-1.
Note 1: Some devices do not require the IRP and RP1 (STATUS<7:6>) bits. These bits are
not used by the Section 5. CPU and ALU and should be maintained clear. Use of
these bits as general purpose R/W bits is NOT recommended, since this may affect
upward code compatibility with future products.
Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction.
DS31005A-page 5-6
 1997 Microchip Technology Inc.
Section 5. CPU and ALU
Register 5-1:
STATUS Register
R/W-0
IRP
bit 7
bit 7
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 0
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
For devices with only Bank0 and Bank1 the IRP bit is reserved, always maintain this bit clear.
bit 6:5
RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. For devices with only Bank0 and Bank1 the IRP bit is reserved,
always maintain this bit clear.
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note:
For borrow the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
5
CPU and ALU
 1997 Microchip Technology Inc.
DS31005A-page 5-7
PICmicro MID-RANGE MCU FAMILY
5.7
OPTION_REG Register
The OPTION_REG register is a readable and writable register which contains various control bits
to configure the TMR0/WDT prescaler, the external INT Interrupt, TMR0, and the weak pull-ups
on PORTB.
Register 5-2: OPTION_REG Register
R/W-1
RBPU
bit 7
R/W-1
INTEDG
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
bit 0
Legend
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
Note:
DS31005A-page 5-8
- n = Value at POR reset
To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler
to the Watchdog Timer.
 1997 Microchip Technology Inc.
Section 5. CPU and ALU
5.8
PCON Register
The Power Control (PCON) register contains flag bit(s), that together with the TO and PD bits,
allows the user to differentiate between the device resets.
Note 1: BOR is unknown on Power-on Reset. It must then be set by the user and checked
on subsequent resets to see if BOR is clear, indicating a brown-out has occurred.
The BOR status bit is a don't care and is not necessarily predictable if the brown-out
circuit is disabled (by clearing the BODEN bit in the Configuration word).
Note 2: It is recommended that the POR bit be cleared after a power-on reset has been
detected, so that subsequent power-on resets may be detected.
Register 5-3: PCON Register
R-u
MPEEN
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PER
R/W-0
POR
R/W-0
BOR
bit 0
bit 7
MPEEN: Memory Parity Error Circuitry Status bit
This bit reflects the value of the MPEEN configuration bit.
bit 6:3
Unimplemented: Read as '0'
bit 2
PER: Memory Parity Error Reset Status bit
1 = No error occurred
0 = A program memory fetch parity error occurred
(must be set in software after a Power-on Reset occurs)
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
5
CPU and ALU
 1997 Microchip Technology Inc.
DS31005A-page 5-9
PICmicro MID-RANGE MCU FAMILY
5.9
Design Tips
Question 1:
My program algorithm does not seem to function correctly.
Answer 1:
1.
2.
The destination of the instruction may be specifying the W register (d = 0) instead of the
file register (d = 1).
The register bank select bits (RP1:RP0 or IRP) may not be properly selected. Also if interrupts are used, the register bank select bits may not be properly restored when exiting the
interrupt handler.
Question 2:
I cannot seem to modify the STATUS register flags.
Answer 2:
if the STATUS register is the destination for an instruction that affects the Z, DC, or C bits, the
write to these bits is disabled. These bits are set or cleared based on device logic. Therefore, to
modify bits in the STATUS register it is recommended to use the BCF and BSF instructions.
DS31005A-page 5-10
 1997 Microchip Technology Inc.
Section 5. CPU and ALU
5.10
Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the Mid-Range MCU family (that is they may be written for the Base-Line, or High-End families), but the concepts are pertinent, and could be used
(with modification and possible limitations). The current application notes related to the CPU or
the ALU are:
Title
Application Note #
Fixed Point Routines
AN617
IEEE 754 Compliant Floating Point Routines
AN575
Digital Signal Processing with the PIC16C74
AN616
Math Utility Routines
AN544
Implementing IIR Digital Filters
AN540
Implementation of Fast Fourier Transforms
AN542
Tone Generation
AN543
Servo Control of a DC Brushless Motor
AN532
Implementation of the Data Encryption Standard using the PIC17C42
AN583
PIC16C5X / PIC16CXX Utility Math Routines
AN526
Real Time Operating System for PIC16/17
AN585
5
CPU and ALU
 1997 Microchip Technology Inc.
DS31005A-page 5-11
PICmicro MID-RANGE MCU FAMILY
5.11
Revision History
Revision A
This is the initial released revision of the CPU and ALU description.
DS31005A-page 5-12
 1997 Microchip Technology Inc.
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