Download Datasheet

TSX561, TSX562, TSX564,
TSX561A, TSX562A, TSX564A
Micropower, wide bandwidth (900 kHz), 16 V CMOS
operational amplifiers
Datasheet - production data
Benefits
• Power savings in power-conscious
applications
627VLQJOH
• Easy interfacing with high impedance sensors
')1[GXDO
Related products
• See TSX63x series for reduced power
consumption (45 μA, 200 kHz)
• See TSX92x series for higher gain bandwidth
products (10 MHz)
0LQL62GXDO
62GXDO
Applications
• Industrial and automotive signal conditioning
• Active filtering
• Medical instrumentation
• High impedance sensors
4)1[TXDG
Description
76623TXDG
Features
• Low power consumption: 235 µA typ. at 5 V
• Supply voltage: 3 V to 16 V
• Gain bandwidth product: 900 kHz typ.
• Low offset voltage
– “A” version: 600 µV max.
– Standard version: 1 mV max.
• Low input bias current: 1 pA typ.
• High tolerance to ESD: 4 kV
• Wide temperature range: -40 to +125 °C
• Automotive qualification
• Tiny packages available
– SOT23-5
– DFN8 2 mm x 2 mm, MiniSO8, SO8
– QFN16 3 mm x 3 mm, TSSOP14
August 2013
This is information on a product in full production.
The TSX56x, TSX56xA series of operational
amplifiers benefit from STMicroelectronics® 16 V
CMOS technology to offer state-of-the-art
accuracy and performance in the smallest
industrial packages. The TSX56x, TSX56xA have
pinouts compatible with industrial standards and
offer an outstanding speed/power consumption
ratio, 900 kHz gain bandwidth product while
consuming only 250 µA at 16 V. Such features
make the TSX56x, TSX56xA ideal for sensor
interfaces and industrial signal conditioning. The
wide temperature range and high ESD tolerance
ease use in harsh automotive applications.
Table 1.
Device summary
Version
Standard Vio
Enhanced Vio
Single
TSX561
TSX561A
Dual
TSX562
TSX562A
Quad
TSX564
TSX564A
DocID023274 Rev 4
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www.st.com
Contents
TSX56x, TSX56xA
Contents
1
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 4
3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
4.1
Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2
Rail-to-rail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3
Input offset voltage drift over temperature . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4
Long term input offset voltage drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5
PCB layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6
Macromodel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1
SOT23-5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2
DFN8 2x2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3
MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.4
SO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.5
QFN16 3x3 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.6
TSSOP14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28
DocID023274 Rev 4
TSX56x, TSX56xA
Pin connections
Figure 1. Pin connections for each package (top view)
Single
SOT23-5 (TSX561)
Dual
287
9&&
287
9&&
,1
287
,1
287
,1
,1
,1
,1
9&&
,1
9&&
,1
DFN8 2x2 (TSX562)
MiniSO8 and SO8 (TSX562)
,1
287
287
,1
Quad
,1
9&&
9&&
1&
1&
,1
,1
,1
287
287
,1
,1
1
Pin connections
QFN16 3x3 (TSX564)
DocID023274 Rev 4
TSSOP14 (TSX564)
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Absolute maximum ratings and operating conditions
2
TSX56x, TSX56xA
Absolute maximum ratings and operating conditions
Table 2. Absolute maximum ratings (AMR)
Symbol
VCC
Vid
Vin
Iin
Tstg
Rthja
Rthjc
Tj
Parameter
Supply voltage
(2)
±VCC
V
(3)
VCC- - 0.2 to VCC++ 0.2
(4)
10
mA
-65 to +150
°C
Input voltage
Storage temperature
Thermal resistance junction to ambient
SOT23-5
DFN8 2x2
MiniSO8
SO8
QFN16 3x3
TSSOP14
(5)(6)
250
120
190
125
80
100
°C/W
Thermal resistance junction to case
DFN8 2x2
QFN16 3x3
33
30
Maximum junction temperature
150
°C
4
kV
HBM: human body
ESD
Unit
18
Differential input voltage
Input current
Value
(1)
model(7)
MM: machine model for
TSX561(8)
MM: machine model for TSX562 and TSX564
200
(8)
100
V
CDM: charged device model(9)
1.5
kV
Latch-up immunity
200
mA
1. All voltage values, except differential voltage, are with respect to network ground terminal.
2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.
3. VCC - Vin must not exceed 18 V, Vin must not exceed 18 V.
4. Input current must be limited by a resistor in series with the inputs.
5. Short-circuits can cause excessive heating and destructive dissipation.
6. Rth are typical values.
7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for
all couples of pin combinations with other pins floating.
8. Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two
pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin
combinations with other pins floating.
9. Charged device model: all pins plus package are charged together to the specified voltage and then
discharged directly to ground.
Table 3. Operating conditions
Symbol
4/28
Parameter
VCC
Supply voltage
Vicm
Common mode input voltage range
Toper
Operating free air temperature range
Value
3 to 16
DocID023274 Rev 4
VCC- - 0.1 to VCC+ + 0.1
-40 to +125
Unit
V
°C
TSX56x, TSX56xA
3
Electrical characteristics
Electrical characteristics
Table 4. Electrical characteristics at VCC+ = +3.3 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and
RL=10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
Vio
Offset voltage
TSX56xA, T = 25 °C
600
TSX56xA, -40 °C < T < 125 °C
1800
TSX56x, T = 25 °C
1
TSX56x, -40 °C < T < 125 °C
2.2
Input offset voltage drift
-40 °C < T < 125 °C(1)
2
12
Iio
Input offset current
(Vout = VCC/2)
T = 25 °C
1
100(2)
-40 °C < T < 125 °C
1
200(2)
Iib
Input bias current
(Vout = VCC/2)
T = 25 °C
1
100(2)
-40 °C < T < 125 °C
1
200(2)
ΔVio/ΔT
T = 25 °C
63
-40 °C < T < 125 °C
59
47
CMR1
T = 25 °C
CMR2
Common mode rejection ratio
CMR = 20 log (ΔVic/ΔVio)
(Vic = -0.1 V to VCC+0.1 V,
Vout = VCC/2, RL > 1 MΩ)
-40 °C < T < 125 °C
45
Large signal voltage gain
(Vout = 0.5 V to (VCC - 0.5 V),
RL > 1 MΩ)
T = 25 °C
85
Avd
-40 °C < T < 125 °C
83
VOH
High level output voltage
(VOH = VCC - Vout)
T = 25 °C
70
-40 °C < T < 125 °C
100
T = 25 °C
70
-40 °C < T < 125 °C
100
Low level output voltage
Isink (Vout = VCC)
Iout
Isource (Vout = 0 V)
ICC
Supply current
(per channel, Vout = VCC/2,
RL > 1 MΩ)
mV
μV/°C
pA
80
Common mode rejection ratio
CMR = 20 log (ΔVic/ΔVio)
(Vic = -0.1 V to VCC-1.5 V,
Vout = VCC/2, RL > 1 MΩ)
VOL
μV
66
dB
T = 25 °C
4.3
-40 °C < T < 125 °C
2.5
T = 25 °C
3.3
-40 °C < T < 125 °C
2.5
T = 25 °C
-40 °C < T < 125 °C
DocID023274 Rev 4
mV
5.3
mA
4.3
220
300
350
µA
5/28
28
Electrical characteristics
TSX56x, TSX56xA
Table 4. Electrical characteristics at VCC+ = +3.3 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and
RL=10 kΩ connected to VCC/2 (unless otherwise specified) (continued)
Symbol
Parameter
Conditions
Min.
Typ.
600
800
Max.
Unit
AC performance
GBP
Gain bandwidth product
Fu
Unity gain frequency
Φm
Phase margin
Gm
Gain margin
SR
Slew rate
∫ en
en
THD+N
RL = 10 kΩ, CL = 100 pF
kHz
55
Degree
9
dB
RL = 10 kΩ, CL = 100 pF,
Vout = 0.5 V to VCC - 0.5 V
1
V/μs
Low-frequency peak-to-peak
input noise
Bandwidth: f = 0.1 to 10 Hz
16
µVpp
Equivalent input noise voltage
density
f = 1 kHz
f = 10 kHz
55
29
nV
-----------Hz
0.004
%
Follower configuration,
fin = 1 kHz,
Total harmonic distortion + noise RL = 100 kΩ,
Vicm = (VCC -1.5 V)/2,
BW = 22 kHz, Vout = 1 Vpp
1. See Section 4.3: Input offset voltage drift over temperature on page 15.
2. Guaranteed by design.
6/28
690
DocID023274 Rev 4
TSX56x, TSX56xA
Electrical characteristics
Table 5. Electrical characteristics at VCC+ = +5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and
RL = 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
Vio
Offset voltage
TSX56xA, T = 25 °C
600
TSX56xA, -40 °C < T < 125 °C
1800
TSX56x, T = 25 °C
1
TSX56x, -40 °C < T < 125 °C
2.2
Input offset voltage drift
-40 °C < T < 125 °C(1)
2
Long-term input offset voltage
drift
T = 25 °C(2)
5
Iio
Input offset current
(Vout = VCC/2)
T = 25 °C
1
100(3)
-40 °C < T < 125 °C
1
200(3)
Iib
Input bias current
(Vout = VCC/2)
T = 25 °C
1
100(3)
-40 °C < T < 125 °C
1
200(3)
ΔVio/ΔT
ΔVio
66
CMR1
Common mode rejection ratio T = 25 °C
CMR = 20 log (ΔVic/ΔVio)
(Vic = -0.1 V to VCC - 1.5 V,
-40 °C < T < 125 °C
Vout = VCC/2, RL > 1 MΩ)
50
CMR2
Common mode rejection ratio T = 25 °C
CMR = 20 log (ΔVic/ΔVio)
(Vic = -0.1 V to VCC + 0.1 V,
-40 °C < T < 125 °C
Vout = VCC/2, RL > 1 MΩ)
12
63
69
dB
47
85
-40 °C < T < 125 °C
83
VOH
High level output voltage
(VOH = VCC - Vout)
RL = 10 kΩ, T = 25 °C
RL = 10 kΩ, -40 °C < T < 125 °C
70
100
Low level output voltage
RL = 10 kΩ, T = 25 °C
RL = 10 kΩ, -40 °C < T < 125 °C
70
100
Isource
ICC
Supply current
(per channel, Vout = VCC/2,
RL > 1 MΩ)
Vout = VCC, T = 25 °C
11
Vout = VCC, -40 °C < T < 125 °C
8
Vout = 0 V, T = 25 °C
9
Vout = 0 V, -40 °C < T < 125 °C
7
T = 25 °C
-40 °C < T < 125 °C
DocID023274 Rev 4
pA
84
T = 25 °C
Iout
μV/°C
nV
month
Large signal voltage gain
(Vout = 0.5 V to (VCC - 0.5 V),
RL > 1 MΩ)
Isink
mV
---------------------------
Avd
VOL
μV
mV
14
mA
12
235
350
400
µA
7/28
28
Electrical characteristics
TSX56x, TSX56xA
Table 5. Electrical characteristics at VCC+ = +5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and
RL = 10 kΩ connected to VCC/2 (unless otherwise specified) (continued)
Symbol
Parameter
Conditions
Min.
Typ.
700
850
Max.
Unit
AC performance
GBP
Gain bandwidth product
Fu
Unity gain frequency
Φm
Phase margin
Gm
Gain margin
SR
Slew rate
∫ en
Low-frequency peak-to-peak
input noise
en
THD+N
RL = 10 kΩ, CL = 100 pF
kHz
55
Degree
9
dB
RL = 10 kΩ, CL = 100 pF,
Vout = 0.5 V to VCC - 0.5 V
1.1
V/μs
Bandwidth: f = 0.1 to 10 Hz
15
µVpp
55
29
nV
-----------Hz
0.002
%
Equivalent input noise voltage f = 1 kHz
density
f = 10 kHz
Total harmonic distortion +
noise
730
Follower configuration,
fin = 1 kHz,
RL = 100 kΩ, Vicm = (VCC - 1.5 V)/2,
BW = 22 kHz, Vout = 2 Vpp
1. See Section 4.3: Input offset voltage drift over temperature on page 15.
2. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.
3. Guaranteed by design.
8/28
DocID023274 Rev 4
TSX56x, TSX56xA
Electrical characteristics
Table 6. Electrical characteristics at VCC+ = +16 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and
RL = 10 kΩ connected to VCC/2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
Vio
Offset voltage
TSX56xA, T = 25 °C
600
TSX56xA, -40 °C < T < 125 °C
1800
TSX56x, T = 25 °C
1
TSX56x, -40 °C < T < 125 °C
ΔVio/ΔT Input offset voltage drift
2.2
-40 °C < T < 125 °C(1)
2
12
T = 25 °C(2)
Iio
Input offset current
(Vout = VCC/2)
T = 25 °C
1
100(3)
-40 °C < T < 125 °C
1
200(3)
Iib
Input bias current
(Vout = VCC/2)
T = 25 °C
1
100(3)
-40 °C < T < 125 °C
1
200(3)
76
-40 °C < T < 125 °C
72
CMR1
T = 25 °C
60
CMR2
Common mode rejection ratio
CMR = 20 log (ΔVic/ΔVio)
(Vic = -0.1 V to VCC + 0.1 V,
Vout = VCC/2, RL > 1 MΩ)
-40 °C < T < 125 °C
56
T = 25 °C
76
SVR
Common mode rejection ratio
20 log (ΔVCC/ΔVio)
(VCC = 3 V to 16 V,
Vout = Vicm = VCC/2)
-40 °C < T < 125 °C
72
Large signal voltage gain
(Vout = 0.5 V to (VCC - 0.5 V),
RL > 1 MΩ)
T = 25 °C
85
Avd
-40 °C < T < 125 °C
83
VOH
High level output voltage
(VOH = VCC - Vout)
RL = 10 kΩ, T = 25 °C
RL = 10 kΩ, -40 °C < T < 125 °C
70
100
Low level output voltage
RL = 10 kΩ, T = 25 °C
RL = 10 kΩ, -40 °C < T < 125 °C
70
100
Isink
Iout
Isource
ICC
Supply current
(per channel, Vout = VCC/2,
RL > 1 MΩ)
pA
95
Common mode rejection ratio
CMR = 20 log (ΔVic/ΔVio)
(Vic = -0.1 V to VCC - 1.5 V,
Vout = VCC/2, RL > 1 MΩ)
VOL
μV/°C
---------------------------
1.6
T = 25 °C
mV
μV
month
Long-term input offset voltage
drift
ΔVio
μV
78
dB
Vout = VCC, T = 25 °C
40
Vout = VCC, -40 °C < T < 125 °C
35
Vout = 0 V, T = 25 °C
30
Vout = 0 V, -40 °C < T < 125 °C
25
T = 25 °C
-40 °C < T < 125 °C
DocID023274 Rev 4
90
mV
92
mA
90
250
360
400
µA
9/28
28
Electrical characteristics
TSX56x, TSX56xA
Table 6. Electrical characteristics at VCC+ = +16 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 °C, and
RL = 10 kΩ connected to VCC/2 (unless otherwise specified) (continued)
Symbol
Parameter
Conditions
Min.
Typ.
750
900
Max.
Unit
AC performance
GBP
Gain bandwidth product
Fu
Unity gain frequency
Φm
Phase margin
Gm
Gain margin
SR
Slew rate
∫ en
Low-frequency peak-to-peak
input noise
en
THD+N
RL = 10 kΩ, CL = 100 pF
kHz
55
Degree
9
dB
RL = 10 kΩ, CL = 100 pF,
Vout = 0.5 V to VCC - 0.5 V
1.1
V/μs
Bandwidth: f = 0.1 to 10 Hz
15
µVpp
48
27
nV
-----------Hz
0.0005
%
Equivalent input noise voltage f = 1 kHz
density
f = 10 kHz
Total harmonic distortion +
noise
750
Follower configuration, fin = 1 kHz,
RL = 100 kΩ, Vicm = (VCC - 1.5 V)/2,
BW = 22 kHz, Vout = 5 Vpp
1. See Section 4.3: Input offset voltage drift over temperature on page 15.
2. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.
3. Guaranteed by design.
10/28
DocID023274 Rev 4
TSX56x, TSX56xA
Electrical characteristics
Figure 3. Input offset voltage distribution
at VCC = 16 V and Vicm = 8 V
Figure 2. Supply current vs. supply voltage at
Vicm = VCC/2
Figure 4. Input offset voltage temperature
Figure 5. Input offset voltage vs. input common
coefficient distribution at VCC = 16 V, Vicm = 8 V
mode voltage at VCC = 12 V
Figure 6. Input offset voltage vs. temperature at VCC = 16 V
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9&& 99LFP 9
$0
DocID023274 Rev 4
11/28
28
Electrical characteristics
TSX56x, TSX56xA
Figure 7. Output current vs. output voltage
at VCC = 3.3 V
Figure 8. Output current vs. output voltage
at VCC = 5 V
Figure 9. Output current vs. output voltage
at VCC = 16 V
Figure 10. Bode diagram at VCC = 3.3 V
Figure 11. Bode diagram at VCC = 5 V
Figure 12. Bode diagram at VCC = 16 V
12/28
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TSX56x, TSX56xA
Electrical characteristics
Figure 13. Phase margin vs. capacitive load
at VCC = 12 V
Figure 14. GBP vs. input common mode voltage
at VCC = 12 V
Figure 15. Avd vs. input common mode voltage
at VCC = 12 V
Figure 16. Slew rate vs. supply voltage
Figure 17. Noise vs. frequency at VCC = 3.3 V
Figure 18. Noise vs. frequency at VCC = 5 V
DocID023274 Rev 4
13/28
28
Electrical characteristics
TSX56x, TSX56xA
Figure 19. Noise vs. frequency at VCC = 16 V
Figure 20. Distortion + noise vs. output voltage
amplitude
Figure 21. Distortion + noise vs. amplitude
at Vicm = VCC/2 and VCC = 12 V
Figure 22. Distortion + noise vs. frequency
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DocID023274 Rev 4
TSX56x, TSX56xA
Application information
4
Application information
4.1
Operating voltages
The amplifiers of the TSX56x and TSX56xA series can operate from 3 V to 16 V. Their
parameters are fully specified at 3.3 V, 5 V and 16 V power supplies. However, the
parameters are very stable in the full VCC range. Additionally, the main specifications are
guaranteed in extended temperature ranges from -40 to +125 ° C.
4.2
Rail-to-rail input
The TSX56x and TSX56xA devices are built with two complementary PMOS and NMOS
input differential pairs. The devices have a rail-to-rail input, and the input common mode
range is extended from VCC- - 0.1 V to VCC+ + 0.1 V.
However, the performance of these devices is clearly optimized for the PMOS differential
pairs (which means from VCC- - 0.1 V to VCC+ - 1.5 V).
Beyond VCC+ - 1.5 V, the operational amplifiers are still functional but with degraded
performance, as can be observed in the electrical characteristics section of this datasheet
(mainly Vio and GBP). These performances are suitable for a number of applications
needing to be rail-to-rail.
The devices are designed to prevent phase reversal.
4.3
Input offset voltage drift over temperature
The maximum input voltage drift over the temperature variation is defined as the offset
variation related to the offset value measured at 25 °C. The operational amplifier is one of
the main circuits of the signal conditioning chain, and the amplifier input offset is a major
contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated
during production at application level. The maximum input voltage drift over temperature
enables the system designer to anticipate the effects of temperature variations.
The maximum input voltage drift over temperature is computed in Equation 1.
Equation 1
ΔV io
V io ( T ) – V io ( 25° C )
------------ = max -------------------------------------------------ΔT
T – 25° C
with T = -40 °C and 125 °C.
The datasheet maximum value is guaranteed by measurement on a representative sample
size ensuring a Cpk (process capability index) greater than 2.
DocID023274 Rev 4
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28
Application information
4.4
TSX56x, TSX56xA
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
•
Voltage acceleration, by changing the applied voltage
•
Temperature acceleration, by changing the die temperature (below the maximum
junction temperature allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2.
Equation 2
A FV = e
β ⋅ ( VS – VU )
Where:
AFV is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3.
Equation 3
A FT = e
Ea ⎛ 1
1
------ ⋅ ------ – ------⎞
⎝ T U T S⎠
k
Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate
k is the Boltzmann constant (8.6173 x 10-5 eV.K-1)
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die under temperature stress (K)
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and
the temperature acceleration factor (Equation 4).
Equation 4
A F = A FT × A FV
AF is calculated using the temperature and voltage defined in the mission profile of the
product. The AF value can then be used in Equation 5 to calculate the number of months of
use equivalent to 1000 hours of reliable stress duration.
16/28
DocID023274 Rev 4
TSX56x, TSX56xA
Application information
Equation 5
Months = A F × 1000 h × 12 months ⁄ ( 24 h × 365.25 days )
To evaluate the op-amp reliability, a follower stress condition is used where VCC is defined
as a function of the maximum operating voltage and the absolute maximum rating (as
recommended by JEDEC rules).
The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at
different measurement conditions (see Equation 6).
Equation 6
V CC = maxV op with V icm = V CC ⁄ 2
The long term drift parameter (ΔVio), estimating the reliability performance of the product, is
obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the
calculated number of months (Equation 7).
Equation 7
V io drift
ΔV io = -----------------------------( months )
where Vio drift is the measured drift value in the specified test conditions after 1000 h stress
duration.
4.5
PCB layouts
For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible
to the power supply pins.
4.6
Macromodel
Accurate macromodels of the TSX56x, TSX56xA devices are available on the
STMicroelectronics’ website at www.st.com. These models are a trade-off between
accuracy and complexity (that is, time simulation) of the TSX56x and TSX56xA operational
amplifiers. They emulate the nominal performance of a typical device within the specified
operating conditions mentioned in the datasheet. They also help to validate a design
approach and to select the right operational amplifier, but they do not replace on-board
measurements.
DocID023274 Rev 4
17/28
28
Package information
5
TSX56x, TSX56xA
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
18/28
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TSX56x, TSX56xA
5.1
Package information
SOT23-5 package information
Figure 23. SOT23-5 package mechanical drawing
Table 7. SOT23-5 package mechanical data
Dimensions
Ref.
A
Millimeters
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
0.90
1.20
1.45
0.035
0.047
0.057
A1
0.15
0.006
A2
0.90
1.05
1.30
0.035
0.041
0.051
B
0.35
0.40
0.50
0.013
0.015
0.019
C
0.09
0.15
0.20
0.003
0.006
0.008
D
2.80
2.90
3.00
0.110
0.114
0.118
D1
1.90
0.075
e
0.95
0.037
E
2.60
2.80
3.00
0.102
0.110
0.118
F
1.50
1.60
1.75
0.059
0.063
0.069
L
0.10
0.35
0.60
0.004
0.013
0.023
K
0°
10 °
0°
DocID023274 Rev 4
10 °
19/28
28
Package information
5.2
TSX56x, TSX56xA
DFN8 2x2 package information
Figure 24. DFN8 2x2 package mechanical drawing
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Table 8. DFN8 2x2 package mechanical data
Dimensions
Ref.
Inches
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.70
0.75
0.80
0.028
0.030
0.031
A1
0.00
0.02
0.05
0.000
0.001
0.002
b
0.15
0.20
0.25
0.006
0.008
0.010
D
2.00
0.079
E
2.00
0.079
e
0.50
0.020
L
N
20/28
Millimeters
0.045
0.55
0.65
8
DocID023274 Rev 4
0.018
0.022
8
0.026
TSX56x, TSX56xA
5.3
Package information
MiniSO8 package information
Figure 25. MiniSO8 package mechanical drawing
Table 9. MiniSO8 package mechanical data
Dimensions
Symbol
Millimeters
Min.
Typ.
A
Inches
Max.
Min.
Typ.
1.10
A1
0
A2
0.75
b
Max.
0.043
0.15
0
0.95
0.030
0.22
0.40
0.009
0.016
c
0.08
0.23
0.003
0.009
D
2.80
3.00
3.20
0.11
0.118
0.126
E
4.65
4.90
5.15
0.183
0.193
0.203
E1
2.80
3.00
3.10
0.11
0.118
0.122
e
L
0.85
0.65
0.40
0.60
0.006
0.033
0.026
0.80
0.016
0.024
L1
0.95
0.037
L2
0.25
0.010
k
ccc
0°
0.037
8°
0.10
DocID023274 Rev 4
0°
0.031
8°
0.004
21/28
28
Package information
5.4
TSX56x, TSX56xA
SO8 package information
Figure 26. SO8 package mechanical drawing
Table 10. SO8 package mechanical data
Dimensions
Ref.
Millimeters
Min.
Typ.
A
Max.
Min.
Typ.
1.75
0.25
Max.
0.069
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.010
D
4.80
4.90
5.00
0.189
0.193
0.197
E
5.80
6.00
6.20
0.228
0.236
0.244
E1
3.80
3.90
4.00
0.150
0.154
0.157
e
0.004
0.010
0.049
1.27
0.050
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
L1
k
ccc
22/28
Inches
1.04
0
0.040
8°
0.10
DocID023274 Rev 4
1°
8°
0.004
TSX56x, TSX56xA
QFN16 3x3 package information
Figure 27. QFN16 3x3 package mechanical drawing
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5.5
Package information
6($7,1*
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DocID023274 Rev 4
23/28
28
Package information
TSX56x, TSX56xA
Table 11. QFN16 3x3 package mechanical data
Dimensions
Ref.
Millimeters
Min.
Max.
Min.
Typ.
Max.
A
0.50
0.65
0.020
0.026
A1
0
0.05
0
0.002
b
0.18
0.30
0.007
0.25
0.010
D
3.00
0.118
E
3.00
0.118
e
0.50
0.020
L
24/28
Typ.
Inches
0.30
0.50
0.012
0.012
0.020
aaa
0.15
0.006
bbb
0.10
0.004
ccc
0.10
0.004
ddd
0.05
0.002
eee
0.08
0.003
DocID023274 Rev 4
TSX56x, TSX56xA
5.6
Package information
TSSOP14 package information
Figure 28. TSSOP14 package mechanical drawing
Table 12. TSSOP14 package mechanical data
Dimensions
Symbol
Millimeters
Min.
Typ.
A
Inches
Max.
Min.
Typ.
1.20
A1
0.05
A2
0.80
b
Max.
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0089
D
4.90
5.00
5.10
0.193
0.197
0.201
E
6.20
6.40
6.60
0.244
0.252
0.260
E1
4.30
4.40
4.50
0.169
0.173
0.176
e
L
0.65
0.45
L1
k
aaa
1.00
0.60
0.0256 BSC
0.75
1.00
0°
8°
0°
0.10
0.018
DocID023274 Rev 4
8°
0.024
0.030
25/28
28
Ordering information
6
TSX56x, TSX56xA
Ordering information
Table 13. Order codes
Order code
Temperature range
TSX561ILT
Channel
number
Package
1
SOT23-5
TSX562IQ2T
DFN8 2 x 2
TSX562IST
-40 to 125 °C
TSX562IDT
TSX564IQ4T
2
4
TSX564IPT
TSX561IYLT(1)
(1)
TSX562IYST
TSX562IYDT(2)
1
-40 to 125 °C
automotive grade
(1)
2
TSX562I
QFN16 3 x 3
K23
TSSOP14
TSX564I
SOT23-5
SO8
TSX561AILT
1
SOT23-5
-40 to 125 °C
TSX564AIPT
(1)
TSX562AIYST
(1)
TSX562AIYDT(2)
TSX564AIYPT(1)
-40 to 125 °C
automotive grade
2
K116
MiniSO8
TSSOP14
TSX562AIDT
K23
SO8
4
TSX562AIST
Marking
MiniSO8
TSX564IYPT
TSX561AIYLT
Packaging
MiniSO8
Tape and reel
TSX562Y
TSX564IY
K117
SO8
TSX562AI
4
TSSOP14
TSX564AI
1
SOT23-5
2
4
MiniSO8
K118
SO8
TSX562AY
TSSOP14
TSX564AIY
1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001
and Q 002 or equivalent.
2. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC
Q001 and Q 002 or equivalent are ongoing.
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TSX56x, TSX56xA
7
Revision history
Revision history
Table 14. Document revision history
Date
Revision
06-Jun-2012
1
Initial release.
2
Added TSX562, TSX564, TSX562A, and TSX564A devices.
Updated Features, Description, Figure 1, Table 1 (added DFN8,
MiniSO8, QFN16, and TSSOP14 package).
Updated Table 1 (updated ESD MM values).
Updated Table 4 and Table 5 (added footnotes), Section 5 (added
Figure 24 to Figure 28 and Table 8 to Table 12), Table 13 (added dual
and quad devices).
Minor corrections throughout document.
3
Replaced the silhouette, pinout, package diagram, and mechanical
data of the DFN8 2x2 and QFN16 3x3 packages.
Added Benefits and Related products.
Table 1: updated Rthja values and added Rthjc values for DFN8 2x2 and
QFN16 3x3.
Updated Section 4.3, Section 4.4, and Section 4.6
Replaced Figure 23: SOT23-5 package mechanical drawing and
Table 7: SOT23-5 package mechanical data.
4
Added SO8 package for dual version TSX562 and TSX562A.
Table 2: updated for SO8 package
Table 13: added order codes TSX562IDT, TSX562IYDT, TSX562AIDT,
TSX562AIYDT; updated automotive grade status.
18-Sep-2012
23-May-2013
09-Aug-2013
Changes
DocID023274 Rev 4
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28
TSX56x, TSX56xA
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