AKM AK4524

ASAHI KASEI
[AK4524]
AK4524
24Bit 96kHz Audio CODEC
GENERAL DESCRIPTION
The AK4524 is a high performance 24bit CODEC for the 96kHz recording system. The ADC has an
Enhanced Dual Bit architecture with wide dynamic range. The DAC uses the new developed Advanced
Multi Bit architecture and achieves low outband noise and high jitter tolerance by use of SCF (switched
capacitor filter) techniques. The AK4524 has an input PGA and is well suited MD, DVTR system and
musical instruments.
FEATURES
· 24bit 2ch ADC
- 64x Oversampling
- Single-End Inputs
- S/(N+D): 90dB
- Dynamic Range, S/N: 100dB
- Digital HPF for offset cancellation
- Input PGA with +18dB gain & 0.5dB step
- Input DATT with -72dB att
- I/F format: MSB justified or I2S
· 24bit 2ch DAC
- 128x Oversampling
- 24bit 8 times Digital Filter
Ripple: ±0.005dB, Attenuation: 75dB
- SCF
- Differential Outputs
- S/(N+D): 94dB
- Dynamic Range, S/N: 110dB
- De-emphasis for 32kHz, 44.1kHz, 48kHz sampling
- Output DATT with -72dB att
- Soft Mute
- I/F format: MSB justified, LSB justified or I2S
· High Jitter Tolerance
· 3-wire Serial Interface for Volume Control
· Master Clock
- X’tal Oscillating Circuit
- 256fs/384fs/512fs/768fs/1024fs
· Master Mode/Slave Mode
· 5V operation
· 3V Power Supply Pin for 3V I/F
· Small 28pin VSOP package
M0050-E-01
1999/5
-1-
ASAHI KASEI
[AK4524]
n Block Diagram
VD
VT
DGND
PD
AINL
ADC
AINR
HPF
DATT
Audio I/F
Controller
VCOM
AOUTL+
AOUTLAOUTR+
AOUTRVREF
VA
AGND
DAC
Control Register I/F
CS
CCLK
CDTI
LRCK
BICK
SDTO
SDTI
M/ S
DATT
SMUTE
Clock Gen. & Divider
CIF
CLKO XTO
XTI
XTALE
Block Diagram
M0050-E-01
1999/5
-2-
ASAHI KASEI
[AK4524]
n Ordering Guide
AK4524VF
AKD4524
-10~+70°C
Evaluation Board
28pin VSOP (0.65mm pitch)
n Pin Layout
VCOM
1
28
AOUTR+
AINR
2
27
AOUTR-
AINL
3
26
AOUTL+
VREF
4
25
AOUTL-
AGND
5
24
DGND
VA
6
23
VD
22
VT
(Internal pull down) TEST
AK4524
Top
View
7
XTO
8
21
CLKO
XTI
9
20
M/ S
XTALE
10
19
PD
LRCK
11
18
CIF
BICK
12
17
CS
SDTO
13
16
CCLK
SDTI
14
15
CDTI
M0050-E-01
1999/5
-3-
ASAHI KASEI
[AK4524]
PIN/FUNCTION
No.
Pin Name
I/O
1
VCOM
O
2
3
AINR
AINL
I
I
4
VREF
I
5
6
7
8
9
AGND
VA
TEST
XTO
XTI
I
O
I
10
XTALE
I
11
12
13
14
15
16
17
LRCK
BICK
SDTO
SDTI
CDTI
CCLK
CS
18
CIF
I
19
PD
I
20
M/ S
I
21
22
23
24
25
26
27
28
CLKO
VT
VD
DGND
AOUTLAOUTL+
AOUTRAOUTR+
O
O
O
O
O
I/O
I/O
O
I
I
I
I
Function
Common Voltage Output Pin, VA/2
Bias voltage of ADC inputs and DAC outputs.
Rch Analog Input Pin
Lch Analog Input Pin
Voltage Reference Input Pin, VA
Used as a voltage reference by ADC & DAC. VREF is connected externally to
filtered VA.
Analog Ground Pin
Analog Power Supply Pin, 4.75 ~ 5.25V
Test Pin
(Internal pull-down pin)
X’tal Output Pin
X’tal/Master Clock Input Pin
X’tal Osc Enable Pin
“H”: Enable, “L”: Disable
Input/Output Channel Clock Pin
Audio Serial Data Clock Pin
Audio Serial Data Output Pin
Audio Serial Data Input Pin
Control Data Input Pin
Control Data Clock Pin
Chip Select Pin
Control Data I/F Format Pin
“H”: CS falling trigger, “L”: CS rising trigger
Power-Down Mode Pin
“H”: Power up, “L”: Power down, reset and initialize the control register.
Master/Slave Mode Pin
“H”: Master mode, “L”: Slave mode
Master Clock Output Pin
Output Buffer Power Supply Pin, 2.7 ~ 5.25V
Digital Power Supply Pin, 4.75 ~ 5.25V
Digital Ground Pin
Lch Negative Analog Output Pin
Lch Positive Analog Output Pin
Rch Negative Analog Output Pin
Rch Positive Analog Output Pin
Note: All input pins except pull-down pins should not be left floating.
M0050-E-01
1999/5
-4-
ASAHI KASEI
[AK4524]
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND=0V; Note 1)
Parameter
Power Supplies:
Analog
Digital
Output Buffer
VD-VA
Input Current, Any Pin Except Supplies
Analog Input Voltage
Digital Input Voltage
Ambient Temperature (powered applied)
Storage Temperature
Symbol
VA
VD
VT
VDA
IIN
VINA
VIND
Ta
Tstg
min
-0.3
-0.3
-0.3
-0.3
-0.3
-10
-65
max
6.0
6.0
6.0
0.3
±10
VA+0.3
VA+0.3
70
150
Units
V
V
V
V
mA
V
V
°C
°C
Note:1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND=0V; Note 1)
Parameter
Power Supplies
Analog
(Note 2) Digital
Output Buffer
Voltage Reference
Symbol
VA
VD
VT
VREF
min
4.75
4.75
2.7
3.0
typ
5.0
5.0
3.0
-
max
5.25
VA
VD
VA
Units
V
V
V
V
Note:1. All voltages with respect to ground.
2. VA and VD should be powered at the same time or VA should be powered earlier than VD.
The power up sequence between VA and VT, or VD and VT is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
M0050-E-01
1999/5
-5-
ASAHI KASEI
[AK4524]
ANALOG CHARACTERISTICS
(Ta=25°C; VA, VD, VT=5.0V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency =1kHz; 24bit Data;
Measurement frequency = 10Hz ~ 20kHz at fs=44.1kHz, 10Hz ~ 40kHz at fs=96kHz; unless otherwise specified)
Parameter
min
typ
max
Units
Input PGA Characteristics:
Input Voltage
(Note 3)
2.7
2.9
3.1
Vpp
Input Resistance
5
10
15
kW
Step Size
0.2
0.5
0.8
dB
Gain Control Range
0
18
dB
ADC Analog Input Characteristics: IPGA=0dB
Resolution
24
Bits
S/(N+D)
(-0.5dBFS)
fs=44.1kHz
84
90
dB
fs=96kHz
80
88
dB
DR
S/N
(-60dBFS)
fs=44.1kHz, A-weighted
fs=96kHz
fs=44.1kHz, A-weighted
fs=96kHz
Interchannel Isolation
Interchannel Gain Mismatch
Gain Drift
Power Supply Rejection
(Note 4)
DAC Analog Output Characteristics:
Resolution
S/(N+D)
(0dBFS)
fs=44.1kHz
fs=96kHz
DR
(-60dBFS)
fs=44.1kHz, A-weighted
fs=96kHz
S/N
fs=44.1kHz, A-weighted
fs=96kHz
Interchannel Isolation
Interchannel Gain Mismatch
Gain Drift
Output Voltage
(Note 5)
Load Resistance
(In case of AC load)
Output Current
(In case of AC load)
Load Capacitance
94
88
94
88
90
100
96
100
96
105
0.2
20
50
0.5
24
88
85
104
96
104
96
100
5.0
1
94
93
110
104
110
104
110
0.2
20
5.4
0.5
5.8
1.5
25
dB
dB
dB
dB
dB
dB
ppm/°C
dB
Bits
dB
dB
dB
dB
dB
dB
dB
dB
ppm/°C
Vpp
kW
mA
pF
Note: 3. Full scale (0dB) of the input voltage at PGA=0dB.
This voltage is proportional to VREF. Vin=0.58 x VREF.
4. PSR is applied to VA, VD, VT with 1kHz, 50mVpp. VREF pin is held a constant voltage.
5. Full scale (0dB) of the output voltage when summing the differential outputs, AOUT+/- by unity gain.
This voltage is proportional to VREF. Vout=1.08 x VREF x Gain.
M0050-E-01
1999/5
-6-
ASAHI KASEI
[AK4524]
Parameter
Power Supplies
min
typ
max
Units
30
16
24
45
24
36
mA
mA
mA
10
10
100
100
uA
uA
Power Supply Current
Normal Operation ( PD = “H”)
VA
VD+VT
(fs=44.1kHz)
(fs=96kHz)
(Note 6)
Power-down mode ( PD = “L”)
VA
VD+VT
Note: 6. XTALE=”L” and all digital input pins are held VD or DGND.
FILTER CHARACTERISTICS
(Ta=25°C; VA, VD=4.75 ~ 5.25V; VT=2.7 ~ 5.25V; fs=44.1kHz; DEM=OFF)
Parameter
Symbol
min
ADC Digital Filter (Decimation LPF):
PB
0
Passband
(Note 7)
-0.005dB
-0.02dB
-0.06dB
-6.0dB
Stopband
SB
24.34
Passband Ripple
PR
Stopband Attenuation
SA
80
Group Delay
(Note 8)
GD
Group Delay Distortion
DGD
ADC Digital Filter (HPF):
Frequency Response (Note 5) -3dB
FR
-0.5dB
-0.1dB
DAC Digital Filter:
Passband
(Note 7)
-0.01dB
PB
0
-6.0dB
Stopband
SB
24.1
Passband Ripple
PR
Stopband Attenuation
SA
75
Group Delay
(Note 8)
GD
DAC Digital Filter + SCF:
Frequency Response:
FR
0 ~ 20.0kHz
~ 40kHz (Note 9)
typ
max
Units
20.02
22.20
22.05
19.76
-
31
0
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
us
0.9
2.7
6.0
Hz
Hz
Hz
±0.005
30
kHz
kHz
kHz
dB
dB
1/fs
±0.2
±0.3
dB
dB
22.05
20.0
±0.005
Note: 7. The passband and stopband frequencies scale with fs. For example, 20.02kHz at -0.02dB is 0.454 x fs.
The reference frequency of these responses is 1kHz.
8. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to
setting the 24bit data of both channels to the output register for ADC.
For DAC, this time is from setting the 24bit data of both channels on input register to the output of analog
signal.
9. fs=96kHz.
M0050-E-01
1999/5
-7-
ASAHI KASEI
[AK4524]
DIGITAL CHARACTERISTICS
(Ta=25°C; VA, VD=4.75 ~ 5.25V; VT=2.7 ~ 5.25V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout=-100uA) (Note 10)
Low-Level Output Voltage (Iout=100uA)
Input Leakage Current
Symbol
VIH
VIL
VOH
VOL
Iin
min
2.2
2.7 / VT-0.5
-
typ
-
Max
0.8
0.5
±10
Units
V
V
V
V
uA
Note: 10. Min value is lower voltage of 2.7V or VT-0.4V.
SWITCHING CHARACTERISTICS
(Ta=25°C; VA, VD=4.75 ~ 5.25V, VT=2.7 ~ 5.25V; CL=20pF)
Parameter
Symbol
Master Clock Timing
Crystal Resonator
External Clock
CLKO Output
(X’tal mode)
min
typ
max
Units
Frequency
Frequency
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
11.2896
8.192
0.4/fCLK
0.4/fCLK
24.576
49.152
MHz
MHz
ns
ns
Frequency
Duty Cycle
fMCK
dMCK
11.2896
35
24.576
65
MHz
%
fsn
fsd
fsq
32
64
128
45
48
96
192
55
kHz
kHz
kHz
%
%
LRCK Frequency
Normal Speed Mode (DFS0=”0”, DFS1=”0”)
Double Speed Mode (DFS0=”1”, DFS1=”0”)
Quad Speed Mode (DFS0=”0”, DFS1=”1”)
Duty Cycle
Slave mode
Master mode
Audio Interface Timing
Slave mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “­”
(Note 11)
BICK “­” to LRCK Edge
(Note 11)
LRCK to SDTO (MSB) (Except I2S mode)
BICK “¯” to SDTO
SDTI Hold Time
SDTI Setup Time
Master mode
BICK Frequency
BICK Duty
BICK “¯” to LRCK
BICK “¯” to SDTO
SDTI Hold Time
SDTI Setup Time
50
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
81
33
33
20
20
40
40
20
20
64fs
50
-20
-20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
M0050-E-01
1999/5
-8-
ASAHI KASEI
Parameter
Control Interface Timing
CIF=”0”
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CS “H” Time
CS “L” Time
CS “­” to CCLK “­”
CCLK “­” to CS “­”
CIF=”1”
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CS “H” Time
CS “L” Time
CS “¯” to CCLK “­”
CCLK “­” to CS “¯”
Reset Timing
(Note 12)
PD Pulse Width
RSTAD “­” to SDTO valid (Note 13)
[AK4524]
Symbol
min
typ
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSW
tCSS
tCSH
200
80
80
40
40
150
150
150
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSW
tCSS
tCSH
200
80
80
40
40
150
150
150
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPD
tPDV
150
516
max
Units
ns
1/fs
Note:12. The AK4524 can be reset by bringing PD “L”.
13. These cycles are the number of LRCK rising from RSTAD bit.
M0050-E-01
1999/5
-9-
ASAHI KASEI
[AK4524]
n Timing Diagram
1/fCLK
MCLK
1.5V
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
CLKO
1.5V
tH
tL
dMCK=tH/(tH+tL) or tL/(tH+tL)
Clock Timing
VIH
VIL
LRCK
tBLR
tLRB
VIH
VIL
BICK
tLRS
tBSD
VIH
VIL
SDTO
tSDS
tSDH
VIH
VIL
SDTI
Audio Interface Timing (Slave mode)
M0050-E-01
1999/5
- 10 -
ASAHI KASEI
[AK4524]
VIH
VIL
LRCK
tMBLR
VIH
VIL
BICK
tBSD
VIH
VIL
SDTO
tSDS
tSDH
VIH
VIL
SDTI
Audio Interface Timing (Master mode)
CS(CIF=H)
VIH
VIL
CS(CIF=L)
VIH
VIL
tCCKL tCCKH
tCSS
VIH
VIL
CCLK
tCDS
CDTI
C1
tCDH
C0
R/W
A4
VIH
VIL
WRITE Command Input Timing
tCSW
CS(CIF=H)
VIH
VIL
CS(CIF=L)
VIH
VIL
tCSH
VIH
VIL
CCLK
CDTI
D3
D2
D1
VIH
VIL
D0
WRITE Data Input Timing
tPD
PD
VIL
Power Down & Reset Timing
M0050-E-01
1999/5
- 11 -
ASAHI KASEI
[AK4524]
OPERATION OVERVIEW
n System Clock Input
The master clock (MCLK) can be either a crystal resonator placed across the XTI and XTO pin, or external clock input to
the XTI pin with the XTO pin left floating. The master clock frequency can be selected by CMODE and CKS0-1 (Table 1).
The sampling speed (normal speed mode, double speed mode or four times speed monitor mode) is selected by DFS0-1
(Table 2). The ADC is powered down during four times speed monitor mode. The frequency of the master clock output
(CLKO) is the same as MCLK frequency and the output can be enabled or disabled by XTALE pin. When the CLKO
output is not used externally, it should be disabled.
When using a crystal oscillator, external loading capacitors (between XTI/XTO and DGND) are required.
In slave mode, the LRCK clock input must be synchronized with MCLK, however the phase is not critical. Internal timing
is synchronized to LRCK upon power-up. All external clocks must be present unless PD =”L” or all parts are powered
down by control register, otherwise excessive current may result from abnormal operation of internal dynamic logic. In
master mode, the clocks should be supplied by critical oscillation except for power down or the external clock (MCLK)
should not be stopped.
CMODE
CKS1
CKS0
MCLK
0
0
0
1
1
0
0
1
0
0
0
1
0
0
1
256fsn
512fsn
1024fsn
384fsn
768fsn
at reset
Table 1. Master clock frequency select
* fsn is a sampling rate at normal speed mode.
DFS1
DFS0
0
0
1
1
0
1
0
1
Sampling Rate
fsn
fsd=2 x fsn
fsq=4 x fsn
fsq=4 x fsn
Monitor mode
Normal speed
Double speed
4 times speed (SDTO=”L”)
4 times speed (SDTO=”L”)
Simple Decimation
2 tap filter
at reset
Table 2. Sampling speed
MCLK
256fsn
512fsn
1024fsn
384fsn
768fsn
fsn=44.1kHz
11.2896MHz
22.5792MHz
45.1584MHz
16.9344MHz
33.8688MHz
fsn=48kHz
12.288MHz
24.576MHz
49.152MHz
18.432MHz
36.864MHz
Normal
Double
4 times
256fsn
512fsn
1024fsn
384fsn
768fsn
N/A
256fsd
512fsd
N/A
384fsd
N/A
128fsq
256fsq
N/A
192fsq
Table 3. Master clock frequency
* X’tal mode operates from 11.2896MHz to 24.576MHz.
* The frequency over 24.576MHz supports only external clock mode.
M0050-E-01
1999/5
- 12 -
ASAHI KASEI
[AK4524]
n Audio Serial Interface Format
Five serial modes selected by the DIF0 and DIF1 pins are supported as shown in Table 4. In all modes the serial data has
MSB first, 2’s compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the
rising edge. The interface supports both master mode and slave mode. In master mode, BICK and LRCK are outputs and
the frequency of BICK is fixed to 64fs.
Mode
DIF2
DIF1
DIF0
SDTO
SDTI
LRCK
BICK
0
1
2
3
4
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
24bit, MSB justified
24bit, MSB justified
24bit, MSB justified
24bit, IIS (I2S)
24bit, MSB justified
16bit, LSB justified
20bit, LSB justified
24bit, MSB justified
24bit, IIS (I2S)
24bit, LSB justified
H/L
H/L
H/L
L/H
H/L
³ 32fs
³ 40fs
³ 48fs
³ 48fs
³ 48fs
at reset
Table 4. Audio data format
LRCK
0
1
2
3
9
10
11
12
13
14
15
0
1
2
9
10
11
12
13
14
15
0
1
BICK(32fs)
SDTO(o)
23 22 21
15 14 13 12 11 10
SDTI(i)
15 14 13
7
0
1
2
3
6
17
4
5
18
19
3
2
20
9
8
23 22 21
15 14 13 12 11 10
9
8
23
1
0
15 14 13
7
1
0
15
30
31
0
1
2
3
6
17
5
18
4
19
3
2
20
31
0
1
BICK(64fs)
SDTO(o)
23 22 21
SDTI(i)
7
Don’t Care
6
5
4
3
23 22 21
15 14 13 12 11
2
1
7
Don’t Care
0
6
5
4
3
23
15 14 13 12 11
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
2
1
0
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
12 11 10
Don’t Care
19 18
0
8
23 22
7
1
0
12 11 10
Don’t Care
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
19 18
0
8
23
7
1
0
Rch Data
Figure 2. Mode 1 Timing
M0050-E-01
1999/5
- 13 -
ASAHI KASEI
[AK4524]
LRCK
0
1
2
18
19
20
21
22
23
24
25
0
1
2
18
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
19
20
21
22
23
24
25
0
1
2
3
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
LRCK
0
1
2
8
9
10
20
21
31
0
1
2
8
9
10
20
21
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
16 15 14
Don’t Care
23:MSB, 0:LSB
23 22
0
12 11
23 22
1
0
16 15 14
Don’t Care
Lch Data
23 22
0
12 11
23
1
0
Rch Data
Figure 5. Mode 4 Timing
M0050-E-01
1999/5
- 14 -
ASAHI KASEI
[AK4524]
n Input Volume
The AK4524 includes two channel independent analog volumes (IPGA) with 37 levels, 0.5dB step in front of ADC and
digital volumes (IATT) with 128 levels (including MUTE) after ADC. The control data of both volumes are assigned in the
same register address. When MSB of the register is “1”, the IPGA changes and the IATT changes at MSB “0”.
The IPGA is analog volumes and improves S/N compared with digital volume (Table 5). Level changes only occur during
zero-crossings to minimize switching noise. Zero-crossing detection is performed channel independently. If there is no
zero-crossings, then the level will change after a time-out. The time-out period (To) scales with fs. The periods of 256/fs,
512/fs, 1024/fs and 2048/fs are selectable by ZTM1-0 bits in normal speed mode. If new value is written to the IPGA
register before IPGA changes by zero-crossing or time-out, the previous value becomes invalid. And then the timer
(channel independent) for time-out is reset and the timer restarts for new IPGA value. Zero-crossing detection can be
enabled by ZCEI in the control register.
The IATT is a pseudo-log volume linear-interpolated internally. When changing the level, the transition between ATT
values has 8032 levels and is done by soft changes. Therefore, there is not any switching noise.
fs=44.1kHz, A-weight
0dB
100dB
Input Gain Setting
+6dB
98dB
+18dB
90dB
Table 5. IPGA+ADC S/N
ZTM1
0
0
1
1
ZTM0
0
1
0
1
fsn
256
512
1024
2048
fsd
512
1024
2048
4096
at reset
Table 6. LRCK cycles for timeout period
n Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 0.9Hz at fs=44.1kHz and
also scales with sampling rate (fs).
n Output Volume
The Ak4524 includes digital volumes (OATT) with 128 levels (including MUTE) which have the same architecture as
IATT’s in front of DAC. T he OATT is a pseudo-log volume linear-interpolated internally. When changing the level, the
transition between ATT values has 8032 levels and is done by soft changes. Therefore, there is not any switching noise.
M0050-E-01
1999/5
- 15 -
ASAHI KASEI
[AK4524]
n De-emphasis Filter
The DAC includes the digital de-emphasis filter (tc=50/15us) by IIR filter. This filter corresponds to three frequencies
(32kHz, 44.1kHz, 48kHz). This setting is done via contorl register. This filter is always OFF at double speed and four times
speed modes.
No
0
1
2
3
DEM1
0
0
1
1
DEM0
0
1
0
1
Mode
44.1kHz
OFF
48kHz
32kHz
at reset
Table 7. De-emphasis control (DFS0=DFS1=”0”)
n Soft Mute Operation
Soft mute operation is performed at digital domain. When SMUTE goes “H”, the output signal is attenuated by -¥ during
1024 LRCK cycles. When SMUTE is returned to “L”, the mute is cancelled and the output attenuation gradually changes
to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting the operation, the
attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal source without stopping
the signal transmission.
Soft mute function is independent to output volume and cascade connected between both functions.
SM U T E
1024/fs
0dB
1024/fs
(1)
(3)
Attenuation
-¥
GD
(2)
GD
Figure 6. Soft Mute
Notes:
(1) The output signal is attenuated by -¥ during 1024 LRCK cycles (1024/fs).
(2) Analog output corresponding to digital input has the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.
M0050-E-01
1999/5
- 16 -
ASAHI KASEI
[AK4524]
n Power Down & Reset
The ADC and DAC of AK4524 are placed in the power-down mode by bringing a power down pin, PD “L” and each
digital filter is also reset at the same time. The internal register values are initialized by PD “L”. This reset should always
be done after power-up. And then as both control registers of ADC and DAC go reset state (RSTAD=RSTDA=”0”), each
register sholud be cancelled after doing the needed setting. In case of the ADC, an analog initialization cycle starts after
exiting the power-down or reset state. Therefore, the output data, SDTO becomes available after 516 cycles of LRCK
clock. This initialization cycle does not affect the DAC operation. Power down mode can be also controlled by the registers
(PWAD, PWDA).
Power Supply
PD pin
RSTAD(register)
RSTDA(register)
PWAD(register)
PWDA(register)
PWVR(register)
ADC Internal State
PD
IATT
Reset INITA
00H
SDTO
DAC Internal State
External clocks
in slave mode
FI
Normal
“0”
XXH
FI
Output
Normal
“0”
*
INITA
00H 00H ® XXH
Output
00H
AOUT
PD
XXH
Reset
OATT
External Mute
Example
00H ® XXH
“0”
PD
Normal
PD
00H ® XXH
XXH
FI
Output
*
Normal
00H ® XXH
00H
“0”
*
XXH
FI
*
MCLK, LRCK, BICK
The clocks can be stopped.
· INITA:
· PD:
· XXH:
· FI:
· AOUT:
Initializing period of ADC analog section (516/fs).
Power down state. The contents of all registers are hold.
The current value in ATT register.
Fade in. After exiting power down and reset state, ATT value fades in.
Some pop noise may occur at “*”.
Figure 7. Reset & Power down sequence
M0050-E-01
1999/5
- 17 -
ASAHI KASEI
[AK4524]
n Relationship between Clock Operation and Power-Down
XTALE pin controls the clock outputs. The operation in slave mode is shown Table 8. Table 9 shows the master mode
operation. When a crystal oscillator is used, XTALE pin is set to “H”. XTALE pin should be “L” at external clock mode.
Slave Mode
XTAL mode
EXT Clock mode
XTALE=L
XTALE=H
PD =H
Inhibit
Inhibit
Normal operation
XTI = MCLK in
XTO = L
CLKO = L
LRCK = Input
BICK = Input
Shut off
XTI = MCLK in
XTO = L
CLKO = L
LRCK = Input
BICK = Input
PD =L
PD =H
Normal operation
XTAL = Oscillation
CLKO = Output
LRCK = Input
BICK = Input
Inhibit
PD =L
Power down
XTAL = Oscillation
CLKO = Output
LRCK = Input
BICK = Input
Inhibit
Table 8. Clock operation at slave mode (M/ S = L)
Master Mode
XTAL mode
EXT Clock mode
XTALE=L
XTALE=H
PD =H
Inhibit
Inhibit
Normal operation
XTI = MCLK in
XTO = L
CLKO = L
LRCK = Output
BICK = Output
Shut off
XTI = MCLK in
XTO = L
CLKO = L
LRCK = H
BICK = L
PD =L
PD =H
Normal operation
XTAL = Oscillation
CLKO = Output
LRCK = Output
BICK = Output
Inhibit
PD =L
Power down
XTAL = Oscillation
CLKO = Output
LRCK = H
BICK = L
Inhibit
Table 9. Clock operation at master mode (M/ S = H)
M0050-E-01
1999/5
- 18 -
ASAHI KASEI
[AK4524]
n Serial Control Interface
The internal registers are written by the 3 wire uP interface pins: CS, CCLK, CDTI. The data on this interface consists of
Chip address (2bits, C0/1) Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits).
Address and data is clocked in on the rising edge of CCLK. Data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CS. The operation of the control serial port may be completely asynchronous with the audio
sample rate. The maximum clock speed of the CCLK is 5MHz. The CS should be “H” or “L” if no access. The chip address
is fixed to “10”. Writing is invalid for the access to the chip address except for “10”. PD = “L” resets the registers to their
default values.
CS (CIF=1)
CS (CIF=0)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “10”)
READ/WRITE (Fixed to “1”:WRITE)
Register Address
Control data
Figure 8. Control I/F Timing
* READ command is not supported.
n Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
Register Name
Power Down Control
Reset Control
Clock and Format Control
Deem and Volume Control
Lch IPGA Control
Rch IPGA Control
Lch ATT Control
Rch ATT Control
D7
0
0
DIF2
SMUTE
IPGL7
IPGR7
0
0
D6
0
0
DIF1
0
IPGL6
IPGR6
ATTL6
ATTR6
D5
0
0
DIF0
0
IPGL5
IPGR5
ATTL5
ATTR5
D4
0
0
CMODE
ZCEI
IPGL4
IPGR4
ATTL4
ATTR4
D3
0
0
CKS1
ZTM1
IPGL3
IPGR3
ATTL3
ATTR3
D2
PWVR
0
CKS0
ZTM0
IPGL2
IPGR2
ATTL2
ATTR2
D1
PWAD
RSTAD
DFS1
DEM1
IPGL1
IPGR1
ATTL1
ATTR1
D0
PEDA
RSTDA
DFS0
DEM0
IPGL0
IPGR0
ATTL0
ATTR0
Note: For addresses from 08H to 1FH, data is not written.
PD = “L” resets the registers to their default values.
M0050-E-01
1999/5
- 19 -
ASAHI KASEI
[AK4524]
n Control Register Setup Sequence
When PD pin goes “L” to “H” upon power-up etc., the AK4524 should operate by the next sequence. In this case, all
control registers are set to initial values and the AK4524 is in the reset state.
(1) Set the clock mode and the audio data interface mode.
(2) Cancel the reset state by setting RSTAD or RSTDA to “1”. Refer to Reset Contorl Register (01H).
(3) ADC outputs and DAC outputs should be muted externally until cancelling each reset state. In master mode, there is
a possibility the frequency and duty of LRCK and BICK outputs become an abnormal state.
The clock mode should be changed after setting RSTAD and RSTDA to “0”. At that time, ADC outputs and DAC outputs
should be muted externally. In master mode, there is a possibility the frequency and duty of LRCK and BICK outputs
become an abnormal state.
n Register Definitions
Addr
00H
Register Name
Power Down Control
RESET
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
PWVR
1
D1
PWAD
1
D0
PWDA
1
PWDA: DAC power down
0: Power down
1: Power up
Only DAC section is powered down by “0” and then the AOUTs go Hi-Z immediately. The OATTs also go
“00H”. But the contents of all register are not initialized and enabled to write to the registers. After exiting
the power down mode, the OATTs fade in the setting value of the control register (06H & 07H). The analog
outputs should be muted externally as some pop noise may occur when entering to and exiting from this
mode.
PWAD: ADC power down
0: Power down
1: Power up
Only ADC section is powered down by “0” and then the SDTO goes “L” immediately. The IPGAs also go
“00H”. But the contents of all register are not initialized and enabled to write to the registers. After exiting
the power down mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time,
ADCs output “0” during first 516 LRCK cycles.
PWVR: Vref power down
0: Power down
1: Power up
All sections are powered down by “0” and then both ADC and DAC do not operate. The contents of all
register are not initialized and enabled to write to the registers. When PWAD and PWDA go “0” and PWVR
goes “1”, only VREF section can be powered up.
M0050-E-01
1999/5
- 20 -
ASAHI KASEI
Addr
01H
Register Name
Reset Control
RESET
[AK4524]
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
RSTAD
0
D0
RSTDA
0
RSTDA: DAC reset
0: Reset
1: Normal Operation
The internal timing is reset by “0” and then the AOUTs go VCOM voltage immediately. The OATTs also
go “00H”. But the contents of all register are not initialized and enabled to write to the registers. After
exiting the power down mode, the OATTs fade in the setting value of the control register (06H & 07H). The
analog outputs should be muted externally as some pop noise may occur when entering to and exiting from
this mode.
RSTDA: ADC reset
0: Reset
1: Normal Operation
The internal timing is reset by “0” and then SDTO goes “L” immediately. The IPGAs also go “00H”. But
the contents of all register are not initialized and enabled to write to the register. After exiting the power
down mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time, ADCs
output “0” during first 516 LRCK cycles.
Addr
02H
Register Name
Clock and Format Control
RESET
D7
DIF2
0
D6
DIF1
1
D5
DIF0
0
D4
CMODE
0
D3
CKS1
0
D2
CKS0
0
D1
DFS1
0
D0
DFS0
0
DFS1-0: Sampling Speed Control (see Table 2)
Initial: Normal speed
CMODE, CKS1-0: Master Clock Frequency Select (see Table 1)
Initial: 256fs
DIF2-0: Audio data interface modes (see Table 4)
000: Mode 0
001: Mode 1
010: Mode 2
011: Mode 3
100: Mode 4
Initial: 24bit MSB justified for both ADC and DAC
M0050-E-01
1999/5
- 21 -
ASAHI KASEI
Addr
03H
Register Name
Deem and Volume Control
RESET
[AK4524]
D7
SMUTE
0
D6
0
0
D5
0
0
D4
ZCEI
1
D3
ZTM1
1
D2
ZTM0
0
D1
DEM1
0
D0
DEM0
1
D2
IPGL2
IPGR2
1
D1
IPGL1
IPGR1
1
D0
IPGL0
IPGR0
1
DEM1-0: De-emphasis response (see Table 7)
00: 44.1kHz
01: OFF
10: 48kHz
11: 32kHz
Initial: OFF
ZTM1-0: Zero crossing time out period select (see Table 6)
Initial: 1024fs
ZCEI: ADC IPGA Zero crossing enable
0: Input PGA gain changes occur immediately
1: Input PGA gain changes occur only on zero-crossing or after timeout.
Initial: 1 (Enable)
SMUTE: DAC Input Soft Mute control
0: Normal operation
1: DAC outputs soft-muted
The soft mute is independent of the output ATT and performed digitally.
Addr
04H
05H
Register Name
Lch IPGA Control
Rch IPGA Control
RESET
D7
IPGL7
IPGR7
0
D6
IPGL6
IPGR6
1
D5
IPGL5
IPGR5
1
D4
IPGL4
IPGR4
1
D3
IPGL3
IPGR3
1
IPGL/R7-0: ADC Input Gain Level
Refer to Table 10
Initial: 7FH (0dB)
Digital ATT with 128 levels operates when writing data of less than 7FH. This ATT is a linear ATT with
8032 levels internally and these levels are assigned to pseudo-log data with 128 levels. The transition
between ATT values has 8032 levels and is done by soft changes. For example, when ATT changes from
127 to 126, the internal ATT value decreases from 8031 to 7775 one by one every fs cycles. It takes 8031
cycles ([email protected]=44.1kHz) from 127 to 0 (Mute).
The IPGAs are set to “00H” when PD pin goes “L”. After returning to “H”, the IPGAs fade in the initial
value, “7FH” by 8031 cycles.
The IPGAs are set to “00H” when PWAD goes “0”. After returning to “1”, the IPGAs fade in the current
value. But the ADCs output “0” during first 516 cycles.
The IPAGs are set to “00H” when RSTAD goes “0”. After returning to “1”, the IPGAs fade in the current
value. But the ADCs output “0” during first 516 cycles.
M0050-E-01
1999/5
- 22 -
ASAHI KASEI
Data
255 - 165
164
163
162
:
130
129
128
127
126
125
:
112
111
110
:
96
95
94
:
79
78
77
:
64
63
62
:
48
47
46
:
32
31
30
:
16
15
14
:
5
4
3
2
1
0
[AK4524]
Internal
(DATT)
8031
7775
7519
:
4191
3999
3871
:
2079
1983
1919
:
1023
975
943
:
495
471
455
:
231
219
211
:
99
93
89
:
33
30
28
:
10
8
6
4
2
0
Gain (dB)
Step width (dB)
+18
+18
+17.5
+17
:
+1.0
+0.5
0
0
-0.28
-0.57
:
-5.65
-6.06
-6.34
:
-11.74
-12.15
-12.43
:
-17.90
-18.32
-18.61
:
-24.20
-24.64
-24.94
:
-30.82
-31.29
-31.61
:
-38.18
-38.73
-39.11
:
-47.73
-48.55
-49.15
:
-58.10
-60.03
-62.53
-66.05
-72.07
MUTE
0.5
0.5
0.5
0.5
0.5
0.5
0.28
0.29
:
0.51
0.41
0.28
:
0.52
0.41
0.28
:
0.53
0.42
0.29
:
0.54
0.43
0.30
:
0.58
0.46
0.32
:
0.67
0.54
0.38
:
0.99
0.83
0.60
:
1.58
1.94
2.50
3.52
6.02
IPGA
Analog volume with 0.5dB step
IATT
External 128 levels are converted to internal
8032 linear levels of DATT. Internal DATT
soft-changes between DATAs.
DATT=2^m x (2 x l + 33) – 33
m: MSB 3-bits of data
l: LSB 4-bits of data
Table 10. IPGA code table
M0050-E-01
1999/5
- 23 -
ASAHI KASEI
Addr
06H
07H
[AK4524]
Register Name
Lch OATT Control
Rch OATT Control
RESET
D7
0
0
0
D6
ATTL6
ATTR6
1
D5
ATTL5
ATTR5
1
D4
ATTL4
ATTR4
1
D3
ATTL3
ATTR3
1
D2
ATTL2
ATTR2
1
D1
ATTL1
ATTR1
1
D0
ATTL0
ATTR0
1
ATTL/R6-0: DAC ATT Level
Refer to Table 11
Initial: 7FH (0dB)
The AK4524 includes digital ATT with 128 levels equivalent to ADC’s.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
ATT (dB)
Step (dB)
127
111
95
79
63
47
31
Step(dB)
ATT(dB)
The OATTs are set to “00H” when PD pin goes “L”. After returning to “H”, the OATTs fade in the initial
value, “7FH” by 8031 cycles.
The OATTs are set to “00H” when PWDA goes “0”. After returning to “1”, the OATTs fade in the current
value.
The OATTs are set to “00H” when RSTDA goes “0”. Afer returning to “1”, the OATTs fade in the current
Value.
15
Input Data(Level)
Figure 9. ATT characteristics
M0050-E-01
1999/5
- 24 -
ASAHI KASEI
Data
127
126
125
:
112
111
110
:
96
95
94
:
79
78
77
:
64
63
62
:
48
47
46
:
32
31
30
:
16
15
14
:
5
4
3
2
1
0
[AK4524]
Internal
(DATT)
8031
7775
7519
:
4191
3999
3871
:
2079
1983
1919
:
1023
975
943
:
495
471
455
:
231
219
211
:
99
93
89
:
33
30
28
:
10
8
6
4
2
0
Gain (dB)
Step width (dB)
0
-0.28
-0.57
:
-5.65
-6.06
-6.34
:
-11.74
-12.15
-12.43
:
-17.90
-18.32
-18.61
:
-24.20
-24.64
-24.94
:
-30.82
-31.29
-31.61
:
-38.18
-38.73
-39.11
:
-47.73
-48.55
-49.15
:
-58.10
-60.03
-62.53
-66.05
-72.07
MUTE
0.28
0.29
:
0.51
0.41
0.28
:
0.52
0.41
0.28
:
0.53
0.42
0.29
:
0.54
0.43
0.30
:
0.58
0.46
0.32
:
0.67
0.54
0.38
:
0.99
0.83
0.60
:
1.58
1.94
2.50
3.52
6.02
OATT
External 128 levels are converted to internal
8032 linear levels of DATT. Internal DATT
soft-changes between DATAs.
DATT=2^m x (2 x l + 33) – 33
m: MSB 3-bits of data
l: LSB 4-bits of data
Table 11. OATT code table
M0050-E-01
1999/5
- 25 -
ASAHI KASEI
[AK4524]
SYSTEM DESIGN
Figure 10 & Figure 11 show the system connection diagram. This is an example which the AK4524 operates at X’tal mode.
In case of external clock mode, please refer to Figure 11. An evaluation board (AKD4524) is available which demonstrates
application circuits, the optimum layout, power supply arrangements and measurement results.
4.75 ~ 5.25V
Analog Supply
0.1u 10u
+
10u +
1
VCOM
AOUTR+ 28
2
AINR
AOUTR-
27
3
AINL
AOUTL+
26
4
VREF
AOUTL-
25
5
AGND
DGND
24
6
VA
VD
23
VT
22
Rch
LPF
Rch Out
Lch
LPF
Lch Out
0.1u
AK4524
7
TEST
8
XTO
CLKO
21
9
XTI
M/ S
20
10 XTALE
PD
19
11 LRCK
CIF
18
12 BICK
CS
17
13 SDTO
CCLK
16
14 SDTI
CDTI
15
5
0.1u
0.1u
2.7 ~ 5.25V
Digital Supply
C
C
VD
Audio
Controller
Mode
Setting
Notes:
- X’tal Oscillation circuit is specified from 11.2896MHz to 24.576MHz.
- AGND and DGND of AK4524 should be distributed separately from the ground of external controller etc.
- When AOUT+/- drives some capcitive load, some resistor sholud be added in series between AOUT+/- and
capacitive load.
- All input pins except pull-down pin (TEST) should not be left floating.
Figure 10. Typical Connection Diagram (X’tal mode)
X’tal Frequency
11.2896MHz, 12.288MHz
16.384MHz, 16.9344MHz, 18.432MHz
22.5792MHz, 24.576MHz
C
33pF
15pF
10pF
Table 12. External capacitance example for X’tal
(Please contact X’tal oscillator manufacturer)
M0050-E-01
1999/5
- 26 -
ASAHI KASEI
[AK4524]
4.75 ~ 5.25V
Analog Supply
0.1u 10u
+
10u +
1
VCOM
AOUTR+ 28
2
AINR
AOUTR-
27
3
AINL
AOUTL+
26
4
VREF
AOUTL-
25
5
AGND
DGND
24
6
VA
VD
23
7
TEST
VT
22
8
XTO
CLKO
21
9
XTI
M/ S
20
10 XTALE
PD
19
11 LRCK
CIF
18
12 BICK
CS
17
13 SDTO
CCLK
16
14 SDTI
CDTI
15
Rch
LPF
Rch Out
Lch
LPF
Lch Out
0.1u
Audio
Controller
AK4524
5
0.1u
0.1u
2.7 ~ 5.25V
Digital Supply
Mode
Setting
Figure 11. Typical Connection Diagram (EXT clock mode)
1. Grounding and Power Supply Decoupling
The AK4524 requires careful attention to power supply and grounding arrangements. VA and VD are usually supplied
from analog supply in system. Alternatively if VA and VD are supplied separately, the power up sequence is taken care.
VT is a power supply pin to interface with the external ICs and is supplied from digital supply in system. AGND and
DGND of the AK4524 should be connected to analog ground plane. System analog ground and digital ground should be
connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be
as near to the AK4524 as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference
The differential voltage between VREF and AGND sets the analog input/output range. VREF pin is normally connected to
VA with a 0.1uF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 10uF parallel with a
0.1uF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be
drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order to
avoid unwanted coupling into the AK4524.
M0050-E-01
1999/5
- 27 -
ASAHI KASEI
[AK4524]
3. Analog Inputs
The IPGA inputs are single-ended and the input resistance 5kW (min). The input signal range scales with the VREF voltage
and nominally 0.58 x VREF Vpp centerd in the internal common voltage (about VA/2). Usually the input signal is AC
coupled with capacitor. The cut-off frequency is fc=(1/2pRC). The AK4524 can accept input voltages from AGND to VA.
The ADC output data format is 2’s complement. The output code is 7FFFFFH(@24bit) for input above a positive full scale
and 800000H(@24bit) for input below a negative fill scale. The ideal code is 000000H(@24bit) with no input signal. The
DC offset including ADC own DC offset removed by the internal HPF.
The AK4524 samples the analog inputs at 64fs. The digital filter rejects noise above the stopband except for multiples of
64fs. The AK4524 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
4. Analog Outputs
The analog outputs are full differential outputs and nominally 0.54 x VREF Vpp centered in the internal common voltage
(about VA/2). The differential outputs are summed externally, Vout=(AOUT+)-(AOUT-) between AOUT+ and AOUT-.
If the summing gain is 1, the output range is 5.4Vpp ([email protected]=5V). The bias voltage of the external summing circuit is
supplied externally. The input data format is 2’s complement. The output voltage is a positive full scale for
7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal AOUT is 0V for 000000H(@24bit).
The internal switched-capacitor filter and the external LPF attenuate the noise generated by the delta-sigma modulator
beyond the audio passband.
Differential outputs can eliminate any DC offset on analog outputs without using capacitors. Figure 12 to Figure 14 show
the example of external op-amp circuit summing the differential outputs.
4.7k
4.7k
AOUTR1
Vop
3300p
4.7k
R1
AOUT+
Vop
4.7k
470p
+
Analog
Out
470p
1k
BIAS 0.1u
47u
+
1k
When R1=200ohm
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
When R1=180ohm
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Figure 12. External 2nd order LPF Example (using single supply op-amp)
M0050-E-01
1999/5
- 28 -
ASAHI KASEI
[AK4524]
4.7k
4.7k
AOUT470p
R1
+Vop
3300p
4.7k
R1
4.7k
Analog
Out
+
AOUT+
-Vop
470p
When R1=200ohm
fc=93.2kHz, Q=0.712, g=-0.1dB at 40kHz
When R1=180ohm
fc=98.2kHz, Q=0.681, g=-0.2dB at 40kHz
Figure 13. External 2nd order LPF Example (using dual supply op-amp)
180p
4.7k
4.7k
AOUT+Vop
4.7k
4.7k
Analog
Out
+
AOUT+
180p
-Vop
fc=188kHz
Figure 14. External low cost 1st order LPF Example (using dual supply op-amp)
n Peripheral I/F Example
The digital inputs of the AK4524 are TTL inputs and can accept the signal of device with a nominal 3V supply. The digital
output can interface with the peripheral device with a nominal 3V supply when the VT supply operates at a nominal 3V
supply.
5V Analog
3V Digital
Audio signal
Analog
Digital
DSP
I/F
3 or 5V Digital
AK4524
Control signal
uP &
Others
Figure 15. Power supply connection example
M0050-E-01
1999/5
- 29 -
ASAHI KASEI
[AK4524]
PACKAGE
28pin VSOP (Unit: mm)
*9.8±0.2
1.25±0.2
0.675
28
A
7.6±0.2
*5.6±0.2
15
14
1
+0.1
0.15-0.05
0.65
0.22±0.1
0.1±0.1
0.5±0.2
Detail A
| 0.10
1.0
Seating Plane
NOTE: Dimension "*" does not include mold flash.
0-10°
n Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder plate
M0050-E-01
1999/5
- 30 -
ASAHI KASEI
[AK4524]
MARKING
AKM
AK4524VF
XXXBYYYYC
XXXBYYYYC: data code identifier
XXXB: Lot number (X: Digit number, B: Alpha character)
YYYYC: Assembly date (Y: Digit number, C: Alpha character)
IMPORTANT NOTICE
· These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
· AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
· Any export of these products, or devices or systems containing them, may require an export license or
other official approval under the law and regulations of the country of export pertaining to customs and
tariffs, currency exchange, or strategic materials.
· AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
· It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and
hold AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
M0050-E-01
1999/5
- 31 -