Atmel-8387-8-and16-bit-AVR-Microcontroller-XMEGA-A4U Datasheet

8/16-bit Atmel XMEGA Microcontroller
ATxmega128A4U / ATxmega64A4U /
ATxmega32A4U / ATxmega16A4U
Features
z High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
z Nonvolatile program and data memories
16K - 128KB of in-system self-programmable flash
4K - 8KB boot section
1K - 2KB EEPROM
2K - 8KB internal SRAM
Peripheral Features
z Four-channel DMA controller
z Eight-channel event system
z Five 16-bit timer/counters
z Three timer/counters with 4 output compare or input capture channels
z Two timer/counters with 2 output compare or input capture channels
z High-resolution extensions on all timer/counters
z Advanced waveform extension (AWeX) on one timer/counter
z One USB device interface
z USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
z 32 Endpoints with full configuration flexibility
z Five USARTs with IrDA support for one USART
z Two Two-wire interfaces with dual address match (I2C and SMBus compatible)
z Two serial peripheral interfaces (SPIs)
z AES and DES crypto engine
z CRC-16 (CRC-CCITT) and CRC-32 (IEEE® 802.3) generator
z 16-bit real time counter (RTC) with separate oscillator
z One twelve-channel, 12-bit, 2msps Analog to Digital Converter
z One two-channel, 12-bit, 1msps Digital to Analog Converter
z Two Analog Comparators with window compare function, and current sources
z External interrupts on all general purpose I/O pins
z Programmable watchdog timer with separate on-chip ultra low power oscillator
z QTouch® library support
z Capacitive touch buttons, sliders and wheels
Special microcontroller features
z Power-on reset and programmable brown-out detection
z Internal and external clock options with PLL and prescaler
z Programmable multilevel interrupt controller
z Five sleep modes
z Programming and debug interfaces
z PDI (program and debug interface)
I/O and packages
z 34 Programmable I/O pins
z 44 - lead TQFP
z 44 - pad VQFN/QFN
z 49 - ball VFBGA
Operating voltage
z 1.6 – 3.6V
Operating frequency
z 0 – 12MHz from 1.6V
z 0 – 32MHz from 2.7V
z
z
z
z
z
z
z
z
z
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1.
Ordering Information
Ordering code
Flash (bytes)
EEPROM (bytes)
SRAM (bytes)
128K + 8K
2K
8K
ATxmega128A4U-AUR
128K + 8K
2K
8K
ATxmega64A4U-AU
64K + 4K
2K
4K
64K + 4K
2K
4K
ATxmega32A4U-AU
32K + 4K
1K
4K
ATxmega32A4U-AUR(4)
32K + 4K
1K
4K
ATxmega16A4U-AU
16K + 4K
1K
2K
16K + 4K
1K
2K
128K + 8K
2K
8K
128K + 8K
2K
8K
ATxmega64A4U-MH
64K + 4K
2K
4K
ATxmega64A4U-MHR(4)
64K + 4K
2K
4K
ATxmega32A4U-MH
32K + 4K
1K
4K
ATxmega32A4U-MHR(4)
32K + 4K
1K
4K
ATxmega16A4U-MH
16K + 4K
1K
2K
ATxmega16A4U-MHR(4)
16K + 4K
1K
2K
ATxmega128A4U-CU
128K + 8K
2K
8K
128K + 8K
2K
8K
64K + 4K
2K
4K
64K + 4K
2K
4K
ATxmega32A4U-CU
32K + 4K
1K
4K
ATxmega32A4U-CUR(4)
32K + 4K
1K
4K
ATxmega16A4U-CU
16K + 4K
1K
2K
16K + 4K
1K
2K
ATxmega128A4U-AU
(4)
ATxmega64A4U-AUR
(4)
Speed (MHz)
Power supply
Package (1)(2)(3)
Temp.
44A
ATxmega16A4U-AUR
(4)
ATxmega128A4U-MH
ATxmega128A4U-MHR
(4)
PW
32
1.6 - 3.6V
-40°C - 85°C
44M1
ATxmega128A4U-CUR
(4)
ATxmega64A4U-CU
ATxmega64A4U-CUR
(4)
49C2
ATxmega16A4U-CUR
(4)
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Ordering code
Flash (bytes)
EEPROM (bytes)
SRAM (bytes)
ATxmega128A4U-AN
128K + 8K
2K
8K
ATxmega128A4U-ANR(4)
128K + 8K
2K
8K
ATxmega64A4U-AN
64K + 4K
2K
4K
ATxmega64A4U-ANR(4)
64K + 4K
2K
4K
ATxmega32A4U-AN
32K + 4K
1K
4K
ATxmega32A4U-ANR(4)
32K + 4K
1K
4K
ATxmega16A4U-AN
16K + 4K
1K
2K
ATxmega16A4U-ANR(4)
16K + 4K
1K
2K
ATxmega128A4U-M7
128K + 8K
2K
8K
ATxmega128A4U-M7R(4)
128K + 8K
2K
8K
ATxmega64A4U-M7
64K + 4K
2K
4K
ATxmega64A4U-M7R(4)
64K + 4K
2K
4K
ATxmega32A4U-M7
32K + 4K
1K
4K
ATxmega32A4U-M7R(4)
32K + 4K
1K
4K
ATxmega16A4U-M7
16K + 4K
1K
2K
ATxmega16A4U-M7R(4)
16K + 4K
1K
2K
Speed (MHz)
Power supply
Package (1)(2)(3)
Temp.
44A
32
1.6 - 3.6V
0°C - 105°C
PW
44M1
Notes:
1.
2.
3.
4.
This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
For packaging information, see “Instruction Set Summary” on page 63.
Tape and Reel
Package Type
44A
44-Lead, 10 x 10mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP)
44M1
44-Pad, 7x7x1mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad no lead package (VQFN)
PW
44-Pad, 7x7x1mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad no lead package (VQFN)
49C2
49-Ball (7 x 7 Array), 0.65mm Pitch, 5.0 x 5.0 x 1.0mm, very thin, fine-pitch ball grid array package (VFBGA)
Typical Applications
Industrial control
Climate control
Low power battery applications
Factory automation
RF and ZigBee®
Power tools
Building control
USB connectivity
HVAC
Board control
Sensor control
Utility metering
White goods
Optical
Medical applications
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2.
Pinout/Block Diagram
Figure 2-1. Block Diagram and QFN/TQFP pinout
Power
Ground
Programming, debug, test
AVCC
GND
PR1
PR0
RESET/PDI
PDI
38
37
36
35
34
PA1
41
39
PA2
42
PA0
PA3
43
40
PA4
External clock / Crystal pins
General Purpose I /O
44
Digital function
Analog function / Oscillators
Port R
XOSC
PA6
2
PA7
3
PB0
4
PB1
5
PB2
6
PB3
7
GND
8
VCC
9
DATA BUS
Port A
1
33
PE3
OSC/CLK
Control
Internal
oscillators
Watchdog
Power
Supervision
32
PE2
Sleep
Controller
Real Time
Counter
Watchdog
Timer
Reset
Controller
31
VCC
Event System
Controller
Crypto /
CRC
OCD
Prog/Debug
Interface
30
GND
29
PE1
28
PE0
27
PD7
26
PD6
25
PD5
24
PD4
23
PD3
AREF
ADC
AC0:1
Port B
PA5
TOSC
Interrupt
Controller
AREF
BUS
matrix
Internal
references
DAC
DMA
Controller
CPU
FLASH
EEPROM
SRAM
DATA BUS
Note:
1.
TWI
USART0
TC0
USB
17
18
19
20
PC7
GND
VCC
PD0
22
16
PC6
PD2
15
PC5
21
14
PC4
PD1
SPI
13
PC3
Port E
12
Port D
PC2
Port C
USART0:1
TC0:1
SPI
11
TWI
PC1
TC0:1
10
USART0:1
PC0
IRCOM
EVENT ROUTING NETWORK
For full details on pinout and pin functions refer to “Pinout and Pin Functions” on page 55.
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Figure 2-2. BGA pinout
Top view
1
2
3
4
5
Bottom view
6
7
7
6
5
4
3
2
1
A
A
B
B
C
C
D
D
E
E
F
F
G
G
Table 2-1.
BGA pinout
1
2
3
4
5
6
7
A
PA3
AVCC
GND
PR1
PR0
PDI_DATA
PE3
B
PA4
PA1
PA0
GND
PE2
VCC
C
PA5
PA2
PA6
PA7
GND
PE1
GND
D
PB1
PB2
PB3
PB0
GND
PD7
PE0
E
GND
GND
PC3
GND
PD4
PD5
PD6
F
VCC
PC0
PC4
PC6
PD0
PD1
PD3
G
PC1
PC2
PC5
PC7
GND
VCC
PD2
RESET/
PDI_CLK
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3.
Overview
The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers
based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA
devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the
system designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The AVR XMEGA A4U devices provide the following features: in-system programmable flash with read-while-write
capabilities; internal EEPROM and SRAM; four-channel DMA controller, eight-channel event system and
programmable multilevel interrupt controller, 34 general purpose I/O lines, 16-bit real-time counter (RTC); five flexible,
16-bit timer/counters with compare and PWM channels; five USARTs; two two-wire serial interfaces (TWIs); one full
speed USB 2.0 interface; two serial peripheral interfaces (SPIs); AES and DES cryptographic engine; one twelvechannel, 12-bit ADC with programmable gain; one 2-channel 12-bit DAC; two analog comparators (ACs) with window
mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and
prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available.
The ATx devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the
SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down
mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI,
USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to
run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the
external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the
external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the
asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual
peripheral can optionally be stopped in active mode and idle sleep mode.
Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers.
The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory
can be reprogrammed in-system through the PDI. A boot loader running in the device can use any interface to
download the application program to the flash memory. The boot loader software in the boot flash section will continue
to run while the application flash section is updated, providing true read-while-write operation. By combining an 8/16bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that
provides a highly flexible and cost effective solution for many embedded applications.
All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including C
compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
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3.1
Block Diagram
Figure 3-1. XMEGA A4U Block Diagram
PR[0..1]
Digital function
Programming, debug, test
Analog function
Oscillator/Crystal/Clock
XTAL1/
TOSC1
General Purpose I/O
XTAL2/
TOSC2
Oscillator
Circuits/
Clock
Generation
PORT R (2)
Real Time
Counter
DATA BUS
PA[0..7]
PORT A (8)
Watchdog
Timer
Event System
Controller
Oscillator
Control
SRAM
ACA
DMA
Controller
ADCA
AREFA
Watchdog
Oscillator
Sleep
Controller
Prog/Debug
Controller
BUS Matrix
Power
Supervision
POR/BOD &
RESET
PDI
VCC
GND
RESET/
PDI_CLK
PDI_DATA
Int. Refs.
AES
Tempref
OCD
AREFB
DES
Interrupt
Controller
CPU
CRC
PORT B (8)
DACB
NVM Controller
Flash
IRCOM
EEPROM
DATA BUS
PORT D (8)
TWIE
TCE0
USARTE0
USB
SPID
TCD0:1
USARTD0:1
SPIC
PORT C (8)
TWIC
TCC0:1
EVENT ROUTING NETWORK
USARTC0:1
PB[0..7]
PORT E (4)
TOSC1 (optional)
TOSC2
(optional)
PC[0..7]
PD[0..7]
PE[0..3]
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4.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
4.1
Recommended reading
z
Atmel AVR XMEGA AU manual
z
XMEGA application notes
This device data sheet only contains part specific information with a short description of each peripheral and module.
The XMEGA AU manual describes the modules and peripherals in depth. The XMEGA application notes contain
example code and show applied use of the modules and peripherals.
All documentation are available from www.atmel.com/avr.
5.
Capacitive touch sensing
The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR
microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced
reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key
events. The QTouch library includes support for the QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR
microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling
the touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the QTouch library user
guide - also available for download from the Atmel website.
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6.
AVR CPU
6.1
Features
z 8/16-bit, high-performance Atmel AVR RISC CPU
z
z
142 instructions
Hardware multiplier
z 32x8-bit registers directly connected to the ALU
z Stack in RAM
z Stack pointer accessible in I/O memory space
z Direct addressing of up to 16MB of program memory and 16MB of data memory
z True 16/24-bit access to 16/24-bit I/O registers
z Efficient support for 8-, 16-, and 32-bit arithmetic
z Configuration change protection of system-critical features
6.2
Overview
All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and
perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute
the program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and
Programmable Multilevel Interrupt Controller” on page 29.
6.3
Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While
one instruction is being executed, the next instruction is pre-fetched from the program memory. This enables
instructions to be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.
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Figure 6-1. Block diagram of the AVR CPU architecture.
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and
a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status
register is updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all
have single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or
between a register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program
and data space addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different memory
spaces.
The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be
memory mapped in the data memory.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the
I/O memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to
0x3F. The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be
accessed as data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five
different addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.
The program memory is divided in two sections, the application program section and the boot program section. Both
sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for selfprogramming of the application flash memory must reside in the boot program section. The application section
contains an application table section with separate lock bits for write and read/write protection. The application table
section can be used for safe storing of nonvolatile data in the program memory.
6.4
ALU - Arithmetic Logic Unit
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and
a register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general
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purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a
register and an immediate are executed and the result is stored in the register file. After an arithmetic or logic
operation, the status register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
6.4.1
Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports
different variations of signed and unsigned integer and fractional numbers:
z
Multiplication of unsigned integers
z
Multiplication of signed integers
z
Multiplication of a signed integer with an unsigned integer
z
Multiplication of unsigned fractional numbers
z
Multiplication of signed fractional numbers
z
Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
6.5
Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The
program counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the
general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the
SRAM. After reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write
accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM
can easily be accessed through the five different addressing modes supported in the AVR CPU.
6.6
Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
6.7
Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH
and POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that
pushing data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is
automatically loaded after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed,
it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or
before interrupts are enabled.
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During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can
be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For
devices with more than 128KB of program memory, the return address is three bytes, and hence the SP is
decremented/incremented by three. The return address is popped off the stack when returning from interrupts using
the RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by
one when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable
interrupts for up to four instructions or until the next I/O memory write.
After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-1 on page 16.
6.8
Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The
register file supports the following input/output schemes:
z
One 8-bit output operand and one 8-bit result input
z
Two 8-bit output operands and one 8-bit result input
z
Two 8-bit output operands and one 16-bit result input
z
One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling
efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables
in flash program memory.
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7.
Memories
7.1
Features
z Flash program memory
z
z
z
z
z
z
z
z
One linear address space
In-system programmable
Self-programming and boot loader support
Application section for application code
Application table section for application code or data storage
Boot section for application code or boot loader code
Separate read/write protection lock bits for all sections
Built in fast CRC check of a selectable flash program memory section
z Data memory
z
z
z
z
z
z
z
One linear address space
Single-cycle access from CPU
SRAM
EEPROM
z Byte and page accessible
z Optional memory mapping for direct load and store
I/O memory
z Configuration and status registers for all peripherals and modules
z 16 bit-accessible general purpose registers for global variables or flags
Bus arbitration
z Deterministic priority handling between CPU, DMA controller, and other bus masters
Separate buses for SRAM, EEPROM and I/O memory
z Simultaneous bus access for CPU and DMA controller
z Production signature row memory for factory programmed data
ID for each microcontroller device type
Serial number for each device
z Calibration bytes for factory calibrated peripherals
z
z
z User signature row
One flash page in size
Can be read and written from software
z Content is kept after chip erase
z
z
7.2
Overview
The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable
code can reside only in the program memory, while data can be stored in the program memory and the data memory.
The data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are
linear and require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and
read/write operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and
can only be written by an external programmer.
The available memory size configurations are shown in “Ordering Information” on page 2. In addition, each device has
a Flash memory signature row for calibration data, device identification, serial number etc.
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7.3
Flash Program Memory
The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The
flash memory can be accessed for read and write from an external programmer through the PDI or from application
software running in the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is
organized in two main sections, the application section and the boot loader section. The sizes of the different sections
are fixed, but device-dependent. These two sections have separate lock bits, and can have different levels of
protection. The store program memory (SPM) instruction, which is used to write to the flash from the application
software, will only operate when executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe storage of
nonvolatile data in the program memory.
Table 7-1.
Flash Program Memory (Hexadecimal address).
Word Address
ATxmega128A4U
ATxmega64A4U
0
ATxmega32A4U
0
ATxmega16A4U
0
0
Application Section
(128K/64K/32K/16K)
...
7.3.1
EFFF
/
77FF
/
37FF
/
17FF
F000
/
7800
/
3800
/
1800
FFFF
/
7FFF
/
3FFF
/
1FFF
10000
/
8000
/
4000
/
2000
10FFF
/
87FF
/
47FF
/
27FF
Application Table Section
(8K/4K/4K/4K)
Boot Section
(8K/4K/4K/4K)
Application Section
The Application section is the section of the flash that is used for storing the executable application code. The
protection level for the application section can be selected by the boot lock bits for this section. The application section
can not store any boot loader code since the SPM instruction cannot be executed from the application section.
7.3.2
Application Table Section
The application table section is a part of the application section of the flash memory that can be used for storing data.
The size is identical to the boot loader section. The protection level for the application table section can be selected by
the boot lock bits for this section. The possibilities for different protection levels on the application section and the
application table section enable safe parameter storage in the program memory. If this section is not used for data,
application code can reside here.
7.3.3
Boot Loader Section
While the application section is used for storing the application code, the boot loader software must be located in the
boot loader section because the SPM instruction can only initiate programming when executing from this section. The
SPM instruction can access the entire flash, including the boot loader section itself. The protection level for the boot
loader section can be selected by the boot loader lock bits. If this section is not used for boot loader software,
application code can be stored here.
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7.3.4
Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration data
for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to
the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and
written to the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical
Characteristics” on page 72.
The production signature row also contains an ID that identifies each microcontroller device type and a serial number
for each manufactured device. The serial number consists of the production lot number, wafer number, and wafer
coordinates for the device. The device ID for the available devices is shown in Table 7-2.
The production signature row cannot be written or erased, but it can be read from application software and external
programmers.
Table 7-2.
Device ID bytes for Atmel AVR XMEGA A4U devices.
Device
7.3.5
Device ID bytes
Byte 2
Byte 1
Byte 0
ATxmega16A4U
41
94
1E
ATxmega32A4U
41
95
1E
ATxmega64A4U
46
96
1E
ATxmega128A4U
46
97
1E
User Signature Row
The user signature row is a separate memory section that is fully accessible (read and write) from application software
and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as
calibration data, custom serial number, identification numbers, random number seeds, etc. This section is not erased
by chip erase commands that erase the flash, and requires a dedicated erase command. This ensures parameter
storage during multiple program/erase operations and on-chip debug sessions.
7.4
Fuses and Lock bits
The fuses are used to configure important system functions, and can only be written from an external programmer.
The application software can read the fuses. The fuses are used to configure reset sources such as brownout detector
and watchdog, and startup configuration.
The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should
be blocked). Lock bits can be written by external programmers and application software, but only to stricter protection
levels. Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip
erase, the lock bits are erased after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value
zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
7.5
Data Memory
The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external
memory if available. The data memory is organized as one continuous memory section, see Figure 7-1. To simplify
development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR
XMEGA devices.
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Figure 7-1. Data memory map (Hexadecimal address).
Byte Address
ATxmega64A4U
0
FFF
I/O Registers (4K)
1000
EEPROM (2K)
17FF
Byte Address
ATxmega32A4U
0
FFF
1000
13FF
RESERVED
2000
2FFF
Byte Address
Internal SRAM (4K)
I/O Registers (4K)
EEPROM (1K)
Byte Address
ATxmega16A4U
0
FFF
1000
13FF
RESERVED
2000
2FFF
Internal SRAM (4K)
I/O Registers (4K)
EEPROM (1K)
RESERVED
2000
27FF
Internal SRAM (2K)
ATxmega128A4U
0
FFF
I/O Registers (4K)
1000
EEPROM (2K)
17FF
RESERVED
2000
3FFF
7.6
Internal SRAM (8K)
EEPROM
All devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or
memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory
mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM
is accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address
0x1000.
7.7
I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,
single-cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules in XMEGA A4U is shown in the “Peripheral Module Address
Map” on page 61.
7.7.1
General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
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7.8
Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA
controller read and DMA controller write, etc.) can access different memory sections at the same time.
7.9
Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read
from SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write)
takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle.
Refer to the instruction summary for more details on instructions and instruction timing.
7.10
Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device
type. A separate register contains the revision number of the device.
7.11
I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock
the I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the
lock is enabled, all related I/O registers are locked and they can not be written from the application software. The lock
registers themselves are protected by the configuration change protection mechanism.
7.12
Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for
the flash and byte accessible for the EEPROM.
Table 7-3 on page 17 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write
and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For
Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the
page number and the least significant address bits (FWORD) give the word in the page.
Table 7-3.
Devices
Number of words and pages in the flash.
PC size
bits
Flash size
Page Size
bytes
words
FWORD
FPAGE
Application
Size
No of
pages
Boot
Size
No of
pages
ATxmega16A4U
14
16K + 4K
128
Z[6:0]
Z[13:7]
16K
64
4K
16
ATxmega32A4U
15
32K + 4K
128
Z[6:0]
Z[14:7]
32K
128
4K
16
ATxmega64A4U
16
64K + 4K
128
Z[6:0]
Z[15:7]
64K
256
4K
16
ATxmega128A4U
17
128K + 8K
128
Z[6:0]
Z[16:7]
128K
512
8K
32
Table 7-4 shows EEPROM memory organization for the Atmel AVR XMEGA A4U devices. EEEPROM write and
erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a
time. For EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in
the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the
page.
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Table 7-4.
Number of bytes and pages in the EEPROM.
Devices
EEPROM
Size
Page Size
E2BYTE
E2PAGE
No of Pages
bytes
ATxmega16A4U
1K
32
ADDR[4:0]
ADDR[10:5]
32
ATxmega32A4U
1K
32
ADDR[4:0]
ADDR[10:5]
32
ATxmega64A4U
2K
32
ADDR[4:0]
ADDR[10:5]
64
ATxmega128A4U
2K
32
ADDR[4:0]
ADDR[10:5]
64
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8.
DMAC – Direct Memory Access Controller
8.1
Features
z Allows high speed data transfers with minimal CPU intervention
from data memory to data memory
from data memory to peripheral
z from peripheral to data memory
z from peripheral to peripheral
z
z
z Four DMA channels with separate
transfer triggers
interrupt vectors
z addressing modes
z
z
z Programmable channel priority
z From 1 byte to 16MB of data in a single transaction
z
z
Up to 64KB block transfers with repeat
1, 2, 4, or 8 byte burst transfers
z Multiple addressing modes
Static
Incremental
z Decremental
z
z
z Optional reload of source and destination addresses at the end of each
Burst
Block
z Transaction
z
z
z Optional interrupt on end of transaction
z Optional connection to CRC generator for CRC on DMA data
8.2
Overview
The four-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and
thus offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees
up CPU time. The four DMA channels enable up to four independent and parallel transfers.
The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between
peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from
communication modules. The DMA controller can also read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from
1 byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source
and destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination
addresses can be done after each burst or block transfer, or when a transaction is complete. Application software,
peripherals, and events can trigger DMA transfers.
The four DMA channels have individual configuration and control settings. This include source, destination, transfer
triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a
transaction is complete or when the DMA controller detects an error on a DMA channel.
To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the
first is finished, and vice versa.
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9.
Event System
9.1
Features
z System for direct peripheral-to-peripheral communication and signaling
z Peripherals can directly send, receive, and react to peripheral events
CPU and DMA controller independent operation
100% predictable signal timing
z Short and guaranteed response time
z
z
z Eight event channels for up to eight different and parallel signal routing configurations
z Events can be sent and/or used by most peripherals, clock system, and software
z Additional functions include
z
z
Quadrature decoders
Digital filtering of I/O pin state
z Works in active mode and idle sleep mode
9.2
Overview
The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one
peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system
for short and predictable response times between peripherals. It allows for autonomous peripheral control and
interaction without the use of interrupts, CPU, or DMA controller resources, and is thus a powerful tool for reducing the
complexity, size and execution time of application code. It also allows for synchronized timing of actions in several
peripheral modules.
A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt
conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event
routing network. How events are routed and used by the peripherals is configured in software.
Figure 9-1 on page 20 shows a basic diagram of all connected peripherals. The event system can directly connect
together analog and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR
communication module (IRCOM), and USB interface. It can also be used to trigger DMA transactions (DMA
controller). Events can also be generated from software and the peripheral clock.
Figure 9-1. Event system overview and connected peripherals.
CPU /
Software
DMA
Controller
Event Routing Network
ADC
AC
clkPER
Prescaler
Real Time
Counter
Event
System
Controller
Timer /
Counters
DAC
USB
Port pins
IRCOM
The event routing network consists of eight software-configurable multiplexers that control how events are routed and
used. These are called event channels, and allow for up to eight parallel event routing configurations. The maximum
routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.
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10.
System Clock and Clock options
10.1
Features
z Fast start-up time
z Safe run-time clock switching
z Internal oscillators:
32MHz run-time calibrated and tuneable oscillator
2MHz run-time calibrated oscillator
z 32.768kHz calibrated oscillator
z 32kHz ultra low power (ULP) oscillator with 1kHz output
z
z
z External clock options
0.4MHz - 16MHz crystal oscillator
32.768kHz crystal oscillator
z External clock
z
z
z PLL with 20MHz - 128MHz output frequency
z
z
Internal and external clock options and 1x to 31x multiplication
Lock detector
z Clock prescalers with 1x to 2048x division
z Fast peripheral clocks running at two and four times the CPU clock
z Automatic run-time calibration of internal oscillators
z External oscillator and PLL lock failure detection with optional non-maskable interrupt
10.2
Overview
Atmel AVR XMEGA A4U devices have a flexible clock system supporting a large number of clock sources. It
incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency
phase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A
calibration feature (DFLL) is available, and can be used for automatic run-time calibration of the internal oscillators to
remove frequency drift over voltage and temperature. An oscillator failure monitor can be enabled to issue a nonmaskable interrupt and switch to the internal oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the
device will always start up running from the 2MHz internal oscillator. During normal operation, the system clock
source and prescalers can be changed from software at any time.
Figure 10-1 on page 22 presents the principal clock system in the XMEGA A4U family of devices. Not all of the clocks
need to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and
power reduction registers, as described in “Power Management and Sleep Modes” on page 24.
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Figure 10-1. The clock system, clock sources and clock distribution.
Real Time
Counter
RAM
Peripherals
AVR CPU
Non-Volatile
Memory
clkPER
clkCPU
clkPER2
clkPER4
USB
clkUSB
Brown-out
Detector
System Clock Prescalers
Watchdog
Timer
Prescaler
clkSYS
clkRTC
System Clock Multiplexer
(SCLKSEL)
RTCSRC
USBSRC
DIV32
DIV32
DIV32
PLL
PLLSRC
DIV4
XOSCSEL
32 kHz
Int. ULP
32.768 kHz
Int. OSC
32.768 kHz
TOSC
32 MHz
Int. Osc
2 MHz
Int. Osc
XTAL2
XTAL1
TOSC2
TOSC1
10.3
0.4 – 16 MHz
XTAL
Clock Sources
The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock
sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,
depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other
clock sources, DFLLs and PLL, are turned off by default.
The internal oscillators do not require any external components to run. For details on characteristics and accuracy of
the internal oscillators, refer to the device datasheet.
10.3.1 32kHz Ultra Low Power Internal Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low
power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides
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a 1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the
device. This oscillator can be selected as the clock source for the RTC.
10.3.2 32.768kHz Calibrated Internal Oscillator
This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default
frequency close to its nominal frequency. The calibration register can also be written from software for run-time
calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz
output and a 1.024kHz output.
10.3.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low
frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator
can be used as a clock source for the system clock and RTC, and as the DFLL reference clock.
10.3.4 0.4 - 16MHz Crystal Oscillator
This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz.
10.3.5 2MHz Run-time Calibrated Internal Oscillator
The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during
production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic runtime calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.
10.3.6 32MHz Run-time Calibrated Internal Oscillator
The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to
provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for
automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the
oscillator accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz.
The production signature row contains 48MHz calibration values intended used when the oscillator is used a fullspeed USB clock source.
10.3.7 External Clock Sources
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.
XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a
32.768kHz crystal oscillator.
10.3.8 PLL with 1x-31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a userselectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output
frequencies from all clock sources.
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11.
Power Management and Sleep Modes
11.1
Features
z Power management for adjusting power consumption and functions
z Five sleep modes
Idle
Power down
z Power save
z Standby
z Extended standby
z
z
z Power reduction register to disable clock and turn off unused peripherals in active and idle modes
11.2
Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application
code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the
device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals
and all enabled reset sources can restore the microcontroller from sleep to active mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When
this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This
reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power
management than sleep modes alone.
11.3
Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power.
XMEGA microcontrollers have five different sleep modes tuned to match the typical functional stages during
application execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to
wake the device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep
mode. When an enabled interrupt occurs, the device will wake up and execute the interrupt service routine before
continuing normal program execution from the first instruction after the SLEEP instruction. If other, higher priority
interrupts are pending when the wake-up occurs, their interrupt service routines will be executed according to their
priority before the interrupt service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for
four cycles before execution starts.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device
will reset, start up, and execute from the reset vector.
11.3.1 Idle Mode
In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed),
but all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled
interrupt will wake the device.
11.3.2 Power-down Mode
In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only
of asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the
two-wire interface address match interrupt, asynchronous port interrupts, and the USB resume interrupt.
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11.3.3 Power-save Mode
Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep
running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.
11.3.4 Standby Mode
Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running
while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.
11.3.5 Extended Standby Mode
Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources
are kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.
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12.
System Control and Reset
12.1
Features
z Reset the microcontroller and set it to initial state when a reset source goes active
z Multiple reset sources that cover different situations
z
z
z
z
z
z
Power-on reset
External reset
Watchdog reset
Brownout reset
PDI reset
Software reset
z Asynchronous operation
z
No running system clock in the device is required for reset
z Reset status register for reading the reset source from the application code
12.2
Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a
reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. The
I/O pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set
to their initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the
content of the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts
running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to
move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software
reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows
which sources have issued a reset since the last power-on.
12.3
Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:
z
Reset counter delay
z
Oscillator startup
z
Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
12.4
Reset Sources
12.4.1 Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.
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12.4.2 Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during
chip erase and when the PDI is enabled.
12.4.3 External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin
is driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will
be held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
12.4.4 Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from
the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for
one to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 28.
12.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the
reset control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to
execute any instruction from when a software reset is requested until it is issued.
12.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during
external programming and debugging. This reset source is accessible only from external debuggers and
programmers.
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13.
WDT – Watchdog Timer
13.1
Features
z Issues a device reset if the timer is not reset before its timeout period
z Asynchronous operation from dedicated oscillator
z 1kHz output of the 32kHz ultra low power oscillator
z 11 selectable timeout periods, from 8ms to 8s
z Two operation modes:
z
z
Normal mode
Window mode
z Configuration lock to prevent unwanted changes
13.2
Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to
recover from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined
timeout period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue
a microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the
application code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT
must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.
Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent
clock source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For
increased safety, a fuse for locking the WDT settings is also available.
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14.
Interrupts and Programmable Multilevel Interrupt Controller
14.1
Features
z Short and predictable interrupt response time
z Separate interrupt configuration and vector address for each interrupt
z Programmable multilevel interrupt controller
Interrupt prioritizing according to level and vector address
Three selectable interrupt levels for all interrupts: low, medium and high
z Selectable, round-robin priority scheme within low-level interrupts
z Non-maskable interrupts for critical functions
z
z
z Interrupt vectors optionally placed in the application section or the boot loader section
14.2
Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can
have one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and
configured, it will generate an interrupt request when the interrupt condition is present. The programmable multilevel
interrupt controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is
acknowledged by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can
be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts
are prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level,
the interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the
highest interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all
interrupts are serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
14.3
Interrupt vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts
in each peripheral. The base addresses for the Atmel AVR XMEGA A4U devices are shown in Table 14-1 on page 30.
Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU
manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1 on page
30. The program address is the word address.
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Table 14-1. Reset and interrupt vectors
Program address
(base address)
Source
0x000
RESET
0x002
OSCF_INT_vect
Crystal oscillator failure interrupt vector (NMI)
0x004
PORTC_INT_base
Port C interrupt base
0x008
PORTR_INT_base
Port R interrupt base
0x00C
DMA_INT_base
DMA controller interrupt base
0x014
RTC_INT_base
Real time counter interrupt base
0x018
TWIC_INT_base
Two-Wire Interface on Port C interrupt base
0x01C
TCC0_INT_base
Timer/counter 0 on port C interrupt base
0x028
TCC1_INT_base
Timer/counter 1 on port C interrupt base
0x030
SPIC_INT_vect
SPI on port C interrupt vector
0x032
USARTC0_INT_base
USART 0 on port C interrupt base
0x038
USARTC1_INT_base
USART 1 on port C interrupt base
0x03E
AES_INT_vect
AES interrupt vector
0x040
NVM_INT_base
Nonvolatile Memory interrupt base
0x044
PORTB_INT_base
Port B interrupt base
0x056
PORTE_INT_base
Port E interrupt base
0x05A
TWIE_INT_base
Two-wire Interface on Port E interrupt base
0x05E
TCE0_INT_base
Timer/counter 0 on port E interrupt base
0x06A
TCE1_INT_base
Timer/counter 1 on port E interrupt base
0x074
USARTE0_INT_base
USART 0 on port E interrupt base
0x080
PORTD_INT_base
Port D interrupt base
0x084
PORTA_INT_base
Port A interrupt base
0x088
ACA_INT_base
Analog Comparator on Port A interrupt base
0x08E
ADCA_INT_base
Analog to Digital Converter on Port A interrupt base
0x09A
TCD0_INT_base
Timer/counter 0 on port D interrupt base
0x0A6
TCD1_INT_base
Timer/counter 1 on port D interrupt base
0x0AE
SPID_INT_vector
SPI on port D interrupt vector
0x0B0
USARTD0_INT_base
USART 0 on port D interrupt base
0x0B6
USARTD1_INT_base
USART 1 on port D interrupt base
0x0FA
USB_INT_base
USB on port D interrupt base
Interrupt description
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15.
I/O Ports
15.1
Features
z 34 general purpose input and output pins with individual configuration
z Output driver with configurable driver and pull settings:
Totem-pole
Wired-AND
z Wired-OR
z Bus-keeper
z Inverted I/O
z
z
z Input with synchronous and/or asynchronous sensing with interrupts and events
Sense both edges
Sense rising edges
z Sense falling edges
z Sense low level
z
z
z Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations
z Optional slew rate control
z Asynchronous pin change sensing that can wake the device from all sleep modes
z Two port interrupts with pin masking per I/O port
z Efficient and safe access to port pins
Hardware read-modify-write through dedicated toggle/clear/set registers
Configuration of multiple pins in a single operation
z Mapping of port registers into bit-accessible I/O memory space
z
z
z Peripheral clocks output on port pin
z Real-time counter clock output to port pin
z Event channels can be output on port pin
z Remapping of digital peripheral pin functions
z
15.2
Selectable USART, SPI, and timer/counter input/output pin locations
Overview
One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with
configurable driver and pull settings. They also implement synchronous and asynchronous input sensing with
interrupts and events for selectable pin change conditions. Asynchronous pin-change sensing means that a pin
change can wake the device from all sleep modes, included the modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins
have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor
configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other
pin.
The port pin configuration also controls input and output selection of other device functions. It is possible to have both
the peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to
events from the event system that can be used to synchronize and control external functions. Other digital
peripherals, such as USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to
optimize pin-out versus application needs.
The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, and PORTR.
15.3
Output Driver
All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to
reduce electromagnetic emission.
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15.3.1 Push-pull
Figure 15-1. I/O configuration - Totem-pole.
DIRn
OUTn
Pn
INn
15.3.2 Pull-down
Figure 15-2. I/O configuration - Totem-pole with pull-down (on input).
DIRn
OUTn
Pn
INn
15.3.3 Pull-up
Figure 15-3. I/O configuration - Totem-pole with pull-up (on input).
DIRn
OUTn
Pn
INn
15.3.4 Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last
level was ‘1’, and pull-down if the last level was ‘0’.
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Figure 15-4. I/O configuration - Totem-pole with bus-keeper.
DIRn
OUTn
Pn
INn
15.3.5 Others
Figure 15-5. Output configuration - Wired-OR with optional pull-down.
OUTn
Pn
INn
Figure 15-6. I/O configuration - Wired-AND with optional pull-up.
INn
Pn
OUTn
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15.4
Input sensing
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is
shown in Figure 15-7.
Figure 15-7. Input sensing system overview.
Asynchronous sensing
EDGE
DETECT
Interrupt
Control
IREQ
Synchronous sensing
Pn
Synchronizer
INn
D Q D Q
INVERTED I/O
R
EDGE
DETECT
Event
R
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
15.5
Alternate Port Functions
Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function
is enabled, it might override the normal port pin function or pin value. This happens when other peripherals that
require pins are enabled or configured to use pins. If and how a peripheral will override and use pins is described in
the section for that peripheral. “Pinout and Pin Functions” on page 55 shows which modules on peripherals that
enable alternate functions on a pin, and which alternate functions that are available on a pin.
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16.
TC0/1 – 16-bit Timer/Counter Type 0 and 1
16.1
Features
z Five 16-bit timer/counters
Three timer/counters of type 0
Two timer/counters of type 1
z Split-mode enabling two 8-bit timer/counter from each timer/counter type 0
z
z
z 32-bit timer/counter support by cascading two timer/counters
z Up to four compare or capture (CC) channels
z
z
Four CC channels for timer/counters of type 0
Two CC channels for timer/counters of type 1
z Double buffered timer period setting
z Double buffered capture or compare channels
z Waveform generation:
Frequency generation
Single-slope pulse width modulation
z Dual-slope pulse width modulation
z
z
z Input capture:
Input capture with noise cancelling
Frequency capture
z Pulse width capture
z 32-bit input capture
z
z
z Timer overflow and error interrupts/events
z One compare match or input capture interrupt/event per CC channel
z Can be used with event system for:
Quadrature decoding
Count and direction control
z Capture
z
z
z Can be used with DMA and to trigger DMA transactions
z High-resolution extension
z
Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)
z Advanced waveform extension:
z
Low- and high-side output with programmable dead-time insertion (DTI)
z Event controlled fault protection for safe disabling of drivers
16.2
Overview
Atmel AVR XMEGA devices have a set of five flexible 16-bit Timer/Counters (TC). Their capabilities include accurate
program execution timing, frequency and waveform generation, and input capture with time and frequency
measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32bit capture.
A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be
used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC
channels can be used together with the base counter to do compare match control, frequency generation, and pulse
width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either
capture or compare functions, but cannot perform both at the same time.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.
The event system can also be used for direction control and capture trigger or to synchronize operations.
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There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and
timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0.
Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels
each.
Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced
waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and
high-side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It
can also generate a synchronized bit pattern across the port pins.
The advanced waveform extension can be enabled to provide extra and more advanced features for the
Timer/Counter. This are only available for Timer/Counter 0. See “AWeX – Advanced Waveform Extension” on page
38 for more details.
The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times
by using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High
Resolution Extension” on page 39 for more details.
Figure 16-1. Overview of a Timer/Counter and closely related peripherals.
Timer/Counter
Base Counter
Timer Period
Counter
Prescaler
Control Logic
clkPER
Event
System
Buffer
Capture
Control
Waveform
Generation
Dead-Time
Insertion
Pattern
Generation
Fault
Protection
PORT
Comparator
AWeX
Hi-Res
clkPER4
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
PORTC and PORTD each has one Timer/Counter 0 and one Timer/Counter1. PORTE has one Timer/Conter0.
Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1 and TCE0, respectively.
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17.
TC2 - Timer/Counter Type 2
17.1
Features
z Six eight-bit timer/counters
z
z
Three Low-byte timer/counter
Three High-byte timer/counter
z Up to eight compare channels in each Timer/Counter 2
z
z
Four compare channels for the low-byte timer/counter
Four compare channels for the high-byte timer/counter
z Waveform generation
z
Single slope pulse width modulation
z Timer underflow interrupts/events
z One compare match interrupt/event per compare channel for the low-byte timer/counter
z Can be used with the event system for count control
z Can be used to trigger DMA transactions
17.2
Overview
There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of
two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width
modulation (PWM) channels with individually controlled duty cycles, and is intended for applications that require a
high number of PWM channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte
timer/counter, respectively. The difference between them is that only the low-byte timer/counter can be used to
generate compare match interrupts, events and DMA triggers. The two eight-bit timer/counters have a shared clock
source and separate period and compare settings. They can be clocked and timed from the peripheral clock, with
optional prescaling, or from the event system. The counters are always counting down.
PORTC, and PORTD each has one Timer/Counter 2.
Notation of these are TCC2 (Time/Counter C2) and TCD2, respectively.
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18.
AWeX – Advanced Waveform Extension
18.1
Features
z Waveform output with complementary output from each compare channel
z Four dead-time insertion (DTI) units
8-bit resolution
Separate high and low side dead-time setting
z Double buffered dead time
z Optionally halts timer during dead-time insertion
z
z
z Pattern generation unit creating synchronised bit pattern across the port pins
z
z
Double buffered pattern generation
Optional distribution of one compare channel output across the port pins
z Event controlled fault protection for instant and predictable fault triggering
18.2
Overview
The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation
(WG) modes. It is primarily intended for use with different types of motor control and other power control applications.
It enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down
external drivers. It can also generate a synchronized bit pattern across the port pins.
Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when
any AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the
non-inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS
switching. The DTI output will override the normal port value according to the port override setting.
The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In
addition, the WG output from compare channel A can be distributed to and override all the port pins. When the pattern
generator unit is enabled, the DTI unit is bypassed.
The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will
disable the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the
selection of fault triggers.
The AWeX is available for TCC0. The notation of this is AWEXC.
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19.
Hi-Res – High Resolution Extension
19.1
Features
z Increases waveform generator resolution up to 8x (three bits)
z Supports frequency, single-slope PWM, and dual-slope PWM generation
z Supports the AWeX when this is used for the same timer/counter
19.2
Overview
The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from
a timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope
PWM generation. It can also be used with the AWeX if this is used for the same timer/counter.
The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the
peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res
extension is enabled.
There are three hi-res extensions that each can be enabled for each timer/counters pair on PORTC, PORTD and
PORTE. The notation of these are HIRESC, HIRESD and HIRESE, respectively.
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20.
RTC – 16-bit Real-Time Counter
20.1
Features
z 16-bit resolution
z Selectable clock source
32.768kHz external crystal
External clock
z 32.768kHz internal oscillator
z 32kHz internal ULP oscillator
z
z
z Programmable 10-bit clock prescaling
z One compare register
z One period register
z Clear counter on period overflow
z Optional interrupt/event on overflow and compare match
20.2
Overview
The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes,
to keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.
The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the
configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC
needs a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz
internal oscillator or the 32kHz internal ULP oscillator.
The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the
counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the
maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the
maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event
when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period
register value.
Figure 20-1. Real-time counter overview.
External Clock
TOSC1
TOSC2
32.768kHz Crystal Osc
32.768kHz Int. Osc
DIV32
DIV32
32kHz int ULP (DIV32)
PER
RTCSRC
clkRTC
10-bit
prescaler
=
TOP/
Overflow
=
”match”/
Compare
CNT
COMP
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21.
USB – Universal Serial Bus Interface
21.1
Features
z One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface
z Integrated on-chip USB transceiver, no external components needed
z 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints
z
z
One input endpoint per endpoint address
One output endpoint per endpoint address
z Endpoint address transfer type selectable to
Control transfers
Interrupt transfers
z Bulk transfers
z Isochronous transfers
z
z
z Configurable data payload size per endpoint, up to 1023 bytes
z Endpoint configuration and data buffers located in internal SRAM
z
z
Configurable location for endpoint configuration data
Configurable location for each endpoint's data buffer
z Built-in direct memory access (DMA) to internal SRAM for:
z
z
Endpoint configurations
Reading and writing endpoint data
z Ping-pong operation for higher throughput and double buffered operation
z
z
Input and output endpoint data buffers used in a single direction
CPU/DMA controller can update data buffer during transfer
z Multipacket transfer for reduced interrupt load and software intervention
z
z
Data payload exceeding maximum packet size is transferred in one continuous transfer
No interrupts or software interaction on packet transaction level
z Transaction complete FIFO for workflow management when using multiple endpoints
z
Tracks all completed transactions in a first-come, first-served work queue
z Clock selection independent of system clock source and selection
z Minimum 1.5MHz CPU clock required for low speed USB operation
z Minimum 12MHz CPU clock required for full speed operation
z Connection to event system
z On chip debug possibilities during USB transactions
21.2
Overview
The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface.
The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total
of 31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be
configured for any of the four transfer types; control, interrupt, bulk, or isochronous. The data payload size is also
selectable, and it supports data payloads up to 1023 bytes.
No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration
for each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint
configurations and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to
the number of endpoints in use and the configuration of these. The USB module has built-in direct memory access
(DMA), and will read/write data from/to the SRAM when a USB transaction takes place.
To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and
output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer
while the USB module writes/reads the others, and vice versa. This gives double buffered communication.
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Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as
multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB
transfers.
For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle
and a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any
sleep mode.
PORTD has one USB. Notation of this is USB.
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22.
TWI – Two-Wire Interface
22.1
Features
z Two Identical two-wire interface peripherals
z Bidirectional, two-wire communication interface
Phillips I2C compatible
z System Management Bus (SMBus) compatible
z
z Bus master and slave operation supported
Slave operation
Single bus master operation
z Bus master in multi-master bus environment
z Multi-master arbitration
z
z
z Flexible slave address match functions
7-bit and general call address recognition in hardware
10-bit addressing supported
z Address mask register for dual address match or address range masking
z Optional software address recognition for unlimited number of addresses
z
z
z Slave can operate in all sleep modes, including power-down
z Slave address match can wake device from all sleep modes
z 100kHz and 400kHz bus frequency support
z Slew-rate limited output drivers
z Input filter for bus noise and spike suppression
z Support arbitration between start/repeated start and data bit (SMBus)
z Slave arbitration allows support for address resolve protocol (ARP) (SMBus)
22.2
Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management
Bus (SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each
bus line.
A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing
a slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or
several masters that can take control of the bus. An arbitration process handles priority if more than one master tries
to transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.
The TWI module supports master and slave functionality. The master and slave functionality are separated from each
other, and can be enabled and configured separately. The master module supports multi-master bus operation and
arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick
command and smart mode can be enabled to auto-trigger operations and reduce software complexity.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit
addressing is also supported. A dedicated address mask register can act as a second address match register or as a
register for address range masking. The slave continues to operate in all sleep modes, including power-down mode.
This enables the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the
address matching to let this be handled in software instead.
The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors,
collision, and clock hold on the bus are also detected and indicated in separate status flags available in both master
and slave modes.
It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an
external TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than
used by the TWI bus.
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PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.
23.
SPI – Serial Peripheral Interface
23.1
Features
z Two Identical SPI peripherals
z Full-duplex, three-wire synchronous data transfer
z Master or slave operation
z Lsb first or msb first data transfer
z Eight programmable bit rates
z Interrupt flag at the end of transmission
z Write collision flag to indicate data collision
z Wake up from idle sleep mode
z Double speed master mode
23.2
Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It
allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several
microcontrollers. The SPI supports full-duplex communication.
A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions.
PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID.
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24.
USART
24.1
Features
z Five identical USART peripherals
z Full-duplex operation
z Asynchronous or synchronous operation
z
z
Synchronous clock rates up to 1/2 of the device clock frequency
Asynchronous clock rates up to 1/8 of the device clock frequency
z Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
z Fractional baud rate generator
z
z
Can generate desired baud rate from any system clock frequency
No need for external oscillator with certain frequencies
z Built-in error detection and correction schemes
Odd or even parity generation and parity check
Data overrun and framing error detection
z Noise filtering includes false start bit detection and digital low-pass filter
z
z
z Separate interrupts for
Transmit complete
Transmit data register empty
z Receive complete
z
z
z Multiprocessor communication mode
z
z
Addressing scheme to address a specific devices on a multidevice bus
Enable unaddressed devices to automatically ignore all frames
z Master SPI mode
z
z
Double buffered operation
Operation up to 1/2 of the peripheral clock frequency
z IRCOM module for IrDA compliant pulse modulation/demodulation
24.2
Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial
communication module. The USART supports full-duplex communication and asynchronous and synchronous
operation. The USART can be configured to operate in SPI master mode and used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide range of standards. The
USART is buffered in both directions, enabling continued data transmission without any delay between frames.
Separate interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and
buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and
parity check can also be enabled.
The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud
rates from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific
frequency to achieve a required baud rate. It also supports external clock input in synchronous slave operation.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive
buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both
modes. The registers are used in both modes, but their functionality differs for some control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and
demodulation for baud rates up to 115.2Kbps.
PORTC and PORTD each has two USARTs. PORTE has one USART. Notation of these peripherals are USARTC0,
USARTC1, USARTD0, USARTD1 and USARTE0, respectively.
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25.
IRCOM – IR Communication Module
25.1
Features
z Pulse modulation/demodulation for infrared communication
z IrDA compatible for baud rates up to 115.2Kbps
z Selectable pulse modulation scheme
3/16 of the baud rate period
Fixed pulse period, 8-bit programmable
z Pulse modulation disabled
z
z
z Built-in filtering
z Can be connected to and used by any USART
25.2
Overview
Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud
rates up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that
USART.
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26.
AES and DES Crypto Engine
26.1
Features
z Data Encryption Standard (DES) CPU instruction
z Advanced Encryption Standard (AES) crypto module
z DES Instruction
Encryption and decryption
DES supported
z Encryption/decryption in 16 CPU clock cycles per 8-byte block
z
z
z AES crypto module
Encryption and decryption
Supports 128-bit keys
z Supports XOR data load mode to the state memory
z Encryption/decryption in 375 clock cycles per 16-byte block
z
z
26.2
Overview
The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used standards
for cryptography. These are supported through an AES peripheral module and a DES CPU instruction, and the
communication interfaces and the CPU can use these for fast, encrypted communication and secure data storage.
DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into the
register file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block.
The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data
must be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375
peripheral clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out,
and an optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when
encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.
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27.
CRC – Cyclic Redundancy Check Generator
27.1
Features
z Cyclic redundancy check (CRC) generation and checking for
Communication data
Program or data in flash memory
z Data in SRAM and I/O memory space
z
z
z Integrated with flash memory, DMA controller and CPU
Continuous CRC on data going through a DMA channel
Automatic CRC of the complete or a selectable range of the flash memory
z CPU can load data to the CRC generator through the I/O interface
z
z
z CRC polynomial software selectable to
z
z
CRC-16 (CRC-CCITT)
CRC-32 (IEEE 802.3)
z Zero remainder detection
27.2
Overview
A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data,
and it is commonly used to determine the correctness of a data transmission, and data present in the data and
program memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that
can be appended to the data and used as a checksum. When the same data are later received or read, the device or
application repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains
a data error. The application will then detect this and may take a corrective action, such as requesting the data to be
sent again or simply not using the incorrect data.
Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n
bits (any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer
error bursts. The CRC module in Atmel AVR XMEGA devices supports two commonly used CRC polynomials; CRC16 (CRC-CCITT) and CRC-32 (IEEE 802.3).
z
z
CRC-16:
Polynomial:
x16+x12+x5+1
Hex value:
0x1021
CRC-32:
Polynomial:
x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
Hex value:
0x04C11DB7
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28.
ADC – 12-bit Analog to Digital Converter
28.1
Features
z One Analog to Digital Converter (ADC)
z 12-bit resolution
z Up to two million samples per second
Two inputs can be sampled simultaneously using ADC and 1x gain stage
Four inputs can be sampled within 1.5µs
z Down to 2.5µs conversion time with 8-bit resolution
z Down to 3.5µs conversion time with 12-bit resolution
z
z
z Differential and single-ended input
Up to 12 single-ended inputs
12x4 differential inputs without gain
z 8x4 differential inputs with gain
z
z
z Built-in differential gain stage
z 1/2x,
1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options
z Single, continuous and scan conversion options
z Four internal inputs
Internal temperature sensor
DAC output
z AVCC voltage divided by 10
z 1.1V bandgap voltage
z
z
z Four conversion channels with individual input control and result registers
z
Enable four parallel configurations and results
z Internal and external reference options
z Compare function for accurate monitoring of user defined thresholds
z Optional event triggered conversion for accurate timing
z Optional DMA transfer of conversion results
z Optional interrupt/event on compare result
28.2
Overview
The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to
two million samples per second (msps). The input selection is flexible, and both single-ended and differential
measurements can be done. For differential measurements, an optional gain stage is available to increase the
dynamic range. In addition, several internal signal inputs are available. The ADC can provide both signed and
unsigned results.
This is a pipelined ADC that consists of several consecutive stages. The pipelined design allows a high sample rate at
a low system clock frequency. It also means that a new input can be sampled and a new ADC conversion started
while other ADC conversions are still ongoing. This removes dependencies between sample rate and propagation
delay.
The ADC has four conversion channels (0-3) with individual input selection, result registers, and conversion start
control. The ADC can then keep and use four parallel configurations and results, and this will ease use for
applications with high data throughput or for multiple modules using the ADC independently. It is possible to use DMA
to move ADC results directly to memory or peripherals when conversions are done.
Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with
the ADC. The output from the DAC, AVCC/10 and the bandgap voltage can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software
intervention required.
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Figure 28-1. ADC overview.
ADC0
Compare
•
••
ADC11
ADC0
Internal
signals
VINP
CH0 Result
••
•
ADC7
ADC4
CH1 Result
Threshold
(Int Req)
½x - 64x
CH2 Result
•
••
ADC7
Int. signals
<
>
Internal
signals
CH3 Result
VINN
ADC0
•
••
ADC3
Int. signals
Internal 1.00V
Internal AVCC/1.6V
Internal AVCC/2
AREFA
AREFB
Reference
Voltage
Two inputs can be sampled simultaneously as both the ADC and the gain stage include sample and hold circuits, and
the gain stage has 1x gain setting. Four inputs can be sampled within 1.5µs without any intervention by the
application.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from
3.5µs for 12-bit to 2.5µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when
the result is represented as a signed integer (signed 16-bit number).
PORTA has one ADC. Notation of this peripheral is ADCA.
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29.
DAC – 12-bit Digital to Analog Converter
29.1
Features
z
One Digital to Analog Converter (DAC)
z
12-bit resolution
z
Two independent, continuous-drive output channels
z
Up to one million samples per second conversion rate per DAC channel
z
Built-in calibration that removes:
z
z
29.2
z
Offset error
z
Gain error
Multiple conversion trigger sources
z
On new available data
z
Events from the event system
High drive capabilities and support for
z
Resistive loads
z
Capacitive loads
z
Combined resistive and capacitive loads
z
Internal and external reference options
z
DAC output available as input to analog comparator and ADC
z
Low-power mode, with reduced drive strength
z
Optional DMA transfer of data
Overview
The digital-to-analog converter (DAC) converts digital values to voltages. The DAC has two channels, each with 12-bit
resolution, and is capable of converting up to one million samples per second (msps) on each channel. The built-in
calibration system can remove offset and gain error when loaded with calibration values from software.
Figure 29-1. DAC overview.
DMA req
(Data Empty)
CH0DATA
12
D
A
T
A
DAC0
Output
Driver
Int.
driver
AVCC
Internal 1.00V
AREFA
AREFB
Reference
selection
12
Enable
Select
CTRLB
Trigger
CH1DATA
DMA req
(Data Empty)
Trigger
D
A
T
A
CTRLA
Select
Enable
DAC1
To
AC/ADC
Internal Output
enable
Output
Driver
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A DAC conversion is automatically started when new data to be converted are available. Events from the event
system can also be used to trigger a conversion, and this enables synchronized and timed conversions between the
DAC and other peripherals, such as a timer/counter. The DMA controller can be used to transfer data to the DAC.
The DAC has high drive strength, and is capable of driving both resistive and capacitive loads, aswell as loads which
combine both. A low-power mode is available, which will reduce the drive strength of the output. Internal and external
voltage references can be used. The DAC output is also internally available for use as input to the analog comparator
or ADC.
PORTB has one DAC. Notation of this peripheral is DACB.
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30.
AC – Analog Comparator
30.1
Features
z Two Analog Comparators (ACs)
z Selectable propagation delay versus current consumption
z Selectable hysteresis
No
Small
z Large
z
z
z Analog comparator output available on pin
z Flexible input selection
All pins on the port
Output from the DAC
z Bandgap reference voltage
z A 64-level programmable voltage scaler of the internal AVCC voltage
z
z
z Interrupt and event generation on:
Rising edge
Falling edge
z Toggle
z
z
z Window function interrupt and event generation on:
Signal above window
Signal inside window
z Signal below window
z
z
z Constant current source with configurable output pin selection
30.2
Overview
The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this
comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several
different combinations of input change.
Two important properties of the analog comparator’s dynamic behavior are: hysteresis and propagation delay. Both of
these parameters may be adjusted in order to achieve the optimal operation for each application.
The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler.
The analog comparator output state can also be output on a pin for use by external devices.
A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example,
external resistors used to charge capacitors in capacitive touch sensing applications.
The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and
analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be
set in window mode to compare a signal to a voltage range instead of a voltage level.
PORTA has one AC pair. Notation is ACA.
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Figure 30-1. Analog comparator overview.
Pin Input
AC0OUT
Pin Input
Hysteresis
Enable
DAC
Voltage
Scaler
ACnMUXCTRL
ACnCTRL
Interrupt
Mode
WINCTRL
Enable
Bandgap
Interrupt
Sensititivity
Control
&
Window
Function
Interrupts
Events
Hysteresis
Pin Input
AC1OUT
Pin Input
The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in
Figure 30-2.
Figure 30-2. Analog comparator window function.
+
AC0
Upper limit of window
Interrupt
sensitivity
control
Input signal
Interrupts
Events
+
AC1
Lower limit of window
-
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31.
Programming and Debugging
31.1
Features
z Programming
External programming through PDI interface
z Minimal protocol overhead for fast operation
z Built-in error detection and handling for reliable operation
z Boot loader support for programming through any communication interface
z
z Debugging
z
z
z
z
z
z
Nonintrusive, real-time, on-chip debug system
No software or hardware resources required from device except pin connection
Program flow control
z Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor
Unlimited number of user program breakpoints
Unlimited number of user data breakpoints, break on:
z Data location read, write, or both read and write
z Data location content equal or not equal to a value
z Data location content is greater or smaller than a value
z Data location content is within or outside a range
No limitation on device clock frequency
z Program and Debug Interface (PDI)
Two-pin interface for external programming and debugging
Uses the Reset pin and a dedicated pin
z No I/O pins required during programming or debugging
z
z
31.2
Overview
The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip
debugging of a device.
The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the
user signature row.
Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any
software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete
program flow control and support for an unlimited number of program and complex data breakpoints. Application
debug can be done from a C or other high-level language source code level, as well as from an assembler and
disassembler level.
Programming and debugging can be done through the PDI physical layer. This is a two-pin interface that uses the
Reset pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). Any
external programmer or on-chip debugger/emulator can be directly connected to this interface.
32.
Pinout and Pin Functions
The device pinout is shown in “Pinout/Block Diagram” on page 4. In addition to general purpose I/O functionality, each
pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual
pin. Only one of the pin functions can be used at time.
32.1
Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
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32.1.1 Operation/Power Supply
VCC
Digital supply voltage
AVCC
Analog supply voltage
GND
Ground
32.1.2 Port Interrupt functions
SYNC
Port pin with full synchronous and limited asynchronous interrupt function
ASYNC
Port pin with full synchronous and full asynchronous interrupt function
32.1.3 Analog functions
ACn
Analog Comparator input pin n
ACnOUT
Analog Comparator n Output
ADCn
Analog to Digital Converter input pin n
DACn
Digital to Analog Converter output pin n
AREF
Analog Reference input pin
32.1.4 Timer/Counter and AWEX functions
OCnxLS
Output Compare Channel x Low Side for Timer/Counter n
OCnxHS
Output Compare Channel x High Side for Timer/Counter n
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32.1.5 Communication functions
SCL
Serial Clock for TWI
SDA
Serial Data for TWI
SCLIN
Serial Clock In for TWI when external driver interface is enabled
SCLOUT
Serial Clock Out for TWI when external driver interface is enabled
SDAIN
Serial Data In for TWI when external driver interface is enabled
SDAOUT
Serial Data Out for TWI when external driver interface is enabled
XCKn
Transfer Clock for USART n
RXDn
Receiver Data for USART n
TXDn
Transmitter Data for USART n
SS
Slave Select for SPI
MOSI
Master Out Slave In for SPI
MISO
Master In Slave Out for SPI
SCK
Serial Clock for SPI
D-
Data- for USB
D+
Data+ for USB
32.1.6 Oscillators, Clock and Event
TOSCn
Timer Oscillator pin n
XTALn
Input/Output for Oscillator pin n
CLKOUT
Peripheral Clock Output
EVOUT
Event Channel Output
RTCOUT
RTC Clock Source Output
32.1.7 Debug/System functions
RESET
Reset pin
PDI_CLK
Program and Debug Interface Clock pin
PDI_DATA
Program and Debug Interface Data pin
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32.2
Alternate Pin Functions
The tables below show the primary/default function for each pin on a port in the first column, the pin number in the
second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral
that enable and use the alternate pin functions.
For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under
the first table where this apply.
Table 32-1. Port A - alternate functions.
PORT A
PIN #
INTERRUPT
ADCA POS/
GAINPOS
ADCA NEG
ADCA
GAINNEG
ACA POS
ACA NEG
GND
38
AVCC
39
PA0
40
SYNC
ADC0
ADC0
AC0
AC0
PA1
41
SYNC
ADC1
ADC1
AC1
AC1
PA2
42
SYNC/ASYNC
ADC2
ADC2
AC2
PA3
43
SYNC
ADC3
ADC3
AC3
PA4
44
SYNC
ADC4
ADC4
AC4
PA5
1
SYNC
ADC5
ADC5
AC5
PA6
2
SYNC
ADC6
ADC6
AC6
PA7
3
SYNC
ADC7
ADC7
ACAOUT
REFA
AREF
AC3
AC5
AC1OUT
AC7
AC0OUT
Table 32-2. Port B - alternate functions.
PORT B
PIN #
INTERRUPT
ADCA POS
DACB
PB0
4
SYNC
ADC8
PB1
5
SYNC
ADC9
PB2
6
SYNC/ASYNC
ADC10
DAC0
PB3
7
SYNC
ADC11
DAC1
REFB
AREF
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Table 32-3. Port C - alternate functions.
PORT C
PIN #
INTERRUPT
TCC0
AWEXC
TCC1
(1)(2)
USART
C0(3)
USART
C1
SPIC(4)
TWIC
TWIC
w/ext
driver
GND
8
VCC
9
PC0
10
SYNC
OC0A
OC0ALS
PC1
11
SYNC
OC0B
OC0AHS
XCK0
PC2
12
SYNC/
ASYNC
OC0C
OC0BLS
RXD0
SDAOUT
PC3
13
SYNC
OC0D
OC0BHS
TXD0
SCLOUT
PC4
14
SYNC
OC0CLS
OC1A
PC5
15
SYNC
OC0CHS
OC1B
PC6
16
SYNC
PC7
17
SYNC
Notes:
1.
2.
3.
4.
5.
6.
SDAIN
SCL
SCLIN
EVENTOUT
(5)
(6)
SS
XCK1
MOSI
OC0DLS
RXD1
MISO
clkRTC
OC0DHS
TXD1
SCK
clkPER
EVOUT
Pin mapping of all TC0 can optionally be moved to high nibble of port
If TC0 is configured as TC2 all eight pins can be used for PWM output.
Pin mapping of all USART0 can optionally be moved to high nibble of port.
Pins MOSI and SCK for all SPI can optionally be swapped.
CLKOUT can optionally be moved between port C, D and E and between pin 4 and 7.
EVOUT can optionally be moved between port C, D and E and between pin 4 and 7.
Table 32-4.
PORT D
SDA
CLOCKOUT
PIN #
Port D - alternate functions.
INTERRUPT
TCD0
TCD1
USB
USARTD0
GND
18
VCC
19
PD0
20
SYNC
OC0A
PD1
21
SYNC
OC0B
XCK0
PD2
22
SYNC/ASYNC
OC0C
RXD0
PD3
23
SYNC
OC0D
TXD0
PD4
24
SYNC
OC1A
PD5
25
SYNC
OC1B
PD6
26
SYNC
PD7
27
SYNC
USARTD1
SPID
CLOCKOUT
EVENTOUT
clkPER
EVOUT
SS
XCK1
MOSI
D-
RXD1
MISO
D+
TXD1
SCK
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Table 32-5. Port E - alternate functions.
PORT E
PIN #
INTERRUPT
TCE0
USARTE0
PE0
28
SYNC
OC0A
PE1
29
SYNC
OC0B
XCK0
GND
30
VCC
31
PE2
32
SYNC/ASYNC
OC0C
RXD0
PE3
33
SYNC
OC0D
TXD0
TWIE
SDA
SCL
Table 32-6. Port R - alternate functions.
PORT R
PIN #
INTERRUPT
PDI
XTAL
TOSC(1)
PDI
34
PDI_DATA
RESET
35
PDI_CLOCK
PR0
36
SYNC
XTAL2
TOSC2
PR1
37
SYNC
XTAL1
TOSC1
Note:
1.
TOSC pins can optionally be moved to PE2/PE3.
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33.
Peripheral Module Address Map
The address maps show the base address for each peripheral and module in Atmel AVR XMEGA A4U. For complete
register description and summary for each peripheral module, refer to the XMEGA AU manual.
Table 33-1. Peripheral module address map.
Base address
Name
Description
0x0000
GPIO
General Purpose IO Registers
0x0010
VPORT0
Virtual Port 0
0x0014
VPORT1
Virtual Port 1
0x0018
VPORT2
Virtual Port 2
0x001C
VPORT3
Virtual Port 2
0x0030
CPU
CPU
0x0040
CLK
Clock Control
0x0048
SLEEP
Sleep Controller
0x0050
OSC
Oscillator Control
0x0060
DFLLRC32M
DFLL for the 32MHz Internal RC Oscillator
0x0068
DFLLRC2M
DFLL for the 2MHz RC Oscillator
0x0070
PR
Power Reduction
0x0078
RST
Reset Controller
0x0080
WDT
Watch-Dog Timer
0x0090
MCU
MCU Control
0x00A0
PMIC
Programmable MUltilevel Interrupt Controller
0x00B0
PORTCFG
0x00C0
AES
AES Module
0x00D0
CRC
CRC Module
0x0100
DMA
DMA Module
0x0180
EVSYS
Event System
0x01C0
NVM
Non Volatile Memory (NVM) Controller
0x0200
ADCA
Analog to Digital Converter on port A
0x0380
ACA
Analog Comparator pair on port A
0x0400
RTC
Real Time Counter
0x0480
TWIC
Two Wire Interface on port C
0x04A0
TWIE
Two Wire Interface on port E
0x04C0
USB
Universal Serial Bus Interface
0x0600
PORTA
Port Configuration
Port A
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Base address
Name
Description
0x0620
PORTB
Port B
0x0640
PORTC
Port C
0x0660
PORTD
Port D
0x0680
PORTE
Port E
0x07E0
PORTR
Port R
0x0800
TCC0
Timer/Counter 0 on port C
0x0840
TCC1
Timer/Counter 1 on port C
0x0880
AWEXC
Advanced Waveform Extension on port C
0x0890
HIRESC
High Resolution Extension on port C
0x08A0
USARTC0
USART 0 on port C
0x08B0
USARTC1
USART 1 on port C
0x08C0
SPIC
0x08F8
IRCOM
0x0900
TCD0
Timer/Counter 0 on port D
0x0940
TCD1
Timer/Counter 1 on port D
0x0990
HIRESD
0x09A0
USARTD0
USART 0 on port D
0x09B0
USARTD1
USART 1 on port D
0x09C0
SPID
Serial Peripheral Interface on port D
0x0A00
TCE0
Timer/Counter 0 on port E
0x0A80
AWEXE
Advanced Waveform Extensionon port E
0x0A90
HIRESE
High Resolution Extension on port E
0x0AA0
USARTE0
Serial Peripheral Interface on port C
Infrared Communication Module
High Resolution Extension on port D
USART 0 on port E
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34.
Instruction Set Summary
Mnemonic
s
Operand
s
Description
Operation
Flags
#Clock
s
Arithmetic and Logic Instructions
ADD
Rd, Rr
Add without Carry
Rd
←
Rd + Rr
Z,C,N,V,S,H
1
ADC
Rd, Rr
Add with Carry
Rd
←
Rd + Rr + C
Z,C,N,V,S,H
1
ADIW
Rd, K
Add Immediate to Word
Rd
←
Rd + 1:Rd + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract without Carry
Rd
←
Rd - Rr
Z,C,N,V,S,H
1
SUBI
Rd, K
Subtract Immediate
Rd
←
Rd - K
Z,C,N,V,S,H
1
SBC
Rd, Rr
Subtract with Carry
Rd
←
Rd - Rr - C
Z,C,N,V,S,H
1
SBCI
Rd, K
Subtract Immediate with Carry
Rd
←
Rd - K - C
Z,C,N,V,S,H
1
SBIW
Rd, K
Subtract Immediate from Word
Rd + 1:Rd
←
Rd + 1:Rd - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND
Rd
←
Rd • Rr
Z,N,V,S
1
ANDI
Rd, K
Logical AND with Immediate
Rd
←
Rd • K
Z,N,V,S
1
OR
Rd, Rr
Logical OR
Rd
←
Rd v Rr
Z,N,V,S
1
ORI
Rd, K
Logical OR with Immediate
Rd
←
Rd v K
Z,N,V,S
1
EOR
Rd, Rr
Exclusive OR
Rd
←
Rd ⊕ Rr
Z,N,V,S
1
COM
Rd
One’s Complement
Rd
←
$FF - Rd
Z,C,N,V,S
1
NEG
Rd
Two’s Complement
Rd
←
$00 - Rd
Z,C,N,V,S,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd
←
Rd v K
Z,N,V,S
1
CBR
Rd,K
Clear Bit(s) in Register
Rd
←
Rd • ($FFh - K)
Z,N,V,S
1
INC
Rd
Increment
Rd
←
Rd + 1
Z,N,V,S
1
DEC
Rd
Decrement
Rd
←
Rd - 1
Z,N,V,S
1
TST
Rd
Test for Zero or Minus
Rd
←
Rd • Rd
Z,N,V,S
1
CLR
Rd
Clear Register
Rd
←
Rd ⊕ Rd
Z,N,V,S
1
SER
Rd
Set Register
Rd
←
$FF
None
1
MUL
Rd,Rr
Multiply Unsigned
R1:R0
←
Rd x Rr (UU)
Z,C
2
MULS
Rd,Rr
Multiply Signed
R1:R0
←
Rd x Rr (SS)
Z,C
2
MULSU
Rd,Rr
Multiply Signed with Unsigned
R1:R0
←
Rd x Rr (SU)
Z,C
2
FMUL
Rd,Rr
Fractional Multiply Unsigned
R1:R0
←
Rd x Rr<<1 (UU)
Z,C
2
FMULS
Rd,Rr
Fractional Multiply Signed
R1:R0
←
Rd x Rr<<1 (SS)
Z,C
2
FMULSU
Rd,Rr
Fractional Multiply Signed with Unsigned
R1:R0
←
Rd x Rr<<1 (SU)
Z,C
2
DES
K
Data Encryption
if (H = 0) then R15:R0
else if (H = 1) then R15:R0
←
←
Encrypt(R15:R0, K)
Decrypt(R15:R0, K)
PC
←
PC + k + 1
None
2
1/2
Branch instructions
RJMP
k
Relative Jump
IJMP
Indirect Jump to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
0
None
2
EIJMP
Extended Indirect Jump to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
EIND
None
2
PC
←
k
None
3
JMP
k
Jump
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Mnemonic
s
Operand
s
Description
RCALL
k
Relative Call Subroutine
Operation
Flags
#Clock
s
PC
←
PC + k + 1
None
2 / 3 (1)
ICALL
Indirect Call to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
0
None
2 / 3 (1)
EICALL
Extended Indirect Call to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
EIND
None
3 (1)
call Subroutine
PC
←
k
None
3 / 4 (1)
RET
Subroutine Return
PC
←
STACK
None
4 / 5 (1)
RETI
Interrupt Return
PC
←
STACK
I
4 / 5 (1)
if (Rd = Rr) PC
←
PC + 2 or 3
None
1/2/3
CALL
k
CPSE
Rd,Rr
Compare, Skip if Equal
CP
Rd,Rr
Compare
CPC
Rd,Rr
Compare with Carry
CPI
Rd,K
Compare with Immediate
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b) = 0) PC
←
PC + 2 or 3
None
1/2/3
SBRS
Rr, b
Skip if Bit in Register Set
if (Rr(b) = 1) PC
←
PC + 2 or 3
None
1/2/3
SBIC
A, b
Skip if Bit in I/O Register Cleared
if (I/O(A,b) = 0) PC
←
PC + 2 or 3
None
2/3/4
SBIS
A, b
Skip if Bit in I/O Register Set
If (I/O(A,b) =1) PC
←
PC + 2 or 3
None
2/3/4
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC
←
PC + k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC
←
PC + k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC
←
PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC
←
PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC
←
PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC
←
PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC
←
PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC
←
PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC
←
PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC
←
PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC
←
PC + k + 1
None
1/2
BRLT
k
Branch if Less Than, Signed
if (N ⊕ V= 1) then PC
←
PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC
←
PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC
←
PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC
←
PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC
←
PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC
←
PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC
←
PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if (I = 1) then PC
←
PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if (I = 0) then PC
←
PC + k + 1
None
1/2
←
Rr
None
1
Rd - Rr
Z,C,N,V,S,H
1
Rd - Rr - C
Z,C,N,V,S,H
1
Rd - K
Z,C,N,V,S,H
1
Data transfer instructions
MOV
Rd, Rr
Copy Register
Rd
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Mnemonic
s
Operand
s
Description
MOVW
Rd, Rr
Copy Register Pair
LDI
Rd, K
LDS
Operation
Flags
#Clock
s
Rd+1:Rd
←
Rr+1:Rr
None
1
Load Immediate
Rd
←
K
None
1
Rd, k
Load Direct from data space
Rd
←
(k)
None
2 (1)(2)
LD
Rd, X
Load Indirect
Rd
←
(X)
None
1 (1)(2)
LD
Rd, X+
Load Indirect and Post-Increment
Rd
X
←
←
(X)
X+1
None
1 (1)(2)
LD
Rd, -X
Load Indirect and Pre-Decrement
X ← X - 1,
Rd ← (X)
←
←
X-1
(X)
None
2 (1)(2)
LD
Rd, Y
Load Indirect
Rd ← (Y)
←
(Y)
None
1 (1)(2)
LD
Rd, Y+
Load Indirect and Post-Increment
Rd
Y
←
←
(Y)
Y+1
None
1 (1)(2)
LD
Rd, -Y
Load Indirect and Pre-Decrement
Y
Rd
←
←
Y-1
(Y)
None
2 (1)(2)
LDD
Rd, Y+q
Load Indirect with Displacement
Rd
←
(Y + q)
None
2 (1)(2)
LD
Rd, Z
Load Indirect
Rd
←
(Z)
None
1 (1)(2)
LD
Rd, Z+
Load Indirect and Post-Increment
Rd
Z
←
←
(Z),
Z+1
None
1 (1)(2)
LD
Rd, -Z
Load Indirect and Pre-Decrement
Z
Rd
←
←
Z - 1,
(Z)
None
2 (1)(2)
LDD
Rd, Z+q
Load Indirect with Displacement
Rd
←
(Z + q)
None
2 (1)(2)
STS
k, Rr
Store Direct to Data Space
(k)
←
Rd
None
2 (1)
ST
X, Rr
Store Indirect
(X)
←
Rr
None
1 (1)
ST
X+, Rr
Store Indirect and Post-Increment
(X)
X
←
←
Rr,
X+1
None
1 (1)
ST
-X, Rr
Store Indirect and Pre-Decrement
X
(X)
←
←
X - 1,
Rr
None
2 (1)
ST
Y, Rr
Store Indirect
(Y)
←
Rr
None
1 (1)
ST
Y+, Rr
Store Indirect and Post-Increment
(Y)
Y
←
←
Rr,
Y+1
None
1 (1)
ST
-Y, Rr
Store Indirect and Pre-Decrement
Y
(Y)
←
←
Y - 1,
Rr
None
2 (1)
STD
Y+q, Rr
Store Indirect with Displacement
(Y + q)
←
Rr
None
2 (1)
ST
Z, Rr
Store Indirect
(Z)
←
Rr
None
1 (1)
ST
Z+, Rr
Store Indirect and Post-Increment
(Z)
Z
←
←
Rr
Z+1
None
1 (1)
ST
-Z, Rr
Store Indirect and Pre-Decrement
Z
←
Z-1
None
2 (1)
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q)
←
Rr
None
2 (1)
Load Program Memory
R0
←
(Z)
None
3
LPM
LPM
Rd, Z
Load Program Memory
Rd
←
(Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Increment
Rd
Z
←
←
(Z),
Z+1
None
3
Extended Load Program Memory
R0
←
(RAMPZ:Z)
None
3
Extended Load Program Memory
Rd
←
(RAMPZ:Z)
None
3
ELPM
ELPM
Rd, Z
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Mnemonic
s
Operand
s
ELPM
Rd, Z+
SPM
Description
Operation
Flags
#Clock
s
Rd
Z
←
←
(RAMPZ:Z),
Z+1
None
3
Store Program Memory
(RAMPZ:Z)
←
R1:R0
None
-
(RAMPZ:Z)
Z
←
←
R1:R0,
Z+2
None
-
Rd
←
I/O(A)
None
1
I/O(A)
←
Rr
None
1
STACK
←
Rr
None
1 (1)
Extended Load Program Memory and PostIncrement
SPM
Z+
Store Program Memory and Post-Increment
by 2
IN
Rd, A
In From I/O Location
OUT
A, Rr
Out To I/O Location
PUSH
Rr
Push Register on Stack
POP
Rd
Pop Register from Stack
Rd
←
STACK
None
2 (1)
XCH
Z, Rd
Exchange RAM location
Temp
Rd
(Z)
←
←
←
Rd,
(Z),
Temp
None
2
LAS
Z, Rd
Load and Set RAM location
Temp
Rd
(Z)
←
←
←
Rd,
(Z),
Temp v (Z)
None
2
LAC
Z, Rd
Load and Clear RAM location
Temp
Rd
(Z)
←
←
←
Rd,
(Z),
($FFh – Rd) z (Z)
None
2
LAT
Z, Rd
Load and Toggle RAM location
Temp
Rd
(Z)
←
←
←
Rd,
(Z),
Temp ⊕ (Z)
None
2
Rd(n+1)
Rd(0)
C
←
←
←
Rd(n),
0,
Rd(7)
Z,C,N,V,H
1
Rd(n)
Rd(7)
C
←
←
←
Rd(n+1),
0,
Rd(0)
Z,C,N,V
1
Rd(0)
Rd(n+1)
C
←
←
←
C,
Rd(n),
Rd(7)
Z,C,N,V,H
1
Bit and bit-test instructions
LSL
Rd
Logical Shift Left
LSR
Rd
Logical Shift Right
ROL
Rd
Rotate Left Through Carry
ROR
Rd
Rotate Right Through Carry
Rd(7)
Rd(n)
C
←
←
←
C,
Rd(n+1),
Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n)
←
Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)
↔
Rd(7..4)
None
1
BSET
s
Flag Set
SREG(s)
←
1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s)
←
0
SREG(s)
1
SBI
A, b
Set Bit in I/O Register
I/O(A, b)
←
1
None
1
CBI
A, b
Clear Bit in I/O Register
I/O(A, b)
←
0
None
1
BST
Rr, b
Bit Store from Register to T
T
←
Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b)
←
T
None
1
SEC
Set Carry
C
←
1
C
1
CLC
Clear Carry
C
←
0
C
1
SEN
Set Negative Flag
N
←
1
N
1
CLN
Clear Negative Flag
N
←
0
N
1
SEZ
Set Zero Flag
Z
←
1
Z
1
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Mnemonic
s
Operand
s
Description
Operation
Flags
#Clock
s
Z
←
0
Z
1
Global Interrupt Enable
I
←
1
I
1
CLI
Global Interrupt Disable
I
←
0
I
1
SES
Set Signed Test Flag
S
←
1
S
1
CLS
Clear Signed Test Flag
S
←
0
S
1
SEV
Set Two’s Complement Overflow
V
←
1
V
1
CLV
Clear Two’s Complement Overflow
V
←
0
V
1
SET
Set T in SREG
T
←
1
T
1
CLT
Clear T in SREG
T
←
0
T
1
SEH
Set Half Carry Flag in SREG
H
←
1
H
1
CLH
Clear Half Carry Flag in SREG
H
←
0
H
1
None
1
None
1
CLZ
Clear Zero Flag
SEI
MCU control instructions
BREAK
Break
NOP
No Operation
SLEEP
Sleep
(see specific descr. for Sleep)
None
1
WDR
Watchdog Reset
(see specific descr. for WDR)
None
1
Notes:
1.
2.
(See specific descr. for BREAK)
Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.
One extra cycle must be added when accessing Internal SRAM.
XMEGA A4U [DATASHEET]
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35.
Packaging information
35.1
44A
PIN 1 IDENTIFIER
PIN 1
e
B
E1
E
A1
A2
D1
D
C
0°~7°
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
11.75
12.00
12.25
D1
9.90
10.00
10.10
E
11.75
12.00
12.25
E1
9.90
10.00
10.10
B
0.30
0.37
0.45
C
0.09
(0.17)
0.20
L
0.45
0.60
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
06/02/2014
44A, 44-lead, 10 x 10mm body size, 1.0mm body thickness,
0.8 mm lead pitch, thin profile plastic quad flat package (TQFP)
44A
C
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35.2
PW
XMEGA A4U [DATASHEET]
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69
35.3
44M1
D
Marked Pin# 1 I D
E
SE ATING PLAN E
A1
TOP VIE W
A3
A
K
L
Pin #1 Co rner
D2
1
2
3
SIDE VIEW
Pin #1
Triangle
Option A
E2
Option B
K
Option C
b
e
Pin #1
Cham fer
(C 0.30)
Pin #1
Notch
(0.20 R)
B OT TOM VIE W
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
A
0.80
0.90
1.00
A1
–
0.02
0.05
A3
0.20 REF
b
0.18
0.23
0.30
D
6.90
7.00
7.10
D2
5.00
5.20
5.40
E
6.90
7.00
7.10
E2
5.00
5.20
5.40
e
Note: JEDEC Standard MO-220, Fig
. 1 (S AW Singulation) VKKD-3 .
NOT E
0.50 BSC
L
0.59
0.64
0.69
K
0.20
0.26
0.41
02/13/2014
Package Drawing Contact:
[email protected]
TITLE
44M1, 44-pad, 7 x 7 x 1.0mm body, lead
pitch 0.50mm, 5.20mm exposed pad, thermally
enhanced plastic very thin quad flat no
lead package (VQFN)
GPC
ZWS
DRAWING NO.
44M1
XMEGA A4U [DATASHEET]
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REV.
H
70
35.4
49C2
E
A1 BALL ID
0.10
D
A1
TOP VIEW
A
A2
SIDE VIEW
E1
G
e
F
E
D
D1
COMMON DIMENSIONS
(Unit of Measure = mm)
C
B
1
A1 BALL CORNER
MIN
NOM
MAX
A
–
–
1.00
A1
0.20
–
–
A2
0.65
–
–
D
4.90
5.00
5.10
SYMBOL
A
2
3
4
5
b
6
7
e
49 - Ø0.35 ±0.05
BOTTOM VIEW
D1
3.90 BSC
E 4.90
5.00
5.10
E1
b
NOTE
3.90 BSC
0.30
0.35
e
0.40
0.65 BSC
3/14/08
TITLE
49C2, 49-ball (7 x 7 array), 0.65mm pitch,
Package Drawing Contact:
[email protected] 5.0 x 5.0 x 1.0mm, very thin, fine-pitch
ball grid array package (VFBGA)
GPC
CBD
DRAWING NO.
49C2
XMEGA A4U [DATASHEET]
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REV.
A
71
36.
Electrical Characteristics
All typical values are measured at T = 25°C unless other temperature condition is given. All minimum and maximum
values are valid across operating temperature and voltage unless other conditions are given.
36.1
ATxmega16A4U
36.1.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 36-1 may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 36-1. Absolute maximum ratings.
Symbol
Parameter
Condition
Min.
Typ.
-0.3
Max.
Units
4
V
VCC
Power supply voltage
IVCC
Current into a VCC pin
200
mA
IGND
Current out of a Gnd pin
200
mA
VPIN
Pin voltage with respect to Gnd and VCC
-0.5
VCC+0.5
V
IPIN
I/O pin sink/source current
-25
25
mA
TA
Storage temperature
-65
150
°C
Tj
Junction temperature
150
°C
36.1.2 General Operating Ratings
The device must operate within the ratings listed in Table 36-2 in order for all other electrical characteristics and
typical characteristics of the device to be valid.
Table 36-2. General operating conditions.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VCC
Power supply voltage
1.60
3.6
V
AVCC
Analog supply voltage
1.60
3.6
V
TA
Temperature range
-40
85
°C
Tj
Junction temperature
-40
105
°C
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Table 36-3. Operating voltage and frequency.
Symbol
ClkCPU
Parameter
Condition
CPU clock frequency
Min.
Typ.
Max.
VCC = 1.6V
0
12
VCC = 1.8V
0
12
VCC = 2.7V
0
32
VCC = 3.6V
0
32
Units
MHz
The maximum CPU clock frequency depends on VCC. As shown in Figure 36-1 the Frequency vs. VCC curve is linear
between 1.8V < VCC < 2.7V.
Figure 36-1. Maximum Frequency vs. VCC.
MHz
32
Safe Operating Area
12
1.6 1.8
2.7
3.6
V
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36.1.3 Current consumption
Table 36-4. Current consumption for Active mode and sleep modes.
Symbol
Parameter
Condition
Min.
32kHz, Ext. Clk
Active power
consumption (1)
1MHz, Ext. Clk
2MHz, Ext. Clk
VCC = 3.0V
80
VCC = 1.8V
230
VCC = 3.0V
480
VCC = 1.8V
430
600
0.9
1.4
9.6
12
VCC = 3.0V
3.9
VCC = 1.8V
62
VCC = 3.0V
118
VCC = 1.8V
125
225
240
350
3.8
5.5
0.1
1.0
1.2
4.5
T = 105°C
3.5
6.0
WDT and Sampled BOD enabled,
T = 25°C
1.3
3.0
2.4
6.0
4.5
8.0
1MHz, Ext. Clk
VCC = 3.0V
32MHz, Ext. Clk
T = 25°C
T = 85°C
Power-down power
consumption
VCC = 3.0V
WDT and Sampled BOD enabled,
T = 85°C
VCC = 3.0V
WDT and Sampled BOD enabled,
T = 105°C
Power-save power
consumption (2)
Reset power consumption
Notes:
1.
2.
Units
µA
2.4
2MHz, Ext. Clk
ICC
40
VCC = 1.8V
32kHz, Ext. Clk
Idle power
consumption (1)
Max.
VCC = 1.8V
VCC = 3.0V
32MHz, Ext. Clk
Typ.
mA
µA
RTC from ULP clock, WDT and sampled
BOD enabled, T = 25°C
VCC = 1.8V
1.2
VCC = 3.0V
1.3
RTC from 1.024kHz low power
32.768kHz TOSC, T = 25°C
VCC = 1.8V
0.6
2.0
VCC = 3.0V
0.7
2.0
RTC from low power 32.768kHz TOSC,
T = 25°C
VCC = 1.8V
0.8
3.0
VCC = 3.0V
1.0
3.0
Current through RESET pin substracted
VCC = 3.0V
320
mA
µA
µA
µA
All Power Reduction Registers set.
Maximum limits are based on characterization, and not tested in production.
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Table 36-5. Current consumption for modules and peripherals.
Symbol
Parameter
Condition (1)
Min.
Max.
Units
ULP oscillator
1.0
µA
32.768kHz int. oscillator
27
µA
2MHz int. oscillator
32MHz int. oscillator
PLL
85
DFLL enabled with 32.768kHz int. osc. as reference
BOD
µA
115
270
DFLL enabled with 32.768kHz int. osc. as reference
20x multiplication factor,
32MHz int. osc. DIV4 as reference
Watchdog timer
ICC
Typ.
µA
460
220
µA
1.0
µA
Continuous mode
138
Sampled mode, includes ULP oscillator
1.2
µA
Internal 1.0V reference
100
µA
Temperature sensor
95
µA
3.0
ADC
DAC
AC
DMA
250ksps
VREF = Ext ref
250ksps
VREF = Ext ref
No load
CURRLIMIT = LOW
2.6
CURRLIMIT = MEDIUM
2.1
CURRLIMIT = HIGH
1.6
Normal mode
1.9
Low Power mode
1.1
330
Low power mode
130
615kbps between I/O registers and SRAM
108
µA
16
µA
2.5
µA
Rx and Tx enabled, 9600 BAUD
Flash memory and EEPROM programming
Note:
1.
mA
High speed mode
Timer/counter
USART
mA
4.0
µA
8.0
mA
All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external
clock without prescaling, T = 25°C unless other conditions are given.
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36.1.4 Wake-up time from sleep modes
Table 36-6.
Symbol
Device wake-up time from sleep modes with various system clock sources.
Parameter
Wake-up time from idle,
standby, and extended standby
mode
twakeup
Wake-up time from power-save
and power-down mode
Note:
1.
Condition
Min.
Typ. (1)
External 2MHz clock
2.0
32.768kHz internal oscillator
120
2MHz internal oscillator
2.0
32MHz internal oscillator
0.2
External 2MHz clock
4.5
32.768kHz internal oscillator
320
2MHz internal oscillator
9.0
32MHz internal oscillator
5.0
Max.
Units
µs
The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-2. All peripherals and modules
start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 36-2. Wake-up time definition.
Wakeup time
Wakeup request
Clock output
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36.1.5 I/O Pin Characteristics
The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 36-7. I/O pin characteristics.
Symbol
IOH (1)/
IOL (2)
Parameter
Condition
Max.
Units
-20
20
mA
VCC = 2.7 - 3.6V
2.0
VCC+0.3
VCC = 2.0 - 2.7V
0.7*VCC
VCC+0.3
VCC = 1.6 - 2.0V
0.8*VCC
VCC+0.3
VCC = 2.7- 3.6V
-0.3
0.8
VCC = 2.0 - 2.7V
-0.3
0.3*VCC
VCC = 1.6 - 2.0V
-0.3
0.2*VCC
I/O pin source/sink current
VIH
High level input voltage
VIL
Low level input voltage
VCC = 3.0 - 3.6V
High level output voltage
2.4
0.94*VCC
IOH = -1mA
2.0
0.96*VCC
IOH = -2mA
1.7
0.92*VCC
VCC = 3.3V
IOH = -8mA
2.6
2.9
VCC = 3.0V
IOH = -6mA
2.1
2.6
VCC = 1.8V
IOH = -2mA
1.4
1.6
VCC = 3.0 - 3.6V
IOL = 2mA
0.05*VCC
0.4
IOL = 1mA
0.03*VCC
0.4
IOL = 2mA
0.06*VCC
0.7
VCC = 3.3V
IOL = 15mA
0.4
0.76
VCC = 3.0V
IOL = 10mA
0.3
0.64
VCC = 1.8V
IOL = 5mA
0.2
0.46
<0.01
0.1
VCC = 2.3 - 2.7V
VOL
Low level output voltage
IIN
Input leakage current
RP
Pull/buss keeper resistor
tr
Notes:
Rise time
1.
2.
Typ.
IOH = -2mA
VCC = 2.3 - 2.7V
VOH
Min.
T = 25°C
4.0
slew rate limitation
V
V
24
No load
V
7.0
V
µA
kΩ
ns
The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC must not exceed 200mA.
The sum of all IOH for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.
The sum of all IOH for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.
The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC must not exceed 200mA.
The sum of all IOL for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.
The sum of all IOL for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.
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36.1.6 ADC characteristics
Table 36-8. Power supply, reference and input range.
Symbol
Parameter
AVCC
Analog supply voltage
VREF
Reference voltage
Condition
Min.
Typ.
Max.
Units
VCC- 0.3
VCC+ 0.3
V
1.0
AVCC- 0.6
V
Rin
Input resistance
Switched
4.0
kΩ
Csample
Input capacitance
Switched
4.4
pF
RAREF
Reference input resistance
(leakage only)
>10
MΩ
CAREF
Reference input capacitance
Static load
7.0
pF
VIN
Input range
∆V
Conversion range
Differential mode, Vinp - Vinn
Conversion range
Single ended unsigned mode, Vinp
-0.1
AVCC+0.1
V
-VREF
VREF
V
-ΔV
VREF-ΔV
V
Fixed offset voltage
190
LSB
Table 36-9. Clock and timing.
Symbol
ClkADC
fADC
Parameter
Condition
Min.
Typ.
Max.
Units
Maximum is 1/4 of peripheral clock
frequency
100
2000
Measuring internal signals
100
125
Current limitation (CURRLIMIT) off
100
2000
CURRLIMIT = LOW
100
1500
CURRLIMIT = MEDIUM
100
1000
CURRLIMIT = HIGH
100
500
Sampling time
1/2 ClkADC cycle
0.25
5
µs
Conversion time (latency)
(RES+2)/2+(GAIN !=0)
RES (Resolution) = 8 or 12
5
8
ClkADC
cycles
Start-up time
ADC clock cycles
12
24
ClkADC
cycles
After changing reference or input mode
7
7
After ADC flush
1
1
ADC Clock frequency
Sample rate
ADC settling time
XMEGA A4U [DATASHEET]
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kHz
ksps
ClkADC
cycles
78
Table 36-10. Accuracy characteristics.
Symbol
Parameter
Condition (2)
RES
Resolution
Programmable to 8 or 12 bit
Min.
Typ.
Max.
Units
8
12
12
Bits
VCC-1.0V < VREF< VCC-0.6V
±1.2
±2.0
All VREF
±1.5
±3.0
VCC-1.0V < VREF< VCC-0.6V
±1.0
±2.0
All VREF
±1.5
±3.0
guaranteed monotonic
<±0.8
<±1.0
500ksps
INL (1)
Integral non-linearity
2000ksps
DNL (1)
Differential non-linearity
Offset error
mV
Temperature drift
<0.01
mV/K
Operating voltage drift
<0.6
mV/V
External reference
-1.0
AVCC/1.6
10
AVCC/2.0
8.0
Bandgap
±5.0
Gain error
Notes:
1.
2.
lsb
-1.0
Differential
mode
Noise
lsb
mV
Temperature drift
<0.02
mV/K
Operating voltage drift
<0.5
mV/V
Differential mode, shorted input
2msps, VCC = 3.6V, ClkPER = 16MHz
0.4
mV
rms
Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Table 36-11. Gain stage characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Rin
Input resistance
Switched in normal mode
4.0
kΩ
Csample
Input capacitance
Switched in normal mode
4.4
pF
Signal range
Gain stage output
Propagation delay
ADC conversion rate
Sample rate
Same as ADC
INL (1)
Integral non-linearity
Gain error
0
VCC- 0.6
ClkADC
cycles
1.0
100
All gain
settings
500ksps
±1.5
1x gain, normal mode
-0.8
8x gain, normal mode
-2.5
64x gain, normal mode
-3.5
V
1000
kHz
±4
lsb
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%
79
Symbol
Parameter
Offset error,
input referred
Condition
Min.
Typ.
1x gain, normal mode
-2
8x gain, normal mode
-5
64x gain, normal mode
-4
1x gain, normal mode
Noise
1.
Units
mV
0.5
VCC = 3.6V
Ext. VREF
8x gain, normal mode
mV
rms
1.5
64x gain, normal mode
Note:
Max.
11
Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
36.1.7 DAC Characteristics
Table 36-12. Power supply, reference and output range.
Symbol
Parameter
AVCC
Analog supply voltage
AVREF
External reference voltage
Rchannel
DC output impedance
Condition
Linear output voltage range
RAREF
CAREF
Min.
Max.
Units
VCC0.3
VCC+ 0.3
V
1.0
VCC- 0.6
V
50
Ω
AVCC-0.15
V
0.15
Reference input resistance
Reference input capacitance
Static load
Minimum resistance load
Maximum capacitance load
Output sink/source
Typ.
>10
MΩ
7
pF
1.0
1000Ω serial resistance
Operating within accuracy specification
Safe operation
kΩ
100
pF
1.0
nF
AVCC/1000
10
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mA
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Table 36-13. Clock and timing.
Symbol
fDAC
Parameter
Conversion rate
Condition
Cload=100pF,
maximum step size
Min.
Normal mode
Typ.
0
Max.
1000
Low power mode
500
Units
ksps
Table 36-14. Accuracy characteristics.
Symbol
RES
Parameter
Condition
Typ.
Input resolution
VREF= Ext 1.0V
INL (1)
Integral non-linearity
VREF=AVCC
VREF=INT1V
VREF=Ext 1.0V
DNL (1)
Differential non-linearity
VREF=AVCC
VREF=INT1V
Gain error
After calibration
Gain calibration step size
1.
Max.
Units
12
Bits
VCC = 1.6V
±2.0
±3
VCC = 3.6V
±1.5
±2.5
VCC = 1.6V
±2.0
±4
VCC = 3.6V
±1.5
±4
VCC = 1.6V
±5.0
VCC = 3.6V
±5.0
VCC = 1.6V
±1.5
3.0
VCC = 3.6V
±0.6
1.5
VCC = 1.6V
±1.0
3.5
VCC = 3.6V
±0.6
1.5
VCC = 1.6V
±4.5
VCC = 3.6V
±4.5
lsb
lsb
<4.0
lsb
4.0
lsb
Gain calibration drift
VREF= Ext 1.0V
<0.2
mV/K
Offset error
After calibration
<1.0
lsb
Offset calibration step size
Note:
Min.
1.0
Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.
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36.1.8 Analog Comparator Characteristics
Table 36-15. Analog Comparator characteristics.
Symbol
Voff
Ilk
Parameter
Condition
Min.
Typ.
Max.
Units
Input offset voltage
<±10
mV
Input leakage current
<1.0
nA
Input voltage range
-0.1
AVCC
V
AC startup time
100
µs
Vhys1
Hysteresis, none
0
mV
Vhys2
Hysteresis, small
Vhys3
Hysteresis, large
mode = High Speed (HS)
13
mode = Low Power (LP)
30
mode = HS
30
mode = LP
60
VCC = 3.0V, T= 85°C
tdelay
Propagation delay
mode = HS
30
mode = HS
VCC = 3.0V, T= 85°C
mV
90
30
mode = LP
130
mode = LP
64-level voltage scaler
mV
500
ns
130
Integral non-linearity (INL)
0.3
0.5
lsb
36.1.9 Bandgap and Internal 1.0V Reference Characteristics
Table 36-16. Bandgap and Internal 1.0V reference characteristics.
Symbol
Parameter
Startup time
Condition
Min.
As reference for ADC or DAC
Max.
1 ClkPER + 2.5µs
As input voltage to ADC and AC
1.1
Internal 1.00V reference
T= 85°C, after calibration
Variation over voltage and temperature
Relative to T= 85°C, VCC = 3.0V
0.99
1.0
Units
µs
1.5
Bandgap voltage
INT1V
Typ.
V
1.01
±1.5
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%
82
36.1.10 Brownout Detection Characteristics
Table 36-17. Brownout detection characteristics.
Symbol
Parameter
Condition
BOD level 0 falling VCC
VBOT
tBOD
Typ.
Max.
1.60
1.62
1.72
BOD level 1 falling VCC
1.8
BOD level 2 falling VCC
2.0
BOD level 3 falling VCC
2.2
BOD level 4 falling VCC
2.4
BOD level 5 falling VCC
2.6
BOD level 6 falling VCC
2.8
BOD level 7 falling VCC
3.0
Continuous mode
Detection time
VHYST
Min.
V
0.4
Sampled mode
µs
1000
Hysteresis
Units
1.2
%
36.1.11 External Reset Characteristics
Table 36-18. External reset characteristics.
Symbol
tEXT
Parameter
Condition
Min.
Minimum reset pulse width
Reset threshold voltage (VIH)
VRST
Reset threshold voltage (VIL)
RRST
Typ.
Max.
Units
95
1000
ns
VCC = 2.7 - 3.6V
0.60×VCC
VCC = 1.6 - 2.7V
0.60×VCC
VCC = 2.7 - 3.6V
0.50×VCC
VCC = 1.6 - 2.7V
0.40×VCC
Reset pin Pull-up Resistor
V
25
kΩ
36.1.12 Power-on Reset Characteristics
Table 36-19. Power-on reset characteristics.
Symbol
Parameter
VPOT- (1)
POR threshold voltage falling VCC
VPOT+
POR threshold voltage rising VCC
Note:
1.
Condition
Min.
Typ.
VCC falls faster than 1V/ms
0.4
1.0
VCC falls at 1V/ms or slower
0.8
1.0
1.3
Max.
Units
V
1.59
V
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VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
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36.1.13 Flash and EEPROM Memory Characteristics
Table 36-20. Endurance and data retention.
Symbol
Parameter
Condition
Write/Erase cycles
Flash
Data retention
Write/Erase cycles
EEPROM
Data retention
Min.
25°C
10K
85°C
10K
105°C
2K
25°C
100
85°C
25
105°C
10
25°C
100K
85°C
100K
105°C
30K
25°C
100
85°C
25
105°C
10
Typ.
Max.
Units
Cycle
Year
Cycle
Year
Table 36-21. Programming time.
Symbol
Parameter
Typ.(1)
Max.
Units
16KB Flash, EEPROM(2) and
SRAM Erase
45
ms
Application Erase
Section erase
6
ms
Page erase
4
Page write
4
Atomic page erase and write
8
Page erase
4
Page write
4
Atomic page erase and write
8
EEPROM
1.
2.
Min.
Chip Erase
Flash
Notes:
Condition
ms
ms
Programming is timed from the 2MHz internal oscillator.
EEPROM is not erased if the EESAVE fuse is programmed.
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36.1.14 Clock and Oscillator Characteristics
36.1.14.1 Calibrated 32.768kHz Internal Oscillator characteristics
Table 36-22. 32.768kHz internal oscillator characteristics.
Symbol
Parameter
Condition
Min.
Frequency
Factory calibration accuracy
Typ.
Max.
32.768
T = 85°C, VCC = 3.0V
User calibration accuracy
Units
kHz
-0.5
0.5
%
-0.5
0.5
%
Max.
Units
2.2
MHz
36.1.14.2 Calibrated 2MHz RC Internal Oscillator characteristics
Table 36-23. 2MHz internal oscillator characteristics.
Symbol
Parameter
Frequency range
Condition
Min.
DFLL can tune to this frequency over
voltage and temperature
1.8
Factory calibrated frequency
Factory calibration accuracy
Typ.
2.0
T = 85°C, VCC= 3.0V
User calibration accuracy
MHz
-1.5
1.5
%
-0.2
0.2
%
DFLL calibration stepsize
0.21
%
36.1.14.3 Calibrated and tunable 32MHz internal oscillator characteristics
Table 36-24. 32MHz internal oscillator characteristics.
Symbol
Parameter
Frequency range
Condition
Min.
DFLL can tune to this frequency over
voltage and temperature
30
Factory calibrated frequency
Factory calibration accuracy
Typ.
Max.
Units
55
MHz
32
T = 85°C, VCC= 3.0V
User calibration accuracy
MHz
-1.5
1.5
%
-0.2
0.2
%
DFLL calibration step size
0.22
%
36.1.14.4 32kHz Internal ULP Oscillator characteristics
Table 36-25. 32kHz internal ULP oscillator characteristics.
Symbol
Parameter
Condition
Min.
Output frequency
Accuracy
Typ.
Max.
32
-30
Units
kHz
30
%
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36.1.14.5 Internal Phase Locked Loop (PLL) characteristics
Table 36-26. Internal PLL characteristics.
Symbo
l
fIN
Input frequency
fOUT
Note:
Parameter
Output frequency (1)
1.
Condition
Min.
Output frequency must be within fOUT
Typ.
Max.
Units
0.4
64
MHz
VCC= 1.6 - 1.8V
20
48
VCC= 2.7 - 3.6V
20
128
MHz
Start-up time
25
µs
Re-lock time
25
µs
The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
36.1.14.6 External clock characteristics
Figure 36-3. External clock drive waveform
tCH
tCH
tCR
tCF
VIH1
VIL1
tCL
tCK
Table 36-27. External clock used as system clock without prescaling.
Symbol
1/tCK
Clock Frequency (1)
tCK
Clock Period
tCH
Clock High Time
tCL
Clock Low Time
tCR
Rise Time (for maximum frequency)
tCF
Fall Time (for maximum frequency)
ΔtCK
Note:
Parameter
Change in period from one clock cycle to the next
1.
Condition
Min.
Typ.
Max.
VCC = 1.6 - 1.8V
0
12
VCC = 2.7 - 3.6V
0
32
VCC = 1.6 - 1.8V
83.3
VCC = 2.7 - 3.6V
31.5
VCC = 1.6 - 1.8V
30.0
VCC = 2.7 - 3.6V
12.5
VCC = 1.6 - 1.8V
30.0
VCC = 2.7 - 3.6V
12.5
Units
MHz
ns
ns
ns
VCC = 1.6 - 1.8V
10
VCC = 2.7 - 3.6V
3
VCC = 1.6 - 1.8V
10
VCC = 2.7 - 3.6V
3
10
ns
ns
%
The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
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Table 36-28. External clock with prescaler (1)for system clock.
Symbol
1/tCK
Parameter
Condition
Clock Frequency (2)
tCK
Clock Period
tCH
Clock High Time
tCL
Clock Low Time
tCR
Rise Time (for maximum frequency)
tCF
Fall Time (for maximum frequency)
ΔtCK
Notes:
Min.
Typ.
VCC = 1.6 - 1.8V
0
90
VCC = 2.7 - 3.6V
0
142
VCC = 1.6 - 1.8V
11
VCC = 2.7 - 3.6V
7
VCC = 1.6 - 1.8V
4.5
VCC = 2.7 - 3.6V
2.4
VCC = 1.6 - 1.8V
4.5
VCC = 2.7 - 3.6V
2.4
Units
MHz
ns
ns
ns
VCC = 1.6 - 1.8V
1.5
VCC = 2.7 - 3.6V
1.0
VCC = 1.6 - 1.8V
1.5
VCC = 2.7 - 3.6V
1.0
Change in period from one clock cycle to the next
1.
2.
Max.
10
ns
ns
%
System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
36.1.14.7 External 16MHz crystal oscillator and XOSC characteristic
Table 36-29. External 16MHz crystal oscillator and XOSC characteristics.
Symbol
Parameter
Cycle to cycle jitter
Condition
XOSCPWR=0
Min.
FRQRANGE=0
<10
FRQRANGE=1, 2, or 3
<1.0
XOSCPWR=1
Long term jitter
XOSCPWR=0
XOSCPWR=0
XOSCPWR=1
Max.
Units
ns
<1.0
FRQRANGE=0
<6.0
FRQRANGE=1, 2, or 3
<0.5
XOSCPWR=1
Frequency error
Typ.
ns
<0.5
FRQRANGE=0
<0.1
FRQRANGE=1
<0.05
FRQRANGE=2 or 3
<0.005
%
<0.005
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Symbol
Parameter
Duty cycle
Condition
XOSCPWR=0
Min.
FRQRANGE=0
40
FRQRANGE=1
42
FRQRANGE=2 or 3
45
XOSCPWR=1
2.4k
1MHz crystal, CL=20pF
8.7k
2MHz crystal, CL=20pF
2.1k
2MHz crystal
4.2k
8MHz crystal
250
9MHz crystal
195
8MHz crystal
360
9MHz crystal
285
12MHz crystal
155
9MHz crystal
365
12MHz crystal
200
16MHz crystal
105
9MHz crystal
435
12MHz crystal
235
16MHz crystal
125
9MHz crystal
495
12MHz crystal
270
16MHz crystal
145
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal
305
16MHz crystal
160
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal
380
16MHz crystal
205
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
Negative impedance (1)
RQ
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
ESR
Max.
Units
%
48
0.4MHz resonator,
CL=100pF
XOSCPWR=0,
FRQRANGE=0
Typ.
Ω
SF = Safety factor
min(RQ)/SF
kΩ
CXTAL1
Parasitic capacitance
XTAL1 pin
5.4
pF
CXTAL2
Parasitic capacitance
XTAL2 pin
7.1
pF
CLOAD
Parasitic capacitance
load
3.07
pF
Note:
1.
Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
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36.1.14.8 External 32.768kHz crystal oscillator and TOSC characteristics
Table 36-30. External 32.768kHz crystal oscillator and TOSC characteristics.
Symbol
Parameter
Condition
ESR/R1
Recommended crystal equivalent
series resistance (ESR)
CTOSC1
Parasitic capacitance TOSC1 pin
CTOSC2
Parasitic capacitance TOSC2 pin
Recommended safety factor
Note:
1.
Min.
Typ.
Max.
Crystal load capacitance 6.5pF
60
Crystal load capacitance 9.0pF
35
5.4
Alternate TOSC location
4.0
7.1
Alternate TOSC location
4.0
capacitance load matched to
crystal specification
Units
kΩ
pF
pF
3
See Figure 36-4 for definition.
Figure 36-4. TOSC input capacitance.
CL1
TOSC1
CL2
Device internal
External
TOSC2
32.768kHz crystal
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating
without external capacitors.
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36.1.15 SPI Characteristics
Figure 36-5. SPI timing requirements in master mode.
SS
tMOS
tSCKR
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
MISO
(Data input)
tMIH
tSCK
MSB
LSB
tMOH
MOSI
(Data output)
tMOH
MSB
LSB
Figure 36-6. SPI timing requirements in slave mode.
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
MOSI
(Data input)
tSIH
MSB
tSOSSS
MISO
(Data output)
tSSCK
LSB
tSOS
MSB
tSOSSH
LSB
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Table 36-31. SPI timing characteristics and requirements.
Symbol
Parameter
Condition
Min.
Typ.
Max.
tSCK
SCK period
Master
(See Table 21-4 in
XMEGA AU Manual)
tSCKW
SCK high/low width
Master
0.5*SCK
tSCKR
SCK rise time
Master
2.7
tSCKF
SCK fall time
Master
2.7
tMIS
MISO setup to SCK
Master
10
tMIH
MISO hold after SCK
Master
10
tMOS
MOSI setup SCK
Master
0.5*SCK
tMOH
MOSI hold after SCK
Master
1
tSSCK
Slave SCK Period
Slave
4*t ClkPER
tSSCKW
SCK high/low width
Slave
2*t ClkPER
tSSCKR
SCK rise time
Slave
1600
tSSCKF
SCK fall time
Slave
1600
tSIS
MOSI setup to SCK
Slave
3
tSIH
MOSI hold after SCK
Slave
t ClkPER
tSSS
SS setup to SCK
Slave
21
tSSH
SS hold after SCK
Slave
20
tSOS
MISO setup SCK
Slave
8
tSOH
MISO hold after SCK
Slave
13
tSOSS
MISO setup after SS low
Slave
11
tSOSH
MISO hold after SS high
Slave
8
Units
ns
36.1.16 Two-Wire Interface Characteristics
Table 36-32 on page 92 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel
AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols
refer to Figure 36-7 on page 91.
Figure 36-7. Two-wire interface bus timing.
tof
tHIGH
tLOW
tr
SCL
tSU;STA
tHD;STA
tHD;DAT
tSU;DAT
tSU;STO
SDA
tBUF
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Table 36-32. Two-wire interface characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VIH
Input high voltage
0.7*VCC
VCC+0.5
V
VIL
Input low voltage
0.5
0.3*VCC
V
Vhys
Hysteresis of Schmitt trigger inputs
VOL
Output low voltage
tr
Rise time for both SDA and SCL
tof
Output fall time from VIHmin to VILmax
tSP
Spikes suppressed by input filter
II
Input current for each I/O Pin
CI
Capacitance for each I/O Pin
fSCL
SCL clock frequency
0.05*VCC (1)
3mA, sink current
10pF < Cb < 400pF (2)
0.1VCC < VI < 0.9VCC
fPER (3)>max(10fSCL, 250kHz)
0
0.4
V
20+0.1Cb (1)(2)
300
ns
20+0.1Cb (1)(2)
250
ns
0
50
ns
-10
10
µA
10
pF
400
kHz
0
fSCL ≤ 100kHz
RP
Value of pull-up resistor
tHD;STA
Hold time (repeated) START condition
tLOW
Low period of SCL clock
tHIGH
High period of SCL clock
tSU;STA
Set-up time for a repeated START
condition
tHD;DAT
Data hold time
tSU;DAT
Data setup time
tSU;STO
Setup time for STOP condition
Bus free time between a STOP and
START condition
tBUF
Notes:
1.
2.
3.
fSCL > 100kHz
V
V CC – 0.4V
---------------------------3mA
100ns
--------------Cb
300ns
--------------Cb
fSCL ≤ 100kHz
4.0
fSCL > 100kHz
0.6
fSCL ≤ 100kHz
4.7
fSCL > 100kHz
1.3
fSCL ≤ 100kHz
4.0
fSCL > 100kHz
0.6
fSCL ≤ 100kHz
4.7
fSCL > 100kHz
0.6
fSCL ≤ 100kHz
0
3.45
fSCL > 100kHz
0
0.9
fSCL ≤ 100kHz
250
fSCL > 100kHz
100
fSCL ≤ 100kHz
4.0
fSCL > 100kHz
0.6
fSCL ≤ 100kHz
4.7
fSCL > 100kHz
1.3
Ω
µs
µs
µs
µs
µs
ns
µs
µs
Required only for fSCL > 100kHz.
Cb = Capacitance of one bus line in pF.
fPER = Peripheral clock frequency.
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36.2
ATxmega32A4U
36.2.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 36-33 may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 36-33. Absolute maximum ratings.
Symbol
Parameter
Condition
Min.
Typ.
-0.3
Max.
Units
4
V
VCC
Power supply voltage
IVCC
Current into a VCC pin
200
mA
IGND
Current out of a Gnd pin
200
mA
VPIN
Pin voltage with respect to Gnd and VCC
-0.5
VCC+0.5
V
IPIN
I/O pin sink/source current
-25
25
mA
TA
Storage temperature
-65
150
°C
Tj
Junction temperature
150
°C
36.2.2 General Operating Ratings
The device must operate within the ratings listed in Table 36-34 in order for all other electrical characteristics and
typical characteristics of the device to be valid.
Table 36-34. General operating conditions.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VCC
Power supply voltage
1.60
3.6
V
AVCC
Analog supply voltage
1.60
3.6
V
TA
Temperature range
-40
85
°C
Tj
Junction temperature
-40
105
°C
Max.
Units
Table 36-35. Operating voltage and frequency.
Symbol
ClkCPU
Parameter
CPU clock frequency
Condition
Min.
Typ.
VCC = 1.6V
0
12
VCC = 1.8V
0
12
VCC = 2.7V
0
32
VCC = 3.6V
0
32
MHz
The maximum CPU clock frequency depends on VCC. As shown in Figure 36-8 the Frequency vs. VCC curve is linear
between 1.8V < VCC < 2.7V.
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Figure 36-8. Maximum Frequency vs. VCC.
MHz
32
Safe Operating Area
12
1.6 1.8
2.7
3.6
V
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36.2.3 Current consumption
Table 36-36. Current consumption for Active mode and sleep modes.
Symbol
Parameter
Condition
Min.
32kHz, Ext. Clk
Active power
consumption(1)
1MHz, Ext. Clk
2MHz, Ext. Clk
40
VCC = 3.0V
80
VCC = 1.8V
230
VCC = 3.0V
480
VCC = 1.8V
430
600
0.9
1.4
9.6
12
2.4
VCC = 3.0V
3.9
VCC = 1.8V
62
VCC = 3.0V
118
VCC = 1.8V
125
225
240
350
3.8
5.5
0.1
1.0
1.2
4.5
T = 105°C
3.5
6.0
WDT and sampled BOD enabled,
T = 25°C
1.3
3.0
2.4
6.0
4.5
8.0
1MHz, Ext. Clk
2MHz, Ext. Clk
VCC = 3.0V
32MHz, Ext. Clk
T = 25°C
ICC
T = 85°C
Power-down power
consumption
VCC = 3.0V
WDT and sampled BOD enabled,
T = 85°C
VCC = 3.0V
WDT and sampled BOD enabled,
T = 105°C
Power-save power
consumption(2)
Reset power consumption
Notes:
1.
2.
mA
µA
RTC from ULP clock, WDT and
sampled BOD enabled, T = 25°C
VCC = 1.8V
1.2
VCC = 3.0V
1.3
RTC from 1.024kHz low power
32.768kHz TOSC, T = 25°C
VCC = 1.8V
0.6
2.0
VCC = 3.0V
0.7
2.0
RTC from low power 32.768kHz
TOSC, T = 25°C
VCC = 1.8V
0.8
3.0
VCC = 3.0V
1.0
3.0
VCC = 3.0V
320
Current through RESET pin
substracted
Units
µA
VCC = 1.8V
32kHz, Ext. Clk
Idle power
consumption(1)
Max.
VCC = 1.8V
VCC = 3.0V
32MHz, Ext. Clk
Typ.
mA
µA
µA
All Power Reduction Registers set.
Maximum limits are based on characterization, and not tested in production.
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Table 36-37. Current consumption for modules and peripherals.
Symbol
Parameter
Condition (1)
Min.
Max.
Units
ULP oscillator
1.0
µA
32.768kHz int. oscillator
27
µA
2MHz int. oscillator
32MHz int. oscillator
PLL
85
DFLL enabled with 32.768kHz int. osc. as reference
BOD
µA
115
270
DFLL enabled with 32.768kHz int. osc. as reference
20x multiplication factor,
32MHz int. osc. DIV4 as reference
Watchdog timer
ICC
Typ.
µA
460
220
µA
1.0
µA
Continuous mode
138
Sampled mode, includes ULP oscillator
1.2
µA
Internal 1.0V reference
100
µA
Temperature sensor
95
µA
3.0
ADC
DAC
AC
DMA
250ksps
VREF = Ext ref
250ksps
VREF = Ext ref
No load
CURRLIMIT = LOW
2.6
CURRLIMIT = MEDIUM
2.1
CURRLIMIT = HIGH
1.6
Normal mode
1.9
Low power mode
1.1
330
Low power mode
130
615kbps between I/O registers and SRAM
108
µA
16
µA
2.5
µA
Rx and Tx enabled, 9600 BAUD
Flash memory and EEPROM programming
Note:
1.
mA
High speed mode
Timer/counter
USART
mA
4.0
µA
8.0
mA
All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external
clock without prescaling, T = 25°C unless other conditions are given.
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36.2.4 Wake-up time from sleep modes
Table 36-38. Device wake-up time from sleep modes with various system clock sources.
Symbol
Parameter
Wake-up time from idle,
standby, and extended standby
mode
twakeup
Wake-up time from power-save
and power-down mode
Note:
1.
Condition
Min.
Typ. (1)
External 2MHz clock
2.0
32.768kHz internal oscillator
120
2MHz internal oscillator
2.0
32MHz internal oscillator
0.2
External 2MHz clock
4.5
32.768kHz internal oscillator
320
2MHz internal oscillator
9.0
32MHz internal oscillator
5.0
Max.
Units
µs
µs
The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-9. All peripherals and modules
start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 36-9. Wake-up time definition.
Wakeup time
Wakeup request
Clock output
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36.2.5 I/O Pin Characteristics
The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 36-39. I/O pin characteristics.
Symbol
IOH (1)/
Parameter
Condition
Max.
Units
-20
20
mA
VCC = 2.7 - 3.6V
2.0
VCC+0.3
VCC = 2.0 - 2.7V
0.7*VCC
VCC+0.3
VCC = 1.6 - 2.0V
0.8*VCC
VCC+0.3
VCC = 2.7- 3.6V
-0.3
0.8
VCC = 2.0 - 2.7V
-0.3
0.3*VCC
VCC = 1.6 - 2.0V
-0.3
0.2*VCC
I/O pin source/sink current
IOL (2)
VIH
High level input voltage
VIL
Low level input voltage
VCC = 3.0 - 3.6V
High level output voltage
2.4
0.94*VCC
IOH = -1mA
2.0
0.96*VCC
IOH = -2mA
1.7
0.92*VCC
VCC = 3.3V
IOH = -8mA
2.6
2.9
VCC = 3.0V
IOH = -6mA
2.1
2.6
VCC = 1.8V
IOH = -2mA
1.4
1.6
VCC = 3.0 - 3.6V
IOL = 2mA
0.05*VCC
0.4
IOL = 1mA
0.03*VCC
0.4
IOL = 2mA
0.06*VCC
0.7
VCC = 3.3V
IOL = 15mA
0.4
0.76
VCC = 3.0V
IOL = 10mA
0.3
0.64
VCC = 1.8V
IOL = 5mA
0.2
0.46
<0.01
0.1
VCC = 2.3 - 2.7V
VOL
Low level output voltage
IIN
Input leakage current
RP
Pull/buss keeper resistor
tr
Notes:
Rise time
1.
2.
Typ.
IOH = -2mA
VCC = 2.3 - 2.7V
VOH
Min.
T = 25°C
4.0
slew rate limitation
V
V
24
No load
V
7.0
V
µA
kΩ
ns
The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC must not exceed 200mA.
The sum of all IOH for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.
The sum of all IOH for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.
The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC must not exceed 200mA.
The sum of all IOL for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.
The sum of all IOL for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.
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36.2.6 ADC characteristics
Table 36-40. Power supply, reference and input range.
Symbol
Parameter
AVCC
Analog supply voltage
VREF
Reference voltage
Condition
Min.
Typ.
Max.
Units
VCC- 0.3
VCC+ 0.3
V
1
AVCC- 0.6
V
Rin
Input resistance
Switched
4.0
kΩ
Csample
Input capacitance
Switched
4.4
pF
RAREF
Reference input resistance
(leakage only)
>10
MΩ
CAREF
Reference input capacitance
Static load
7
pF
VIN
Input range
∆V
Conversion range
Differential mode, Vinp - Vinn
Conversion range
Single ended unsigned mode, Vinp
-0.1
AVCC+0.1
V
-VREF
VREF
V
-ΔV
VREF-ΔV
V
Fixed offset voltage
190
LSB
Table 36-41. Clock and timing.
Symbol
ClkADC
fADC
Parameter
Condition
Min.
Typ.
Max.
Units
Maximum is 1/4 of peripheral clock
frequency
100
2000
Measuring internal signals
100
125
Current limitation (CURRLIMIT) off
100
2000
CURRLIMIT = LOW
100
1500
CURRLIMIT = MEDIUM
100
1000
CURRLIMIT = HIGH
100
500
Sampling time
1/2 ClkADC cycle
0.25
5
µs
Conversion time (latency)
(RES+2)/2+(GAIN !=0)
RES (Resolution) = 8 or 12
5
8
ClkADC
cycles
Start-up time
ADC clock cycles
12
24
ClkADC
cycles
After changing reference or input mode
7
7
After ADC flush
1
1
ADC clock frequency
Sample rate
ADC settling time
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kHz
ksps
ClkADC
cycles
99
Table 36-42. Accuracy characteristics.
Symbol
Parameter
Condition (2)
Min.
Typ.
Max.
Units
RES
Resolution
Programmable to 8 or 12 bit
8
12
12
Bits
VCC-1.0V < VREF< VCC-0.6V
±1.2
±2.0
All VREF
±1.5
±3.0
VCC-1.0V < VREF< VCC-0.6V
±1.0
±2.0
All VREF
±1.5
±3.0
guaranteed monotonic
<±0.8
<±1.0
500ksps
INL(1)
Integral non-linearity
2000ksps
DNL(1)
Differential non-linearity
Offset error
mV
Temperature drift
<0.01
mV/K
Operating voltage drift
<0.6
mV/V
External reference
-1.0
AVCC/1.6
10
AVCC/2.0
8.0
Bandgap
±5.0
Gain error
Notes:
1.
2.
lsb
-1.0
Differential
mode
Noise
lsb
mV
Temperature drift
<0.02
mV/K
Operating voltage drift
<0.5
mV/V
Differential mode, shorted input
2msps, VCC = 3.6V, ClkPER = 16MHz
0.4
mV
rms
Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Table 36-43. Gain stage characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Rin
Input resistance
Switched in normal mode
4.0
kΩ
Csample
Input capacitance
Switched in normal mode
4.4
pF
Signal range
Gain stage output
Propagation delay
ADC conversion rate
Sample rate
Same as ADC
INL (1)
Integral non-linearity
Gain error
0
VCC- 0.6
ClkADC
cycles
1.0
100
All gain
settings
500ksps
±1.5
1x gain, normal mode
-0.8
8x gain, normal mode
-2.5
64x gain, normal mode
-3.5
V
1000
kHz
±4.0
lsb
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%
100
Symbol
Parameter
Condition
Offset error,
input referred
Min.
1x gain, normal mode
-2.0
8x gain, normal mode
-5.0
64x gain, normal mode
-4.0
1x gain, normal mode
Noise
1.
Max.
Units
mV
0.5
VCC = 3.6V
8x gain, normal mode
64x gain, normal mode
Note:
Typ.
mV
rms
1.5
Ext. VREF
11
Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
36.2.7 DAC Characteristics
Table 36-44. Power supply, reference and output range.
Symbol
Parameter
AVCC
Analog supply voltage
AVREF
External reference voltage
Rchannel
DC output impedance
Condition
Linear output voltage range
RAREF
CAREF
Min.
Max.
Units
VCC- 0.3
VCC+ 0.3
V
1.0
VCC- 0.6
V
50
Ω
AVCC-0.15
V
0.15
Reference input resistance
Reference input capacitance
Static load
Minimum Resistance load
Maximum capacitance load
Output sink/source
Typ.
>10
MΩ
7.0
pF
1.0
kΩ
1000Ω serial resistance
Operating within accuracy specification
100
pF
1.0
nF
AVCC/1000
Safe operation
10
mA
Table 36-45. Clock and timing.
Symbol
fDAC
Parameter
Conversion rate
Condition
Cload=100pF,
maximum step size
Normal mode
Low power mode
Min.
0
Typ.
Max.
1000
500
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Units
ksps
101
Table 36-46. Accuracy characteristics.
Symbol
RES
Parameter
Condition
Typ.
Input resolution
VREF= Ext 1.0V
INL (1)
Integral non-linearity
VREF=AVCC
VREF=INT1V
VREF=Ext 1.0V
DNL (1)
Differential non-linearity
VREF=AVCC
VREF=INT1V
Gain error
After calibration
Gain calibration step size
1.
Max.
Units
12
Bits
VCC = 1.6V
±2.0
±3.0
VCC = 3.6V
±1.5
±2.5
VCC = 1.6V
±2.0
±4.0
VCC = 3.6V
±1.5
±4.0
VCC = 1.6V
±5.0
VCC = 3.6V
±5.0
VCC = 1.6V
±1.5
3.0
VCC = 3.6V
±0.6
1.5
VCC = 1.6V
±1.0
3.5
VCC = 3.6V
±0.6
1.5
VCC = 1.6V
±4.5
VCC = 3.6V
±4.5
lsb
lsb
<4.0
lsb
4.0
lsb
Gain calibration drift
VREF= Ext 1.0V
<0.2
mV/K
Offset error
After calibration
<1.0
lsb
Offset calibration step size
Note:
Min.
1.0
Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.
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36.2.8 Analog Comparator Characteristics
Table 36-47. Analog Comparator characteristics.
Symbol
Voff
Parameter
Condition
Min.
Input offset voltage
Ilk
Input leakage current
Input voltage range
Typ.
Max.
Units
<±10
mV
<1
nA
-0.1
AVCC
V
AC startup time
100
µs
Vhys1
Hysteresis, none
0
mV
Vhys2
Hysteresis, small
Vhys3
Hysteresis, large
mode = High Speed (HS)
13
mode = Low Power (LP)
30
mode = HS
30
mode = LP
60
VCC = 3.0V, T= 85°C
tdelay
Propagation delay
mode = HS
30
mode = HS
VCC = 3.0V, T= 85°C
mV
90
30
mode = LP
130
mode = LP
64-level voltage scaler
mV
500
ns
130
Integral non-linearity (INL)
0.3
0.5
lsb
36.2.9 Bandgap and Internal 1.0V Reference Characteristics
Table 36-48. Bandgap and Internal 1.0V reference characteristics.
Symbol
Parameter
Startup time
Condition
Min.
As reference for ADC or DAC
Max.
1 ClkPER + 2.5µs
As input voltage to ADC and AC
1.1
Internal 1.00V reference
T= 85°C, after calibration
Variation over voltage and temperature
Relative to T= 85°C, VCC = 3.0V
0.99
1.0
Units
µs
1.5
Bandgap voltage
INT1V
Typ.
V
1.01
±1.5
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V
%
103
36.2.10 Brownout Detection Characteristics
Table 36-49. Brownout detection characteristics.
Symbol
Parameter
Condition
BOD level 0 falling VCC
VBOT
tBOD
Typ.
Max.
1.60
1.62
1.72
BOD level 1 falling VCC
1.8
BOD level 2 falling VCC
2.0
BOD level 3 falling VCC
2.2
BOD level 4 falling VCC
2.4
BOD level 5 falling VCC
2.6
BOD level 6 falling VCC
2.8
BOD level 7 falling VCC
3.0
Detection time
VHYST
Min.
Continuous mode
V
0.4
Sampled mode
µs
1000
Hysteresis
Units
1.2
%
36.2.11 External Reset Characteristics
Table 36-50. External reset characteristics.
Symbol
tEXT
Parameter
Condition
Min.
Minimum reset pulse width
Reset threshold voltage (VIH)
VRST
Reset threshold voltage (VIL)
RRST
Typ.
Max.
Units
95
1000
ns
VCC = 2.7 - 3.6V
0.60*VCC
VCC = 1.6 - 2.7V
0.60*VCC
VCC = 2.7 - 3.6V
0.50*VCC
VCC = 1.6 - 2.7V
0.40*VCC
Reset pin Pull-up Resistor
V
25
kΩ
36.2.12 Power-on Reset Characteristics
Table 36-51. Power-on reset characteristics.
Symbol
Parameter
VPOT- (1)
POR threshold voltage falling VCC
VPOT+
POR threshold voltage rising VCC
Note:
1.
Condition
Min.
Typ.
VCC falls faster than 1V/ms
0.4
1.0
VCC falls at 1V/ms or slower
0.8
1.0
1.3
Max.
Units
V
1.59
V
XMEGA A4U [DATASHEET]
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VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
36.2.13 Flash and EEPROM Memory Characteristics
Table 36-52. Endurance and data retention.
Symbol
Parameter
Condition
Write/Erase cycles
Flash
Data retention
Write/Erase cycles
EEPROM
Data retention
Min.
Typ.
25°C
10K
85°C
10K
105°C
2K
25°C
100
85°C
25
105°C
10
25°C
100K
85°C
100K
105°C
30K
25°C
100
85°C
25
105°C
10
Max.
Units
Cycle
Year
Cycle
Year
Table 36-53. Programming time.
Symbol
Parameter
Typ.(1)
Max.
Units
32KB Flash, EEPROM(2) and SRAM erase
50
ms
Application Erase
Section erase
6
ms
Page erase
4
Page write
4
Atomic page erase and write
8
Page erase
4
Page write
4
Atomic page erase and write
8
EEPROM
1.
2.
Min.
Chip Erase
Flash
Notes:
Condition
ms
ms
Programming is timed from the 2MHz internal oscillator.
EEPROM is not erased if the EESAVE fuse is programmed.
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36.2.14 Clock and Oscillator Characteristics
36.2.14.1 Calibrated 32.768kHz Internal Oscillator characteristics
Table 36-54. 32.768kHz internal oscillator characteristics.
Symbol
Parameter
Condition
Min.
Frequency
Factory calibration accuracy
Typ.
Max.
32.768
T = 85°C, VCC = 3.0V
User calibration accuracy
Units
kHz
-0.5
0.5
%
-0.5
0.5
%
Max.
Units
2.2
MHz
36.2.14.2 Calibrated 2MHz RC Internal Oscillator characteristics
Table 36-55. 2MHz internal oscillator characteristics.
Symbol
Parameter
Frequency range
Condition
Min.
DFLL can tune to this frequency over
voltage and temperature
1.8
Factory calibrated frequency
Factory calibration accuracy
Typ.
2.0
T = 85°C, VCC= 3.0V
User calibration accuracy
MHz
-1.5
1.5
%
-0.2
0.2
%
DFLL calibration stepsize
0.21
%
36.2.14.3 Calibrated and tunable 32MHz internal oscillator characteristics
Table 36-56. 32MHz internal oscillator characteristics.
Symbol
Parameter
Frequency range
Condition
Min.
DFLL can tune to this frequency over
voltage and temperature
30
Factory calibrated frequency
Factory calibration accuracy
Typ.
Max.
Units
55
MHz
32
T = 85°C, VCC= 3.0V
User calibration accuracy
MHz
-1.5
1.5
%
-0.2
0.2
%
DFLL calibration step size
0.22
%
36.2.14.4 32kHz Internal ULP Oscillator characteristics
Table 36-57. 32kHz internal ULP oscillator characteristics.
Symbol
Parameter
Condition
Min.
Output frequency
Accuracy
Typ.
Max.
32
-30
Units
kHz
30
%
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36.2.14.5 Internal Phase Locked Loop (PLL) characteristics
Table 36-58. Internal PLL characteristics.
Symbo
l
fIN
Input frequency
Output frequency (1)
fOUT
Note:
Parameter
1.
Condition
Min.
Output frequency must be within fOUT
Typ.
Max.
Units
0.4
64
MHz
VCC= 1.6 - 1.8V
20
48
VCC= 2.7 - 3.6V
20
128
MHz
Start-up time
25
µs
Re-lock time
25
µs
The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
36.2.14.6 External clock characteristics
Figure 36-10. External clock drive waveform
tCH
tCH
tCR
tCF
VIH1
VIL1
tCL
tCK
Table 36-59. External clock used as system clock without prescaling.
Symbol
Clock Frequency (1)
1/tCK
tCK
Clock Period
tCH
Clock High Time
tCL
Clock Low Time
tCR
Rise Time (for maximum frequency)
tCF
Fall Time (for maximum frequency)
ΔtCK
Note:
Parameter
Change in period from one clock cycle to the next
1.
Condition
Min.
Typ.
Max.
VCC = 1.6 - 1.8V
0
12
VCC = 2.7 - 3.6V
0
32
VCC = 1.6 - 1.8V
83.3
VCC = 2.7 - 3.6V
31.5
VCC = 1.6 - 1.8V
30.0
VCC = 2.7 - 3.6V
12.5
VCC = 1.6 - 1.8V
30.0
VCC = 2.7 - 3.6V
12.5
Units
MHz
ns
ns
ns
VCC = 1.6 - 1.8V
10
VCC = 2.7 - 3.6V
3
VCC = 1.6 - 1.8V
10
VCC = 2.7 - 3.6V
3
10
ns
ns
%
The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
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Table 36-60. External clock with prescaler (1)for system clock.
Symbol
Parameter
Condition
Clock Frequency (2)
1/tCK
tCK
Clock Period
tCH
Clock High Time
tCL
Clock Low Time
tCR
Rise Time (for maximum frequency)
tCF
Fall Time (for maximum frequency)
ΔtCK
Notes:
Min.
Typ.
VCC = 1.6 - 1.8V
0
90
VCC = 2.7 - 3.6V
0
142
VCC = 1.6 - 1.8V
11
VCC = 2.7 - 3.6V
7
VCC = 1.6 - 1.8V
4.5
VCC = 2.7 - 3.6V
2.4
VCC = 1.6 - 1.8V
4.5
VCC = 2.7 - 3.6V
2.4
Units
MHz
ns
ns
ns
VCC = 1.6 - 1.8V
1.5
VCC = 2.7 - 3.6V
1.0
VCC = 1.6 - 1.8V
1.5
VCC = 2.7 - 3.6V
1.0
Change in period from one clock cycle to the next
1.
2.
Max.
10
ns
ns
%
System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
36.2.14.7 External 16MHz crystal oscillator and XOSC characteristic
Table 36-61. External 16MHz crystal oscillator and XOSC characteristics.
Symbol
Parameter
Cycle to cycle jitter
Condition
XOSCPWR=0
Min.
FRQRANGE=0
<10
FRQRANGE=1, 2, or 3
<1
XOSCPWR=1
Long term jitter
XOSCPWR=0
XOSCPWR=0
FRQRANGE=0
FRQRANGE=1, 2, or 3
XOSCPWR=0
XOSCPWR=1
Units
ns
<6
<0.5
ns
<0.5
FRQRANGE=0
<0.1
FRQRANGE=1
<0.05
FRQRANGE=2 or 3
<0.005
XOSCPWR=1
Duty cycle
Max.
<1
XOSCPWR=1
Frequency error
Typ.
%
<0.005
FRQRANGE=0
40
FRQRANGE=1
42
FRQRANGE=2 or 3
45
%
48
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Symbol
Parameter
Condition
0.4MHz resonator,
CL=100pF
2.4k
1MHz crystal, CL=20pF
8.7k
2MHz crystal, CL=20pF
2.1k
2MHz crystal
4.2k
8MHz crystal
250
9MHz crystal
195
8MHz crystal
360
9MHz crystal
285
12MHz crystal
155
9MHz crystal
365
12MHz crystal
200
16MHz crystal
105
9MHz crystal
435
12MHz crystal
235
16MHz crystal
125
9MHz crystal
495
12MHz crystal
270
16MHz crystal
145
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal
305
16MHz crystal
160
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal
380
16MHz crystal
205
XOSCPWR=0,
FRQRANGE=0
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
Negative
impedance (1)
RQ
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
ESR
Min.
Typ.
Max.
Units
Ω
SF = Safety factor
min(RQ)/SF
kΩ
CXTAL1
Parasitic
capacitance XTAL1
pin
5.4
pF
CXTAL2
Parasitic
capacitance XTAL2
pin
7.1
pF
CLOAD
Parasitic
capacitance load
3.07
pF
Note:
1.
Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
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36.2.14.8 External 32.768kHz crystal oscillator and TOSC characteristics
Table 36-62. External 32.768kHz crystal oscillator and TOSC characteristics.
Symbol
Parameter
Condition
ESR/R1
Recommended crystal equivalent
series resistance (ESR)
CTOSC1
Parasitic capacitance TOSC1 pin
CTOSC2
Parasitic capacitance TOSC2 pin
Recommended safety factor
Note:
1.
Min.
Typ.
Max.
Crystal load capacitance 6.5pF
60
Crystal load capacitance 9.0pF
35
5.4
Alternate TOSC location
4.0
7.1
Alternate TOSC location
4.0
capacitance load matched to
crystal specification
Units
kΩ
pF
pF
3.0
See Figure 36-11 for definition.
Figure 36-11.TOSC input capacitance.
CL1
TOSC1
CL2
Device internal
External
TOSC2
32.768kHz crystal
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating
without external capacitors.
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36.2.15 SPI Characteristics
Figure 36-12. SPI timing requirements in master mode.
SS
tMOS
tSCKR
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
MISO
(Data input)
tMIH
tSCK
MSB
LSB
tMOH
MOSI
(Data output)
tMOH
MSB
LSB
Figure 36-13. SPI timing requirements in slave mode.
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
MOSI
(Data input)
tSIH
MSB
tSOSSS
MISO
(Data output)
tSSCK
LSB
tSOS
MSB
tSOSSH
LSB
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Table 36-63. SPI timing characteristics and requirements.
Symbol
Parameter
Condition
Min.
Typ.
Max.
tSCK
SCK period
Master
(See Table 21-4 in
XMEGA AU Manual)
tSCKW
SCK high/low width
Master
0.5×SCK
tSCKR
SCK rise time
Master
2.7
tSCKF
SCK fall time
Master
2.7
tMIS
MISO setup to SCK
Master
10
tMIH
MISO hold after SCK
Master
10
tMOS
MOSI setup SCK
Master
0.5×SCK
tMOH
MOSI hold after SCK
Master
1.0
tSSCK
Slave SCK Period
Slave
4×t ClkPER
tSSCKW
SCK high/low width
Slave
2×t ClkPER
tSSCKR
SCK rise time
Slave
1600
tSSCKF
SCK fall time
Slave
1600
tSIS
MOSI setup to SCK
Slave
3.0
tSIH
MOSI hold after SCK
Slave
t ClkPER
tSSS
SS setup to SCK
Slave
21
tSSH
SS hold after SCK
Slave
20
tSOS
MISO setup SCK
Slave
8.0
tSOH
MISO hold after SCK
Slave
13
tSOSS
MISO setup after SS low
Slave
11
tSOSH
MISO hold after SS high
Slave
8.0
Units
ns
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36.2.16 Two-Wire Interface Characteristics
Table 36-64 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR
XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer
to Figure 36-14.
Figure 36-14. Two-wire interface bus timing.
tof
tHIGH
tLOW
tr
SCL
tSU;STA
tHD;STA
tHD;DAT
tSU;STO
tSU;DAT
SDA
tBUF
Table 36-64. Two-wire interface characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VIH
Input high voltage
0.7VCC
VCC+0.5
V
VIL
Input low voltage
0.5
0.3×VCC
V
Vhys
Hysteresis of Schmitt trigger inputs
VOL
Output low voltage
tr
Rise time for both SDA and SCL
tof
Output fall time from VIHmin to VILmax
tSP
Spikes suppressed by Input filter
II
Input current for each I/O Pin
CI
Capacitance for each I/O Pin
fSCL
SCL clock frequency
0.05VCC (1)
3mA, sink current
10pF < Cb < 400pF (2)
0.1VCC < VI < 0.9VCC
fPER (3)>max(10fSCL, 250kHz)
0
0.4
V
20+0.1Cb (1)(2)
300
ns
20+0.1Cb (1)(2)
250
ns
0
50
ns
-10
10
µA
10
pF
400
kHz
0
fSCL ≤ 100kHz
RP
tHD;STA
Value of pull-up resistor
Hold time (repeated) START condition
tLOW
Low period of SCL Clock
tHIGH
High period of SCL Clock
tSU;STA
Set-up time for a repeated START
condition
fSCL > 100kHz
V
V CC – 0.4V
---------------------------3mA
fSCL ≤ 100kHz
4.0
fSCL > 100kHz
0.6
fSCL ≤ 100kHz
4.7
fSCL > 100kHz
1.3
fSCL ≤ 100kHz
4.0
fSCL > 100kHz
0.6
fSCL ≤ 100kHz
4.7
fSCL > 100kHz
0.6
100ns
--------------Cb
300ns
--------------Cb
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µs
µs
µs
µs
113
Symbol
Parameter
tHD;DAT
Data hold time
tSU;DAT
Data setup time
tSU;STO
Setup time for STOP condition
Bus free time between a STOP and
START condition
tBUF
Notes:
1.
2.
3.
Condition
Min.
Typ.
Max.
fSCL ≤ 100kHz
0
3.45
fSCL > 100kHz
0
0.9
fSCL ≤ 100kHz
250
fSCL > 100kHz
100
fSCL ≤ 100kHz
4.0
fSCL > 100kHz
0.6
fSCL ≤ 100kHz
4.7
fSCL > 100kHz
1.3
Units
µs
ns
µs
µs
Required only for fSCL > 100kHz.
Cb = Capacitance of one bus line in pF.
fPER = Peripheral clock frequency.
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36.3
ATxmega64A4U
36.3.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 36-65 may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 36-65. Absolute maximum ratings.
Symbol
Parameter
Condition
Min.
Typ.
-0.3
Max.
Units
4.0
V
VCC
Power supply voltage
IVCC
Current into a VCC pin
200
mA
IGND
Current out of a Gnd pin
200
mA
VPIN
Pin voltage with respect to Gnd and VCC
-0.5
VCC+0.5
V
IPIN
I/O pin sink/source current
-25
25
mA
TA
Storage temperature
-65
150
°C
Tj
Junction temperature
150
°C
36.3.2 General Operating Ratings
The device must operate within the ratings listed in Table 36-66 in order for all other electrical characteristics and
typical characteristics of the device to be valid.
Table 36-66. General operating conditions.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VCC
Power supply voltage
1.60
3.6
V
AVCC
Analog supply voltage
1.60
3.6
V
TA
Temperature range
-40
85
°C
Tj
Junction temperature
-40
105
°C
Max.
Units
Table 36-67. Operating voltage and frequency.
Symbol
ClkCPU
Parameter
CPU clock frequency
Condition
Min.
Typ.
VCC = 1.6V
0
12
VCC = 1.8V
0
12
VCC = 2.7V
0
32
VCC = 3.6V
0
32
MHz
The maximum CPU clock frequency depends on VCC. As shown in Figure 36-15 the Frequency vs. VCC curve is linear
between 1.8V < VCC < 2.7V.
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Figure 36-15.Maximum Frequency vs. VCC.
MHz
32
Safe Operating Area
12
1.6 1.8
2.7
3.6
V
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36.3.3 Current consumption
Table 36-68. Current consumption for Active mode and sleep modes.
Symbol
Parameter
Condition
Min.
32kHz, Ext. Clk
Active power
consumption (1)
1MHz, Ext. Clk
2MHz, Ext. Clk
VCC = 3.0V
132
VCC = 1.8V
223
VCC = 3.0V
476
VCC = 1.8V
400
600
0.8
1.4
8.2
12
VCC = 3.0V
3.5
VCC = 1.8V
57
VCC = 3.0V
110
VCC = 1.8V
115
225
216
350
3.5
5.5
0.1
1.0
1.2
4.5
T = 105°C
2.4
6.0
WDT and Sampled BOD enabled,
T = 25°C
1.4
3.0
2.4
6.0
3.5
8.0
1MHz, Ext. Clk
VCC = 3.0V
32MHz, Ext. Clk
T = 25°C
T = 85°C
Power-down power
consumption
VCC = 3.0V
WDT and Sampled BOD enabled,
T = 85°C
VCC = 3.0V
WDT and Sampled BOD enabled,
T = 105°C
Power-save power
consumption (2)
Reset power consumption
Notes:
1.
2.
Units
µA
2.4
2MHz, Ext. Clk
ICC
52
VCC = 1.8V
32kHz, Ext. Clk
Idle power
consumption (1)
Max.
VCC = 1.8V
VCC = 3.0V
32MHz, Ext. Clk
Typ.
mA
µA
RTC from ULP clock, WDT and
sampled BOD enabled, T = 25°C
VCC = 1.8V
1.2
VCC = 3.0V
1.5
RTC from 1.024kHz low power
32.768kHz TOSC, T = 25°C
VCC = 1.8V
0.6
2.0
VCC = 3.0V
0.7
2.0
RTC from low power 32.768kHz TOSC,
T = 25°C
VCC = 1.8V
0.8
3.0
VCC = 3.0V
1.0
3.0
Current through RESET pin substracted
VCC = 3.0V
140
mA
µA
µA
All Power Reduction Registers set.
Maximum limits are based on characterization, and not tested in production.
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Table 36-69. Current consumption for modules and peripherals.
Symbol
Parameter
Condition (1)
Min.
Max.
Units
ULP oscillator
1.0
µA
32.768kHz int. oscillator
29
µA
2MHz int. oscillator
32MHz int. oscillator
PLL
85
DFLL enabled with 32.768kHz int. osc. as reference
BOD
120
300
DFLL enabled with 32.768kHz int. osc. as reference
20x multiplication factor,
32MHz int. osc. DIV4 as reference
Watchdog timer
ICC
Typ.
465
µA
µA
320
µA
1.0
µA
Continuous mode
138
Sampled mode, includes ULP oscillator
1.0
µA
Internal 1.0V reference
103
µA
Temperature sensor
100
µA
3.0
ADC
DAC
AC
DMA
250ksps
VREF = Ext ref
250ksps
VREF = Ext ref
No load
CURRLIMIT = LOW
2.6
CURRLIMIT = MEDIUM
2.1
CURRLIMIT = HIGH
1.6
Normal mode
1.9
Low power mode
1.1
330
Low pPower mode
130
615KBps between I/O registers and SRAM
108
µA
16
µA
2.5
µA
8.0
mA
Rx and Tx enabled, 9600 BAUD
Flash memory and EEPROM programming
Note:
1.
mA
High speed mode
Timer/counter
USART
mA
µA
All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external
clock without prescaling, T = 25°C unless other conditions are given.
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36.3.4 Wake-up time from sleep modes
Table 36-70. Device wake-up time from sleep modes with various system clock sources.
Symbol
Parameter
Wake-up time from idle,
standby, and extended standby
mode
twakeup
Wake-up time from power-save
and power-down mode
Note:
1.
Condition
Min.
Typ. (1)
External 2MHz clock
2.0
32.768kHz internal oscillator
120
2MHz internal oscillator
2.0
32MHz internal oscillator
0.2
External 2MHz clock
4.5
32.768kHz internal oscillator
320
2MHz internal oscillator
9.0
32MHz internal oscillator
4.0
Max.
Units
µs
µs
The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-16. All peripherals and modules
start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 36-16.Wake-up time definition.
Wakeup time
Wakeup request
Clock output
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36.3.5 I/O Pin Characteristics
The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 36-71. I/O pin characteristics.
Symbol
IOH (1)/
IOL (2)
Parameter
Condition
Max.
Units
-20
20
mA
VCC = 2.7- 3.6V
2.0
VCC+0.3
VCC = 2.0 - 2.7V
0.7*VCC
VCC+0.3
VCC = 1.6 - 2.0V
0.8*VCC
VCC+0.3
VCC = 2.7- 3.6V
-0.3
0.8
VCC = 2.0 - 2.7V
-0.3
0.3*VCC
VCC = 1.6 - 2.0V
-0.3
0.2*VCC
I/O pin source/sink current
VIH
High level input voltage
VIL
Low level input voltage
VCC = 3.0 - 3.6V
High level output voltage
2.4
0.94*VCC
IOH = -1mA
2.0
0.96*VCC
IOH = -2mA
1.7
0.92*VCC
VCC = 3.3V
IOH = -8mA
2.6
2.9
VCC = 3.0V
IOH = -6mA
2.1
2.6
VCC = 1.8V
IOH = -2mA
1.4
1.6
VCC = 3.0 - 3.6V
IOL = 2mA
0.02*VCC
0.4
IOL = 1mA
0.01*VCC
0.4
IOL = 2mA
0.02*VCC
0.7
VCC = 3.3V
IOL = 15mA
0.4
0.76
VCC = 3.0V
IOL = 10mA
0.3
0.64
VCC = 1.8V
IOL = 5mA
0.2
0.46
T = 25°C
<0.01
0.1
XOSC and
TOSC pins
<0.02
1.1
VCC = 2.3 - 2.7V
VOL
Low level output voltage
IIN
Input leakage current
RP
Pull/buss keeper resistor
tr
Notes:
Rise time
Typ.
IOH = -2mA
VCC = 2.3 - 2.7V
VOH
Min.
4.0
slew rate limitation
1.
The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC must not exceed 200mA.
The sum of all IOH for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.
The sum of all IOH for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.
2.
The sum of all IOL for PORTA and PORTB must not exceed 100mA.
V
V
24
No load
V
7.0
V
µA
kΩ
ns
The sum of all IOL for PORTC must not exceed 200mA.
The sum of all IOL for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.
The sum of all IOL for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.
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36.3.6 ADC characteristics
Table 36-72. Power supply, reference and input range.
Symbol
Parameter
AVCC
Analog supply voltage
VREF
Reference voltage
Condition
Min.
Typ.
Max.
Units
VCC- 0.3
VCC+ 0.3
V
1.0
AVCC- 0.6
V
Rin
Input resistance
Switched
4.0
kΩ
Csample
Input capacitance
Switched
4.4
pF
RAREF
Reference input resistance
(leakage only)
>10
MΩ
CAREF
Reference input capacitance
Static load
7.0
pF
VIN
Input range
∆V
Conversion range
Differential mode, Vinp - Vinn
Conversion range
Single ended unsigned mode, Vinp
-0.1
AVCC+0.1
V
-VREF
VREF
V
-ΔV
VREF-ΔV
V
Fixed offset voltage
190
lsb
Table 36-73. Clock and timing.
Symbol
ClkADC
fADC
Parameter
Condition
Min.
Typ.
Max.
Units
Maximum is 1/4 of peripheral clock
frequency
100
2000
Measuring internal signals
100
125
Current limitation (CURRLIMIT) off
100
2000
CURRLIMIT = LOW
100
1500
CURRLIMIT = MEDIUM
100
1000
CURRLIMIT = HIGH
100
500
Sampling time
1/2 ClkADC cycle
0.25
5
µs
Conversion time (latency)
(RES+2)/2+(GAIN !=0)
RES (Resolution) = 8 or 12
5
8
ClkADC
cycles
Start-up time
ADC clock cycles
12
24
ClkADC
cycles
After changing reference or input mode
7
7
After ADC flush
1
1
ADC clock frequency
Sample rate
ADC settling time
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ksps
ClkADC
cycles
121
Table 36-74. Accuracy characteristics.
Symbol
Parameter
Condition (2)
RES
Resolution
Programmable to 8 or 12 bit
Min.
Typ.
Max.
Units
8
12
12
Bits
VCC-1.0V < VREF< VCC-0.6V
±1.2
±2
All VREF
±1.5
±3
VCC-1.0V < VREF< VCC-0.6V
±1.0
±2
All VREF
±1.5
±3
guaranteed monotonic
<±0.8
<±1
500ksps
INL (1)
Integral non-linearity
2000ksps
DNL (1)
Differential non-linearity
Offset error
mV
Temperature drift
<0.01
mV/K
Operating voltage drift
<0.6
mV/V
External reference
-1
AVCC/1.6
10
AVCC/2.0
8
Bandgap
±5
Gain error
Notes:
1.
2.
lsb
-1
Differential
mode
Noise
lsb
mV
Temperature drift
<0.02
mV/K
Operating voltage drift
<0.5
mV/V
Differential mode, shorted input
2msps, VCC = 3.6V, ClkPER = 16MHz
0.4
mV
rms
Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Table 36-75. Gain stage characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Rin
Input resistance
Switched in normal mode
4.0
kΩ
Csample
Input capacitance
Switched in normal mode
4.4
pF
Signal range
Gain stage output
Propagation delay
ADC conversion rate
Sample rate
Same as ADC
Integral non-linearity
500ksps
INL (1)
Gain error
0
VCC- 0.6
ClkADC
cycles
1.0
100
All gain
settings
±1.5
1x gain, normal mode
-0.8
8x gain, normal mode
-2.5
64x gain, normal mode
-3.5
V
1000
kHz
±4.0
lsb
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122
Symbol
Parameter
Condition
Offset error,
input referred
Min.
Typ.
1x gain, normal mode
-2
8x gain, normal mode
-5
64x gain, normal mode
-4
1x gain, normal mode
Noise
1.
Units
mV
0.5
VCC = 3.6V
Ext. VREF
8x gain, normal mode
mV
rms
1.5
64x gain, normal mode
Note:
Max.
11
Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
36.3.7 DAC Characteristics
Table 36-76. Power supply, reference and output range.
Symbol
Parameter
AVCC
Analog supply voltage
AVREF
External reference voltage
Rchannel
DC output impedance
Condition
Linear output voltage range
RAREF
CAREF
Min.
Typ.
Max.
Units
VCC- 0.3
VCC+ 0.3
V
1.0
VCC- 0.6
V
50
Ω
AVCC-0.15
V
0.15
Reference input resistance
Reference input capacitance
Static load
Minimum resistance load
Maximum capacitance load
Output sink/source
>10
MΩ
7
pF
1.0
kΩ
1000Ω serial resistance
Operating within accuracy specification
100
pF
1.0
nF
AVCC/1000
Safe operation
10
mA
Table 36-77. Clock and timing.
Symbol
fDAC
Parameter
Conversion rate
Condition
Cload=100pF,
maximum step size
Normal mode
Low power mode
Min.
0
Typ.
Max.
1000
500
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Units
ksps
123
Table 36-78. Accuracy characteristics.
Symbol
RES
Parameter
Condition
Typ.
Input resolution
VREF= Ext 1.0V
INL (1)
Integral non-linearity
VREF=AVCC
VREF=INT1V
VREF=Ext 1.0V
DNL (1)
Differential non-linearity
VREF=AVCC
VREF=INT1V
Gain error
After calibration
Gain calibration step size
1.
Max.
Units
12
Bits
VCC = 1.6V
±2.0
±3.0
VCC = 3.6V
±1.5
±2.5
VCC = 1.6V
±2.0
±4.0
VCC = 3.6V
±1.5
±4.0
VCC = 1.6V
±5.0
VCC = 3.6V
±5.0
VCC = 1.6V
±1.5
3.0
VCC = 3.6V
±0.6
1.5
VCC = 1.6V
±1.0
3.5
VCC = 3.6V
±0.6
1.5
VCC = 1.6V
±4.5
VCC = 3.6V
±4.5
lsb
lsb
<4.0
lsb
4.0
lsb
Gain calibration drift
VREF= Ext 1.0V
<0.2
mV/K
Offset error
After calibration
<1.0
lsb
Offset calibration step size
Note:
Min.
1.0
Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.
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36.3.8 Analog Comparator Characteristics
Table 36-79. Analog Comparator characteristics.
Symbol
Voff
Parameter
Condition
Min.
Input offset voltage
Ilk
Input leakage current
Input voltage range
Typ.
Max.
Units
<±10
mV
<1
nA
-0.1
AVCC
V
AC startup time
100
µs
Vhys1
Hysteresis, none
0
mV
Vhys2
Hysteresis, small
Vhys3
Hysteresis, large
mode = High Speed (HS)
20
mode = Low Power (LP)
30
mode = HS
35
mode = LP
60
VCC = 3.0V, T= 85°C
mode = HS
Propagation delay
64-level voltage scaler
mV
30
mode = HS
tdelay
mV
90
30
VCC = 3.0V, T= 85°C
mode = LP
130
mode = LP
130
Integral non-linearity (INL)
0.3
500
0.5
ns
lsb
36.3.9 Bandgap and Internal 1.0V Reference Characteristics
Table 36-80. Bandgap and Internal 1.0V reference characteristics.
Symbol
Parameter
Startup time
Condition
Min.
As reference for ADC or DAC
Max.
1 ClkPER + 2.5µs
As input voltage to ADC and AC
1.1
Internal 1.00V reference
T= 85°C, after calibration
Variation over voltage and temperature
Relative to T= 85°C, VCC = 3.0V
0.99
1
Units
µs
1.5
Bandgap voltage
INT1V
Typ.
V
1.01
±1.5
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V
%
125
36.3.10 Brownout Detection Characteristics
Table 36-81. Brownout detection characteristics.
Symbol
Parameter
Condition
BOD level 0 falling VCC
VBOT
tBOD
Typ.
Max.
1.50
1.62
1.72
BOD level 1 falling VCC
1.8
BOD level 2 falling VCC
2.0
BOD level 3 falling VCC
2.2
BOD level 4 falling VCC
2.4
BOD level 5 falling VCC
2.6
BOD level 6 falling VCC
2.8
BOD level 7 falling VCC
3.0
Continuous mode
Detection time
VHYST
Min.
V
0.4
Sampled mode
µs
1000
Hysteresis
Units
1.2
%
36.3.11 External Reset Characteristics
Table 36-82. External reset characteristics.
Symbol
tEXT
Parameter
Condition
Minimum reset pulse width
Reset threshold voltage (VIH)
VRST
Reset threshold voltage (VIL)
RRST
Min.
Typ.
1000
95
VCC = 2.7 - 3.6V
0.60×VCC
VCC = 1.6 - 2.7V
0.60×VCC
VCC = 2.7 - 3.6V
0.50×VCC
VCC = 1.6 - 2.7V
0.40×VCC
Reset pin Pull-up Resistor
Max.
Units
ns
V
25
kΩ
36.3.12 Power-on Reset Characteristics
Table 36-83. Power-on reset characteristics.
Symbol
Parameter
VPOT- (1)
POR threshold voltage falling VCC
VPOT+
POR threshold voltage rising VCC
Note:
1.
Condition
Min.
Typ.
VCC falls faster than 1V/ms
0.4
1.0
VCC falls at 1V/ms or slower
0.8
1.0
1.3
Max.
Units
V
1.59
VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
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36.3.13 Flash and EEPROM Memory Characteristics
Table 36-84. Endurance and data retention.
Symbol
Parameter
Condition
Write/Erase cycles
Flash
Data retention
Write/Erase cycles
EEPROM
Data retention
Min.
25°C
10K
85°C
10K
105°C
2K
25°C
100
85°C
25
105°C
10
25°C
100K
85°C
100K
105°C
30K
25°C
100
85°C
25
105°C
10
Typ.
Max.
Units
Cycle
Year
Cycle
Year
Table 36-85. Programming time.
Symbol
Parameter
64KB Flash, EEPROM
Application Erase
EEPROM
1.
2.
(2)
Chip Erase
Flash
Notes:
Condition
Min.
and SRAM Erase
Typ.(1)
Max.
Units
55
ms
Section erase
6
ms
Page erase
4
Page write
4
Atomic page erase and write
8
Page erase
4
Page write
4
Atomic page erase and write
8
ms
ms
Programming is timed from the 2MHz internal oscillator.
EEPROM is not erased if the EESAVE fuse is programmed.
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36.3.14 Clock and Oscillator Characteristics
36.3.14.1 Calibrated 32.768kHz Internal Oscillator characteristics
Table 36-86. 32.768kHz internal oscillator characteristics.
Symbol
Parameter
Condition
Min.
Frequency
Factory calibration accuracy
Typ.
Max.
32.768
T = 85°C, VCC = 3.0V
User calibration accuracy
Units
kHz
-0.5
0.5
%
-0.5
0.5
%
Max.
Units
2.2
MHz
36.3.14.2 Calibrated 2MHz RC Internal Oscillator characteristics
Table 36-87. 2MHz internal oscillator characteristics.
Symbol
Parameter
Frequency range
Condition
Min.
DFLL can tune to this frequency over
voltage and temperature
1.8
Factory calibrated frequency
Factory calibration accuracy
Typ.
2.0
T = 85°C, VCC= 3.0V
User calibration accuracy
MHz
-1.5
1.5
%
-0.2
0.2
%
DFLL calibration stepsize
0.21
%
36.3.14.3 Calibrated and tunable 32MHz internal oscillator characteristics
Table 36-88. 32MHz internal oscillator characteristics.
Symbol
Parameter
Frequency range
Condition
Min.
DFLL can tune to this frequency over
voltage and temperature
30
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
DFLL calibration step size
Typ.
Max.
Units
55
MHz
32
T = 85°C, VCC= 3.0V
MHz
-1.5
1.5
%
-0.2
0.2
%
0.22
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128
36.3.14.4 32kHz Internal ULP Oscillator characteristics
Table 36-89. 32kHz internal ULP oscillator characteristics.
Symbol
Parameter
Condition
Min.
Factory calibrated frequency
Factory calibrated accuracy
Typ.
Max.
32
T = 85°C, VCC = 3.0V
Accuracy
Units
kHz
-12
12
%
-30
30
%
Max.
Units
MHz
36.3.14.5 Internal Phase Locked Loop (PLL) characteristics
Table 36-90. Internal PLL characteristics.
Symbo
l
fIN
Input frequency
Output frequency (1)
fOUT
Note:
Parameter
1.
Condition
Min.
Typ.
Output frequency must be within fOUT
0.4
64
VCC= 1.6 - 1.8V
20
48
VCC= 2.7 - 3.6V
20
128
MHz
Start-up time
25
µs
Re-lock time
25
µs
The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
36.3.14.6 External clock characteristics
Figure 36-17. External clock drive waveform
tCH
tCH
tCR
tCF
VIH1
VIL1
tCL
tCK
Table 36-91. External clock used as system clock without prescaling.
Symbol
1/tCK
Parameter
Clock Frequency (1)
tCK
Clock Period
tCH
Clock High Time
Condition
Min.
Typ.
Max.
VCC = 1.6 - 1.8V
0
12
VCC = 2.7 - 3.6V
0
32
VCC = 1.6 - 1.8V
83.3
VCC = 2.7 - 3.6V
31.5
VCC = 1.6 - 1.8V
30.0
VCC = 2.7 - 3.6V
12.5
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Units
MHz
ns
ns
129
Symbol
Parameter
tCL
Clock Low Time
tCR
Rise Time (for maximum frequency)
tCF
Fall Time (for maximum frequency)
ΔtCK
Note:
Condition
Min.
VCC = 1.6 - 1.8V
30.0
VCC = 2.7 - 3.6V
12.5
Typ.
Units
ns
VCC = 1.6 - 1.8V
10
VCC = 2.7 - 3.6V
3
VCC = 1.6 - 1.8V
10
VCC = 2.7 - 3.6V
3
Change in period from one clock cycle to the next
1.
Max.
10
ns
ns
%
The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
Table 36-92. External clock with prescaler (1)for system clock.
Symbol
Parameter
Condition
Clock Frequency (2)
1/tCK
tCK
Clock Period
tCH
Clock High Time
tCL
Clock Low Time
tCR
Rise Time (for maximum frequency)
tCF
Fall Time (for maximum frequency)
ΔtCK
Notes:
Min.
Typ.
VCC = 1.6 - 1.8V
0
90
VCC = 2.7 - 3.6V
0
142
VCC = 1.6 - 1.8V
11
VCC = 2.7 - 3.6V
7
VCC = 1.6 - 1.8V
4.5
VCC = 2.7 - 3.6V
2.4
VCC = 1.6 - 1.8V
4.5
VCC = 2.7 - 3.6V
2.4
Units
MHz
ns
ns
ns
VCC = 1.6 - 1.8V
1.5
VCC = 2.7 - 3.6V
1.0
VCC = 1.6 - 1.8V
1.5
VCC = 2.7 - 3.6V
1.0
Change in period from one clock cycle to the next
1.
2.
Max.
10
ns
ns
%
System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
36.3.14.7 External 16MHz crystal oscillator and XOSC characteristic
Table 36-93. External 16MHz crystal oscillator and XOSC characteristics.
Symbol
Parameter
Cycle to cycle jitter
Condition
XOSCPWR=0
XOSCPWR=1
Min.
Typ.
FRQRANGE=0
<10
FRQRANGE=1, 2, or 3
<1
Max.
Units
ns
<1
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Symbol
Parameter
Long term jitter
Condition
XOSCPWR=0
Min.
FRQRANGE=0
XOSCPWR=0
FRQRANGE=1, 2, or 3
XOSCPWR=0
FRQRANGE=0
<0.1
FRQRANGE=1
<0.05
FRQRANGE=2 or 3
<0.005
FRQRANGE=0
40
FRQRANGE=1
42
FRQRANGE=2 or 3
45
1MHz crystal, CL=20pF
8.7k
2MHz crystal, CL=20pF
2.1k
2MHz crystal
4.2k
8MHz crystal
250
9MHz crystal
195
8MHz crystal
360
9MHz crystal
285
12MHz crystal
155
9MHz crystal
365
RQ
Negative impedance (1)
12MHz crystal
200
16MHz crystal
105
9MHz crystal
435
12MHz crystal
235
16MHz crystal
125
9MHz crystal
495
12MHz crystal
270
16MHz crystal
145
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal
305
16MHz crystal
160
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal
380
16MHz crystal
205
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
%
48
2.4k
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
%
<0.005
0.4MHz resonator,
CL=100pF
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
ns
<0.5
XOSCPWR=1
XOSCPWR=0,
FRQRANGE=0
Units
<0.5
XOSCPWR=1
Duty cycle
Max.
<6
XOSCPWR=1
Frequency error
Typ.
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Ω
131
Symbol
Parameter
Condition
Min.
ESR
SF = Safety factor
Typ.
Max.
Units
min(RQ)/SF
kΩ
CXTAL1
Parasitic capacitance
XTAL1 pin
5.60
pF
CXTAL2
Parasitic capacitance
XTAL2 pin
7.62
pF
CLOAD
Parasitic capacitance
load
3.23
pF
Note:
1.
Numbers for negative impedance are not tested in production but guaranteed from design and characterization
36.3.14.8 External 32.768kHz crystal oscillator and TOSC characteristics
Table 36-94. External 32.768kHz crystal oscillator and TOSC characteristics.
Symbol
Parameter
Condition
ESR/R1
Recommended crystal equivalent
series resistance (ESR)
CTOSC1
Parasitic capacitance TOSC1 pin
CTOSC2
Parasitic capacitance TOSC2 pin
Recommended safety factor
Note:
1.
Min.
Typ.
Max.
Crystal load capacitance 6.5pF
60
Crystal load capacitance 9.0pF
35
5.4
Alternate TOSC location
Units
kΩ
pF
4.0
7.1
Alternate TOSC location
pF
4.0
capacitance load matched to
crystal specification
3
See Figure 36-18 for definition.
Figure 36-18. TOSC input capacitance.
CL1
TOSC1
CL2
Device internal
External
TOSC2
32.768kHz crystal
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating
without external capacitors.
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36.3.15 SPI Characteristics
Figure 36-19.SPI timing requirements in master mode.
SS
tMOS
tSCKR
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
MISO
(Data input)
tMIH
tSCK
MSB
LSB
tMOH
MOSI
(Data output)
tMOH
MSB
LSB
Figure 36-20.SPI timing requirements in slave mode.
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
MOSI
(Data input)
tSIH
MSB
tSOSSS
MISO
(Data output)
tSSCK
LSB
tSOS
MSB
tSOSSH
LSB
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Table 36-95. SPI timing characteristics and requirements.
Symbol
Parameter
Condition
Min.
Typ.
Max.
tSCK
SCK period
Master
(See Table 21-4 in
XMEGA AU Manual)
tSCKW
SCK high/low width
Master
0.5*SCK
tSCKR
SCK rise time
Master
2.7
tSCKF
SCK fall time
Master
2.7
tMIS
MISO setup to SCK
Master
11
tMIH
MISO hold after SCK
Master
0
tMOS
MOSI setup SCK
Master
0.5*SCK
tMOH
MOSI hold after SCK
Master
1.0
tSSCK
Slave SCK Period
Slave
4*t ClkPER
tSSCKW
SCK high/low width
Slave
2*t ClkPER
tSSCKR
SCK rise time
Slave
1600
tSSCKF
SCK fall time
Slave
1600
tSIS
MOSI setup to SCK
Slave
3.0
tSIH
MOSI hold after SCK
Slave
tPER
tSSS
SS setup to SCK
Slave
20
tSSH
SS hold after SCK
Slave
20
tSOS
MISO setup SCK
Slave
8.0
tSOH
MISO hold after SCK
Slave
13.0
tSOSS
MISO setup after SS low
Slave
11.0
tSOSH
MISO hold after SS high
Slave
8.0
Units
ns
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36.3.16 Two-Wire Interface Characteristics
Table 36-96 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR
XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer
to Figure 36-21.
Figure 36-21.Two-wire interface bus timing.
tof
tHIGH
tLOW
tr
SCL
tSU;STA
tHD;STA
tHD;DAT
tSU;STO
tSU;DAT
SDA
tBUF
Table 36-96. Two-wire interface characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VIH
Input high voltage
0.7*VCC
VCC+0.5
V
VIL
Input low voltage
-0.5
0.3*VCC
V
Vhys
Hysteresis of Schmitt trigger inputs
0.05*VCC (1)
0
V
0
0.4
V
20+0.1Cb (1)(2)
0
ns
20+0.1Cb (1)(2)
300
ns
0
50
ns
-10
10
µA
0
10
pF
0
400
kHz
VOL
Output low voltage
tr
Rise time for both SDA and SCL
tof
Output fall time from VIHmin to VILmax
tSP
Spikes suppressed by input filter
II
Input current for each I/O pin
CI
Capacitance for each I/O pin
fSCL
SCL clock frequency
3mA, sink current
10pF < Cb < 400pF (2)
0.1VCC < VI < 0.9VCC
fPER (3)>max(10fSCL, 250kHz)
fSCL ≤ 100kHz
RP
tHD;STA
Value of pull-up resistor
Hold time (repeated) START condition
tLOW
Low period of SCL clock
tHIGH
High period of SCL clock
tSU;STA
Set-up time for a repeated START
condition
fSCL > 100kHz
V CC – 0.4V
---------------------------3mA
fSCL ≤ 100kHz
4.0
fSCL > 100kHz
0.6
fSCL ≤ 100kHz
4.7
fSCL > 100kHz
1.3
fSCL ≤ 100kHz
4.0
fSCL > 100kHz
0.6
fSCL ≤ 100kHz
4.7
fSCL > 100kHz
0.6
100ns
--------------Cb
300ns
--------------Cb
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Ω
µs
µs
µs
µs
135
Symbol
Parameter
tHD;DAT
Data hold time
tSU;DAT
Data setup time
tSU;STO
Setup time for STOP condition
Bus free time between a STOP and
START condition
tBUF
Notes:
1.
2.
3.
Condition
Min.
Typ.
Max.
fSCL ≤ 100kHz
0
3.45
fSCL > 100kHz
0
0.9
fSCL ≤ 100kHz
250
fSCL > 100kHz
100
fSCL ≤ 100kHz
4.0
fSCL > 100kHz
0.6
fSCL ≤ 100kHz
4.7
fSCL > 100kHz
1.3
Units
µs
ns
µs
µs
Required only for fSCL > 100kHz.
Cb = Capacitance of one bus line in pF.
fPER = Peripheral clock frequency.
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36.4
ATxmega128A4U
36.4.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 36-97 may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or other conditions beyond those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 36-97. Absolute maximum ratings.
Symbol
Parameter
Condition
Min.
Typ.
-0.3
Max.
Units
4
V
VCC
Power supply voltage
IVCC
Current into a VCC pin
200
mA
IGND
Current out of a Gnd pin
200
mA
VPIN
Pin voltage with respect to Gnd and VCC
-0.5
VCC+0.5
V
IPIN
I/O pin sink/source current
-25
25
mA
TA
Storage temperature
-65
150
°C
Tj
Junction temperature
150
°C
36.4.2 General Operating Ratings
The device must operate within the ratings listed in Table 36-98 in order for all other electrical characteristics and
typical characteristics of the device to be valid.
Table 36-98. General operating conditions.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VCC
Power supply voltage
1.60
3.6
V
AVCC
Analog supply voltage
1.60
3.6
V
TA
Temperature range
-40
85
°C
Tj
Junction temperature
-40
105
°C
Max.
Units
Table 36-99. Operating voltage and frequency.
Symbol
ClkCPU
Parameter
CPU clock frequency
Condition
Min.
Typ.
VCC = 1.6V
0
12
VCC = 1.8V
0
12
VCC = 2.7V
0
32
VCC = 3.6V
0
32
MHz
The maximum CPU clock frequency depends on VCC. As shown in Figure 36-22 the Frequency vs. VCC curve is linear
between 1.8V < VCC < 2.7V.
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Figure 36-22.Maximum Frequency vs. VCC.
MHz
32
Safe Operating Area
12
1.6 1.8
2.7
3.6
V
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36.4.3 Current consumption
Table 36-100.Current consumption for Active mode and sleep modes.
Symbol
Parameter
Condition
Min.
32kHz, Ext. Clk
Active power
consumption (1)
1MHz, Ext. Clk
2MHz, Ext. Clk
135
VCC = 1.8V
255
VCC = 3.0V
535
VCC = 1.8V
460
600
1.0
1.4
9.5
12
3.9
VCC = 1.8V
62
VCC = 3.0V
118
VCC = 1.8V
125
225
240
350
3.8
5.5
0.1
1.0
1.5
4.5
T = 105°C
0.1
8.6
WDT and Sampled BOD enabled,
T = 25°C
1.4
3.0
2.8
6.0
1.4
8.8
1MHz, Ext. Clk
VCC = 3.0V
T = 25°C
VCC = 3.0V
T = 85°C
WDT and Sampled BOD enabled,
T = 85°C
Reset power consumption
Notes:
1.
2.
µA
mA
VCC = 3.0V
RTC from ULP clock, WDT and
sampled BOD enabled, T = 25°C
VCC = 1.8V
1.2
VCC = 3.0V
1.5
RTC from 1.024kHz low power
32.768kHz TOSC, T = 25°C
VCC = 1.8V
0.6
2.0
VCC = 3.0V
0.7
2.0
RTC from low power 32.768kHz
TOSC, T = 25°C
VCC = 1.8V
0.8
3.0
VCC = 3.0V
1.0
3.0
VCC = 3.0V
300
Current through RESET pin
substracted
mA
µA
WDT and Sampled BOD enabled,
T = 105°C
Power-save power
consumption (2)
Units
µA
VCC = 3.0V
32MHz, Ext. Clk
Power-down power
consumption
VCC = 3.0V
2.9
2MHz, Ext. Clk
ICC
55
VCC = 1.8V
32kHz, Ext. Clk
Idle power
consumption (1)
Max.
VCC = 1.8V
VCC = 3.0V
32MHz, Ext. Clk
Typ.
µA
µA
All Power Reduction Registers set.
Maximum limits are based on characterization, and not tested in production.
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Table 36-101.Current consumption for modules and peripherals.
Symbol
Parameter
Condition (1)
Min.
µA
32.768kHz int. oscillator
29
µA
PLL
85
DFLL enabled with 32.768kHz int. osc. as reference
BOD
µA
115
270
DFLL enabled with 32.768kHz int. osc. as reference
20x multiplication factor,
32MHz int. osc. DIV4 as reference
Watchdog timer
µA
440
320
µA
1.0
µA
Continuous mode
138
Sampled mode, includes ULP oscillator
1.2
µA
Internal 1.0V reference
260
µA
Temperature sensor
250
µA
3.0
mA
ADC
DAC
AC
DMA
250ksps
VREF = Ext ref
250ksps
VREF = Ext ref
No load
CURRLIMIT = LOW
2.6
CURRLIMIT = MEDIUM
2.1
CURRLIMIT = HIGH
1.6
Normal mode
1.9
Low power mode
1.1
USART
mA
High speed mode
330
Low power mode
130
615kbps between I/O registers and SRAM
108
µA
16
µA
2.5
µA
Timer/counter
Rx and Tx enabled, 9600 BAUD
Flash memory and EEPROM programming
1.
Units
1.0
32MHz int. oscillator
Note:
Max.
ULP oscillator
2MHz int. oscillator
ICC
Typ.
4.0
µA
8.0
mA
All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz external
clock without prescaling, T = 25°C unless other conditions are given.
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36.4.4 Wake-up time from sleep modes
Table 36-102. Device wake-up time from sleep modes with various system clock sources.
Symbol
Parameter
Wake-up time from idle,
standby, and extended standby
mode
twakeup
Wake-up time from power-save
and power-down mode
Note:
1.
Condition
Min.
Typ. (1)
External 2MHz clock
2.0
32.768kHz internal oscillator
120
2MHz internal oscillator
2.0
32MHz internal oscillator
0.2
External 2MHz clock
4.5
32.768kHz internal oscillator
320
2MHz internal oscillator
9.0
32MHz internal oscillator
5.0
Max.
Units
µs
µs
The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-23. All peripherals and modules
start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 36-23.Wake-up time definition.
Wakeup time
Wakeup request
Clock output
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36.4.5 I/O Pin Characteristics
The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 36-103.I/O pin characteristics.
Symbol
IOH (1)/
Parameter
Condition
Max.
Units
-20
20
mA
VCC = 2.7 - 3.6V
2.0
VCC+0.3
VCC = 2.0 - 2.7V
0.7*VCC
VCC+0.3
VCC = 1.6 - 2.0V
0.8*VCC
VCC+0.3
VCC = 2.7- 3.6V
-0.3
0.8
VCC = 2.0 - 2.7V
-0.3
0.3*VCC
VCC = 1.6 - 2.0V
-0.3
0.2*VCC
I/O pin source/sink current
IOL (2)
VIH
High level input voltage
VIL
Low level input voltage
VCC = 3.0 - 3.6V
High level output voltage
2.4
0.94*VCC
IOH = -1mA
2.0
0.96*VCC
IOH = -2mA
1.7
0.92*VCC
VCC = 3.3V
IOH = -8mA
2.6
2.9
VCC = 3.0V
IOH = -6mA
2.1
2.6
VCC = 1.8V
IOH = -2mA
1.4
1.6
VCC = 3.0 - 3.6V
IOL = 2mA
0.05
0.4
IOL = 1mA
0.03
0.4
IOL = 2mA
0.06
0.7
VCC = 3.3V
IOL = 15mA
0.4
0.76
VCC = 3.0V
IOL = 10mA
0.3
0.64
VCC = 1.8V
IOL = 5mA
0.2
0.46
<0.01
0.1
VCC = 2.3 - 2.7V
VOL
Low level output voltage
IIN
Input leakage current
RP
Pull/buss keeper resistor
tr
Notes:
Rise time
1.
2.
Typ.
IOH = -2mA
VCC = 2.3 - 2.7V
VOH
Min.
T = 25°C
4.0
slew rate limitation
V
V
24
No load
V
7.0
V
µA
kΩ
ns
The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC must not exceed 200mA.
The sum of all IOH for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.
The sum of all IOH for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.
The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC must not exceed 200mA.
The sum of all IOL for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.
The sum of all IOL for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.
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36.4.6 ADC characteristics
Table 36-104.Power supply, reference and input range.
Symbol
Parameter
AVCC
Analog supply voltage
VREF
Reference voltage
Rin
Condition
Min.
Typ.
Max.
Units
VCC- 0.3
VCC+ 0.3
V
1
AVCC- 0.6
V
Input resistance
Switched
4.0
kΩ
Csample
Input capacitance
Switched
4.4
pF
RAREF
Reference input resistance
(leakage only)
>10
MΩ
CAREF
Reference input capacitance
Static load
7
pF
VIN
Input range
∆V
Conversion range
Differential mode, Vinp - Vinn
Conversion range
Single ended unsigned mode, Vinp
-0.1
AVCC+0.1
V
-VREF
VREF
V
-ΔV
VREF-ΔV
V
Fixed offset voltage
190
lsb
Table 36-105.Clock and timing.
Symbol
ClkADC
fADC
Parameter
Condition
Min.
Typ.
Max.
Units
Maximum is 1/4 of Peripheral clock
frequency
100
2000
Measuring internal signals
100
125
Current limitation (CURRLIMIT) off
100
2000
CURRLIMIT = LOW
100
1500
CURRLIMIT = MEDIUM
100
1000
CURRLIMIT = HIGH
100
500
Sampling time
1/2 ClkADC cycle
0.25
5
µs
Conversion time (latency)
(RES+2)/2+(GAIN !=0)
RES (Resolution) = 8 or 12
5
8
ClkADC
cycles
Start-up time
ADC clock cycles
12
24
ClkADC
cycles
After changing reference or input mode
7
7
After ADC flush
1
1
ADC Clock frequency
Sample rate
ADC settling time
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kHz
ksps
ClkADC
cycles
143
Table 36-106. Accuracy characteristics.
Symbol
Parameter
Condition (2)
RES
Resolution
Programmable to 8 or 12 bit
Min.
Typ.
Max.
Units
8
12
12
Bits
VCC-1.0V < VREF< VCC-0.6V
±1.2
±2
lsb
All VREF
±1.5
±3
VCC-1.0V < VREF< VCC-0.6V
±1.0
±2
All VREF
±1.5
±3
guaranteed monotonic
<±0.8
<±1
500ksps
INL (1)
Integral non-linearity
2000ksps
DNL (1)
Differential non-linearity
Offset error
-1.0
mV
Temperature drift
<0.01
mV/K
Operating voltage drift
<0.6
mV/V
External reference
-1
AVCC/1.6
10
AVCC/2.0
8.0
Bandgap
±5
Differential
mode
Gain error
Noise
Notes:
1.
2.
lsb
mV
Temperature drift
<0.02
mV/K
Operating voltage drift
<0.5
mV/V
Differential mode, shorted input
2msps, VCC = 3.6V, ClkPER = 16MHz
0.4
mV
rms
Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Table 36-107. Gain stage characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Rin
Input resistance
Switched in normal mode
4.0
kΩ
Csample
Input capacitance
Switched in normal mode
4.4
pF
Signal range
Gain stage output
Propagation delay
ADC conversion rate
Sample rate
Same as ADC
INL (1)
Integral Non-Linearity
Gain error
0
VCC- 0.6
ClkADC
cycles
1.0
100
All gain
settings
500ksps
±1.5
1x gain, normal mode
-0.8
8x gain, normal mode
-2.5
64x gain, normal mode
-3.5
V
1000
kHz
±4.0
lsb
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%
144
Symbol
Parameter
Condition
Offset error,
input referred
Min.
1x gain, normal mode
-2.0
8x gain, normal mode
-5.0
64x gain, normal mode
-4.0
1x gain, normal mode
Noise
1.
Max.
Units
mV
0.5
VCC = 3.6V
8x gain, normal mode
64x gain, normal mode
Note:
Typ.
mV
rms
1.5
Ext. VREF
11
Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
36.4.7 DAC Characteristics
Table 36-108. Power supply, reference and output range.
Symbol
Parameter
AVCC
Analog supply voltage
AVREF
External reference voltage
Rchannel
DC output impedance
Condition
Linear output voltage range
RAREF
CAREF
Min.
Typ.
VCC+ 0.3
1.0
VCC- 0.6
V
50
Ω
AVCC-0.15
V
Reference input resistance
Static load
Minimum Resistance load
>10
MΩ
7.0
pF
1
Maximum capacitance load
kΩ
1000Ω serial resistance
Operating within accuracy specification
Output sink/source
Units
VCC- 0.3
0.15
Reference input capacitance
Max.
100
pF
1
nF
AVCC/1000
Safe operation
10
mA
Table 36-109. Clock and timing.
Symbol
fDAC
Parameter
Conversion rate
Condition
Cload=100pF,
maximum step size
Normal mode
Low power mode
Min.
0
Typ.
Max.
1000
500
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Units
ksps
145
Table 36-110.Accuracy characteristics.
Symbol
RES
Parameter
Condition
Typ.
Input resolution
VREF= Ext 1.0V
INL (1)
Integral non-linearity
VREF=AVCC
VREF=INT1V
VREF=Ext 1.0V
DNL (1)
Differential non-linearity
VREF=AVCC
VREF=INT1V
Gain error
After calibration
Gain calibration step size
1.
Max.
Units
12
Bits
VCC = 1.6V
±2.0
±3.0
VCC = 3.6V
±1.5
±2.5
VCC = 1.6V
±2.0
±4.0
VCC = 3.6V
±1.5
±4.0
VCC = 1.6V
±5.0
VCC = 3.6V
±5.0
VCC = 1.6V
±1.5
3.0
VCC = 3.6V
±0.6
1.5
VCC = 1.6V
±1.0
3.5
VCC = 3.6V
±0.6
1.5
VCC = 1.6V
±4.5
VCC = 3.6V
±4.5
lsb
lsb
<4.0
lsb
4.0
lsb
Gain calibration drift
VREF= Ext 1.0V
<0.2
mV/K
Offset error
After calibration
<1.0
lsb
Offset calibration step size
Note:
Min.
1.0
Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.
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36.4.8 Analog Comparator Characteristics
Table 36-111. Analog Comparator characteristics.
Symbol
Voff
Parameter
Condition
Min.
Input offset voltage
Ilk
Input leakage current
Input voltage range
Typ.
Max.
Units
<±10
mV
<1
nA
-0.1
AVCC
V
AC startup time
100
µs
Vhys1
Hysteresis, none
0
mV
Vhys2
Hysteresis, small
Vhys3
Hysteresis, large
mode = High Speed (HS)
13
mode = Low Power (LP)
30
mode = HS
30
mode = LP
60
VCC = 3.0V, T= 85°C
tdelay
Propagation delay
mode = HS
30
mode = HS
VCC = 3.0V, T= 85°C
mV
90
30
mode = LP
130
mode = LP
64-level voltage scaler
mV
500
ns
130
Integral non-linearity (INL)
0.3
0.5
lsb
36.4.9 Bandgap and Internal 1.0V Reference Characteristics
Table 36-112. Bandgap and Internal 1.0V reference characteristics.
Symbol
Parameter
Startup time
Condition
Min.
As reference for ADC or DAC
Max.
1 ClkPER + 2.5µs
As input voltage to ADC and AC
1.1
Internal 1.00V reference
T= 85°C, after calibration
Variation over voltage and temperature
Relative to T= 85°C, VCC = 3.0V
0.99
1.0
Units
µs
1.5
Bandgap voltage
INT1V
Typ.
V
1.01
±1.5
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V
%
147
36.4.10 Brownout Detection Characteristics
Table 36-113. Brownout detection characteristics.
Symbol
Parameter
Condition
BOD level 0 falling VCC
VBOT
tBOD
Typ.
Max.
1.50
1.62
1.72
BOD level 1 falling VCC
1.8
BOD level 2 falling VCC
2.0
BOD level 3 falling VCC
2.2
BOD level 4 falling VCC
2.4
BOD level 5 falling VCC
2.6
BOD level 6 falling VCC
2.8
BOD level 7 falling VCC
3.0
Continuous mode
Detection time
VHYST
Min.
V
0.4
Sampled mode
µs
1000
Hysteresis
Units
1.2
%
36.4.11 External Reset Characteristics
Table 36-114. External reset characteristics.
Symbol
tEXT
Parameter
Condition
Minimum reset pulse width
Reset threshold voltage (VIH)
VRST
Reset threshold voltage (VIL)
RRST
Min.
Typ.
1000
95
VCC = 2.7 - 3.6V
0.60×VCC
VCC = 1.6 - 2.7V
0.60×VCC
Max.
ns
VCC = 2.7 - 3.6V
0.50×VCC
VCC = 1.6 - 2.7V
0.40×VCC
Reset pin Pull-up Resistor
Units
25
V
kΩ
36.4.12 Power-on Reset Characteristics
Table 36-115. Power-on reset characteristics.
Symbol
Parameter
VPOT- (1)
POR threshold voltage falling VCC
VPOT+
POR threshold voltage rising VCC
Note:
1.
Condition
Min.
Typ.
VCC falls faster than 1V/ms
0.4
1.0
VCC falls at 1V/ms or slower
0.8
1.0
1.3
Max.
Units
V
1.59
mV
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VPOT- values are only valid when BOD is disabled. When BOD is enabled VPOT- = VPOT+.
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36.4.13 Flash and EEPROM Memory Characteristics
Table 36-116. Endurance and data retention.
Symbol
Parameter
Condition
Write/Erase cycles
Flash
Data retention
Write/Erase cycles
EEPROM
Data retention
Min.
25°C
10K
85°C
10K
105°C
2K
25°C
100
85°C
25
105°C
10
25°C
100K
85°C
100K
105°C
30K
25°C
100
85°C
25
105°C
10
Typ.
Max.
Units
Cycle
Year
Cycle
Year
Table 36-117. Programming time.
Symbol
Parameter
Typ.(1)
Max.
Units
128KB Flash, EEPROM(2) and SRAM Erase
75
ms
Application Erase
Section erase
6
ms
Page erase
4
Page write
4
Atomic page erase and write
8
Page erase
4
Page write
4
Atomic page erase and write
8
EEPROM
1.
2.
Min.
Chip Erase
Flash
Notes:
Condition
ms
ms
Programming is timed from the 2MHz internal oscillator.
EEPROM is not erased if the EESAVE fuse is programmed.
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36.4.14 Clock and Oscillator Characteristics
36.4.14.1 Calibrated 32.768kHz Internal Oscillator characteristics
Table 36-118. 32.768kHz internal oscillator characteristics.
Symbol
Parameter
Condition
Min.
Frequency
Factory calibration accuracy
Typ.
Max.
32.768
T = 85°C, VCC = 3.0V
User calibration accuracy
Units
kHz
-0.5
0.5
%
-0.5
0.5
%
Max.
Units
2.2
MHz
36.4.14.2 Calibrated 2MHz RC Internal Oscillator characteristics
Table 36-119. 2MHz internal oscillator characteristics.
Symbol
Parameter
Frequency range
Condition
Min.
DFLL can tune to this frequency over
voltage and temperature
1.8
Factory calibrated frequency
Factory calibration accuracy
Typ.
2.0
T = 85°C, VCC= 3.0V
User calibration accuracy
MHz
-1.5
1.5
%
-0.2
0.2
%
DFLL calibration stepsize
0.21
%
36.4.14.3 Calibrated and tunable 32MHz internal oscillator characteristics
Table 36-120. 32MHz internal oscillator characteristics.
Symbol
Parameter
Frequency range
Condition
Min.
DFLL can tune to this frequency over
voltage and temperature
30
Factory calibrated frequency
Factory calibration accuracy
Typ.
Max.
Units
55
MHz
32
T = 85°C, VCC= 3.0V
User calibration accuracy
MHz
-1.5
1.5
%
-0.2
0.2
%
DFLL calibration step size
0.22
%
36.4.14.4 32kHz Internal ULP Oscillator characteristics
Table 36-121. 32kHz internal ULP oscillator characteristics.
Symbol
Parameter
Condition
Min.
Output frequency
Accuracy
Typ.
Max.
32
-30
Units
kHz
30
%
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36.4.14.5 Internal Phase Locked Loop (PLL) characteristics
Table 36-122. Internal PLL characteristics.
Symbo
l
fIN
Input frequency
Output frequency (1)
fOUT
Note:
Parameter
1.
Condition
Min.
Output frequency must be within fOUT
Typ.
Max.
Units
0.4
64
MHz
VCC= 1.6 - 1.8V
20
48
VCC= 2.7 - 3.6V
20
128
MHz
Start-up time
25
µs
Re-lock time
25
µs
The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
36.4.14.6 External clock characteristics
Figure 36-24. External clock drive waveform
tCH
tCH
tCR
tCF
VIH1
VIL1
tCL
tCK
Table 36-123.External clock used as system clock without prescaling.
Symbol
Clock Frequency (1)
1/tCK
tCK
Clock Period
tCH
Clock High Time
tCL
Clock Low Time
tCR
Rise Time (for maximum frequency)
tCF
Fall Time (for maximum frequency)
ΔtCK
Note:
Parameter
Change in period from one clock cycle to the next
1.
Condition
Min.
Typ.
Max.
VCC = 1.6 - 1.8V
0
12
VCC = 2.7 - 3.6V
0
32
VCC = 1.6 - 1.8V
83.3
VCC = 2.7 - 3.6V
31.5
VCC = 1.6 - 1.8V
30.0
VCC = 2.7 - 3.6V
12.5
VCC = 1.6 - 1.8V
30.0
VCC = 2.7 - 3.6V
12.5
Units
MHz
ns
ns
ns
VCC = 1.6 - 1.8V
10
VCC = 2.7 - 3.6V
3
VCC = 1.6 - 1.8V
10
VCC = 2.7 - 3.6V
3
10
ns
ns
%
The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
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Table 36-124. External clock with prescaler (1)for system clock.
Symbol
Parameter
Condition
Clock Frequency (2)
1/tCK
tCK
Clock Period
tCH
Clock High Time
tCL
Clock Low Time
tCR
Rise Time (for maximum frequency)
tCF
Fall Time (for maximum frequency)
ΔtCK
Notes:
Min.
Typ.
VCC = 1.6 - 1.8V
0
90
VCC = 2.7 - 3.6V
0
142
VCC = 1.6 - 1.8V
11
VCC = 2.7 - 3.6V
7
VCC = 1.6 - 1.8V
4.5
VCC = 2.7 - 3.6V
2.4
VCC = 1.6 - 1.8V
4.5
VCC = 2.7 - 3.6V
2.4
Units
MHz
ns
ns
ns
VCC = 1.6 - 1.8V
1.5
VCC = 2.7 - 3.6V
1.0
VCC = 1.6 - 1.8V
1.5
VCC = 2.7 - 3.6V
1.0
Change in period from one clock cycle to the next
1.
2.
Max.
10
ns
ns
%
System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
36.4.14.7 External 16MHz crystal oscillator and XOSC characteristic
Table 36-125. External 16MHz crystal oscillator and XOSC characteristics.
Symbol
Parameter
Cycle to cycle jitter
Condition
XOSCPWR=0
Min.
FRQRANGE=0
<10
FRQRANGE=1, 2, or 3
<1
XOSCPWR=1
Long term jitter
XOSCPWR=0
XOSCPWR=0
XOSCPWR=1
Max.
Units
ns
<1
FRQRANGE=0
FRQRANGE=1, 2, or 3
XOSCPWR=1
Frequency error
Typ.
<6
<0.5
ns
<0.5
FRQRANGE=0
<0.1
FRQRANGE=1
<0.05
FRQRANGE=2 or 3
<0.005
%
<0.005
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Symbol
Parameter
Duty cycle
Condition
XOSCPWR=0
Min.
FRQRANGE=0
40
FRQRANGE=1
42
FRQRANGE=2 or 3
45
XOSCPWR=1
2.4k
1MHz crystal, CL=20pF
8.7k
2MHz crystal, CL=20pF
2.1k
2MHz crystal
4.2k
8MHz crystal
250
9MHz crystal
195
8MHz crystal
360
9MHz crystal
285
12MHz crystal
155
9MHz crystal
365
12MHz crystal
200
16MHz crystal
105
9MHz crystal
435
12MHz crystal
235
16MHz crystal
125
9MHz crystal
495
12MHz crystal
270
16MHz crystal
145
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
12MHz crystal
305
16MHz crystal
160
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
12MHz crystal
380
16MHz crystal
205
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
Negative impedance (1)
RQ
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
ESR
Max.
Units
%
48
0.4MHz resonator,
CL=100pF
XOSCPWR=0,
FRQRANGE=0
Typ.
Ω
SF = Safety factor
min(RQ)/SF
kΩ
CXTAL1
Parasitic capacitance
XTAL1 pin
5.45
pF
CXTAL2
Parasitic capacitance
XTAL2 pin
7.51
pF
CLOAD
Parasitic capacitance
load
3.16
pF
Note:
1.
Numbers for negative impedance are not tested in production but guaranteed from design and characterization.
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36.4.14.8 External 32.768kHz crystal oscillator and TOSC characteristics
Table 36-126. External 32.768kHz crystal oscillator and TOSC characteristics.
Symbol
Parameter
Condition
ESR/R1
Recommended crystal equivalent
series resistance (ESR)
CTOSC1
Parasitic capacitance TOSC1 pin
CTOSC2
Parasitic capacitance TOSC2 pin
Recommended safety factor
Note:
1.
Min.
Typ.
Max.
Crystal load capacitance 6.5pF
60
Crystal load capacitance 9.0pF
35
Units
5.4
Alternate TOSC location
4.0
7.1
Alternate TOSC location
4.0
capacitance load matched to
crystal specification
kΩ
pF
pF
3
See Figure 36-25 for definition.
Figure 36-25. TOSC input capacitance.
CL1
TOSC1
CL2
Device internal
External
TOSC2
32.768kHz crystal
The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating
without external capacitors.
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36.4.15 SPI Characteristics
Figure 36-26. SPI timing requirements in master mode.
SS
tMOS
tSCKR
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
MISO
(Data input)
tMIH
tSCK
MSB
LSB
tMOH
MOSI
(Data output)
tMOH
MSB
LSB
Figure 36-27. SPI timing requirements in slave mode.
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
MOSI
(Data input)
tSIH
MSB
tSOSSS
MISO
(Data output)
tSSCK
LSB
tSOS
MSB
tSOSSH
LSB
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Table 36-127. SPI timing characteristics and requirements.
Symbol
Parameter
Condition
Min.
Typ.
Max.
tSCK
SCK Period
Master
(See Table 21-4 in
XMEGA AU Manual)
tSCKW
SCK high/low width
Master
0.5×SCK
tSCKR
SCK Rise time
Master
2.7
tSCKF
SCK Fall time
Master
2.7
tMIS
MISO setup to SCK
Master
10
tMIH
MISO hold after SCK
Master
10
tMOS
MOSI setup SCK
Master
0.5×SCK
tMOH
MOSI hold after SCK
Master
1
tSSCK
Slave SCK Period
Slave
4×t ClkPER
tSSCKW
SCK high/low width
Slave
2×t ClkPER
tSSCKR
SCK Rise time
Slave
1600
tSSCKF
SCK Fall time
Slave
1600
tSIS
MOSI setup to SCK
Slave
3
tSIH
MOSI hold after SCK
Slave
t ClkPER
tSSS
SS setup to SCK
Slave
21
tSSH
SS hold after SCK
Slave
20
tSOS
MISO setup SCK
Slave
8
tSOH
MISO hold after SCK
Slave
13
tSOSS
MISO setup after SS low
Slave
11
tSOSH
MISO hold after SS high
Slave
8
Units
ns
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36.4.16 Two-Wire Interface Characteristics
Table 36-128 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR
XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer
to Figure 36-28.
Figure 36-28. Two-wire interface bus timing.
tof
tHIGH
tLOW
tr
SCL
tSU;STA
tHD;STA
tHD;DAT
tSU;STO
tSU;DAT
SDA
tBUF
Table 36-128. Two-wire interface characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VIH
Input High Voltage
0.7VCC
VCC+0.5
V
VIL
Input Low Voltage
0.5
0.3×VCC
V
Vhys
Hysteresis of Schmitt Trigger Inputs
VOL
Output Low Voltage
tr
Rise Time for both SDA and SCL
tof
Output Fall Time from VIHmin to VILmax
tSP
Spikes Suppressed by Input Filter
II
Input Current for each I/O Pin
CI
Capacitance for each I/O Pin
fSCL
SCL Clock Frequency
0.05VCC (1)
3mA, sink current
10pF < Cb < 400pF (2)
0.1VCC < VI < 0.9VCC
fPER (3)>max(10fSCL, 250kHz)
0
0.4
V
20+0.1Cb (1)(2)
300
ns
20+0.1Cb (1)(2)
250
ns
0
50
ns
-10
10
µA
10
pF
400
kHz
0
fSCL ≤ 100kHz
RP
tHD;STA
Value of Pull-up resistor
Hold Time (repeated) START condition
tLOW
Low Period of SCL Clock
tHIGH
High Period of SCL Clock
tSU;STA
Set-up time for a repeated START
condition
fSCL > 100kHz
V
V CC – 0.4V
---------------------------3mA
fSCL ≤ 100kHz
4.0
fSCL > 100kHz
0.6
fSCL ≤ 100kHz
4.7
fSCL > 100kHz
1.3
fSCL ≤ 100kHz
4.0
fSCL > 100kHz
0.6
fSCL ≤ 100kHz
4.7
fSCL > 100kHz
0.6
100ns
--------------Cb
300ns
--------------Cb
XMEGA A4U [DATASHEET]
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Ω
µs
µs
µs
µs
157
Symbol
Parameter
tHD;DAT
Data hold time
tSU;DAT
Data setup time
tSU;STO
Setup time for STOP condition
Bus free time between a STOP and
START condition
tBUF
Notes:
1.
2.
3.
Condition
Min.
Typ.
Max.
fSCL ≤ 100kHz
0
3.45
fSCL > 100kHz
0
0.9
fSCL ≤ 100kHz
250
fSCL > 100kHz
100
fSCL ≤ 100kHz
4.0
fSCL > 100kHz
0.6
fSCL ≤ 100kHz
4.7
fSCL > 100kHz
1.3
Units
µs
ns
µs
µs
Required only for fSCL > 100kHz.
Cb = Capacitance of one bus line in pF.
fPER = Peripheral clock frequency.
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37.
Typical Characteristics
37.1
ATxmega16A4U
37.1.1 Current consumption
37.1.1.1 Active mode supply current
Figure 37-1. Active supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
ICC [ µA]
600
540
3.3V
480
3.0V
420
2.7V
360
300
2.2V
240
1.8V
180
120
60
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
Figure 37-2. Active supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
12
3.3V
10
3.0V
2.7V
ICC [mA]
8
6
2.2V
4
1.8V
2
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
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Figure 37-3. Active mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator.
270
-40 °C
250
230
25 °C
210
85 °C
105 °C
ICC [uA]
190
170
150
130
110
90
70
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-4. Active mode supply current vs. VCC.
fSYS = 1MHz external clock.
800
-40 °C
25 °C
85 °C
105 °C
700
ICC [uA]
600
500
400
300
200
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
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Figure 37-5. Active mode supply current vs. VCC.
fSYS = 2MHz internal oscillator.
1600
-40 °C
25 °C
85 °C
105 °C
1400
ICC [uA]
1200
1000
800
600
400
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-6. Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
5900
-40 °C
25 °C
85 °C
105 °C
5400
4900
4400
ICC [uA]
3900
3400
2900
2400
1900
1400
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
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Figure 37-7. Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator.
5650
-40 °C
5425
5200
25 °C
4975
85 °C
105 °C
ICC [uA]
4750
4525
4300
4075
3850
3625
3400
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
37.1.1.2 Idle mode supply current
Figure 37-8. Idle mode supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
I CC [µA]
140
3.3V
120
3.0V
100
2.7V
80
2.2V
60
1.8V
40
20
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency [MHz]
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Figure 37-9. Idle mode supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
4.5
3.3V
4.0
3.0V
3.5
2.7V
I CC [mA]
3.0
2.5
2.0
2.2V
1.5
1.0
1.8V
0.5
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
Figure 37-10. Idle mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator.
35
105 °C
34
33
-40 °C
85 °C
25 °C
ICC [uA]
32
31
30
29
28
27
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
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Figure 37-11. Idle mode supply current vs. VCC.
fSYS = 1MHz external clock.
158
105 °C
85 °C
25 °C
-40 °C
146
134
ICC [uA]
122
110
98
86
74
62
50
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-12. Idle mode supply current vs. VCC.
fSYS = 2MHz internal oscillator.
410
-40 °C
25 °C
85 °C
105 °C
385
360
ICC [uA]
335
310
285
260
235
210
185
160
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
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Figure 37-13. Idle mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
2000
-40 °C
25 °C
85 °C
105 °C
1800
1600
ICC [uA]
1400
1200
1000
800
600
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-14. Idle mode current vs. VCC.
fSYS = 32MHz internal oscillator.
5650
-40 °C
5425
5200
25 °C
4975
85 °C
105 °C
ICC [uA]
4750
4525
4300
4075
3850
3625
3400
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
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37.1.1.3 Power-down mode supply current
Figure 37-15. Power-down mode supply current vs. temperature.
All functions disabled.
3.50
3.6 V
3.00
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
ICC [uA]
2.50
2.00
1.50
1.00
0.50
0.00
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
Figure 37-16. Power-down mode supply current vs. VCC.
All functions disabled.
3.6
105 °C
3.2
2.8
ICC [uA]
2.4
2.0
1.6
1.2
85 °C
0.8
0.4
25 °C
- 40 °C
0.0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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Figure 37-17. Power-down mode supply current vs. VCC.
Watchdog and sampled BOD enabled.
5.1
105 °C
4.6
4.1
ICC [µA]
3.6
3.1
85 °C
2.6
2.1
1.6
25 °C
-40 °C
1.1
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
37.1.1.4 Power-save mode supply current
Figure 37-18. Power-save mode supply current vs.VCC.
Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC.
0.9
Normal mode
0.8
0.7
ICC [µA]
0.6
Low-power mode
0.5
0.4
0.3
0.2
0.1
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
V CC [V]
XMEGA A4U [DATASHEET]
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37.1.1.5 Standby mode supply current
Figure 37-19. Standby supply current vs. VCC.
Standby, fSYS = 1MHz.
12.5
105 °C
11.5
10.5
9.5
85 °C
ICC [uA]
8.5
25 °C
-40 °C
7.5
6.5
5.5
4.5
3.5
2.5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-20. Standby supply current vs. VCC.
25°C, running from different crystal oscillators.
480
16MHz
12MHz
440
ICC [µA]
400
360
320
8MHz
2MHz
280
240
0.454MHz
200
160
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC[V]
XMEGA A4U [DATASHEET]
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37.1.2 I/O Pin Characteristics
37.1.2.1 Pull-up
Figure 37-21. I/O pin pull-up resistor current vs. input voltage.
VCC = 1.8V.
72
64
56
48
I [µA]
40
32
24
- 40 °C
25 °C
85 °C
105 °C
16
8
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VPIN [V]
Figure 37-22. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.0V.
120
105
90
I [µA]
75
60
45
-40 °C
25 °C
85 °C
105 °C
30
15
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VPIN [V]
XMEGA A4U [DATASHEET]
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Figure 37-23. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.3V.
135
120
105
90
I [µA]
75
60
45
-40 °C
25 °C
85 °C
105 °C
30
15
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
-1
0
VPIN [V]
37.1.2.2 Output Voltage vs. Sink/Source Current
Figure 37-24. I/O pin output voltage vs. source current.
VCC = 1.8V.
1.8
1.6
1.4
VPIN [V]
1.2
1.0
0.8
-40 °C
25 °C
0.6
0.4
105 °C
85 °C
0.2
0.0
-10
-9
-8
-7
-6
-5
-4
-3
-2
IPIN [mA]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
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Figure 37-25. I/O pin output voltage vs. source current.
VCC = 3.0V.
3.0
2.7
2.4
2.1
VPIN [V]
1.8
1.5
1.2
- 40 °C
0.9
25 °C 85 °C
0.6
105 °C
0.3
0.0
-32
-28
-24
-20
-16
-12
-8
-4
0
-12
-8
-4
0
IPIN [mA]
Figure 37-26. I/O pin output voltage vs. source current.
VCC = 3.3V.
3.3
3.0
2.7
VPIN [V]
2.4
2.1
1.8
-40 °C
1.5
1.2
25 °C
0.9
0.6
85 °C
0.3
105 °C
0.0
-32
-28
-24
-20
-16
IPIN [mA]
XMEGA A4U [DATASHEET]
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Figure 37-27. I/O pin output voltage vs. source current.
4.0
3.5
3.6V
3.3V
3.0
3.0V
VPIN [V]
2.7V
2.5
2.3V
2.0
1.8V
1.5
1.0
0.5
-24
-21
-18
-15
-12
-9
-6
-3
0
IPIN [mA]
Figure 37-28. I/O pin output voltage vs. sink current.
VCC = 1.8V.
1.0
105 °C
85 °C
0.9
0.8
0.7
25 °C
VPIN [V]
0.6
-40 °C
0.5
0.4
0.3
0.2
0.1
0.0
0
2
4
6
8
10
12
14
16
IPIN [mA]
XMEGA A4U [DATASHEET]
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Figure 37-29. I/O pin output voltage vs. sink current.
VCC = 3.0V.
0.7
0.6
105 °C
85 °C
0.5
25 °C
-40 °C
VPIN [V]
0.4
0.3
0.2
0.1
0.0
0
2
4
6
8
10
12
14
16
18
20
IPIN [mA]
Figure 37-30. I/O pin output voltage vs. sink current.
VCC = 3.3V.
1.0
105 °C
85 °C
0.9
25 °C
-40 °C
0.8
0.7
VPIN [V]
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
4
8
12
16
20
24
28
32
IPIN [mA]
Figure 37-31. I/O pin output voltage vs. sink current.
1.5
1.8V
V PIN [V]
1.2
2.3V
2.7V
3.0V
3.3V
3.6V
0.9
0.6
0.3
0
0
5
10
15
20
25
30
I PIN [mA]
XMEGA A4U [DATASHEET]
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37.1.2.3 Thresholds and Hysteresis
Figure 37-32. I/O pin input threshold voltage vs. VCC.
T = 25°C.
1.8
VIH
1.6
VIL
Vthreshold [V]
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vcc [V]
Figure 37-33. I/O pin input threshold voltage vs. VCC.
VIH I/O pin read as “1”.
1.8
-40 °C
25 °C
85 °C
105 °C
1.7
1.6
Vthreshold [V]
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
174
Figure 37-34. I/O pin input threshold voltage vs. VCC.
VIL I/O pin read as “0”.
1.75
-40 °C
25 °C
85 °C
105 °C
1.60
1.45
Vthreshold [V]
1.30
1.15
1.00
0.85
0.70
0.55
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-35. I/O pin input hysteresis vs. VCC.
0.32
0.29
0.26
Vthreshold [V]
0.23
25 °C
0.20
0.17
-40 °C
85 °C
0.14
0.11
105 °C
0.08
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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175
37.1.3 ADC Characteristics
Figure 37-36. INL error vs. external VREF.
T = 25°C, VCC = 3.6V, external reference.
1.8
1.7
1.6
Differential Signed
INL [LSB]
1.5
Single-ended Unsigned
1.4
1.3
1.2
1.1
1
0.9
Single-ended Signed
0.8
0.7
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
1700
1850
3
VREF [V]
Figure 37-37. INL error vs. sample rate.
T = 25°C, VCC = 3.6V, VREF = 3.0V external.
1.4
1.35
1.3
Differential Mode
INL [LSB]
1.25
1.2
Single-ended Unsigned
1.15
1.1
1.05
Single-ended Signed
1
0.95
0.9
500
650
800
950
1100
1250
1400
1550
2000
ADC Sample Rate [kSPS]
XMEGA A4U [DATASHEET]
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176
Figure 37-38. INL error vs. input code
2.0
1.5
INL [LSB]
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
0
512
1024
1536
2048
2560
3072
3584
4096
ADC input code
Figure 37-39. DNL error vs. external VREF.
T = 25°C, VCC = 3.6V, external reference.
0.9
0.88
0.86
DNL [LSB]
Differential Mode
0.84
Single-ended Signed
0.82
0.8
0.78
Single-ended Unsigned
0.76
0.74
0.72
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
XMEGA A4U [DATASHEET]
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177
Figure 37-40. DNL error vs. sample rate.
T = 25°C, VCC = 3.6V, VREF = 3.0V external.
0.9
0.89
Differential Signed
0.88
DNL [LSB]
0.87
0.86
0.85
Single-ended Signed
0.84
0.83
0.82
0.81
Single-ended Unsigned
0.8
0.79
500
650
800
950
1100
1250
1400
1550
1700
1850
2000
ADC Sample Rate [kSPS]
Figure 37-41. DNL error vs. input code.
0.8
0.6
DNL [LSB]
0.4
0.2
0
-0.2
-0.4
-0.6
0
512
1024
1536
2048
2560
3072
3584
4096
ADC Input Code
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
178
Figure 37-42. Gain error vs. VREF.
T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps.
3
Single-ended Signed
Gain Error [mV]
2
1
Differential Mode
0
-1
Single-ended Unsigned
-2
-3
-4
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VREF [V]
Figure 37-43. Gain error vs. VCC.
T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps.
2.2
1.9
Single-ended Signed
Gain Error [mV]
1.6
1.3
Differential Mode
1
0.7
0.4
Single-ended Unsigned
0.1
-0.2
-0.5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VCC [V]
XMEGA A4U [DATASHEET]
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179
Figure 37-44. Offset error vs. VREF.
T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps.
-1
Offset Error [mV]
-1.1
-1.2
-1.3
-1.4
-1.5
Differential Mode
-1.6
-1.7
-1.8
-1.9
-2
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
Figure 37-45. Gain error vs. temperature.
VCC = 3.0V, VREF = external 2.0V.
4
Single-ended signed mode
3
Gain Error [mV]
2
1
Dif f erential mode
0
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
-1
-2
Single-ended unsigned mode
-3
-4
Temperature [ºC]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
180
Figure 37-46. Offset error vs. VCC.
T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps.
-0.3
-0.4
Offset Error [mV]
-0.5
-0.6
-0.7
Differential Signed
-0.8
-0.9
-1
-1.1
-1.2
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-47. Noise vs. VREF.
T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps.
1.3
Single-ended Signed
Noise [mV RMS]
1.15
Single-ended Unsigned
1
0.85
0.7
0.55
Differential Signed
0.4
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
181
Figure 37-48. Noise vs. VCC.
T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps.
1.3
1.2
Single-ended Signed
Noise [mV RMS]
1.1
1
0.9
0.8
Single-ended Unsigned
0.7
0.6
0.5
Differential Signed
0.4
0.3
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
37.1.4 DAC Characteristics
Figure 37-49. DAC INL error vs. VREF.
VCC = 3.6V.
3.0
2.5
INL [LSB]
2.0
1.5
- 40°C
1.0
25°C
85°C
105°C
0.5
0.0
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
182
Figure 37-50. DNL error vs. VREF.
VCC = 3.6V.
1.6
1.4
DNL[LSB]
1.2
1.0
- 40°C
0.8
25ºC
85°C
105°C
0.6
0.4
0.2
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
Figure 37-51. DAC noise vs. temperature.
VCC = 3.0V, VREF = 2.4V .
0.185
0.180
Noise [mV RMS]
0.175
0.170
0.165
0.160
0.155
0.150
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [ºC]
XMEGA A4U [DATASHEET]
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183
37.1.5 Analog Comparator Characteristics
Figure 37-52. Analog comparator hysteresis vs. VCC.
High-speed, small hysteresis.
18
105 °C
85 °C
-40° C
25 °C
17
16
15
14
VHYST [mV]
13
12
11
10
9
8
7
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-53. Analog comparator hysteresis vs. VCC.
Low power, small hysteresis.
35
105 °C
85 °C
34
33
32
VHYST [mV]
31
25 °C
30
29
28
-40 °C
27
26
25
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
184
Figure 37-54. Analog comparator hysteresis vs. VCC.
High-speed mode, large hysteresis.
42
105 °C
85 °C
40
38
25 °C
-40 °C
36
VHYST [mV]
34
32
30
28
26
24
22
20
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-55. Analog comparator hysteresis vs. VCC.
Low power, large hysteresis.
77
105 °C
74
85 °C
71
VHYST [mV]
68
65
25 °C
62
59
-40 °C
56
53
50
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
185
Figure 37-56. Analog comparator current source vs. calibration value.
Temperature = 25°C.
7.4
ICURRENTSOURCE [µA]
6.8
6.2
5.6
5.0
4.4
3.3 V
3.0 V
2.7 V
3.8
3.2
2.2 V
1.8 V
1.6 V
2.6
2.0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CURRCALIBA[3..0]
Figure 37-57. Analog comparator current source vs. calibration value.
VCC = 3.0V.
VCC 3.0V
7
ICURRENTSOURCE [uA]
6.5
6
5.5
5
-40 °C
25 °C
85 °C
105 °C
4.5
4
3.5
3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CURRCALIBA[3..0]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
186
Figure 37-58. Voltage scaler INL vs. SCALEFAC.
T = 25°C, VCC = 3.0V.
0.050
0.025
INL [LSB]
0
-0.025
-0.050
-0.075
-0.100
25°C
-0.125
-0.150
0
10
20
30
40
50
60
70
SCALEFAC
37.1.6 Internal 1.0V reference Characteristics
Figure 37-59. ADC/DAC Internal 1.0V reference
Calibratedvs.
at Ttemperature.
85 C
1.004
1.6 V
1.8 V
2.2 V
2.7 V
3.0 V
3.6 V
1.002
Bandgap Voltage [V]
1.000
0.998
0.996
0.994
0.992
0.990
0.988
0.986
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
187
37.1.7 BOD Characteristics
Figure 37-60. BOD thresholds vs. temperature.
BOD level = 1.6V.
1.635
Rising Vcc
1.630
VBOT [V]
1.625
Falling Vcc
1.620
1.615
1.610
1.605
1.600
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
Figure 37-61. BOD thresholds vs. temperature.
BOD level = 3.0V.
3.06
Rising Vcc
3.05
3.04
VBOT [V]
3.03
3.02
3.01
Falling Vcc
3.00
2.99
2.98
2.97
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
188
37.1.8 External Reset Characteristics
Figure 37-62. Minimum Reset pin pulse width vs. VCC.
130
125
120
115
tRST [ns]
110
105
100
105 °C
85 °C
95
90
25 °C
-40 °C
85
80
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-63. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 1.8V.
72
64
56
IRESET [uA]
48
40
32
24
-40 °C
25 °C
85 °C
105 °C
16
8
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VRESET [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
189
Figure 37-64. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.0V.
120
105
90
IRESET [µA]
75
60
45
-40 °C
25 °C
85 °C
105 °C
30
15
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VRESET [V]
Figure 37-65. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.3V.
140
120
IRESET [uA]
100
80
60
40
-40 °C
25 °C
85 °C
105 °C
20
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
VRESET [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
190
Figure 37-66. Reset pin input threshold voltage vs. VCC.
VIH - Reset pin read as “1”.
2.20
-40 °C
25 °C
85 °C
105 °C
2.05
Vthreshold [V]
1.90
1.75
1.60
1.45
1.30
1.15
1.00
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-67. Reset pin input threshold voltage vs. VCC.
VIL - Reset pin read as “0”.
1.75
-40 °C
25 °C
85 °C
105 °C
1.60
1.45
Vthreshold [V]
1.30
1.15
1.00
0.85
0.70
0.55
0.40
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
191
37.1.9 Power-on Reset Characteristics
Figure 37-68. Power-on reset current consumption vs. VCC.
BOD level = 3.0V, enabled in continuous mode.
ICC [µA]
700
-40 °C
600
25 °C
500
85 °C
105 °C
400
300
200
100
0
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
VCC [V]
Figure 37-69. Power-on reset current consumption vs. VCC.
BOD level = 3.0V, enabled in sampled mode.
650
-40 °C
585
520
25 °C
ICC [µA]
455
85
° °C
105°°C
390
325
260
195
130
65
0
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
192
37.1.10 Oscillator Characteristics
37.1.10.1 Ultra Low-Power internal oscillator
Figure 37-70. Ultra Low-Power internal oscillator frequency vs. temperature.
32.8
32.4
Frequency [kHz]
32.0
31.6
31.2
30.8
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
30.4
30.0
29.6
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
37.1.10.2 32.768kHz Internal Oscillator
Figure 37-71. 32.768kHz internal oscillator frequency vs. temperature.
32.875
3.6 V
3.0 V
2.2 V
2.7 V
1.8 V
1.6 V
32.850
Frequency [kHz]
32.825
32.800
32.775
32.750
32.725
32.700
32.675
32.650
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
193
Figure 37-72. 32.768kHz internal oscillator frequency vs. calibration value.
VCC = 3.0V, T = 25°C.
55
Frequency [kHz]
50
45
40
35
30
25
20
0
26
52
78
104
130
156
182
208
234
260
RC32KCAL[7..0]
37.1.10.3 2MHz Internal Oscillator
Figure 37-73. 2MHz internal oscillator frequency vs. temperature.
DFLL disabled.
2.16
2.14
Frequency [MHz]
2.12
2.10
2.08
2.06
2.04
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
2.02
2.00
1.98
1.96
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
194
Figure 37-74. 2MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator .
2.0085
2.0070
3.6 V
1.6 V
2.2 V
1.8 V
3.0 V
2.7 V
Frequency [MHz]
2.0055
2.0040
2.0025
2.0010
1.9995
1.9980
1.9965
1.9950
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
Figure 37-75. 2MHz internal oscillator CALA calibration step size.
VCC = 3V.
0.31 %
Frequency Step size [%]
0.29 %
0.27 %
0.25 %
0.23 %
0.21 %
-40 °C
0.19 %
25 °C
85 °C
105 °C
0.17 %
0.15 %
0
16
32
48
64
80
96
112
128
CALA
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
195
37.1.10.4 32MHz Internal Oscillator
Figure 37-76. 32MHz internal oscillator frequency vs. temperature.
DFLL disabled.
36.0
35.5
Frequency [MHz]
35.0
34.5
34.0
33.5
33.0
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
32.5
32.0
31.5
31.0
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
Figure 37-77. 32MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
32.145
3.6 V
1.61.6
V V
1.8 V
2.2 V
2.7 V
3.0 V
32.120
Frequency [MHz]
32.095
32.070
32.045
32.020
31.995
31.970
31.945
31.920
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
196
Figure 37-78. 32MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
0.38 %
Frequency Step size [%]
0.34 %
0.30 %
0.26 %
0.22 %
85°C
105°C
25°C
- 40°C
0.18 %
0.14 %
0.10 %
0
16
32
48
64
80
96
112
128
CALA
Figure 37-79. 32MHz internal oscillator frequency vs. CALB calibration value.
VCC = 3.0V.
75
- 40°C
25°C
85°C
105°C
70
Frequency [MHz]
65
60
55
50
45
40
35
30
25
0
8
16
24
32
40
48
56
64
CALB
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
197
37.1.10.5 32MHz internal oscillator calibrated to 48MHz
Figure 37-80. 48MHz internal oscillator frequency vs. temperature.
DFLL disabled.
54
53
Frequency [MHz]
52
51
50
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
49
48
47
46
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
Figure 37-81. 48MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
48.25
3.6 V
1.6 V
1.8 V
2.7 V
2.2 V
48.20
Frequency [MHz]
48.15
48.10
3.0 V
48.05
48.00
47.95
47.90
47.85
47.80
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
198
Figure 37-82. 48MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
V
3.0 V
CC
0.34 %
Frequency Step size [%]
0.31 %
0.28 %
0.25 %
0.22 %
0.19 %
-40 °C
25 °C
0.16 %
85 °C
105 °C
0.13 %
0.10 %
0
16
32
48
64
80
96
112
128
CALA
37.1.11 Two-Wire Interface characteristics
Figure 37-83. SDA hold time vs. supply voltage.
300
295
290
Holdtime [ns]
285
105°C
280
85°C
275
270
25°C
265
- 40°C
260
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Vcc [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
199
37.1.12 PDI characteristics
Figure 37-84. Maximum PDI frequency vs. VCC.
34
25 °C
105 °C
-40 °C
85 °C
31
28
f MAX [MHz]
25
22
19
16
13
10
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
200
37.2
ATxmega32A4U
37.2.1 Current consumption
37.2.1.1 Active mode supply current
Figure 37-85.Active supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
ICC [ µA]
600
540
3.3V
480
3.0V
420
2.7V
360
300
2.2V
240
1.8V
180
120
60
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
Figure 37-86.Active supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
12
3.3V
10
3.0V
2.7V
ICC [mA]
8
6
2.2V
4
1.8V
2
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
201
Figure 37-87.Active mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator.
270
-40 °C
250
230
25 °C
210
85 °C
105 °C
ICC [uA]
190
170
150
130
110
90
70
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-88.Active mode supply current vs. VCC.
fSYS = 1MHz external clock.
800
-40 °C
25 °C
85 °C
105 °C
700
ICC [uA]
600
500
400
300
200
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
202
Figure 37-89.Active mode supply current vs. VCC.
fSYS = 2MHz internal oscillator.
1600
-40 °C
25 °C
85 °C
105 °C
1400
ICC [uA]
1200
1000
800
600
400
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-90.Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
5900
-40 °C
25 °C
85 °C
105 °C
5400
4900
4400
ICC [uA]
3900
3400
2900
2400
1900
1400
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
203
Figure 37-91.Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator.
5650
-40 °C
5425
5200
25 °C
4975
85 °C
105 °C
ICC [uA]
4750
4525
4300
4075
3850
3625
3400
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
37.2.1.2 Idle mode supply current
Figure 37-92.Idle mode supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
I CC [µA]
140
3.3V
120
3.0V
100
2.7V
80
2.2V
60
1.8V
40
20
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency [MHz]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
204
Figure 37-93.Idle mode supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
4.5
3.3V
4.0
3.0V
3.5
2.7V
I CC [mA]
3.0
2.5
2.0
2.2V
1.5
1.0
1.8V
0.5
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
Figure 37-94. Idle mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator.
35
105 °C
34
33
-40 °C
85 °C
25 °C
ICC [uA]
32
31
30
29
28
27
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
205
Figure 37-95. Idle mode supply current vs. VCC.
fSYS = 1MHz external clock.
158
105 °C
85 °C
25 °C
-40 °C
146
134
ICC [uA]
122
110
98
86
74
62
50
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-96. Idle mode supply current vs. VCC.
fSYS = 2MHz internal oscillator.
410
-40 °C
25 °C
85 °C
105 °C
385
360
ICC [uA]
335
310
285
260
235
210
185
160
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
206
Figure 37-97. Idle mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
2000
-40 °C
25 °C
85 °C
105 °C
1800
1600
ICC [uA]
1400
1200
1000
800
600
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-98. Idle mode current vs. VCC.
fSYS = 32MHz internal oscillator.
5650
-40 °C
5425
5200
25 °C
4975
85 °C
105 °C
ICC [uA]
4750
4525
4300
4075
3850
3625
3400
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
207
37.2.1.3 Power-down mode supply current
Figure 37-99. Power-down mode supply current vs. temperature.
All functions disabled.
3.50
3.6 V
3.00
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
ICC [uA]
2.50
2.00
1.50
1.00
0.50
0.00
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
Figure 37-100. Power-down mode supply current vs. VCC.
All functions disabled.
3.6
105 °C
3.2
2.8
ICC [uA]
2.4
2.0
1.6
1.2
85 °C
0.8
0.4
25 °C
- 40 °C
0.0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
208
Figure 37-101. Power-down mode supply current vs. VCC.
Watchdog and sampled BOD enabled.
5.1
105 °C
4.6
4.1
ICC [µA]
3.6
3.1
85 °C
2.6
2.1
1.6
25 °C
-40 °C
1.1
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
37.2.1.4 Power-save mode supply current
Figure 37-102. Power-save mode supply current vs.VCC.
Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC.
0.9
Normal mode
0.8
0.7
ICC [µA]
0.6
Low-power mode
0.5
0.4
0.3
0.2
0.1
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
V CC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
209
37.2.1.5 Standby mode supply current
Figure 37-103. Standby supply current vs. VCC.
Standby, fSYS = 1MHz.
12.5
105 °C
11.5
10.5
9.5
85 °C
ICC [uA]
8.5
25 °C
-40 °C
7.5
6.5
5.5
4.5
3.5
2.5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-104. Standby supply current vs. VCC.
25°C, running from different crystal oscillators.
480
16MHz
12MHz
440
ICC [µA]
400
360
320
8MHz
2MHz
280
240
0.454MHz
200
160
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC[V]
XMEGA A4U [DATASHEET]
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37.2.2 I/O Pin Characteristics
37.2.2.1 Pull-up
Figure 37-105. I/O pin pull-up resistor current vs. input voltage.
VCC = 1.8V.
72
64
56
48
I [µA]
40
32
24
- 40 °C
25 °C
85 °C
105 °C
16
8
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VPIN [V]
Figure 37-106. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.0V.
120
105
90
I [µA]
75
60
45
-40 °C
25 °C
85 °C
105 °C
30
15
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VPIN [V]
XMEGA A4U [DATASHEET]
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Figure 37-107. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.3V.
135
120
105
90
I [µA]
75
60
45
-40 °C
25 °C
85 °C
105 °C
30
15
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
-1
0
VPIN [V]
37.2.2.2 Output Voltage vs. Sink/Source Current
Figure 37-108. I/O pin output voltage vs. source current.
VCC = 1.8V.
1.8
1.6
1.4
VPIN [V]
1.2
1.0
0.8
-40 °C
25 °C
0.6
0.4
105 °C
85 °C
0.2
0.0
-10
-9
-8
-7
-6
-5
-4
-3
-2
IPIN [mA]
XMEGA A4U [DATASHEET]
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Figure 37-109. I/O pin output voltage vs. source current.
VCC = 3.0V.
3.0
2.7
2.4
2.1
VPIN [V]
1.8
1.5
1.2
- 40 °C
0.9
25 °C 85 °C
0.6
105 °C
0.3
0.0
-32
-28
-24
-20
-16
-12
-8
-4
0
-12
-8
-4
0
IPIN [mA]
Figure 37-110. I/O pin output voltage vs. source current.
VCC = 3.3V.
3.3
3.0
2.7
VPIN [V]
2.4
2.1
1.8
-40 °C
1.5
1.2
25 °C
0.9
0.6
85 °C
0.3
105 °C
0.0
-32
-28
-24
-20
-16
IPIN [mA]
XMEGA A4U [DATASHEET]
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Figure 37-111. I/O pin output voltage vs. source current.
4.0
3.5
3.6V
3.3V
3.0
3.0V
VPIN [V]
2.7V
2.5
2.3V
2.0
1.8V
1.5
1.0
0.5
-24
-21
-18
-15
-12
-9
-6
-3
0
IPIN [mA]
Figure 37-112. I/O pin output voltage vs. sink current.
VCC = 1.8V.
1.0
105 °C
85 °C
0.9
0.8
0.7
25 °C
VPIN [V]
0.6
-40 °C
0.5
0.4
0.3
0.2
0.1
0.0
0
2
4
6
8
10
12
14
16
IPIN [mA]
XMEGA A4U [DATASHEET]
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Figure 37-113. I/O pin output voltage vs. sink current.
VCC = 3.0V.
0.7
0.6
105 °C
85 °C
0.5
25 °C
-40 °C
VPIN [V]
0.4
0.3
0.2
0.1
0.0
0
2
4
6
8
10
12
14
16
18
20
IPIN [mA]
Figure 37-114. I/O pin output voltage vs. sink current.
VCC = 3.3V.
1.0
105 °C
85 °C
0.9
25 °C
-40 °C
0.8
0.7
VPIN [V]
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
4
8
12
16
20
24
28
32
IPIN [mA]
Figure 37-115. I/O pin output voltage vs. sink current.
1.5
1.8V
V PIN [V]
1.2
2.3V
2.7V
3.0V
3.3V
3.6V
0.9
0.6
0.3
0
0
5
10
15
20
25
30
I PIN [mA]
XMEGA A4U [DATASHEET]
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37.2.2.3 Thresholds and Hysteresis
Figure 37-116. I/O pin input threshold voltage vs. VCC.
T = 25°C.
1.8
VIH
1.6
VIL
Vthreshold [V]
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vcc [V]
Figure 37-117. I/O pin input threshold voltage vs. VCC.
VIH I/O pin read as “1”.
1.8
-40 °C
25 °C
85 °C
105 °C
1.7
1.6
Vthreshold [V]
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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Figure 37-118. I/O pin input threshold voltage vs. VCC.
VIL I/O pin read as “0”.
1.75
-40 °C
25 °C
85 °C
105 °C
1.60
1.45
Vthreshold [V]
1.30
1.15
1.00
0.85
0.70
0.55
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-119. I/O pin input hysteresis vs. VCC.
0.32
0.29
0.26
Vthreshold [V]
0.23
25 °C
0.20
0.17
-40 °C
85 °C
0.14
0.11
105 °C
0.08
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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37.2.3 ADC Characteristics
Figure 37-120. INL error vs. external VREF.
T = 25°C, VCC = 3.6V, external reference.
1.8
1.7
1.6
Differential Signed
INL [LSB]
1.5
Single-ended Unsigned
1.4
1.3
1.2
1.1
1
0.9
Single-ended Signed
0.8
0.7
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
1700
1850
3
VREF [V]
Figure 37-121. INL error vs. sample rate.
T = 25°C, VCC = 3.6V, VREF = 3.0V external.
1.4
1.35
1.3
Differential Mode
INL [LSB]
1.25
1.2
Single-ended Unsigned
1.15
1.1
1.05
Single-ended Signed
1
0.95
0.9
500
650
800
950
1100
1250
1400
1550
2000
ADC Sample Rate [kSPS]
XMEGA A4U [DATASHEET]
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Figure 37-122. INL error vs. input code
2.0
1.5
INL [LSB]
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
0
512
1024
1536
2048
2560
3072
3584
4096
ADC input code
Figure 37-123. DNL error vs. external VREF.
T = 25°C, VCC = 3.6V, external reference.
0.9
0.88
0.86
DNL [LSB]
Differential Mode
0.84
Single-ended Signed
0.82
0.8
0.78
Single-ended Unsigned
0.76
0.74
0.72
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
XMEGA A4U [DATASHEET]
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Figure 37-124. DNL error vs. sample rate.
T = 25°C, VCC = 3.6V, VREF = 3.0V external.
0.9
0.89
Differential Signed
0.88
DNL [LSB]
0.87
0.86
0.85
Single-ended Signed
0.84
0.83
0.82
0.81
Single-ended Unsigned
0.8
0.79
500
650
800
950
1100
1250
1400
1550
1700
1850
2000
ADC Sample Rate [kSPS]
Figure 37-125. DNL error vs. input code.
0.8
0.6
DNL [LSB]
0.4
0.2
0
-0.2
-0.4
-0.6
0
512
1024
1536
2048
2560
3072
3584
4096
ADC Input Code
XMEGA A4U [DATASHEET]
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Figure 37-126. Gain error vs. VREF.
T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps.
3
Single-ended Signed
Gain Error [mV]
2
1
Differential Mode
0
-1
Single-ended Unsigned
-2
-3
-4
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VREF [V]
Figure 37-127. Gain error vs. VCC.
T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps.
2.2
1.9
Single-ended Signed
Gain Error [mV]
1.6
1.3
Differential Mode
1
0.7
0.4
Single-ended Unsigned
0.1
-0.2
-0.5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VCC [V]
XMEGA A4U [DATASHEET]
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Figure 37-128. Offset error vs. VREF.
T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps.
-1
Offset Error [mV]
-1.1
-1.2
-1.3
-1.4
-1.5
Differential Mode
-1.6
-1.7
-1.8
-1.9
-2
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
Figure 37-129. Gain error vs. temperature.
VCC = 3.0V, VREF = external 2.0V.
4
Single-ended signed mode
3
Gain Error [mV]
2
1
Dif f erential mode
0
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
-1
-2
Single-ended unsigned mode
-3
-4
Temperature [ºC]
XMEGA A4U [DATASHEET]
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Figure 37-130. Offset error vs. VCC.
T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps.
-0.3
-0.4
Offset Error [mV]
-0.5
-0.6
-0.7
Differential Signed
-0.8
-0.9
-1
-1.1
-1.2
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-131. Noise vs. VREF.
T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps.
1.3
Single-ended Signed
Noise [mV RMS]
1.15
Single-ended Unsigned
1
0.85
0.7
0.55
Differential Signed
0.4
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
XMEGA A4U [DATASHEET]
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Figure 37-132. Noise vs. VCC.
T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps.
1.3
1.2
Single-ended Signed
Noise [mV RMS]
1.1
1
0.9
0.8
Single-ended Unsigned
0.7
0.6
0.5
Differential Signed
0.4
0.3
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
37.2.4 DAC Characteristics
Figure 37-133. DAC INL error vs. VREF.
VCC = 3.6V.
3.0
2.5
INL [LSB]
2.0
1.5
- 40°C
1.0
25°C
85°C
105°C
0.5
0.0
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
XMEGA A4U [DATASHEET]
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Figure 37-134. DNL error vs. VREF.
VCC = 3.6V.
1.6
1.4
DNL[LSB]
1.2
1.0
- 40°C
0.8
25ºC
85°C
105°C
0.6
0.4
0.2
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
Figure 37-135. DAC noise vs. temperature.
VCC = 3.0V, VREF = 2.4V .
0.185
0.180
Noise [mV RMS]
0.175
0.170
0.165
0.160
0.155
0.150
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [ºC]
XMEGA A4U [DATASHEET]
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37.2.5 Analog Comparator Characteristics
Figure 37-136. Analog comparator hysteresis vs. VCC.
High-speed, small hysteresis.
18
105 °C
85 °C
-40° C
25 °C
17
16
15
14
VHYST [mV]
13
12
11
10
9
8
7
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-137. Analog comparator hysteresis vs. VCC.
Low power, small hysteresis.
35
105 °C
85 °C
34
33
32
VHYST [mV]
31
25 °C
30
29
28
-40 °C
27
26
25
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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Figure 37-138. Analog comparator hysteresis vs. VCC.
High-speed mode, large hysteresis.
42
105 °C
85 °C
40
38
25 °C
-40 °C
36
VHYST [mV]
34
32
30
28
26
24
22
20
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-139. Analog comparator hysteresis vs. VCC.
Low power, large hysteresis.
77
105 °C
74
85 °C
71
VHYST [mV]
68
65
25 °C
62
59
-40 °C
56
53
50
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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Figure 37-140. Analog comparator current source vs. calibration value.
Temperature = 25°C.
7.4
ICURRENTSOURCE [µA]
6.8
6.2
5.6
5.0
4.4
3.3 V
3.0 V
2.7 V
3.8
3.2
2.2 V
1.8 V
1.6 V
2.6
2.0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CURRCALIBA[3..0]
Figure 37-141. Analog comparator current source vs. calibration value.
VCC = 3.0V.
VCC 3.0V
7
ICURRENTSOURCE [uA]
6.5
6
5.5
5
-40 °C
25 °C
85 °C
105 °C
4.5
4
3.5
3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CURRCALIBA[3..0]
XMEGA A4U [DATASHEET]
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Figure 37-142. Voltage scaler INL vs. SCALEFAC.
T = 25°C, VCC = 3.0V.
0.050
0.025
INL [LSB]
0
-0.025
-0.050
-0.075
-0.100
25°C
-0.125
-0.150
0
10
20
30
40
50
60
70
SCALEFAC
37.2.6 Internal 1.0V reference Characteristics
Figure 37-143. ADC/DAC Internal 1.0V reference
vs.T temperature.
Calibrated at
85 C
1.004
1.6 V
1.8 V
2.2 V
2.7 V
3.0 V
3.6 V
1.002
Bandgap Voltage [V]
1.000
0.998
0.996
0.994
0.992
0.990
0.988
0.986
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
XMEGA A4U [DATASHEET]
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37.2.7 BOD Characteristics
Figure 37-144. BOD thresholds vs. temperature.
BOD level = 1.6V.
1.635
Rising Vcc
1.630
VBOT [V]
1.625
Falling Vcc
1.620
1.615
1.610
1.605
1.600
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
Figure 37-145. BOD thresholds vs. temperature.
BOD level = 3.0V.
3.06
Rising Vcc
3.05
3.04
VBOT [V]
3.03
3.02
3.01
Falling Vcc
3.00
2.99
2.98
2.97
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
230
37.2.8 External Reset Characteristics
Figure 37-146. Minimum Reset pin pulse width vs. VCC.
130
125
120
115
tRST [ns]
110
105
100
105 °C
85 °C
95
90
25 °C
-40 °C
85
80
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-147. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 1.8V.
72
64
56
IRESET [uA]
48
40
32
24
-40 °C
25 °C
85 °C
105 °C
16
8
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VRESET [V]
XMEGA A4U [DATASHEET]
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Figure 37-148. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.0V.
120
105
90
IRESET [µA]
75
60
45
-40 °C
25 °C
85 °C
105 °C
30
15
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VRESET [V]
Figure 37-149. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.3V.
140
120
IRESET [uA]
100
80
60
40
-40 °C
25 °C
85 °C
105 °C
20
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
VRESET [V]
XMEGA A4U [DATASHEET]
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232
Figure 37-150. Reset pin input threshold voltage vs. VCC.
VIH - Reset pin read as “1”.
2.20
-40 °C
25 °C
85 °C
105 °C
2.05
Vthreshold [V]
1.90
1.75
1.60
1.45
1.30
1.15
1.00
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-151. Reset pin input threshold voltage vs. VCC.
VIL - Reset pin read as “0”.
1.75
-40 °C
25 °C
85 °C
105 °C
1.60
1.45
Vthreshold [V]
1.30
1.15
1.00
0.85
0.70
0.55
0.40
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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37.2.9 Power-on Reset Characteristics
Figure 37-152. Power-on reset current consumption vs. VCC.
BOD level = 3.0V, enabled in continuous mode.
ICC [µA]
700
-40 °C
600
25 °C
500
85 °C
105 °C
400
300
200
100
0
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
VCC [V]
Figure 37-153. Power-on reset current consumption vs. VCC.
BOD level = 3.0V, enabled in sampled mode.
650
-40 °C
585
520
25 °C
ICC [µA]
455
85
° °C
105°°C
390
325
260
195
130
65
0
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
VCC [V]
XMEGA A4U [DATASHEET]
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37.2.10 Oscillator Characteristics
37.2.10.1 Ultra Low-Power internal oscillator
Figure 37-154. Ultra Low-Power internal oscillator frequency vs. temperature.
32.8
32.4
Frequency [kHz]
32.0
31.6
31.2
30.8
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
30.4
30.0
29.6
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
37.2.10.2 32.768kHz Internal Oscillator
Figure 37-155. 32.768kHz internal oscillator frequency vs. temperature.
32.875
3.6 V
3.0 V
2.2 V
2.7 V
1.8 V
1.6 V
32.850
Frequency [kHz]
32.825
32.800
32.775
32.750
32.725
32.700
32.675
32.650
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
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Figure 37-156. 32.768kHz internal oscillator frequency vs. calibration value.
VCC = 3.0V, T = 25°C.
55
Frequency [kHz]
50
45
40
35
30
25
20
0
26
52
78
104
130
156
182
208
234
260
RC32KCAL[7..0]
37.2.10.3 2MHz Internal Oscillator
Figure 37-157. 2MHz internal oscillator frequency vs. temperature.
DFLL disabled.
2.16
2.14
Frequency [MHz]
2.12
2.10
2.08
2.06
2.04
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
2.02
2.00
1.98
1.96
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
236
Figure 37-158. 2MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator .
2.0085
2.0070
3.6 V
1.6 V
2.2 V
1.8 V
3.0 V
2.7 V
Frequency [MHz]
2.0055
2.0040
2.0025
2.0010
1.9995
1.9980
1.9965
1.9950
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
Figure 37-159. 2MHz internal oscillator CALA calibration step size.
VCC = 3V.
0.31 %
Frequency Step size [%]
0.29 %
0.27 %
0.25 %
0.23 %
0.21 %
-40 °C
0.19 %
25 °C
85 °C
105 °C
0.17 %
0.15 %
0
16
32
48
64
80
96
112
128
CALA
XMEGA A4U [DATASHEET]
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37.2.10.4 32MHz Internal Oscillator
Figure 37-160. 32MHz internal oscillator frequency vs. temperature.
DFLL disabled.
36.0
35.5
Frequency [MHz]
35.0
34.5
34.0
33.5
33.0
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
32.5
32.0
31.5
31.0
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
Figure 37-161. 32MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
32.145
3.6 V
1.61.6
V V
1.8 V
2.2 V
2.7 V
3.0 V
32.120
Frequency [MHz]
32.095
32.070
32.045
32.020
31.995
31.970
31.945
31.920
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
XMEGA A4U [DATASHEET]
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238
Figure 37-162. 32MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
0.38 %
Frequency Step size [%]
0.34 %
0.30 %
0.26 %
0.22 %
85°C
105°C
25°C
- 40°C
0.18 %
0.14 %
0.10 %
0
16
32
48
64
80
96
112
128
CALA
Figure 37-163. 32MHz internal oscillator frequency vs. CALB calibration value.
VCC = 3.0V.
75
- 40°C
25°C
85°C
105°C
70
Frequency [MHz]
65
60
55
50
45
40
35
30
25
0
8
16
24
32
40
48
56
64
CALB
XMEGA A4U [DATASHEET]
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37.2.10.5 32MHz internal oscillator calibrated to 48MHz
Figure 37-164. 48MHz internal oscillator frequency vs. temperature.
DFLL disabled.
54
53
Frequency [MHz]
52
51
50
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
49
48
47
46
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
Figure 37-165. 48MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
48.25
3.6 V
1.6 V
1.8 V
2.7 V
2.2 V
48.20
Frequency [MHz]
48.15
48.10
3.0 V
48.05
48.00
47.95
47.90
47.85
47.80
-40
-25
-10
5
20
35
50
65
80
95
110
Temperature [°C]
XMEGA A4U [DATASHEET]
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240
Figure 37-166. 48MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
0.34 %
Frequency Step size [%]
0.31 %
0.28 %
0.25 %
0.22 %
0.19 %
-40 °C
25 °C
0.16 %
85 °C
105 °C
0.13 %
0.10 %
0
16
32
48
64
80
96
112
128
CALA
37.2.11 Two-Wire Interface characteristics
Figure 37-167. SDA hold time vs. supply voltage.
300
295
290
Holdtime [ns]
285
105°C
280
85°C
275
270
25°C
265
- 40°C
260
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Vcc [V]
XMEGA A4U [DATASHEET]
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37.2.12 PDI characteristics
Figure 37-168. Maximum PDI frequency vs. VCC.
34
25 °C
105 °C
-40 °C
85 °C
31
28
f MAX [MHz]
25
22
19
16
13
10
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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37.3
ATxmega64A4U
37.3.1 Current consumption
37.3.1.1 Active mode supply current
Figure 37-169. Active supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
700
3.6V
600
ICC [µA]
500
3.0V
400
2.7V
300
2.2V
200
1.8V
1.6V
100
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
Figure 37-170. Active supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
12
3.6V
10
3.0V
ICC [mA]
8
2.7V
6
4
2.2V
2
1.8V
1.6V
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
243
Figure 37-171. Active mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator.
250
- 40°C
ICC [µA]
230
210
25°C
190
85°C
105°C
170
150
130
110
90
70
50
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-172. Active mode supply current vs. VCC.
fSYS = 1MHz external clock.
680
- 40°C
25°C
85°C
105°C
630
580
530
ICC [µA]
480
430
380
330
280
230
180
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
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Figure 37-173. Active mode supply current vs. VCC.
fSYS = 2MHz internal oscillator.
1300
- 40°C
25°C
85°C
105°C
1200
1100
ICC [µA]
1000
900
800
700
600
500
400
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-174. Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
4.8
- 40°C
25°C
85°C
105°C
4.4
4.0
ICC [mA]
3.6
3.2
2.8
2.4
2.0
1.6
1.2
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
245
Figure 37-175. Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator.
12.0
- 40°C
11.5
25°C
85°C
105°C
11.0
ICC [mA]
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
37.3.1.2 Idle mode supply current
Figure 37-176. Idle mode supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
150
3.6 V
135
ICC [µA]
120
105
3.0 V
90
2.7 V
75
2.2 V
60
1.8 V
1.6 V
45
30
15
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
246
Figure 37-177. Idle mode supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
4.5
3.6 V
ICC [mA]
4.0
3.5
3.0 V
3.0
2.7 V
2.5
2.0
2.2 V
1.5
1.0
1.8 V
1.6 V
0.5
0.0
0
4
8
12
16
F
20
24
28
32
[MH ]
Figure 37-178. Idle mode supply current vs. VCC.
fSYS = 32.768kHz internal
. Internal Oscillator
fSYSoscillator
32.768kHz
34.75
105°C
- 40°C
34.00
33.25
85°C
25°C
ICC [µA]
32.50
31.75
31.00
30.25
29.50
28.75
28.00
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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247
Figure 37-179. Idle mode supply current vs. VCC.
fSYS = 1MHz external clock.
153
105°C
85°C
25°C
- 40°C
141
129
ICC [µA]
117
105
93
81
69
57
45
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-180. Idle mode supply current vs. VCC.
fSYS = 2MHz internal oscillator.
400
- 40°C
25°C
85°C
105°C
375
350
325
ICC [µA]
300
275
250
225
200
175
150
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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Figure 37-181. Idle mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
1850
- 40°C
25°C
85°C
105°C
1700
1550
ICC [µA]
1400
1250
1100
950
800
650
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-182. Idle mode current vs. VCC.
fSYS = 32MHz internal oscillator.
5.1
4.9
- 40°C
4.7
25°C
85°C
105°C
ICC [mA]
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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249
37.3.1.3 Power-down mode supply current
Figure 37-183. Power-down mode supply current vs. temperature.
All functions disabled.
2.7
3.6 V
2.4
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
2.1
ICC [µA]
1.8
1.5
1.2
0.9
0.6
0.3
0.0
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
Figure 37-184. Power-down mode supply current vs. VCC.
All functions disabled.
2.7
105°C
2.4
2.1
ICC [µA]
1.8
1.5
1.2
0.9
85°C
0.6
0.3
25°C
- 40°C
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
250
Figure 37-185. Power-down mode supply current vs. VCC.
Watchdog and sampled BOD enabled.
4.10
105°C
3.80
3.50
3.20
ICC [µA]
2.90
2.60
2.30
85°C
2.00
1.70
25°C
- 40°C
1.40
1.10
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
37.3.1.4 Power-save mode supply current
Figure 37-186. Power-save mode supply current vs.VCC.
Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC.
0.9
Normal mode
0.8
0.7
ICC [µA]
0.6
Low-power mode
0.5
0.4
0.3
0.2
0.1
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
V CC [V]
XMEGA A4U [DATASHEET]
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251
37.3.1.5 Standby mode supply current
Figure 37-187. Standby supply current vs. VCC.
Standby, fSYS = 1MHz.
12.5
105 °C
11.5
10.5
9.5
85 °C
ICC [uA]
8.5
25 °C
-40 °C
7.5
6.5
5.5
4.5
3.5
2.5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-188. Standby supply current vs. VCC.
25°C, running from different crystal oscillators.
480
16MHz
12MHz
440
ICC [µA]
400
360
320
8MHz
2MHz
280
240
0.454MHz
200
160
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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37.3.2 I/O Pin Characteristics
37.3.2.1 Pull-up
Figure 37-189. I/O pin pull-up resistor current vs. input voltage.
VCC = 1.8V.
70
60
IPIN [uA]
50
40
30
20
- 40°C
25°C
85°C
105°C
10
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VPIN [V]
Figure 37-190. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.0V.
120
105
90
IPIN [µA]
75
60
45
30
- 40°C
25°C
85°C
105°C
15
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VPIN [V]
XMEGA A4U [DATASHEET]
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253
Figure 37-191. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.3V.
135
120
105
IPIN [µA]
90
75
60
45
- 40°C
25°C
85°C
105°C
30
15
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
VPIN [V]
37.3.2.2 Output Voltage vs. Sink/Source Current
Figure 37-192. I/O pin output voltage vs. source current.
VCC = 1.8V.
1.9
1.7
VPIN [V]
1.5
1.3
- 40°C
1.1
25°C
0.9
105°C
85°C
0.7
0.5
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
IPIN [mA]
XMEGA A4U [DATASHEET]
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Figure 37-193. I/O pin output voltage vs. source current.
VCC = 3.0V.
3.2
2.8
2.4
VPIN [V]
2.0
1.6
- 40°C
1.2
25°C
0.8
85°C
105°C
0.4
0.0
-30
-27
-24
-21
-18
-15
-12
-9
-6
-3
0
-9
-6
-3
0
IPIN [mA]
Figure 37-194. I/O pin output voltage vs. source current.
VCC = 3.3V.
3.6
3.2
2.8
VPIN [V]
2.4
- 40°C
2.0
1.6
25°C
1.2
105°C
0.8
85°C
0.4
0.0
-30
-27
-24
-21
-18
-15
-12
IPIN [mA]
XMEGA A4U [DATASHEET]
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Figure 37-195. I/O pin output voltage vs. source current.
3.7
3.6 V
3.3 V
3.3
3.0 V
2.9
VPIN [V]
2.7 V
2.5
2.1
1.8 V
1.6 V
1.7
1.3
0.9
0.5
-24
-21
-18
-15
-12
-9
-6
-3
0
IPIN [mA]
Figure 37-196. I/O pin output voltage vs. sink current.
VCC = 1.8V.
1.0
85°C
0.9
0.8
25°C
0.7
105°C
VPIN [V]
0.6
- 40°C
0.5
0.4
0.3
0.2
0.1
0.0
0
2
4
6
8
10
12
14
16
18
20
IPIN [mA]
XMEGA A4U [DATASHEET]
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Figure 37-197. I/O pin output voltage vs. sink current.
VCC = 3.0V.
1.0
105°C
85°C
0.9
25°C
0.8
- 40°C
0.7
VPIN [V]
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
3
6
9
12
15
18
21
24
27
30
IPIN [mA]
Figure 37-198. I/O pin output voltage vs. sink current.
VCC = 3.3V.
1.0
105°C
85°C
0.9
0.8
25°C
- 40°C
0.7
VPIN [V]
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
3
6
9
12
15
18
21
24
27
30
IPIN [mA]
XMEGA A4U [DATASHEET]
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Figure 37-199. I/O pin output voltage vs. sink current.
1.50
1.6 V
1.35
1.8 V
1.20
VPIN [V]
1.05
2.7 V
3.0 V
3.3 V
3.6 V
0.90
0.75
0.60
0.45
0.30
0.15
0.00
0
3
6
9
12
15
18
21
24
27
30
IPIN [mA]
37.3.2.3 Thresholds and Hysteresis
Figure 37-200. I/O pin input threshold voltage vs. VCC.
T = 25°C.
1.8
VIH
1.6
VIL
Vthreshold [V]
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vcc [V]
XMEGA A4U [DATASHEET]
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Figure 37-201. I/O pin input threshold voltage vs. VCC.
VIH I/O pin read as “1”.
1.8
-40 °C
25 °C
85 °C
105 °C
1.7
1.6
Vthreshold [V]
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-202. I/O pin input threshold voltage vs. VCC.
VIL I/O pin read as “0”.
1.75
-40 °C
25 °C
85 °C
105 °C
1.60
1.45
Vthreshold [V]
1.30
1.15
1.00
0.85
0.70
0.55
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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Figure 37-203. I/O pin input hysteresis vs. VCC.
0.32
0.29
0.26
Vthreshold [V]
0.23
25 °C
0.20
0.17
-40 °C
85 °C
0.14
0.11
105 °C
0.08
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
37.3.3 ADC Characteristics
Figure 37-204. INL error vs. external VREF.
T = 25°C, VCC = 3.6V, external reference.
2.7
2.4
Single-ended unsigned mode
2.1
INL [LSB]
1.8
1.5
1.2
Dif f erential mode
0.9
0.6
0.3
Single-ended signed mode
0.0
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
XMEGA A4U [DATASHEET]
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Figure 37-205. INL error vs. sample rate.
T = 25°C, VCC = 2.7V, VREF = 1.0V external.
1.6
1.4
Single-ended signed mode
1.2
INL [LSB]
1.0
0.8
Dif f erential mode
0.6
Single-ended signed mode
0.4
0.2
0.0
500
650
800
950
1100
1250
1400
1550
1700
1850
2000
ADC sample rate [kSps]
Figure 37-206. INL error vs. input code
2.0
1.5
1.0
INL [LSB]
0.5
0.0
-0.5
-1.0
-1.5
-2.0
0
512
1024
1536
2048
2560
3072
3584
4096
ADC input code
XMEGA A4U [DATASHEET]
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Figure 37-207. DNL error vs. external VREF.
T = 25°C, VCC = 3.6V, external reference.
1.1
1.0
Single-ended unsigned mode
0.9
DNL [LSB]
0.8
0.7
0.6
Dif f erential mode
0.5
0.4
Single-ended signed mode
0.3
0.2
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
Figure 37-208. DNL error vs. sample rate.
T = 25°C, VCC = 2.7V, VREF = 1.0V external.
0.43
0.41
Single-ended unsigned mode
0.38
DNL [LSB]
0.36
Dif f erential mode
0.33
0.31
0.28
0.26
Single-ended signed mode
0.23
500
650
800
950
1100
1250
1400
1550
1700
1850
2000
ADC sample rate [kSps]
XMEGA A4U [DATASHEET]
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Figure 37-209. DNL error vs. input code.
1.0
0.8
0.6
0.4
DNL [LSB]
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512
1024
1536
2048
2560
3072
3584
4096
ADC input code
Figure 37-210. Gain error vs. VREF.
T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps.
12
Gain Error [mV]
10
Single-ended signed mode
8
Single-ended unsigned mode
6
4
2
Dif f erential mode
0
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
XMEGA A4U [DATASHEET]
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Figure 37-211. Gain error vs. VCC.
T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps.
7
6
Single-ended signed mode
Gain Error [mV]
5
4
Single-ended unsigned mode
3
2
Dif f erential mode
1
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
2.6
2.8
3.0
Vcc [V]
Figure 37-212. Offset error vs. VREF.
T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps.
-1.0
-1.1
-1.1
Offset Error [mV]
-1.2
-1.2
Dif f erential mode
-1.3
-1.3
-1.4
-1.4
-1.5
-1.5
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
Vref [V]
XMEGA A4U [DATASHEET]
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Figure 37-213. Gain error vs. temperature.
VCC = 2.7V, VREF = external 1.0V.
8
7
Single-ended signed mode
Gain Error [mV]
6
5
4
Single-ended unsigned mode
3
2
Dif f erential mode
1
0
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [oC]
Figure 37-214. Offset error vs. VCC.
T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps.
-0.3
-0.4
Offset Error [mV]
-0.5
Dif f erential mode
-0.6
-0.7
-0.8
-0.9
-1.0
-1.1
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA A4U [DATASHEET]
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265
Figure 37-215. Noise vs. VREF.
T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps.
0.9
Single-ended signed mode
0.8
Noise [mV RMS]
0.7
0.6
Single-ended unsigend mode
0.5
0.4
0.3
Dif f erential mode
0.2
0.1
0.0
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vref [V]
Figure 37-216. Noise vs. VCC.
T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps.
0.8
Single-ended signed mode
0.7
Noise [mV RMS]
0.6
0.5
Single-ended unsigned mode
0.4
0.3
Dif f erential mode
0.2
0.1
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vcc [V]
XMEGA A4U [DATASHEET]
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37.3.4 DAC Characteristics
Figure 37-217. DAC INL error vs. VREF.
VCC = 3.6V.
2.4
2.1
DACINL [LSB]
1.8
1.5
- 40°C
25°C
85°C
105°C
1.2
0.9
0.6
0.3
0.0
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
Figure 37-218. DNL error vs. VREF.
VCC = 3.6V.
1.8
1.6
1.4
DAC DNL [LSB]
1.2
1.0
0.8
- 40°C
0.6
25°C
85°C
105°C
0.4
0.2
0.0
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Vref [V]
XMEGA A4U [DATASHEET]
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Figure 37-219. DAC noise vs. temperature.
VCC = 2.7V, VREF = 1.0V .
0.178
0.176
0.174
Noise[mV RMS]
0.172
0.170
0.168
0.166
0.164
0.162
0.160
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [oC]
37.3.5 Analog Comparator Characteristics
Figure 37-220. Analog comparator hysteresis vs. VCC.
High-speed, small hysteresis.
25
24
105°C
23
85°C
VHYST [mV]
22
25°C
21
20
19
- 40°C
18
17
16
15
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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Figure 37-221. Analog comparator hysteresis vs. VCC.
Low power, small hysteresis.
36
105°C
85°C
34
VHYST [mV]
32
30
25°C
28
- 40°C
26
24
22
20
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-222. Analog comparator hysteresis vs. VCC.
High-speed mode, large hysteresis.
47
105°C
85°C
45
43
25°C
VHYST [mV]
41
39
- 40°C
37
35
33
31
29
27
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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Figure 37-223. Analog comparator hysteresis vs. VCC.
Low power, large hysteresis.
76
105°C
85°C
73
70
67
VHYST [mV]
64
25°C
61
58
55
- 40°C
52
49
46
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-224. Analog comparator current source vs. calibration value.
Temperature = 25°C.
8
ICURRENTSOURCE [µA]
7
6
5
3.6V
3.0V
2.7V
2.2V
1.8V
1.6V
4
3
2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CURRCALIBA[3..0]
XMEGA A4U [DATASHEET]
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Figure 37-225. Analog comparator current source vs. calibration value.
VCC = 3.0V.
7.2
6.8
ICURRENTSOURCE [uA]
6.4
6.0
5.6
5.2
4.8
4.4
- 40°C
25°C
85°C
105°C
4.0
3.6
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CURRCALIBA[3..0]
Figure 37-226. Voltage scaler INL vs. SCALEFAC.
T = 25°C, VCC = 3.0V.
0.15
0.12
0.09
INL [LSB]
0.06
0.03
0.00
-0.03
-0.06
-0.09
-0.12
-0.15
0
8
16
24
32
40
48
56
64
SCALEFAC
XMEGA A4U [DATASHEET]
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37.3.6 Internal 1.0V reference Characteristics
Figure 37-227. ADC/DAC Internal 1.0V reference vs. temperature.
1.004
1.6 V
1.8 V
2.2 V
2.7 V
3.0 V
3.6 V
Bandgap Voltage [V]
1.002
1.000
0.998
0.996
0.994
0.992
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
37.3.7 BOD Characteristics
Figure 37-228. BOD thresholds vs. temperature.
BOD level = 1.6V.
1.644
1.641
1.638
Rising Vcc
VBOT [V]
1.635
1.632
Falling Vcc
1.629
1.626
1.623
1.620
1.617
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
XMEGA A4U [DATASHEET]
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272
Figure 37-229. BOD thresholds vs. temperature.
BOD level = 3.0V.
3.08
3.07
Rising Vcc
3.06
VBOT [V]
3.05
3.04
3.03
Falling Vcc
3.02
3.01
3.00
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
37.3.8 External Reset Characteristics
Figure 37-230. Minimum Reset pin pulse width vs. VCC.
135
130
125
tRST [ns]
120
115
110
105
100
105°C
85°C
95
90
25°C
- 40°C
85
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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Figure 37-231. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 1.8V.
80
70
IRESET [µA]
60
50
40
30
- 40°C
25°C
85°C
105°C
20
10
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
VRESET [V]
Figure 37-232. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.0V.
120
105
IRESET [µA]
90
75
60
45
30
- 40°C
25°C
85°C
105°C
15
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
VRESET [V]
XMEGA A4U [DATASHEET]
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Figure 37-233. Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.3V.
150
135
120
IRESET [µA]
105
90
75
60
45
- 40°C
25°C
85°C
105°C
30
15
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
VRESET [V]
Figure 37-234. Reset pin input threshold voltage vs. VCC.
VIH - Reset pin read as “1”.
2.2
- 40°C
25°C
85°C
105°C
2.1
VTHRESHOLD [V]
1.9
1.8
1.6
1.5
1.3
1.2
1.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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Figure 37-235. Reset pin input threshold voltage vs. VCC.
VIL - Reset pin read as “0”.
1.75
- 40°C
25°C
85°C
105°C
1.60
VTHRESHOLD [V]
1.45
1.30
1.15
1.00
0.85
0.70
0.55
0.40
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
37.3.9 Power-on Reset Characteristics
Figure 37-236. Power-on reset current consumption vs. VCC.
BOD level = 3.0V, enabled in continuous mode.
300
105°C
85°C
25°C
- 40°C
250
I CC [µA]
200
150
100
50
0
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
VCC [V]
XMEGA A4U [DATASHEET]
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Figure 37-237. Power-on reset current consumption vs. VCC.
BOD level = 3.0V, enabled in sampled mode.
300
105°C
250
I CC [µA]
200
85°C
25°C
- 40°C
150
100
50
0
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
VCC [V]
37.3.10 Oscillator Characteristics
37.3.10.1 Ultra Low-Power internal oscillator
Figure 37-238. Ultra Low-Power internal oscillator frequency vs. temperature.
34.0
33.7
Frequency [kHz]
33.4
33.1
32.8
32.5
32.2
31.9
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
31.6
31.3
31.0
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
XMEGA A4U [DATASHEET]
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277
37.3.10.2 32.768kHz Internal Oscillator
Figure 37-239. 32.768kHz internal oscillator frequency vs. temperature.
32.85
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
32.82
32.79
Frequency [kHz]
32.76
32.73
32.70
32.67
32.64
32.61
32.58
32.55
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
Figure 37-240. 32.768kHz internal oscillator frequency vs. calibration value.
VCC = 3.0V, T = 25°C.
53
50
Frequency [kHz]
47
44
41
38
35
32
29
26
23
0
30
60
90
120
150
180
210
240
270
RC32KCAL[7..0]
XMEGA A4U [DATASHEET]
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37.3.10.3 2MHz Internal Oscillator
Figure 37-241. 2MHz internal oscillator frequency vs. temperature.
DFLL disabled.
2.12
2.10
Frequency [MHz]
2.08
2.06
2.04
2.02
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
2.00
1.98
1.96
1.94
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
Figure 37-242. 2MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator .
2.010
3.6 V
1.8 V
2.2 V
3.0 V
1.6 V
2.7 V
2.008
2.006
Frequency [MHz]
2.004
2.002
2.000
1.998
1.996
1.994
1.992
1.990
1.988
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
XMEGA A4U [DATASHEET]
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279
Figure 37-243. 2MHz internal oscillator CALA calibration step size.
VCC = 3V.
0.28 %
Frequency Step size [%]
0.26 %
0.24 %
0.22 %
0.20 %
- 40°C
25°C
105°C
85°C
0.18 %
0.16 %
0.14 %
0.12 %
0
16
32
48
64
80
96
112
128
CALA
37.3.10.4 32MHz Internal Oscillator
Figure 37-244. 32MHz internal oscillator frequency vs. temperature.
DFLL disabled.
35.5
35.0
Frequency [MHz]
34.5
34.0
33.5
33.0
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
32.5
32.0
31.5
31.0
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
280
Figure 37-245. 32MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
32.12
32.08
Frequency [MHz]
32.04
32.00
3.6 V
31.96
31.92
31.88
31.84
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
31.80
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
Figure 37-246. 32MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
0.34 %
Frequency Step size[%]
0.31 %
0.28 %
- 40°C
0.25 %
0.22 %
0.19 %
0.16 %
85°C
105°C
0.13 %
25°C
0.10 %
0
15
30
45
60
75
90
105
120
135
CALA
XMEGA A4U [DATASHEET]
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Figure 37-247. 32MHz internal oscillator CALB calibration step size.
VCC = 3.0V
2.80 %
Frequency Step size [%]
2.60 %
2.40 %
2.20 %
2.00 %
1.80 %
1.60 %
1.40 %
- 40°C
25°C
85°C
105°C
1.20 %
1.00 %
0.80 %
0
8
16
24
32
40
48
56
64
CALB
37.3.10.5 32MHz internal oscillator calibrated to 48MHz
Figure 37-248. 48MHz internal oscillator frequency vs. temperature.
DFLL disabled.
53.4
52.6
Frequency[MHz]
51.8
51.0
50.2
49.4
48.6
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
47.8
47.0
46.2
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
282
Figure 37-249. 48MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
48.15
3.6 V
48.10
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
48.05
Frequency[MHz]
48.00
47.95
47.90
47.85
47.80
47.75
47.70
-45
-30
-15
0
15
30
45
60
75
90
105
Temperature [°C]
Figure 37-250. 48MHz internal oscillator CALA calibration step size.
VCC = 3.0V
0.30 %
Frequency Step size [%]
0.28 %
0.26 %
0.24 %
0.22 %
- 40°C
0.20 %
0.18 %
105°C
25°C
85°C
0.16 %
0.14 %
0.12 %
0.10 %
0
16
32
48
64
80
96
112
128
CALA
XMEGA A4U [DATASHEET]
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283
37.3.11 Two-Wire Interface characteristics
Figure 37-251. SDA hold time vs. supply voltage.
300
295
290
Holdtime [ns]
285
105°C
280
85°C
275
270
25°C
265
- 40°C
260
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Vcc [V]
37.3.12 PDI characteristics
Figure 37-252. Maximum PDI frequency vs. VCC.
30
-
Maximum Frequency [MHz]
28
26
24
- 40°C
22
85°C
25°C
20
105°C
18
16
14
12
10
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
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37.4
ATxmega128A4U
37.4.1 Current consumption
37.4.1.1 Active mode supply current
Figure 37-253. Active supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
800
3.6V
700
600
Icc [µA]
3.0V
500
2.7V
400
2.2V
300
1.8V
1.6V
200
100
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
Figure 37-254. Active supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
13.5
12.0
3.6V
Icc [mA]
10.5
3.0V
9.0
2.7V
7.5
6.0
4.5
2.2V
3.0
1.8V
1.5
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
XMEGA A4U [DATASHEET]
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285
Figure 37-255. Active mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator
IccVcc [uA]
270
240
- 40 °C
210
25 °C
180
85 °C
105 °C
150
120
90
60
30
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-256. Active mode supply current vs. VCC.
fSYS = 1MHz external clock.
800
-40 °C
25 °C
85 °C
105 °C
700
600
Icc [uA]
500
400
300
200
100
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
286
Figure 37-257. Active mode supply current vs. VCC.
fSYS = 2MHz internal oscillator
-40 °C
25 °C
85 °C
105 °C
1400
1225
1050
Icc [uA]
875
700
525
350
175
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vcc [V]
Figure 37-258. Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz.
5800
-40 °C
25 °C
85 °C
105 °C
5200
4600
Icc [uA]
4000
3400
2800
2200
1600
1000
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
287
Figure 37-259. Active mode supply current vs. VCC.
fSYS = 32MHz internal oscillator.
13.4
12.6
-40 °C
25 °C
85 °C
105 °C
11.8
Icc [mA]
11.0
10.2
9.4
8.6
7.8
7.0
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
37.4.1.2 Idle mode supply current
Figure 37-260. Idle mode supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C
160
3.6 V
Icc [µA]
140
120
3.0 V
100
2.7 V
80
2.2 V
60
1.8 V
1.6 V
40
20
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
288
Figure 37-261. Idle mode supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C
5.4
3.6V
4.8
4.2
3.0V
Icc [mA]
3.6
2.7V
3.0
2.4
1.8
2.2V
1.2
1.8V
0.6
0
0
4
8
12
16
20
24
28
32
Frenquecy [MHz]
Figure 37-262. Idle mode supply current vs. VCC.
fSYS = 32.768kHz internal oscillator.
38
105 °C
37
36
35
-40 °C
Icc [uA]
34
85 °C
33
25 °C
32
31
30
29
28
27
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA A4U [DATASHEET]
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289
Figure 37-263. Idle mode supply current vs. VCC.
fSYS = 1MHz external clock
160
105 °C
85 °C
25 °C
-40 °C
150
140
130
Icc[uA]
120
110
100
90
80
70
60
50
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-264. Idle mode supply current vs. VCC.
fSYS = 2MHz internal oscillator
105 °C
85 °C
25 °C
-40 °C
330
310
290
270
Icc [uA]
250
230
210
190
170
150
130
110
90
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
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Figure 37-265. Idle mode supply current vs. VCC.
fSYS = 32MHz internal oscillator prescaled to 8MHz
2000
-40 °C
25 °C
85 °C
105 °C
1800
Icc [uA]
1600
1400
1200
1000
800
600
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 37-266. Idle mode current vs. VCC.
fSYS = 32MHz internal oscillator
5000
-40 °C
25 °C
85 °C
105 °C
4750
4500
Icc [uA]
4250
4000
3750
3500
3250
3000
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Vcc [V]
XMEGA A4U [DATASHEET]
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291
37.4.1.3 Power-down mode supply current
Figure 37-267. Power-down mode supply current vs. temperature.
All functions disabled
5.0
3.6 V
4.5
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
4.0
3.5
Icc [uA]
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
Figure 37-268. Power-down mode supply current vs. VCC.
All functions disabled
5.0
105 °C
4.5
4.0
3.5
Icc [uA]
3.0
2.5
2.0
85 °C
1.5
1.0
0.5
25 °C
-40 °C
0.0
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
292
Figure 37-269. Power-down mode supply current vs. VCC.
Watchdog and sampled BOD enabled
7.3
105 °C
6.8
6.3
5.8
5.3
Icc [uA]
4.8
4.3
3.8
3.3
85 °C
2.8
2.3
1.8
1.3
25 °C
-40 °C
0.8
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
37.4.1.4 Power-save mode supply current
Figure 37-270. Power-save mode supply current vs.VCC.
Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC.
0.9
Normal mode
0.8
0.7
ICC [µA]
0.6
Low-power mode
0.5
0.4
0.3
0.2
0.1
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
V CC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
293
37.4.1.5 Standby mode supply current
Figure 37-271. Standby supply current vs. VCC.
Standby, fSYS = 1MHz
12.5
105 °C
11.5
10.5
9.5
85 °C
ICC [uA]
8.5
25 °C
-40 °C
7.5
6.5
5.5
4.5
3.5
2.5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-272. Standby supply current vs. VCC.
T = 25°C, running from different crystal oscillators
480
16MHz
12MHz
440
ICC [µA]
400
360
320
8MHz
2MHz
280
240
0.454MHz
200
160
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC[V]
XMEGA A4U [DATASHEET]
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37.4.2 I/O Pin Characteristics
37.4.2.1 Pull-up
Figure 37-273. I/O pin pull-up resistor current vs. input voltage.
VCC = 1.8V
72
64
56
I [uA]
48
40
32
24
16
-40 °C
25 °C
85 °C
105 °C
8
0
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
Vpin [V]
Figure 37-274. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.0V
120
105
90
I [uA]
75
60
45
30
-40 °C
25 °C
85 °C
105 °C
15
0
0.1
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vpin [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
295
Figure 37-275. I/O pin pull-up resistor current vs. input voltage.
VCC = 3.3V.
135
120
105
I [uA]
90
75
60
45
30
-40 °C
25 °C
85 °C
105 °C
15
0
0.1
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
3.1
3.4
Vpin [V]
37.4.2.2 Output Voltage vs. Sink/Source Current
Figure 37-276. I/O pin output voltage vs. source current.
VCC = 1.8V
1.9
1.8
1.7
1.6
1.5
Vpin [V]
1.4
1.3
1.2
1.1
1.0
-40 °C
0.9
105 °C
85 °C
25 °C
0.8
0.7
0.6
0.5
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
Ipin [mA]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
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Figure 37-277. I/O pin output voltage vs. source current.
VCC = 3.0V
3.30
2.95
2.60
Vpin [V]
2.25
1.90
1.55
-40 °C
25 °C
85 °C
-24
-21
105 °C
1.20
0.85
0.50
-30
-27
-18
-15
-12
-9
-6
-3
0
-12
-9
-6
-3
0
Ipin [mA]
Figure 37-278. I/O pin output voltage vs. source current.
VCC = 3.3V
3.5
3.2
2.9
Vpin [V]
2.6
2.3
2.0
1.7
-40 °C
1.4
25 °C
1.1
85 °C
0.8
105 °C
0.5
-30
-27
-24
-21
-18
-15
Ipin [mA]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
297
Figure 37-279. I/O pin output voltage vs. source current
3.65
3.6 V
3.30
3.3 V
2.95
3.0 V
2.7 V
Vpin [V]
2.60
2.25
1.90
1.8 V
1.6 V
1.55
1.20
0.85
0.50
-24
-21
-18
-15
-12
-9
-6
-3
0
Ipin [mA]
Figure 37-280. I/O pin output voltage vs. sink current.
VCC = 1.8V
1.0
0.9
105 °C
0.8
85 °C
Vpin [V]
0.7
25 °C
-40 °C
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
2
4
6
8
10
12
14
16
18
20
Ipin [mA]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
298
Figure 37-281. I/O pin output voltage vs. sink current.
VCC = 3.0V
1.1
105 °C
85 °C
1.0
0.9
25 °C
-40 °C
0.8
Vpin [V]
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
3
6
9
12
15
18
21
24
27
30
Ipin [mA]
Figure 37-282. I/O pin output voltage vs. sink current.
VCC = 3.3V
105 °C
85 °C
1.0
Vpin [V]
0.9
0.8
25 °C
0.7
-40 °C
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
3
6
9
12
15
18
21
24
27
30
Ipin [mA]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
299
Figure 37-283. I/O pin output voltage vs. sink current
1.50
1.35
1.20
1.8 V
1.05
2.7 V
3.0 V
3.3 V
3.6 V
Vpin [V]
1.6 V
0.90
0.75
0.60
0.45
0.30
0.15
0.00
0
3
6
9
12
15
18
21
24
27
30
Ipin [mA]
37.4.2.3 Thresholds and Hysteresis
Figure 37-284. I/O pin input threshold voltage vs. VCC.
T = 25°C
1.8
VIH
1.6
VIL
Vthreshold [V]
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vcc [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
300
Figure 37-285. I/O pin input threshold voltage vs. VCC.
VIH I/O pin read as “1”
105 °C
85 °C
25 °C
-40 °C
1.8
1.7
1.6
Vthreshold [V]
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
Figure 37-286. I/O pin input threshold voltage vs. VCC.
VIL I/O pin read as “0”
1.75
105 °C
85 °C
25 °C
-40 °C
1.60
1.45
Vthreshold [V]
1.30
1.15
1.00
0.85
0.70
0.55
0.40
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
301
Figure 37-287. I/O pin input hysteresis vs. VCC
0.41
0.39
0.37
0.35
Vthreshold [V]
0.33
-40 °C
0.31
25 °C
0.29
0.27
0.25
85 °C
0.23
0.21
0.19
105 °C
0.17
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
37.4.3 ADC Characteristics
Figure 37-288. INL error vs. external VREF
T = 25°C, VCC = 3.6V, external reference
1.8
1.7
1.6
Differential Signed
INL [LSB]
1.5
Single-ended Unsigned
1.4
1.3
1.2
1.1
1
0.9
Single-ended Signed
0.8
0.7
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
302
Figure 37-289. INL error vs. sample rate
T = 25°C, VCC = 3.6V, VREF = 3.0V external
1.4
1.35
1.3
Differential Mode
INL [LSB]
1.25
1.2
Single-ended Unsigned
1.15
1.1
1.05
Single-ended Signed
1
0.95
0.9
500
650
800
950
1100
1250
1400
1550
1700
1850
2000
ADC Sample Rate [kSPS]
Figure 37-290. INL error vs. input code
2.0
1.5
INL [LSB]
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
0
512
1024
1536
2048
2560
3072
3584
4096
ADC input code
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
303
Figure 37-291. DNL error vs. external VREF
T = 25°C, VCC = 3.6V, external reference
0.9
0.88
0.86
DNL [LSB]
Differential Mode
0.84
Single-ended Signed
0.82
0.8
0.78
Single-ended Unsigned
0.76
0.74
0.72
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
Figure 37-292. DNL error vs. sample rate
T = 25°C, VCC = 3.6V, VREF = 3.0V external
0.9
0.89
Differential Signed
0.88
DNL [LSB]
0.87
0.86
0.85
Single-ended Signed
0.84
0.83
0.82
0.81
Single-ended Unsigned
0.8
0.79
500
650
800
950
1100
1250
1400
1550
1700
1850
2000
ADC Sample Rate [kSPS]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
304
Figure 37-293. DNL error vs. input code
0.8
0.6
DNL [LSB]
0.4
0.2
0
-0.2
-0.4
-0.6
0
512
1024
1536
2048
2560
3072
3584
4096
ADC Input Code
Figure 37-294. Gain error vs. VREF
T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps
3
Single-ended Signed
Gain Error [mV]
2
1
Differential Mode
0
-1
Single-ended Unsigned
-2
-3
-4
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
305
Figure 37-295. Gain error vs. VCC
T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps
2.2
1.9
Single-ended Signed
Gain Error [mV]
1.6
1.3
Differential Mode
1
0.7
0.4
Single-ended Unsigned
0.1
-0.2
-0.5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-296. Offset error vs. VREF
T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps
-1
Offset Error [mV]
-1.1
-1.2
-1.3
-1.4
-1.5
Differential Mode
-1.6
-1.7
-1.8
-1.9
-2
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
306
Figure 37-297. Gain error vs. temperature
VCC = 3.0V, VREF = external 2.0V
3
2
Gain Error [mV]
Single-ended Signed
1
Differential Signed
0
-1
Single-ended Unsigned
-2
-3
-4
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [ºC]
Figure 37-298. Offset error vs. VCC
T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps
-0.3
-0.4
Offset Error [mV]
-0.5
-0.6
-0.7
Differential Signed
-0.8
-0.9
-1
-1.1
-1.2
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
307
Figure 37-299. Noise vs. VREF
T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps
1.3
Single-ended Signed
Noise [mV RMS]
1.15
Single-ended Unsigned
1
0.85
0.7
0.55
Differential Signed
0.4
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
Figure 37-300. Noise vs. VCC
T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps
1.3
1.2
Single-ended Signed
Noise [mV RMS]
1.1
1
0.9
0.8
Single-ended Unsigned
0.7
0.6
0.5
Differential Signed
0.4
0.3
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
308
37.4.4 DAC Characteristics
Figure 37-301. DAC INL error vs. VREF
VCC = 3.6V
1.9
1.8
INL [LSB]
1.7
1.6
1.5
1.4
1.3
1.2
25°C
1.1
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
VREF [V]
Figure 37-302. DNL error vs. VREF.
T = 25°C, VCC = 3.6V.
0.9
DNL [LSB]
0.85
0.8
0.75
0.7
0.65
25ºC
0.6
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
309
Figure 37-303. DAC noise vs. temperature
VCC = 3.0V, VREF = 2.4V
0.185
0.180
Noise [mV RMS]
0.175
0.170
0.165
0.160
0.155
0.150
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [ºC]
37.4.5 Analog Comparator Characteristics
Figure 37-304. Analog comparator hysteresis vs. VCC.
High-speed, small hysteresis
14
13
105°C
12
85°C
VHYST [mV]
11
10
25°C
9
8
7
-40°
6
5
4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
310
Figure 37-305. Analog comparator hysteresis vs. VCC.
Low power, small hysteresis
30
28
105°C
85°C
26
24
VHYST [mV]
25°C
22
-40°C
20
18
16
14
12
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-306. Analog comparator hysteresis vs. VCC.
High-speed mode, large hysteresis
32
105°C
85°C
30
28
VHYST [mV]
26
25°C
24
22
-40°C
20
18
16
14
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
311
Figure 37-307. Analog comparator hysteresis vs. VCC.
Low power, large hysteresis
68
64
105°C
85°C
60
VHYST [mV]
56
25°C
52
48
-40°C
44
40
36
32
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
Figure 37-308. Analog comparator current source vs. calibration value.
Temperature = 25°C
8
7.5
ICURRENTSOURCE [µA]
7
6.5
6
5.5
5
4.5
3.6V
4
3.0V
3.5
3
2.2V
1.8V
2.5
2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CURRCALIBA[3..0]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
312
Figure 37-309. Analog comparator current source vs. calibration value.
VCC = 3.0V.
7
ICURRENTSOURCE [µA]
6.5
6
5.5
5
4.5
-40°C
25°C
85°C
4
3.5
3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CURRCALIBA[3..0]
Figure 37-310. Voltage scaler INL vs. SCALEFAC.
T = 25°C, VCC = 3.0V.
0.050
0.025
INL [LSB]
0
-0.025
-0.050
-0.075
-0.100
25°C
-0.125
-0.150
0
10
20
30
40
50
60
70
SCALEFAC
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
313
37.4.6 Internal 1.0V reference Characteristics
Figure 37-311. ADC/DAC Internal 1.0V reference vs. temperature
1.0024
1.0020
1.6V
1.8V
Bandgap Voltage [V]
1.0016
1.0012
1.0008
1.0004
1.0000
2.7V
3.0V
0.9996
0.9992
3.6V
0.9988
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
37.4.7 BOD Characteristics
Figure 37-312. BOD thresholds vs. temperature.
BOD level = 1.6V
1.596
Rising Vcc
1.593
Vbot [V]
1.590
1.587
1.584
Falling Vcc
1.581
1.578
1.575
1.572
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
314
Figure 37-313. BOD thresholds vs. temperature.
BOD level = 3.0V
3.03
3.02
Rising Vcc
3.01
Vbot [V]
3.00
2.99
2.98
Falling Vcc
2.97
2.96
2.95
2.94
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
95
105
Temperature [°C]
37.4.8 External Reset Characteristics
Figure 37-314. Minimum Reset pin pulse width vs. VCC
135
130
125
120
Trst [ns]
115
110
105
100
105 °C
85 °C
95
90
25 °C
-40 °C
85
80
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
315
Figure 37-315. Reset pin pull-up resistor current vs. reset pin voltage
VCC = 1.8V
80
72
64
Ireset [uA]
56
48
40
32
24
16
-40 °C
25 °C
85 °C
105 °C
8
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Vreset [V]
Figure 37-316. Reset pin pull-up resistor current vs. reset pin voltage
VCC = 3.0V
135
120
105
Ireset [uA]
90
75
60
45
30
-40 °C
25 °C
85 °C
105 °C
15
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
Vreset [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
316
Figure 37-317. Reset pin pull-up resistor current vs. reset pin voltage
VCC = 3.3V
150
135
120
Ireset [uA]
105
90
75
60
45
30
-40 °C
25 °C
85 °C
105 °C
15
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3.0
3.3
Vreset [V]
Figure 37-318. Reset pin input threshold voltage vs. VCC
VIH - Reset pin read as “1”
2.20
-40 °C
25 °C
85 °C
105 °C
2.05
Vthreshold [V]
1.90
1.75
1.60
1.45
1.30
1.15
1.00
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
317
Figure 37-319. Reset pin input threshold voltage vs. VCC
VIL - Reset pin read as “0”
1.8
105 °C
85 °C
25 °C
-40 °C
1.6
VTHRESHOLD [V]
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
37.4.9 Power-on Reset Characteristics
Figure 37-320. Power-on reset current consumption vs. VCC
BOD level = 3.0V, enabled in continuous mode
ICC [µA]
700
-40 °C
600
25 °C
500
85 °C
105 °C
400
300
200
100
0
0.4
0.7
1.0
1.3
1.6
1.9
2.2
2.5
2.8
VCC [V]
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
318
Figure 37-321. Power-on reset current consumption vs. VCC
BOD level = 3.0V, enabled in sampled mode
650
-40 °C
585
520
25 °C
ICC [µA]
455
85
° °C
105°°C
390
325
260
195
130
65
0
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
VCC [V]
37.4.10 Oscillator Characteristics
37.4.10.1 Ultra Low-Power internal oscillator
Figure 37-322. Ultra Low-Power internal oscillator frequency vs. temperature.
33.75
33.50
33.25
Frequency [kHz]
33.00
32.75
32.50
32.25
32.00
3.6 V
3.3 V
3.0 V
2.7 V
1.8 V
1.6 V
31.75
31.50
31.25
31.00
30.75
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
XMEGA A4U [DATASHEET]
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37.4.10.2 32.768kHz Internal Oscillator
Figure 37-323. 32.768kHz internal oscillator frequency vs. temperature
32.82
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
32.79
32.76
Frequency [kHz]
32.73
32.70
32.67
32.64
32.61
32.58
32.55
32.52
32.49
32.46
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
Figure 37-324. 32.768kHz internal oscillator frequency vs. calibration value
VCC = 3.0V, T = 25°C
52
3.0 V
49
46
Frequency [kHz]
43
40
37
34
31
28
25
22
0
24
48
72
96
120
144
168
192
216
240
264
RC32KCA L[7..0]
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37.4.10.3 2MHz Internal Oscillator
Figure 37-325. 2MHz internal oscillator frequency vs. temperature
DFLL disabled
2.16
2.14
2.12
Frequency [MHz]
2.10
2.08
2.06
2.04
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
2.02
2.00
1.98
1.96
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
Figure 37-326. 2MHz internal oscillator frequency vs. temperature
DFLL enabled, from the 32.768kHz internal oscillator
2.006
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
2.004
2.002
Frequency [MHz]
2.000
1.998
1.996
1.994
1.992
1.990
1.988
1.986
1.984
1.982
1.980
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
XMEGA A4U [DATASHEET]
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Figure 37-327. 2MHz internal oscillator CALA calibration step size
VCC = 3V
0.30
0.28
Step Size [%]
0.26
0.24
0.22
0.20
-40 °C
0.18
25 °C
0.16
85 °C
105 °C
0.14
0
10
20
30
40
50
60
70
80
90
100
110
120
130
CALA
37.4.10.4 32MHz Internal Oscillator
Figure 37-328. 32MHz internal oscillator frequency vs. temperature
DFLL disabled
36.00
35.55
35.10
Frequency [MHz]
34.65
34.20
33.75
33.30
32.85
3.6 V
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
32.40
31.95
31.50
31.05
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
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Figure 37-329. 32MHz internal oscillator frequency vs. temperature
DFLL enabled, from the 32.768kHz internal oscillator
32.05
1.8 V
2.2 V
2.7 V
3.0 V
3.3 V
3.6 V
32.02
31.99
Frequency [MHz]
31.96
31.93
31.90
31.87
31.84
31.81
31.78
31.75
31.72
31.69
31.66
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
Figure 37-330. 32MHz internal oscillator CALA calibration step size
VCC = 3.0V
0.32
0.29
Step Size [%]
0.26
0.23
-40 °C
0.20
105 °C
85 °C
25 °C
0.17
0.14
0
10
20
30
40
50
60
70
80
90
100
110
120
130
CALA
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37.4.10.5 32MHz internal oscillator calibrated to 48MHz
Figure 37-331. 48MHz internal oscillator frequency vs. temperature
DFLL disabled
53.9
53.2
52.5
Frequency [MHz]
51.8
51.1
50.4
49.7
49.0
3.6 V
3.3 V
3.0 V
48.3
47.6
2.7 V
2.2 V
1.8 V
46.9
46.2
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
Figure 37-332. 48MHz internal oscillator frequency vs. temperature
DFLL enabled, from the 32.768kHz internal oscillator
48.3
1.8 V
2.2 V
2.7 V
3.0 V
3.3 V
3.6 V
48.2
Frequency [MHz]
48.1
48.0
47.9
47.8
47.7
47.6
47.5
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
Temperature [°C]
XMEGA A4U [DATASHEET]
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Figure 37-333. 48MHz internal oscillator CALA calibration step size
VCC = 3V
0.28
0.26
Step Size [%]
0.24
0.22
0.2
-40 °C
0.18
105 °C
85 °C
25 °C
0.16
0.14
0
10
20
30
40
50
60
70
80
90
100
110
120
130
CALA
37.4.11 Two-Wire Interface characteristics
Figure 37-334. SDA hold time vs. supply voltage
300
295
290
Holdtime [ns]
285
105°C
280
85°C
275
270
25°C
265
- 40°C
260
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
Vcc [V]
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37.4.12 PDI characteristics
Figure 37-335. Maximum PDI frequency vs. VCC
-40 °C
25 °C
85 °C
105 °C
31
Frequency max [MHz]
28
25
22
19
16
13
10
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
Vcc [V]
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38.
Errata
38.1
ATxmega16A4U
38.1.1 Rev. E
z ADC may have missing codes in SE unsigned mode at low temp and low Vcc
z CRC fails for Range CRC when end address is the last word address of a flash section
z AWeX fault protection restore is not done correct in Pattern Generation Mode
1. ADC may have missing codes in SE unsigned mode at low temp and low Vcc
The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V.
Problem fix/Workaround
Use the ADC in SE signed mode.
2. CRC fails for Range CRC when end address is the last word address of a flash section
If boot read lock is enabled, the range CRC cannot end on the last address of the application section. If application table read lock is enabled, the range CRC cannot end on the last address before the application table.
Problem fix/Workaround
Ensure that the end address used in Range CRC does not end at the last address before a section with read lock
enabled. Instead, use the dedicated CRC commands for complete applications sections.
3. AWeX fault protection restore is not done correct in Pattern Generation Mode
When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN
is restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode
(CWCM), this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation
Mode (PGM), OUTOVEN should instead have been restored according to the DTLSBUF register.
Problem fix/Workaround
For CWCM no workaround is required.
For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set correct OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable
the correct outputs again.
38.1.2 Rev. A - D
Not sampled.
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38.2
ATxmega32A4U
38.2.1 Rev. E
z ADC may have missing codes in SE unsigned mode at low temp and low Vcc
z CRC fails for Range CRC when end address is the last word address of a flash section
z AWeX fault protection restore is not done correct in Pattern Generation Mode
1. ADC may have missing codes in SE unsigned mode at low temp and low Vcc
The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V.
Problem fix/Workaround
Use the ADC in SE signed mode.
2. CRC fails for Range CRC when end address is the last word address of a flash section
If boot read lock is enabled, the range CRC cannot end on the last address of the application section. If application table read lock is enabled, the range CRC cannot end on the last address before the application table.
Problem fix/Workaround
Ensure that the end address used in Range CRC does not end at the last address before a section with read lock
enabled. Instead, use the dedicated CRC commands for complete applications sections.
3. AWeX fault protection restore is not done correct in Pattern Generation Mode
When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN
is restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode
(CWCM), this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation
Mode (PGM), OUTOVEN should instead have been restored according to the DTLSBUF register.
Problem fix/Workaround
For CWCM no workaround is required.
For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set correct OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable
the correct outputs again.
38.2.2 Rev. A - D
Not sampled.
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38.3
ATxmega64A4U
38.3.1 Rev. D
z ADC may have missing codes in SE unsigned mode at low temp and low Vcc
z CRC fails for Range CRC when end address is the last word address of a flash section
1. ADC may have missing codes in SE unsigned mode at low temp and low Vcc
The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V.
Problem fix/Workaround
Use the ADC in SE signed mode.
2. CRC fails for Range CRC when end address is the last word address of a flash section
If boot read lock is enabled, the range CRC cannot end on the last address of the application section. If application table read lock is enabled, the range CRC cannot end on the last address before the application table.
Problem fix/Workaround
Ensure that the end address used in Range CRC does not end at the last address before a section with read lock
enabled. Instead, use the dedicated CRC commands for complete applications sections.
38.3.2 Rev. C
z ADC may have missing codes in SE unsigned mode at low temp and low Vcc
z CRC fails for Range CRC when end address is the last word address of a flash section
z AWeX fault protection restore is not done correct in Pattern Generation Mode
1. ADC may have missing codes in SE unsigned mode at low temp and low Vcc
The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V.
Problem fix/Workaround
Use the ADC in SE signed mode.
2. CRC fails for Range CRC when end address is the last word address of a flash section
If boot read lock is enabled, the range CRC cannot end on the last address of the application section. If application table read lock is enabled, the range CRC cannot end on the last address before the application table.
Problem fix/Workaround
Ensure that the end address used in Range CRC does not end at the last address before a section with read lock
enabled. Instead, use the dedicated CRC commands for complete applications sections.
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3. AWeX fault protection restore is not done correct in Pattern Generation Mode
When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN
is restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode
(CWCM), this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation
Mode (PGM), OUTOVEN should instead have been restored according to the DTLSBUF register.
Problem fix/Workaround
For CWCM no workaround is required.
For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set correct OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable
the correct outputs again.
38.3.3 Rev. A - B
Not sampled.
XMEGA A4U [DATASHEET]
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38.4
ATxmega128A4U
38.4.1 rev. A
z ADC may have missing codes in SE unsigned mode at low temp and low Vcc
1. ADC may have missing codes in SE unsigned mode at low temp and low Vcc
The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V.
Problem fix/Workaround
Use the ADC in SE signed mode.
XMEGA A4U [DATASHEET]
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39.
Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision in this
section are referring to the document revision.
39.1
8387H –09/2014
1.
Updated “Ordering Information” on page 2. Added ordering information for ATxmega16A4U/32A4U/64A4U/128A4U @
105°C
2.
Updated the Application Table Section from 4K/4K/4K/4K to 8K/4K/4K/4K in the Figure 7-1 on page 14
3.
Updated Table 36-4 on page 74, Table 36-36 on page 95, Table 36-68 on page 117 and Table 36-100 on page 139. Added
Icc Power-down power consumption for T=105°C for all functions disabled and for WDT and sampled BOD enabled
4.
Updated Table 36-20 on page 84, Table 36-52 on page 105, Table 36-84 on page 127 and Table 36-116 on page 149.
Updated all tables to include values for T=85°C and T=105°C. Removed T=55°C
Added 105°C Typical Characterization plots for:
5.
ATxmega16A4U
ATxmega32A4U
ATxmega64A4U
ATxmega128A4U
6.
Changed Vcc to AVcc in Figure 28-1 on page 50 and in the text in Section 28. “ADC – 12-bit Analog to Digital Converter” on
page 49 andSection 30. “AC – Analog Comparator” on page 53.
7.
Changed values for 128A4U in Table 7-3 on page 17. Page size = 128, FWORD = Z(6:0)
8.
Changed unit notation for parameter tSU;DAT to ns in Table 36-32 on page 92, Table 36-64 on page 113, and Table 36-128
on page 157.
39.2
8387G – 03/2014
1.
Removed “Preliminary” from the datasheet
2.
Updated “Errata” on page 327: added ERRATA “Rev. D” and “Rev. C” for “ATxmega64A4U” on page 329
39.3
8387F – 01/2014
1.
Removed JTAG references from the datasheet
2.
Updated Figure 30-1 on page 54. The positive Mux has two “Input” while the negative Mux has four “Input”
39.4
1.
8387E – 11/2013
Updated Flash size column in “Ordering Information” on page 2 for:
ATxmega128A4U-AU, ATxmega128A4U-AUR, ATxmega128A4U-MH and ATxmega128A4U-MHR
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39.5
8387D – 02/2013
1.
Updated typos in “Ordering Information” on page 2.
2.
Updated PE2 and PE3 pins in “Pinout/Block Diagram” on page 4 to indicate that these can be used as TOSC pins.
3.
Renamed pin 19 from VDD to VCC in Figure 2-1 on page 4.
4.
Updated page size for ATxmega128A4U in Table 7-3 on page 17.
5.
Added column for TWI using external driver interface in Table 32-3 on page 59.
6.
Updated ATxmega16A4U leakage current in Table 36-7 on page 77.
7.
Added application erase time for ATxmega16A4U in Table 36-21 on page 84.
8.
Updated limits for VIH and VIL:
ATxmega16A4U: Table 36-7 on page 77
ATxmega32A4U: Table 36-39 on page 98
ATxmega64A4U: Table 36-71 on page 120
ATxmega128A4U:Table 36-103 on page 142
9.
Updated DAC clock and timing characteristics:
ATxmega16A4U: Table 36-13 on page 81
ATxmega32A4U: Table 36-45 on page 101
ATxmega64A4U: Table 36-77 on page 123
ATxmega128A4U: Table 36-109 on page 145.
10.
Updated ATxmega16A4U “ External clock characteristics” on page 86.
11.
Added ESR parameter to the External 16MHz crystal oscillator and XOSC characteristics:
ATxmega16A4U: Table 36-29 on page 87
ATxmega32A4U: Table 36-61 on page 108
ATxmega64A4U: Table 36-93 on page 130
ATxmega128A4U: Table 36-125 on page 152.
12.
Updated ATxmega32A4U leakage current in Table 36-39 on page 98.
13.
Added application erase time for ATxmega32A4U in Table 36-53 on page 105.
14.
Updated ATxmega32A4U “ External clock characteristics” on page 107.
15.
Updated ATxmega32A4U current consumption in electrical characteristics section, see “Current consumption” on
page 117.
16.
Updated electrical characteristics for “ATxmega64A4U” on page 115.
17.
Updated typical characteristics for “ATxmega64A4U” on page 243.
18.
Added application erase time for ATxmega128A4U in Table 36-117 on page 149.
19.
Updated ATxmega128A4U “ External clock characteristics” on page 151.
39.6
8387C – 03/2012
1.
Updated “Ordering Information” on page 2. Added a new package PW.
2.
Updated “Packaging information” on page 68. A new package PW added.
3.
Updated the Table 36-4 on page 74 with new values for ICC active power consumption.
4.
Updated all typical characteristics in “ Active mode supply current” on page 159.
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5.
Updated all typical characteristics in “Power-down mode supply current” on page 166.
6.
Added electrical characteristics for “ATxmega32A4U” on page 93.
7.
Added electrical characteristics for “ATxmega64A4U” on page 115.
8.
Added electrical characteristics for “ATxmega128A4U” on page 137.
9.
Added typical characteristics for “ATxmega64A4U” on page 243
10.
Added typical characteristics for “ATxmega64A4U” on page 243.
12.
Added typical characteristics for “ATxmega128A4U” on page 285.
13.
Updated “Errata” on page 327.
14.
Used Atmel new datasheet template that includes Atmel new addresses on the last page.
39.7
8387B – 12/2011
1.
Updated Figure 2-1 on page 4: “Block Diagram and QFN/TQFP pinout”
2.
Updated Figure 3-1 on page 7: “XMEGA A4U Block Diagram”
3.
Updated “Overview” on page 13.
4.
Updated “ADC – 12-bit Analog to Digital Converter” on page 49.
5.
Updated Figure 28-1 on page 50: “ADC overview.”
6.
Updated “Instruction Set Summary” on page 63.
7.
Updated “Electrical Characteristics” on page 72.
8.
Updated “Typical Characteristics” on page 159.
9.
The order of several figures in the chapter “Typical Characteristics” has been changed
10.
Several new figures have been added to and some figures have been removed from chapter “Typical Characteristics”
11.
Several minor changes/corrections in text and figures have been performed
12.
Table 32-2 on page 59 has been corrected
13.
Table 32-4 on page 60 has been corrected
14.
Table 36-29 on page 85 has been corrected
15.
Table 36-30 on page 86 has been corrected
16.
The heading ”I/O Pin Characteristics” on page 164 has been corrected (the text “and Reset” has been removed)
39.8
1.
8387A – 07/2011
Initial revision.
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Table of Contents
1.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.
Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
4.
Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1
Recommended reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.
Capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.
AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7.
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
8.
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fuses and Lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Memory and Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash and EEPROM Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
15
15
16
16
17
17
17
17
17
DMAC – Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.1
8.2
9.
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ALU - Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1
9.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10. System Clock and Clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.1
10.2
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
11.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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11.2
11.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12.1
12.2
12.3
12.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
26
26
13. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.1
13.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
14. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . . . . . . . . . . . 29
14.1
14.2
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
15. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
15.1
15.2
15.3
15.4
15.5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
31
34
34
16. TC0/1 – 16-bit Timer/Counter Type 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
16.1
16.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
17. TC2 - Timer/Counter Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.1
17.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
18. AWeX – Advanced Waveform Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
18.1
18.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
19. Hi-Res – High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
19.1
19.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
20. RTC – 16-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
20.1
20.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
21. USB – Universal Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
21.1
21.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
22. TWI – Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
22.1
22.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
23. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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23.1
23.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
24. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
24.1
24.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
25. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
25.1
25.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
26. AES and DES Crypto Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
26.1
26.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
27. CRC – Cyclic Redundancy Check Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
27.1
27.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
28. ADC – 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
28.1
28.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
29. DAC – 12-bit Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
29.1
29.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
30. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
30.1
30.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
31. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
31.1
31.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
32. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
32.1
32.2
Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Alternate Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
33. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
34. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
35. Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
35.1
35.2
35.3
35.4
44A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44M1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
69
70
71
36. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
36.1
36.2
36.3
36.4
ATxmega16A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
ATxmega32A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
ATxmega64A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
ATxmega128A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
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37. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
37.1
37.2
37.3
37.4
ATxmega16A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATxmega32A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATxmega64A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATxmega128A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
159
201
243
285
38. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
38.1
38.2
38.3
38.4
ATxmega16A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATxmega32A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATxmega64A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ATxmega128A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
327
328
329
331
39. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
39.1
39.2
39.3
39.4
39.5
39.6
39.7
39.8
8387H – 05/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8387G – 03/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8387F – 01/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8387E – 11/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8387D – 02/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8387C – 03/2012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8387B – 12/2011. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8387A – 07/2011. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
332
332
332
332
332
333
334
334
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
iv
XXXXXX
Atmel Corporation
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© 2014 Atmel Corporation. / Rev.: Atmel-8387H-AVR-ATxmega16A4U-32A4U-64A4U-128A4U-Datasheet_09/2014.
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