FUNCTIONAL BLOCK DIAGRAM 16 RF2 GND 4 15 GND GND 5 14 GND GND 6 13 GND GND 12 17 GND RF1 3 RFC 10 GND 11 18 GND GND 2 GND 9 GND 1 PACKAGE BASE 14081-001 20 GND 19 GND 21 VCTL 22 VDD 23 GND ADRF5130 24 GND Reflective, 50 Ω design Low insertion loss: 0.6 dB typical at 2 GHz High isolation: 50 dB typical at 2 GHz High power handling Continuous average power: 43 dBm Peak power: 46.5 dBm High linearity 0.1 dB compression (P0.1dB): >46 dBm typical Input third-order intercept (IP3): 68 dBm typical at 2 GHz ESD ratings Human body model (HBM): 2 kV, Class 2 Charged device model (CDM): TBD Single positive supply VDD: 5 V Positive control, TTL compatible VCTL: 0 V or 5 V 24-lead, 4 mm × 4 mm LFCSP package (16 mm2) GND 8 FEATURES GND 7 Preliminary Technical Data High Power 44 W Peak, Silicon SPDT, Reflective Switch, 0.7 GHz to 3.5 GHz ADRF5130 Figure 1. APPLICATIONS Cellular/4G infrastructure Wireless infrastructure Military and high reliability applications Test equipment Pin diode replacement GENERAL DESCRIPTION The ADRF5130 is a high power, reflective, 0.7 GHz to 3.5 GHz, silicon, single-pole, double-throw (SPDT) switch in a leadless, surface-mount package. The switch is ideal for high power and cellular infrastructure applications, like long-term evolution (LTE) base stations. The ADRF5130 has high power handling of 43 dBm (typical), a low insertion loss of 0.6 dB, input linearity of 68 dBm (typical) third-order intercept, and 0.1 dB compression point Rev. PrA (P0.1dB) of 46 dBm. On-chip circuitry operates at a single, positive supply voltage of 5 V and typical bias current of 1 mA, making the ADRF5130 an ideal alternative to pin diode-based switches. The device comes in a RoHS compliant, compact, 24-lead, 4 mm × 4 mm LFCSP package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF5130 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................5 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................6 Functional Block Diagram .............................................................. 1 Insertion Loss, Isolation, and Return Loss ................................6 General Description ......................................................................... 1 Theory of Operation .........................................................................7 Specifications..................................................................................... 3 Applications Information .................................................................8 Absolute Maximum Ratings............................................................ 4 Outline Dimensions ....................................................................... 10 ESD Caution .................................................................................. 4 Pin Configuration and Function Descriptions ............................. 5 Rev. PrA | Page 2 of 10 Preliminary Technical Data ADRF5130 SPECIFICATIONS VDD = 5 V, VCTL = 0 V or VDD, TA = 25°C, 50 Ω system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS ISOLATION RFC to RF1/RF2 (Worst Case) RF1 to RF2 (Worst Case) RETURN LOSS RFC RFC to RF1/RF2 SWITCHING SPEED Rise and Fall Time (tRISE, tFALL) On and Off time (tON, tOFF) Radio Frequency (RF) SETTLING TIME INPUT POWER 1 dB Compression (P1dB) 0.1 dB Compression (P0.1dB) INPUT THIRD-ORDER INTERCEPT (IP3) RECOMMENDED OPERATING CONDITIONS Bias Voltage Range (VDD) Control Voltage Range (VCTL) Maximum RF Input Power TCASE = 105°C TCASE = 85°C TCASE = 25°C TCASE = −40°C Case Temperature Range (TCASE) DIGITAL INPUT CONTROL VOLTAGE Low (VIL) High (VIH) SUPPLY CURRENT (IDD) Test Conditions/Comments Min 0.7 0.7 GHz to 2.0 GHz 2.0 GHz to 3.5 GHz 0.6 0.7 Unit GHz dB dB 0.7 GHz to 2.0 GHz 2.0 GHz to 3.5 GHz 0.7 GHz to 2.0 GHz 2.0 GHz to 3.5 GHz 50 46 51 41 dB dB dB dB 0.7 GHz to 2.0 GHz 2.0 GHz to 3.5GHz 0.7 GHz to 2.0 GHz 2.0 GHz to 3.5 GHz 23 17 21 17 dB dB dB dB 90% to 10% of RF output 50% VCTL to 10% to 90% of RF output 50% VCTL to 0.1 dB margin of final RF output 155 750 TBD ns ns ns TBD 46 dB dB 68 65 dBm dBm Two-tone input power = 25 dBm/tone 0.7 GHz to 2 GHz 2 GHz to 3.5 GHz 0.7 GHz to 3.5 GHz Typ Max 3.5 4.5 0 5.4 VDD V V −40 41 TBD TBD 43 38.5 44 TBD TBD TBD TBD TBD TBD +105 dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm °C 0 1.3 0.8 5.0 V V mA Continuous wave (CW) 8 dB peak to average ratio (PAR) LTE, average 8 dB PAR LTE, single event (<10 sec), average CW 8 dB PAR LTE, average 8 dB PAR LTE, single event (<10 sec), average CW 8 dB PAR LTE, average 8 dB PAR LTE, single event (<10 sec), average CW 8 dB PAR LTE, average 8 dB PAR LTE, single event (<10 sec), average VDD = 4.5 V to 5.4 V, TCASE = −40°C to +105°C, at <1 μA typical VDD = 5 V 1.06 Rev. PrA | Page 3 of 10 ADRF5130 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Bias Voltage Range (VDD) Control Voltage Range (VCTL) RF Input Power1 Channel Temperature Storage Temperature Range Peak Reflow Temperature Thermal Resistance (Channel to Package Bottom) ESD Sensitivity HBM CDM 1 Rating −0.3 V to +5.5 V −0.3 V to +5.5 V 46.5 dBm 135°C −65°C to +150°C 260°C 17°C/W Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 2 kV (Class 2) TBD For recommended operating conditions, see Table 1. Rev. PrA | Page 4 of 10 Preliminary Technical Data ADRF5130 19 GND 20 GND 21 VCTL 22 VDD 23 GND 24 GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND 1 18 GND GND 2 17 GND ADRF5130 16 RF2 TOP VIEW (Not to Scale) GND 4 15 GND GND 12 RFC 10 GND 11 GND 9 13 GND GND 8 14 GND GND 6 GND 7 GND 5 PACKAGE BASE NOTES 1. EXPOSED PAD. EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND. 14081-002 RF1 3 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 2, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 17, 18, 19, 20, 23, 24 3 Mnemonic GND 10 RFC 16 RF2 21 VCTL 22 VDD EPAD RF1 Description Ground. The package bottom has an exposed metal pad that must connect to the printed circuit board (PCB) RF ground. See Figure 3 for the GND interface schematic. RF Port 1. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin. RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin. RF Port 2. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin. Control Input. See Figure 4 for the VCTL interface schematic. Refer to Table 4 and the recommended digital input control voltage range in Table 1. Supply Voltage. Exposed Pad. The exposed pad must be connected to RF/dc ground. Table 4. Truth Table Control Input, VCTL State Low High RFC to RF1 Off On Signal Path State RFC to RF2 On Off INTERFACE SCHEMATICS VCTL 14081-003 GND 14081-004 VDD Figure 4. Control Interface Figure 3. Ground Interface Rev. PrA | Page 5 of 10 ADRF5130 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS 0 0 –0.5 –0.5 –1.0 –1.5 –2.0 –1.0 –1.5 +105°C +85°C +25°C –40°C –2.0 RF1 RF2 0 1 2 3 4 5 FREQUENCY (GHz) –2.5 14081-005 –2.5 0 2 3 4 5 FREQUENCY (GHz) Figure 5. Insertion Loss of RF1 and RF2 vs. Frequency at VDD = 5 V Figure 8. Insertion Loss vs. Frequency, Over Temperature at VDD = 5 V 0 0 RF1 RF2 –10 RF1 ON RF2 ON –10 –20 –20 –30 ISOLATION (dB) –40 –50 –60 –30 –40 –50 –60 –70 –70 –80 0 1 2 3 4 5 FREQUENCY (GHz) –80 14081-006 –90 Figure 6. Isolation Between RFC and RF1/RF2 vs. Frequency at VDD = 5 V 0 1 2 3 4 5 FREQUENCY (GHz) 14081-009 ISOLATION (dB) 1 14081-008 INSERTION LOSS (dB) INSERTION LOSS (dB) INSERTION LOSS, ISOLATION, AND RETURN LOSS Figure 9. Isolation Between RF1 and RF2 vs. Frequency at VDD = 5 V, Switch Mode On 0 74 RFC RF1 RF2 –5 72 –15 70 IP3 (dBm) –20 –25 –30 68 66 –35 +105°C +85°C +25°C –40°C 64 –45 0 1 2 3 4 FREQUENCY (GHz) 5 62 0.5 1.0 1.5 2.0 2.5 3.0 3.5 FREQUENCY (GHz) Figure 7. Return Loss vs. Frequency at VDD = 5 V Figure 10. IP3 vs. Frequency over Temperature, VDD = 5 V Rev. PrA | Page 6 of 10 4.0 14081-010 –40 14081-007 RETURN LOSS (dB) –10 Preliminary Technical Data ADRF5130 THEORY OF OPERATION The ADRF5130 requires a single-supply voltage applied to the VDD pin. Bypass capacitors are recommended on the supply line to minimize RF coupling. The ADRF5130 is controlled via a digital control voltage applied to the VCTL pin. A small bypassing capacitor is recommended on these digital signal lines to improve the RF signal isolation. The ideal power-up sequence is as follows: 1. 2. 3. 4. The ADRF5130 is internally matched to 50 Ω at the RF input port (RFC) and the RF output ports (RF1 and RF2); therefore, no external matching components are required. The RFx pins are dc-coupled, and dc blocking capacitors are required on the RF lines. The design is bidirectional; the input and outputs are interchangeable. Connect GND. Power up VDD. Power up the digital control input. Powering the digital control input before the VDD supply can inadvertently forward bias and damage ESD protection structures. Power up the RF input. Depending on the logic level applied to the VCTL pin, one RF output port (for example, RF1) is set to on mode, by which an insertion loss path is provided from the input to the output, while the other RF output port (for example, RF2) is set to off mode, by which the output is isolated from the input. Table 5. Switch Operation Mode Digital Control Input, VCTL 0 1 Switch Mode RFC to RF1 RFC to RF2 Off mode: the RF1 port is isolated from the RFC port On mode: a low insertion loss path from the RFC port and is internally terminated to a 50 Ω load to absorb to the RF2 port. the applied RF signals. On mode: a low insertion loss path from the RFC port Off mode: the RF2 port is isolated from the RFC port to the RF1 port. and is internally terminated to a 50 Ω load to absorb the applied RF signals. Rev. PrA | Page 7 of 10 ADRF5130 Preliminary Technical Data APPLICATIONS INFORMATION slug must connect directly to the ground plane, as shown in Figure 12. The evaluation board shown in Figure 12 is available from Analog Devices, Inc., upon request. Generate the evaluation printed circuit board (PCB) used in the application circuit shown in Figure 11 with proper RF circuit design techniques. Signal lines at the RF port must have a 50 Ω impedance, and the package ground leads and backside ground Table 6. Bill of Materials for ADRF5130-EVALZ Evaluation Board Reference Designator J1 to J3 C1 to C4, C7 C6 C5 C8 to C15, C18 to C21 R1 U1 PCB1 Circuit board material: Roger 4350 or Arlon 25FR. Reference this evaluation board number when ordering the complete evaluation board. R1 VCTL VDD GND GND 20 19 VCTL 21 GND VDD 5 14 6 13 GND GND RF2 GND GND C3 RF2 C12 TO C15 GND GND 12 11 15 10 4 RFC GND 16 GND GND 3 8 GND 17 9 C18 TO C21 C2 RFC Figure 11. Application Circuit Rev. PrA | Page 8 of 10 14081-011 C8 TO C11 RF1 18 2 GND C1 1 7 RF1 GND 22 24 GND C7 C4 23 C5 GND C6 GND 2 GND 1 Description PCB mount SMA connector 100 pF capacitor, 0402 package 1 μF capacitor, 0402 package 1 nF capacitor, 0402 package Do not insert 0 Ω resistor, 0402 package ADRF5130 SPDT switch 600-01532-00-22 evaluation PCB Preliminary Technical Data ADRF5130 J1 GND VDD TP3 RFC C2 C4 C5 C6 4321 U1 R1 C7 1234 4321 RF2 600-01532-00-2 TP2 C3 VCTL J3 14081-012 J2 TP1 THRU CAL RF1 C1 Figure 12. ADRF5130-EVALZ Evaluation Board Rev. PrA | Page 9 of 10 ADRF5130 Preliminary Technical Data OUTLINE DIMENSIONS Figure 13. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.90 mm Package Height MOD 4926 Dimensions shown in millimeters ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR14081-0-5/16(PrA) Rev. PrA | Page 10 of 10