SC183C 2.5MHz, 2A Synchronous Step-Down Regulator POWER MANAGEMENT Features Description The SC183C is a 2A synchronous step-down regulator designed to operate with an input voltage range of 2.9 to 5.5 Volts. The device offers fifteen pre-determined outputs voltages via four control pins programmable from 0.8 to 3.3 Volts. The control pins allow for on-the-fly voltage changes, enabling system designers to implement dynamic power savings. The SC183C is also capable of adjusting output voltage via an external resistor divider. VIN Range: 2.9 – 5.5V VOUT Options: 0.8 - 3.3V Up to 2A Output Current Ultra-Small Footprint, <1mm Height Solution 2.5MHz Switching Frequency Efficiency Up to 93% Low Output Noise Across Load Range Excellent Transient Response Start Up into Pre-Bias Output 100% Duty-Cycle Low Dropout Operation <1µA Shutdown Current Internal Soft Start Input Under-Voltage Lockout Output Over-Voltage, Current Limit Protection Over-Temperature Protection Adjustable Output Voltage 3mm x 3mm x 0.6mm thermally enhanced MLPQ-UT16 package Pb-free, Halogen free, and RoHS/WEEE compliant The device operates with a fixed 2.5MHz oscillator frequency, allowing the use of small surface mount external components. Connecting CTL0 — CTL3 to logic low forces the device into shutdown mode reducing the supply current to less than 1µA. Connecting any of the control pins to logic high enables the converter and sets the output voltage according to Table 1. Other features include undervoltage lockout, soft-start to limit in-rush current, and over-temperature protection. The SC183C is available in a thermally-enhanced, 3mm x 3mm x 0.6mm MLPQ-UT16 package. Applications Office Automation and Computing Set-Top Box LCD TV Network Cards Printer Typical Application Circuit VIN LX PVIN CIN 10µF RAVIN 10 SC183C AVIN VOUT CAVIN 1µF November 19, 2010 CTL0 CTL0 CTL1 CTL2 CTL1 CTL2 PGND CTL3 CTL3 AGND L 1.0µH VOUT 1.50V / 2.0A COUT 22µF SC183C Pin Configuration LX LX LX PGND Ordering Information 16 15 14 13 12 PGND 2 11 PGND AGND 3 10 VOUT AVIN 4 9 NC 5 6 7 8 CTL3 T CTL2 PVIN TOP VIEW CTL1 1 CTL0 PVIN Package SC183CULTRT(2)(3) 3mm x 3mm x 0.6mm MLPQ-UT16 SC183CEVB(4) Evaluation Board Notes: (1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. (2) Available in tape and reel only. A reel contains 3,000 devices. (3) Device is Pb-free, Halogen free, and RoHS/WEEE compliant. (4) Please specify the VOUT when ordering. 3mm x 3mm x 0.6mm MLPQ-UT16 θJA = 40°C/W (1) Table 1 – Output Voltage Settings Marking Information Marking for 3mm x 3mm MLPQ-UT 16 Lead Package: yyww = Datecode (Example: 0852) xxxx = Semtech Lot number (Example: E901) © 2010 Semtech Corp. Device CTL3 CTL2 CTL1 CTL0 Output Voltage 0 0 0 0 Shutdown 0 0 0 1 0.80 0 0 1 0 1.00 0 0 1 1 1.025 0 1 0 0 1.05 0 1 0 1 1.20 0 1 1 0 1.25 0 1 1 1 1.30 1 0 0 0 1.50 1 0 0 1 1.80 1 0 1 0 2.20 1 0 1 1 2.50 1 1 0 0 2.60 1 1 0 1 2.80 1 1 1 0 3.00 1 1 1 1 3.30 www.semtech.com SC183C Recommended Operating Conditions Absolute Maximum Ratings Supply Voltage PVIN and AVIN …………………… 2.9 to 5.5V PVIN and AVIN Supply Voltages ………………… -0.3 to 6.0V Maximum Output Current ………………………………… 2.0A LX Voltage ………….. -1 to PVIN+1V, -3V (20ns Max), 6V Max Input Capacitor ………………………………………… 10uF VOUT Voltage …………………………… -0.3 to AVIN+0.3V Output Capacitor ……………………………………… 22uF CTLx Voltage …………………………… -0.3 to AVIN+0.3V Output Inductor Operating Junction Temperature ….…….….… -40 to +125 °C Peak IR Reflow Temperature …………………………. 260°C ……………………………………… 2.2uH Thermal Information ESD Protection Level(2) …………………………………. 2.5kV Thermal Resistance, Junction to Ambient(1) ………… 40 °C/W Maximum Junction Temperature …………………… +150 °C Storage Temperature Range ………………… -65 to +150 °C Exceeding the absolute maximum ratings may result in permanent damage to the device and/or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B. Electrical Characteristics Unless specified: PVIN= AVIN= 5.0V, VOUT= 1.50V, CIN= 10µF, COUT= 22µF, L= 2.2µH, -40°C≤ TJ≤ +125 °C. Unless otherwise noted typical values are TA= +25 °C. Parameter Symbol Under-Voltage Lockout Conditions Min Typ Max Units Rising AVIN, PVIN=AVIN 2.70 2.80 2.90 V Hysteresis 240 300 ΔVOUT PVIN= AVIN= 2.9 to 5.5V; IOUT=0A -2.0 ILIMIT Peak LX current 2.5 IQ No load 10 ISHDN CTL0-3= AGND 1 10 ILX= 100mA, TJ= 25 °C 0.10 0.125 ILX= 100mA, TJ= 125 °C 0.14 0.18 ILX= -100mA, TJ= 25 °C 0.09 0.115 ILX= -100mA, TJ= 125 °C 0.125 0.160 PVIN= AVIN= 5.5V; LX= 0V; CTL0-3= AGND 1 10 UVLO Output Voltage Tolerance(1) Current Limit Supply Current Shutdown Current High Side Switch Resistance Low Side Switch Resistance(2) LX Leakage Current(2) RDSON_P RDSON_N ILK(LX) Load Regulation ΔVLOAD-REG PVIN= AVIN= 5.5V; LX= 5.0V; CTL0-3= AGND -10 PVIN= AVIN= 5.0V; IOUT=1mA to 2A 3.0 mV +2.0 % 3.75 A mA -1 µA Ω µA ±0.5 ±1.0 % 2.125 2.500 2.875 MHz 850 980 µs Oscillator Frequency fOSC Soft-Start Time tSS IOUT= 0 to 2A 50 CTLx Input High Current(2) IEN_HI CTL0-3=AVIN -2.0 2.0 µA CTLx Input Low Current IEN_LO CTL0-3=AGND -2.0 2.0 µA (2) (2) © 2010 Semtech Corp. www.semtech.com SC183C Electrical Characteristics (continued) Parameter Symbol Conditions Min Typ Max CTLx Input High Threshold VEN_HI CTLx Input Low Threshold VEN_LO VOUT Over Voltage Protection VOVP Thermal Shutdown Temperature TSD 160 °C TSD_HYS 10 °C Thermal Shutdown Hysteresis 1.2 Units 110 V 115 0.4 V 120 % Notes: (1) The “Output Voltage Tolerance” includes output voltage accuracy, voltage drift over temperature and the line regulation. (2) The negative current means the current flows through into the pin and the positive current means the current flows through out from the pin. © 2010 Semtech Corp. www.semtech.com SC183C Typical Characteristics Circuit Conditions: CIN= 10mF/6.3V, COUT= 22mF/6.3V. Unless otherwise noted, L= 2.2mH (TOKO: 1127AS-2R2M). Efficiency vs. LoadEfficiency Current (VOUT=1.5V) Efficiency vs. LoadEfficiency Current (VOUT=3.3V) 100% 100% L=1127AS-2R2 (40m_typ) L=1127AS-2R2 (40m_typ) 95% 95% L=1071AS-1R0 (33m_typ) 90% Efficiency (%) Efficiency (%) 90% 85% 80% 75% 70% VIN= 5.0V VOUT= 1.5V TA=25°C 65% 85% L=1071AS-1R0 (33m_typ) 80% 75% L=1071AS-2R2 (50m_typ) 70% VIN= 5.0V VOUT= 3.3V TA=25°C 65% L=1071AS-2R2 (50m_typ) 60% 60% 0.0 0.4 0.8 1.2 Output Current (A) 1.6 0.0 2.0 0.4 0.8 1.2 Output Current (A) 1.6 2.0 Total Loss vs. Load Current (VOUT=3.3V) Total Loss vs. Load Current (VOUT=1.5V) Total Loss Total Loss 1000 1000 VIN= 5.0V VOUT= 1.5V TA=25°C 800 VIN= 5.0V VOUT= 3.3V TA=25°C L=1071AS-2R2 (50m_typ) 800 600 Loss (mW) Loss (mW) L=1071AS-2R2 (50m_typ) L=1071AS-1R0 (33m_typ) 400 600 L=1071AS-1R0 (33m_typ) 400 200 200 L=1127AS-2R2 (40m_typ) L=1127AS-2R2 (40m_typ) 0 0 0.0 0.4 0.8 1.2 Output Current (A) 1.6 0.0 2.0 Load Regulation (VOUT=1.5V) Load Regulation 0.8 1.2 Output Current (A) 1.6 2.0 1.6 2.0 Load Regulation (VOUT=3.3V) Load Regulation 0.5% 0.5% VOUT= 1.5V TA=25°C 0.4% VIN= 5.0V VOUT= 3.3V TA=25°C 0.4% 0.3% 0.3% 0.2% 0.2% Load Regulation Load Regulation 0.4 0.1% VIN= 3.3V 0.0% -0.1% 0.1% 0.0% -0.1% -0.2% -0.2% -0.3% -0.3% VIN= 5.0V -0.4% -0.4% -0.5% -0.5% 0.0 0.4 © 2010 Semtech Corp. 0.8 1.2 Output Current (A) 1.6 0.0 2.0 0.4 0.8 1.2 Output Current (A) www.semtech.com SC183C Typical Characteristics Circuit Conditions: CIN= 10mF/6.3V, COUT= 22mF/6.3V. Unless otherwise noted, L= 2.2mH (TOKO: 1127AS-2R2M). (P & N)vs. Variation Line RDS(ON)RDSON Variation Inputover Voltage RDSON (P & N) Variation Over Temperature RDS(ON) Variation vs. Temperature 30% 20% 25% 15% P-Channel 20% 10% 5% Variation 15% Variation VIN= 5.0V ILX= ±100mA 10% N-Channel 0% -5% 5% -10% 0% ILX= ±100mA TA= 25°C -5% N-Channel P-Channel -15% -20% -10% 2.5 3.0 3.5 4.0 4.5 5.0 -40 5.5 -15 5% 60 85 1.0% 4% 0.8% VOUT= 3.3V 3% 0.6% 2% 0.4% 1% 0.2% Variation Variation 35 SwitchingSwitching Frequency vs. Temperature Frequency Variation Switching Frequency vs. Variation over Line Switching Frequency Input Voltage 0% -1% -2% -0.2% -0.6% IOUT= 0A TA= 25°C -4% 0.0% -0.4% VOUT= 1.5V -3% VIN= 5.0V IOUT= 0A -0.8% -5% -1.0% 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -15 Input Voltage (V) 10 35 60 85 Ambient Temperature (°C) Line Regulation Line Regulation ove Line Line Regulation Temperature Line Regulationvs. over Temperature 1.0% 1.0% 0.8% 0.8% 0.6% 0.6% VOUT= 1.5V 0.4% 0.4% 0.2% Regulation Regulation 10 Ambient Temperature (°C) Input Voltage (V) 0.0% -0.2% -0.4% 0.2% 0.0% -0.2% -0.4% VOUT= 3.3V -0.6% -0.6% IOUT= 0A TA= 25°C -0.8% VOUT= 1.5V IOUT= 0A -0.8% -1.0% -1.0% 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 Input Voltage (V) © 2010 Semtech Corp. -15 10 35 60 85 Ambient Temperature (°C) www.semtech.com SC183C Typical Characteristics Circuit Conditions: CIN= 10mF/6.3V, COUT= 22mF/6.3V. Unless otherwise noted, L= 2.2mH (TOKO: 1127AS-2R2M). HysteresisVariation Variation UVLOUVLO Hysteresis 1.0% 5% 0.8% 4% 0.6% 3% 0.4% 2% 0.2% 1% Variation Variation Rising Threshold Variation UVLOUVLO Rising Threshold Variation 0.0% -0.2% 0% -1% -0.4% -2% -0.6% -3% -0.8% -4% IOUT= 0A IOUT= 0A -5% -1.0% -40 -15 10 35 60 -40 85 -15 10 35 60 85 Ambient Temperature (°C) Ambient Temperature (°C) Dropout Voltage in 100% Duty Cycle Operation 500 TA= 25°C 450 Dropout Voltage (mV) 400 L= 1071AS-2R2M (DCR= 60m_max) 350 300 250 200 150 L= 1127AS-2R2M (DCR=48m_max) 100 50 0 0.0 0.4 0.8 1.2 1.6 2.0 Output Current (A) © 2010 Semtech Corp. www.semtech.com SC183C Typical Waveforms Circuit Conditions: CIN= 10mF/6.3V, COUT= 22mF/6.3V, L= 2.2mH (TOKO: 1127AS-2R2M). Output Voltage Ripple (VOUT=1.5V) Output Voltage Ripple (VOUT=1.5V) Output Voltage Ripple (VOUT=1.5V) Output Voltage Ripple (VOUT=1.5V) VOUT 10mV/div VOUT 10mV/div ILX 1A/div ILX 1A/div VLX 2V/div VLX 2V/div VIN=3.3V IOUT=2A VIN=5.0V IOUT=2A 500ns/div Output Voltage Ripple (VOUT=3.3V) 500ns/div Output Voltage Ripple (VOUT=3.3V) Output Voltage Ripple (VOUT=3.3V) Output Voltage Ripple (VOUT=3.3V) VOUT 10mV/div VOUT 10mV/div ILX 0.5A/div ILX 1A/div VLX 2V/div VLX 2V/div VIN=5.0V IOUT=0A VIN=5.0V IOUT=2A 500ns/div Transient Response (VOUT=1.5V) 500ns/div Transient Response (VOUT=3.3V) Transient Response (VOUT=1.5V; 0A to 1A) Transient Response (VOUT=3.3V; 0A to 1A) VOUT VOUT 100mV/div 100mV/div IOUT IOUT 1A/div 500mA/div VIN=5.0V IOUT=0A to 1A © 2010 Semtech Corp. VIN=5.0V IOUT=0A to 1A 50µs/div 50µs/div www.semtech.com SC183C Typical Waveforms Circuit Conditions: CIN= 10mF/6.3V, COUT= 22mF/6.3V, L= 2.2mH (TOKO: 1127AS-2R2M). Start Up (VOUT=1.5V) Start Up (VOUT=1.5V) Start Up (Enable)(VOUT=1.5V) Start Up (Enable)(VOUT=1.5V) VIN VIN 2V/div 2V/div VEN VEN 2V/div 2V/div VOUT VOUT 0.5V/div 0.5V/div VIN=5.0V ROUT=1k VIN=5.0V ROUT=0.75 (2A) 50µs/div Start Up (VOUT=1.5V), EN=VIN 200µs/div Start Up (VOUT=1.5V), EN=VIN Start Up (Power up VIN) (VOUT=1.5V) Start Up (Power up VIN) (VOUT=1.5V) VIN VIN 2V/div 2V/div VOUT VOUT 0.5V/div 0.5V/div VIN=5.0V ROUT=1k VIN=5.0V ROUT=0.75 (2A) 200µs/div Start Up (VOUT=3.3V) 200µs/div Start Up (VOUT=3.3V) Start Up (Enable)(VOUT=3.3V) Start Up (Enable)(VOUT=3.3V) VIN VIN 2V/div 2V/div VEN VEN 2V/div 2V/div VOUT VOUT 1V/div 1V/div VIN=5.0V ROUT=1k © 2010 Semtech Corp. VIN=5.0V ROUT=1.65 (2A) 100µs/div 200µs/div www.semtech.com SC183C Typical Waveforms Circuit Conditions: CIN= 10mF/6.3V, COUT= 22mF/6.3V, L= 2.2mH (TOKO: 1127AS-2R2M). Start Up (VOUT=3.3V), EN=VIN Start Up (VOUT=3.3V), EN=VIN Start Up (Power up VIN) (VOUT=3.3V) Start Up (Power up VIN) (VOUT=3.3V) VIN VIN 2V/div 2V/div VOUT VOUT 1.5V/div 1.5V/div VIN=5.0V ROUT=1k VIN=5.0V ROUT=1.65 (2A) 200µs/div Shutdown-Disable (1.5V) 200µs/div Shutdown-Disable (3.3V) Shutdown (Disable)(VOUT=1.5V) Shutdown (Disable)(VOUT=3.3V) VIN VIN 2V/div 2V/div VEN VEN 2V/div 2V/div VOUT VOUT 1V/div 1.5V/div VIN=5.0V ROUT=1.5 © 2010 Semtech Corp. VIN=5.0V ROUT=3.3 200µs/div 10 200µs/div www.semtech.com SC183C Pin Descriptions Pin # Pin Name 1,2 Pvin Input supply voltage for the converter power stage. 3 AGND Ground connection for the internal circuitry. AGND needs to be connected to PGND directly. 4 AVIN Power supply for the internal circuitry. Connect a 10W resistor to PVIN and a 1mF capacitor to AGND. 5 CTL0 Control bit 0 - see Table 1 for decoding. This pin has a 1 MΩ internal pulldown resistor. This resistor is switched in circuit whenever the EN pin is below the enable input high threshold, or when the part is in undervoltage lockout. 6 CTL1 Control bit 1 - see Table 1 for decoding. This pin has a 1 MΩ internal pulldown resistor. This resistor is switched in circuit whenever the EN pin is below the enable input high threshold, or when the part is in undervoltage lockout. 7 CTL2 Control bit 2 - see Table 1 for decoding. This pin has a 1 MΩ internal pulldown resistor. This resistor is switched in circuit whenever the EN pin is below the enable input high threshold, or when the part is in undervoltage lockout. 8 CTL3 Control bit 3 - see Table 1 for decoding. This pin has a 1 MΩ internal pulldown resistor. This resistor is switched in circuit whenever the EN pin is below the enable input high threshold, or when the part is in undervoltage lockout. 9 NC 10 VOUT Output voltage sense pin. 11,12,13 PGND Ground connection for converter power stage. 14,15,16 LX © 2010 Semtech Corp. Pin Function No connection. Switching node - connect an inductor between this pin and the output capacitor. 11 www.semtech.com SC183C Block Diagram Current Amp AVIN PVIN Plimit Amp Comp Plimit Oscillator & Slope Generator Control Logic VOUT LX CTL0 CTL1 CTL2 CTL3 Voltage Select Error Amp PWM Comp 500mV Ref PGND AGND © 2010 Semtech Corp. 12 www.semtech.com SC183C Applications Information Detailed Description an external resistor divider. There will be a typical 2µA current flowing into the VOUT pin. The typical schematic for an adjustable output voltage option from the standard 1.0V with CTLx=[0010], is shown in Figure 1. RFB1 and RFB2 are used to adjust the desired output voltage. If the RFB2 current is such that the 2µA VOUT pin current can be ignored, then RFB1 can be found by Equation 1. RFB2 needs to be low enough in value for the current through the resistor chain to be at least 20µA in order to ignore the VOUT pin current. The SC183C is a synchronous step-down converter utilizing a 2.5MHz fixed frequency voltage mode architecture. The switching frequency is chosen to minimize the size of the external inductor and capacitors while maintaining high efficiency. Operation During normal operation, the PMOS MOSFET is activated on each rising edge of the internal oscillator. The voltage feedback loop uses an internal feedback resistor divider. The period is set by the internal oscillator. The device has an internal synchronous NMOS rectifier and does not require a Schottky diode on the LX pin. The device operates as a buck converter in PWM mode with a fixed frequency of 2.5MHz. RFB1 = The SC183C has fifteen pre-determined output voltage values which can be individually selected by programming the CTL input pins (see Table 1 — Output Voltage Settings). Each CTL pin has an active 1 MΩ internal pulldown resistor. The 1MΩ resistor is switched in circuit whenever the CTL input voltage is below the input threshold, or when the part is in undervoltage lockout. It is recommended to tie all high CTL pins together and use an external pull-up resistor to AVIN if there is no enable signal or if the enable input is an open drain/collector signal. The CTL pins may be driven by a microprocessor to allow dynamic voltage adjustment for systems that reduce the supply voltage when entering sleep states. Avoid all zeros being present on the CTL pins when changing programmable output voltages as this would disable the device. CFF is needed to maintain good transient response performance. The correct value of C FF can be found using Equation 2. C FF [nF ] = 2.5 × L CIN 10µF 10 CAVIN 1µF SC183C AVIN The SC183C provides the following protection features: CFF RFB2 10k CTL1 CTL2 PGND CTL3 AGND RFB1 = (VOUT − 1) × RFB 2 Current Limit for CTLx= 0010 (1.0V) The internal PMOS power device in the switching stage is protected by a current limit feature. If the inductor current is above the PMOS current limit for 16 consecutive cycles, the part enters foldback current limit mode and the output current is limited to the current limit holding Figure 1 — Typical Schematic for Adjusting the Output Voltage Up from an Output Voltage of 1.0V (CTLx=[0010]) © 2010 Semtech Corp. Current Limit Over-Voltage Protection Soft-Start Operation Thermal Shutdown VOUT CTL0 Enable • • • • COUT RFB1 (2) Protection Features VOUT LX PVIN (VOUT − 0.5)2 VOSTD ) ×( RFB1[kΩ] ⋅ (VOUT − VOSTD ) VOSTD − 0.5 To simplify the design, it is recommended to program the desired output voltage from a standard 1.0V as shown in Figure 1 with a proper CFF calculated from Equation 2. For programming the output voltage from other standard voltages, RFB1, RFB2 and CFF need to be adjusted to meet Equation 1and 2. SC183C is also capable of regulating a different (higher) output voltage, which is not shown in the Table 1, via RAVIN (1) where VOSTD is the pre-determined output voltage via the CTL pins. Programmable Output Voltage VIN VOUT − VOSTD ⋅ RFB 2 VOSTD 13 www.semtech.com SC183C Applications Information (continued) current (ICL_HOLD) of a few hundred milliampere. Under this condition, the output voltage will be the product of ICL_HOLD and the load resistance. The current limit holding current (ICL_HOLD) will decrease when the output voltage increases. The load presented must fall below the current limit holding current for the part to exit foldback current limit mode. Figure 2 shows how the typical current limit holding current varies with output voltage. The SC183C is capable of sustaining an indefinite short circuit without damage and will resume normal operation when the fault is removed. The foldback current limit mode is disabled during soft-start. The current limit functionality is shown in Figure 4. maintained for 200μs following an internal reference start up of 50μs giving a total nominal startup period of 850μs. During startup, the chip operates by controlling the inductor current swings between 0A and current limit. If at any time VOUT reaches 86% of the target or at the end of the soft-start period, the SC183C will switch to PWM mode operation. Figure 3 shows the typical diagram of soft start operation. The SC183C is capable of starting up into a pre-biased output. When the output is precharged by another supply rail, the SC183C will not discharge the output during the soft start interval. Shut Down When all CTL pins are low, the SC183C will run in shutdown mode, drawing less than 1μA from the input power supply. The internal switches and bandgap voltage will be immediately turned off. Current Limit Holding Current over Vout 300 Current Limit Holding Current (mA) TA= 25°C 250 VIN= 3.6V VIN= 5.0V 200 Thermal Shutdown 150 The device has a thermal shutdown feature to protect the SC183C if the junction temperature exceeds 160°C. During thermal shutdown, the on-chip power devices are disabled, tri-stating the LX output. When the temperature drops by 10°C, it will initiate a soft start cycle to resume normal operation. 100 VIN= 3.3V 50 0 1.0 1.5 2.0 2.5 3.0 3.5 Output Voltage (V) Figure 2 — Typical Current Limit Holding Current Inductor Selection The SC183C converter has internal loop compensation. The compensation is designed to work with a output filter corner frequency of less than 40kHz for a VIN of 5V and 50kHz for a VIN of 3.3V over any operating condition. The corner frequency of the output filter can be defined by Equation 3. Over-Voltage Protection In the event of a 15% over-voltage on the output, the PWM drive is disabled with LX pin floating. fC = Soft-Start (3) Values outside this range may lead to instability, malfunction, or out-of-specification performance. The soft-start mode is activated after AVIN reaches its UVLO and one or more CTL pins are set high to enable the part. A thermal shutdown event will also activate the soft start sequence. Soft-start mode controls the maximum current during startup thus limiting in-rush current. The PMOS current limit is stepped through four soft start levels of approximately 20%, 25%, 40%, & 100%. Each step is © 2010 Semtech Corp. 1 2π L ⋅ COUT In general, the inductance is chosen by making the inductor ripple current to be less than 30% of maximum load current. When choosing an inductor, it is important to consider the change in inductance with DC bias current. 14 www.semtech.com SC183C Applications Information (continued) The inductor saturation current is specified as the current at which the inductance drops a specific percentage from the nominal value. This is approximately 30%. Except for short-circuit or other fault conditions, the peak current must always be less than the saturation current specified by the manufacturer. The peak current is the maximum load current plus one half of the inductor ripple current at the maximum input voltage. Load and/or line transients can cause the peak current to exceed this level for short durations. Maintaining the peak current below the inductor saturation specification keeps the inductor ripple current and the output voltage ripple at acceptable levels. Manufacturers often provide graphs of actual inductance and saturation characteristics versus applied inductor current. The saturation characteristics of the inductor can vary significantly with core temperature. Core and ambient temperatures should be considered when examining the core saturation characteristics. options. The saturation characteristics and DC current ratings are also shown. Manufacturer Part Number DCR Max (Ω) Rated Current (A) L at Rated Current (μH) Dimensions LxWxH (mm) TOKO 1071AS-2R2M 2.20±20% 0.060 1.80 1.54 2.8x3.0x1.5 TOKO 1071AS-1R0N 1.00±30% 0.040 2.70 0.70 2.8x3.0x1.5 TOKO 1127AS-2R2M 2.20±20% 0.048 2.50 1.54 3.5x3.7x1.8 Panasonic ELLVGG1R0N 1.00±23% 0.062 2.20 0.70 3.2x3.2x1.5 Table 2 – Recommended Inductors COUT Selection The internal voltage loop compensation in the SC183C limits the minimum output capacitor value to 22µF if using an inductor value of 2.2µH or 44mF if using an inductor of 1µH. This is due to its influence on the the loop crossover frequency, phase margin, and gain margin. Increasing the output capacitor above this minimum value will reduce the crossover frequency and provide greater phase margin. The total output capacitance should not exceed 50mF to avoid any start-up problems. For most typical applications it is recommended to use an output capacitance of 22mF to 44mF. When choosing the output capacitor’s capacitance, verify the voltage derating effect from the capacitor vendors data sheet. When the inductance has been determined, the DC resistance (DCR) must be examined. The efficiency that can be achieved is dependent upon the DCR of the inductor. Lower values give higher efficiency. The RMS DC current rating of the inductor is associated with losses in the copper windings and the resulting temperature rise of the inductor. This is usually specified as the current which produces a 40˚C temperature rise. Most copper windings are rated to accommodate this temperature rise above maximum ambient. Magnetic fields associated with the output inductor can interfere with nearby circuitry. This can be minimized by the use of low noise shielded inductors which use the minimum gap possible to limit the distance that magnetic fields can radiate from the inductor. However shielded inductors typically have a higher DCR and are thus less efficient than a similar sized non-shielded inductor. Capacitors with X7R or X5R ceramic dielectric are recommended for their low ESR and superior temperature and voltage characteristics. Y5V capacitors should not be used as their temperature coefficients make them unsuitable for this application. The output voltage droop due to a load transient is determined by the capacitance of the ceramic output capacitor. The ceramic capacitor supplies the load current initially until the loop responds. Within a few switching cycles the loop will respond and the inductor current will increase to match the required load. The output voltage droop during the period prior to the loop responding can be related to the choice of output capacitor by the relationship from Equation 4. Final inductor selection depends upon various design considerations such as efficiency, EMI, size, and cost. Table 2 lists the manufacturers of recommended inductor © 2010 Semtech Corp. L (μH) 15 www.semtech.com SC183C Applications Information (continued) COUT = 3 ⋅ ∆I LOAD VDROOP ⋅ f OSC tor should be placed as closely as possible to the PVIN and PGND pins of the SC183C. (4) The output capacitor RMS current ripple may be calculated from Equation 5. I COUT ( RMS ) = 1 VOUT ⋅ (VIN ( MAX ) − VOUT ) L ⋅ f OSC ⋅VIN 2 3 (5) Table 3 lists the manufacturers of recommended output capacitor options. CIN Selection The SC183C source input current is a DC supply current with a triangular ripple imposed on it. To prevent large input voltage ripple, a low ESR ceramic capacitor is required. A minimum value of 4.7μF should be used. It is important to consider the DC voltage coefficient characteristics when determining the actual required value. It should be noted that a 10mF, 6.3V, X5R ceramic capacitor with 5V DC applied may exhibit a capacitance as low as 4.5mF. To estimate the required input capacitor, determine the acceptable input ripple voltage and calculate the minimum value required for CIN from Equation 6. C IN VOUT 1 − VIN = ∆V − ESR ⋅ f OSC I OUT VOUT VIN Manufacturer Part Nunber Value (μF) Type Rated Voltage (VDC) Value at 3.3V (μF) Dimensions LxWxH (mm) Murata GRM21BR60J106K 10±10% X5R 6.3 4.74 2.0x1.25x1.25 (EIA:0805) Murata GRM219R60J106K 10±10% X5R 6.3 4.05 2.0x1.25x0.85 (EIA:0805) Murata GRM21BR60J226M 22±20% X5R 6.3 6.57 2.0x1.25x1.25 (EIA:0805) Murata GRM31CR60J476M 47±20% X5R 6.3 20.3 3.2x1.6x1.6 (EIA:1206) Table 3 – Recommended Capacitors (6) The input capacitor RMS ripple current varies with the input and output voltage. The maximum input capacitor RMS current is found from Equation 7. I CIN ( RMS ) = VOUT VIN VOUT 1 − VIN (7) The input voltage ripple and RMS current ripple are at a maximum when the input voltage is twice the output voltage or 50% duty cycle. The input capacitor provides a low impedance loop for the edges of pulsed current drawn by the PMOS switch. Low ESR/ESL X5R ceramic capacitors are recommended for this function. To minimise stray inductance, the capaci© 2010 Semtech Corp. 16 www.semtech.com SC183C Applications Information (continued) SC4633 Soft Start B Stage 1 A Stage 0 Stage 2 C G F Stage 3 H D Stage 5 Stage 4 E I Stage 6 Figure 3 — Typical Diagram of Soft Start Operation SC183C/SC283/SC4633 Over Current Protection J Stage 7 K Stage 8 Stage 6 M L Figure 4 — Typical Diagram of Current Limit Protection © 2010 Semtech Corp. 17 www.semtech.com SC183C Applications Information (continued) PCB Layout Considerations The layout diagrams in Figure 5 and Figure 6 show a recommended PCB layout for a standard VOUT option and an adjustable VOUT option, respectively. Fundamental layout rules must be followed since the layout is critical for achieving the performance specified in the Electrical Characteristics table. Poor layout can degrade the performance of the DC-DC converter and can contribute to EMI problems, ground bounce, and resistive voltage losses. Poor regulation and instability can result. L VOUT CIN VIN U1 GND COUT GND CTLx (a) Top layer for standard volatge option The following guidelines are recommended when developing a PCB layout: GND 1. The input capacitor, CIN, provides a low impedance loop for the pulsed currents present at the buck converter’s inputs. CIN should therefore be placed as close to the PVIN and PGND pins as possible, and no more than 3mm away from the PVIN pin. Place the CIN and SC183C on the same component side to eliminate the use of vias between CIN and the device pins. Use short wide traces or a copper plane to connect as closely to the IC as possible. Use multiple vias for the ground connection to the ground plane to reduce the parasitic inductance. These measures will minimize EMI and input voltage ripple by localizing the high frequency current pulses. 2. Keep the LX pin traces as short as possible to minimize pickup of high frequency switching edges to other parts of the circuit. COUT and L should be connected as close as possible between the LX and GND pins, with a direct return to the GND pin from COUT. 3. Route the output voltage feedback/sense path away from the inductor and LX node to minimize noise and magnetic interference. 4. Use a ground plane referenced to the SC183C PGND pin. Use several vias to connect to the component side ground to further reduce noise and interference on sensitive circuit nodes. 5. If possible, minimize the resistance from the VOUT and AGND pins to the load. This will reduce the voltage drop on the ground plane and improve the load regulation. And it will also improve the overall efficiency by reducing the copper losses on the output and ground planes. © 2010 Semtech Corp. VOUT VIN GND (b) Bottom layer for standard voltage option Figure 5 — Recommended PCB Top & Bottom Layer Layout for Standard VOUT Option VOUT L VIN CIN U1 COUT GND GND CTLx (a) Top layer for adjustable voltage option GND VOUT VIN RFB1 GND RFB2 CFF (b) Bottom layer for adjustable voltage option Figure 6 — Recommended PCB Top & Bottom Layer Layout for Adjustable VOUT Option 18 www.semtech.com SC183C Outline Drawing – 3x3 MLPQ-UT16 A D B PIN 1 INDICATOR (LASER MARK) DIM E A2 A aaa C C A1 SEATING PLANE A A1 A2 b D D1 E E1 e L N aaa bbb DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .024 .002 (.006) .007 .009 .012 .114 .118 .122 .061 .067 .071 .114 .118 .122 .061 .067 .071 .020 BSC .012 .016 .020 16 .003 .004 .020 .000 0.60 0.05 (0.152) 0.18 0.23 0.30 2.90 3.00 3.10 1.55 1.70 1.80 2.90 3.00 3.10 1.55 1.70 1.80 0.50 BSC 0.30 0.40 0.50 16 0.08 0.10 0.50 0.00 D1 e/2 LxN E/2 E1 2 1 N e D/2 bxN bbb C A B NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 3. DAP IS 1.90 x 1.90mm. Land Pattern – 3x3 MLPQ-UT16 H R DIM (C) K G C G H K P R X Y Z Z Y X P DIMENSIONS INCHES MILLIMETERS (.114) .083 .067 .067 .020 .006 .012 .031 .146 (2.90) 2.10 1.70 1.70 0.50 0.15 0.30 0.80 3.70 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. © 2010 Semtech Corp. 19 www.semtech.com SC183C © Semtech 2010 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. 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