MCP47A1 DATA SHEET (08/16/2012) DOWNLOAD

MCP47A1
6-Bit Volatile DAC with Command Code
• 6-Bit DAC
- 65 Taps: 64 Resistors with Taps to Full-Scale
and Zero-Scale (Wiper Code 00h to 40h)
• VREF Pull-down Resistance: 20 k (typical)
• VOUT Voltage Range
- VSS to VREF
• I2C™ Protocol
- Supports SMBus 2.0 Write Byte/Word
Protocol Formats
- Supports SMBus 2.0 Read Byte/Word
Protocol Formats
- Slave Addresses: 5Ch and 7Ch
• Brown-out Reset Protection (1.5V typical)
• Power-on Default Wiper Setting (Mid-scale)
• Low-Power Operation: 90 µA Static Current (typical)
• Wide Operating Voltage Range:
- 1.8V to 5.5V
• Low Tempco: 15 ppm (typical)
• 100 kHz (typical) Bandwidth (-3 dB) Operation
• Extended Temperature Range (-40°C to +125°C)
• Small Packages, SC70-6
• Lead Free (Pb-free) Package
Package Types
MCP47A1
VDD 1
A
VSS 2
B
6 VREF
W
5 VOUT
SCL 3
4 SDA
SC70-6
Device Block Diagram
VDD
VSS
SDA
SCL
Power-up
and
Brown-out
Control
2-Wire
Interface
and
Control
Logic
A
Wiper Register (RAB = 20K)
Features:
VREF
VOUT
B
Applications
Description
• Set point or offset trimming
• Cost-sensitive mechanical trim pot replacement
The MCP47A1 devices are volatile, 6-Bit digital
potentiometers with a buffered output. The wiper
setting is controlled through an I2C serial interface. The
I2C slave addresses of “010 1110” and “011 1110”
are supported.
 2012 Microchip Technology Inc.
DS25154A-page 1
MCP47A1
VDD
Operating
Range
65
64
20
00h - 40h
20h
5Ch, 7Ch 1.8V (1)
to 5.5V
VSS to VREF
SC70-6
MCP47DA1(2)
I2C
65
64
30
00h - 7Fh
40h
5Ch, 7Ch 1.8V (1)
to 5.5V
1/3 VREF to
2/3 VREF
SC70-6,
SOT-23-6
MCP4706
I2C 256
256
210
00h - FFh
7Fh
Cxh (3)
2.7V to
5.5V
VSS to VDD or SOT-23-6,
VSS to VREF (5) DFN-6 (2x2)
MCP4716
I2C 1024 1024
210
000h - 3FFh 1FFh
Cxh (3)
2.7V to
5.5V
VSS to VDD or SOT-23-6,
VSS to VREF (5) DFN-6 (2x2)
MCP4726
I2C 4096 4096
210
000h - FFFh 3FFh
Cxh (3)
2.7V to
5.5V
VSS to VDD or SOT-23-6,
VSS to VREF (5) DFN-6 (2x2)
MCP4725
I2C 4096 4096
N.A.
000h - FFFh 3FFh
Cxh (4)
2.7V to
5.5V
VOUT
Range
I2C
I2C Slave
Address
# of
Resistors
POR/BOR
Value
# of Taps
MCP47A1
Device
Data
Value
Range
Interface
VREF
Resistance
(k)
Device Features
VSS to VDD
Package(s)
SOT-23-6
Note 1: Analog characteristics only tested from 2.7V to 5.5V.
2: Refer to MCP47DA1 Data Sheet (DS25118).
3: The A2:A0 bits are determined by device ordered.
4: The A2 and A1 bits are determined by device ordered and A0 is determined by the state of the A0 pin.
5: User programmable.
DS25154A-page 2
 2012 Microchip Technology Inc.
MCP47A1
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Voltage on VDD with respect to VSS .......................................................................................................... 0.6V to +7.0V
Voltage on SCL, and SDA with respect to VSS ..................................................................................................... -0.6V to VDD + 0.3V
Voltage on all other pins (VOUT and VREF) with respect to VSS ..................................................................... -0.3V to VDD + 0.3V
Input clamp current, IIK (VI < 0, VI > VDD) ............................................................................................................ ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD).................................................................................................. ±20 mA
Maximum output current sunk by any Output pin .................................................................................................. 25 mA
Maximum output current sourced by any Output pin ............................................................................................ 25 mA
Maximum current out of VSS pin .......................................................................................................................... 100 mA
Maximum current into VDD pin ............................................................................................................................. 100 mA
Maximum current into VREF pin............................................................................................................................. 250 uA
Maximum current sourced by VOUT pin ................................................................................................................. 40 mA
Maximum current sunk by VREF pin ....................................................................................................................... 40 mA
Package power dissipation (TA = +50°C, TJ = +150°C)
SC70-6 ..................................................................................................................................................... 480 mW
Storage temperature .............................................................................................................................. -65°C to +150°C
Ambient temperature with power applied .............................................................................................. -40°C to +125°C
ESD protection on all pins .......................................................................................................................... 6 kV (HBM)
..................................................................................................................................................................... 400V (MM)
 1.5 kV (CDM)
Latchup (JEDEC JESD78A) at +125°C ............................................................................................................. ±100 mA
Soldering temperature of leads (10 seconds) ...................................................................................................... +300°C
Maximum Junction Temperature (TJ) .................................................................................................................. +150°C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
 2012 Microchip Technology Inc.
DS25154A-page 3
MCP47A1
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C  TA  +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to +5.5V. CL = 1 nF, RL = 5 k .
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Supply Voltage
VDD
2.7
—
5.5
V
Analog Characteristics specified
1.8
—
5.5
V
Digital Characteristics specified
—
—
1.65
V
RAM retention voltage (VRAM) < VBOR
VDD Start Voltage
to ensure Wiper to
default reset state
VBOR
VDD Rise Rate to
ensure Power-on
Reset
VDDRR
Delay after device
exits the reset
state
(VDD > VBOR) to
Digital Interface
Active
TBORD
Delay after device
exits the reset
state
(VDD > VBOR) to
VOUT valid
TOUTV
Supply Current
(Note 6)
VREF Input Range
Note 1:
2:
3:
4:
5:
6:
7:
IDD
VREF
Note 5
—
—
Conditions
V/ms
1
µS
20
µS
Within ± 0.5 LSb of VREF / 2
(for default POR/BOR wiper value).
—
130
220
µA
Serial Interface Active,
Write all 0’s to Volatile Wiper,
No Load on VOUT
VDD = 5.5V, VREF = VDD,
FSCL = 400 kHz
—
90
130
µA
Serial Interface Inactive (Static),
(Stop condition, SCL = SDA = VIH),
No Load on VOUT
Wiper = 0, VDD = 5.5V, VREF = VDD
1
—
VDD
V
Note 7
Resistance is defined as the resistance between the VREF pin and the VSS pin.
INL and DNL are measured at VOUT from Code = 00h (Zero-Scale) through Code = 3Fh (Full-Scale - 1).
This specification by design.
Nonlinearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
POR/BOR is not rate dependent.
Supply current is independent of VREF current.
See Section 7.1.3.
DS25154A-page 4
 2012 Microchip Technology Inc.
MCP47A1
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C  TA  +125°C (extended)
DC Characteristics
Parameters
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to +5.5V. CL = 1 nF, RL = 5 k .
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
Max
Units
Conditions
Minimum Output
Voltage
VOUT(MIN)
—
VSS
—
V
Device Output minimum drive
Maximum Output
Voltage
VOUT(MAX)
—
VREF
—
V
Device Output maximum drive
Output Amplifier
Degree (°) CL = 400 pF, RL = 
Phase Margin
PM
—
66
—
Slew Rate
SR
—
0.55
—
V/µs
Short Circuit
Current
ISC
5
15
24
mA
Settling Time
tSETTLING
—
15
—
µs
External Reference (VREF) (Note 3)
CVREF
—
7
—
pF
THD
—
-73
—
dB
Major Code
Transition Glitch
—
45
—
nV-s
Digital
Feedthrough
—
<10
—
nV-s
Input Capacitance
Total Harmonic
Distortion
VREF = 1.65V ± 0.1V,
Frequency = 1 kHz
Dynamic Performance (Note 3)
Note 1:
2:
3:
4:
5:
6:
7:
1 LSb change around major carry
(20h to 1Fh)
Resistance is defined as the resistance between the VREF pin and the VSS pin.
INL and DNL are measured at VOUT from Code = 00h (Zero-Scale) through Code = 3Fh (Full-Scale - 1).
This specification by design.
Nonlinearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
POR/BOR is not rate dependent.
Supply current is independent of VREF current.
See Section 7.1.3.
 2012 Microchip Technology Inc.
DS25154A-page 5
MCP47A1
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C  TA  +125°C (extended)
DC Characteristics
Parameters
Resistance
(± 20%)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to +5.5V. CL = 1 nF, RL = 5 k .
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
Max
Units
RVREF
16.0
20
24.0
k
Taps
Note 1,
Resolution
N
Step Resistance
RS
—
RVREF / 64
—

Nominal
Resistance
Tempco
RVREF/T
—
50
—
ppm/°C
TA = -20°C to +70°C
—
100
—
ppm/°C
TA = -40°C to +85°C
—
150
—
ppm/°C
TA = -40°C to +125°C
Ratiometeric
Tempco
VOUT/T
—
15
—
ppm/°C
Code = Midscale (20h)
VOUT Accuracy
65
Conditions
No Missing Codes
Note 3
0.72
0.75
0.78
V
LVOUTR
5
—
—
k
Resistive Load
LVOUTC
—
—
1
nF
Capacitive Load
Maximum current
through Terminal
(VREF) Note 3
IVREF
—
—
345
µA
VREF = 5.5V
Leakage current
into VREF
IL
—
100
—
nA
VREF = VSS
Full-Scale Error
(code = 40h)
VFSE
-1
±0.35
+1
LSb
VREF = VDD
Zero-Scale Error
(code = 00h)
VZSE
-0.75
±0.35
+0.75
LSb
VREF = VDD
VOUT Integral
Nonlinearity
INL
-1
±0.25
+1
LSb
Note 2, VREF = VDD
VOUT Differential
Nonlinearity
DNL
-0.5
±0.25
+0.5
LSb
Note 2, VREF = VDD
Bandwidth -3 dB
BW
—
100
—
kHz
VDD = 5.0V, VREF = 3.0V ± 2.0V,
Code = 20h
CREF
—
75
—
pF
f =1 MHz, Code = Full-Scale
VOUT Load
Capacitance
(VREF)
Note 1:
2:
3:
4:
5:
6:
7:
VREF = 1.5V, code = 20h
Resistance is defined as the resistance between the VREF pin and the VSS pin.
INL and DNL are measured at VOUT from Code = 00h (Zero-Scale) through Code = 3Fh (Full-Scale - 1).
This specification by design.
Nonlinearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
POR/BOR is not rate dependent.
Supply current is independent of VREF current.
See Section 7.1.3.
DS25154A-page 6
 2012 Microchip Technology Inc.
MCP47A1
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C  TA  +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to +5.5V. CL = 1 nF, RL = 5 k .
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
—
—
V
1.8V  VDD  5.5V
—
0.3VD
V
1.8V  VDD  5.5V
Digital Inputs/Outputs (SDA, SCK)
Schmitt Trigger
High Input
Threshold
VIH
Schmitt Trigger
Low Input
Threshold
VIL
Hysteresis of
Schmitt Trigger
Inputs (Note 3)
VHYS
0.7 VD
D
-0.5
D
N.A.
—
—
V
100 kHz
VDD < 2.0V
N.A.
—
—
V
0.1 VD
—
—
V
—
—
V
VDD  2.0V
SDA
V
DD < 2.0V
and
SCL 400 kHz
VDD  2.0V
VSS
—
0.4
V
VDD  2.0V, IOL = 3 mA
VSS
—
0.2VD
V
VDD < 2.0V, IOL = 1 mA
D
0.05 V
DD
Output Low
Voltage (SDA)
VOL
D
Input Leakage
Current
Pin Capacitance
IIL
-1
—
1
µA
VREF = VDD and VREF = VSS
CIN, COUT
—
10
—
pF
fC = 400 kHz
N
0h
—
40h
hex
RAM (Wiper) Value
Value Range
Wiper POR/BOR
Value
20h
NPOR/BOR
hex
Power Requirements
Power Supply
Sensitivity
Note 1:
2:
3:
4:
5:
6:
7:
PSS
—
0.0015
0.003
5
%/%
VREF = VDD, Code = 20h
Resistance is defined as the resistance between the VREF pin and the VSS pin.
INL and DNL are measured at VOUT from Code = 00h (Zero-Scale) through Code = 3Fh (Full-Scale - 1).
This specification by design.
Nonlinearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
POR/BOR is not rate dependent.
Supply current is independent of VREF current.
See Section 7.1.3.
 2012 Microchip Technology Inc.
DS25154A-page 7
MCP47A1
1.1
I2C Mode Timing Waveforms and Requirements
SCL
93
91
90
92
SDA
START
Condition
STOP
Condition
I2C Bus Start/Stop Bits Timing Waveforms.
FIGURE 1-1:
103
102
100
101
SCL
90
106
91
92
107
SDA
In
110
109
109
SDA
Out
Note:
Refer to specification D102 (Cb) for load conditions.
I2C Bus Data Timing.
FIGURE 1-2:
I2C BUS START/STOP BITS REQUIREMENTS
TABLE 1-1:
I2C AC Characteristics
Param.
Symbol
No.
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40C  TA  +125C (Extended)
Operating Voltage VDD range is described in Section 2.0 “Typical
Performance Curves”
Characteristic
FSCL
D102
Cb
90
TSU:STA
91
92
93
Bus capacitive
loading
START condition
Setup time
THD:STA START condition
Hold time
TSU:STO STOP condition
Setup time
THD:STO STOP condition
Hold time
DS25154A-page 8
Standard Mode
Fast Mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
Min
Max
Units
0
0
—
—
4700
600
4000
600
4000
600
4000
600
100
400
400
400
—
—
—
—
—
—
—
—
kHz
kHz
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
Conditions
Cb = 400 pF, 1.8V - 5.5V
Cb = 400 pF, 2.7V - 5.5V
Only relevant for repeated
START condition
After this period, the first
clock pulse is generated
 2012 Microchip Technology Inc.
MCP47A1
TABLE 1-2:
I2C BUS DATA REQUIREMENTS (SLAVE MODE)
I2C AC Characteristics
Parameter No.
Sym
Characteristic
100
THIGH
Clock high time
101
TLOW
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40C  TA  +125C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Min
Max
Units
100 kHz mode
4000
—
ns
1.8V-5.5V
600
4700
—
—
ns
ns
2.7V-5.5V
Clock low time
400 kHz mode
100 kHz mode
1300
—
—
1000
ns
ns
102A(5)
TRSCL
SCL rise time
400 kHz mode
100 kHz mode
102B(5)
TRSDA
SDA rise time
400 kHz mode
100 kHz mode
20 + 0.1Cb
—
300
1000
ns
ns
(5)
TFSCL
SCL fall time
400 kHz mode
100 kHz mode
20 + 0.1Cb
—
300
300
ns
ns
SDA fall time
400 kHz mode
100 kHz mode
20 + 0.1Cb
—
40
300
ns
ns
400 kHz mode
300
ns
100 kHz mode
20 + 0.1Cb(5)
0
—
ns
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
0
250
100
—
—
—
—
3450
ns
ns
ns
ns
400 kHz mode
100 kHz mode
—
4700
900
—
ns
ns
400 kHz mode
1300
—
ns
103A
103B (5)
TFSDA
106
THD:DAT
Data input hold
time
107
TSU:DAT
Data input
setup time
109
TAA
Output valid
from clock
110
TBUF
Bus free time
2:
3:
4:
5:
6:
1.8V-5.5V
2.7V-5.5V
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
1.8V-5.5V (Note 6)
2.7V-5.5V (Note 6)
Note 5
Note 5
Time the bus must be free
before a new transmission
can start
Philips Spec states N.A.
Input filter spike 100 kHz mode
—
50
ns
suppression
400 kHz mode
—
50
ns
(SDA and SCL)
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tsu; DAT  250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
The MCP47A1 device must provide a data hold time to bridge the undefined part between VIH and VIL of
the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be
tested in order to guarantee that the output data will meet the setup and hold specifications for the
receiving device.
Use Cb in pF for the calculations.
Not tested.
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
TSP
Note 1:
Conditions
 2012 Microchip Technology Inc.
DS25154A-page 9
MCP47A1
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
JA
—
207
—
Conditions
Temperature Ranges
Specified Temperature Range
Thermal Package Resistances
Thermal Resistance, 6L-SC70
Note 1:
°C/W Note 1
Package Power Dissipation (PDIS) is calculated as follows:
PDIS = (TJ - TA) / JA,
where: TJ = Junction Temperature, TA = Ambient Temperature.
DS25154A-page 10
 2012 Microchip Technology Inc.
MCP47A1
2.0
TYPICAL PERFORMANCE CURVES
Note 1: The graphs and tables provided following this note are a statistical summary based on a limited number
of samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF.
Typical Device
1.00
0.75
0.75
0.50
0.50
0.25
0.25
INL (LSb)
INL (LSb)
Typical Device
1.00
0.00
0.25
0.00
0.25
0.50
0.75
40C 5.5V
+25C 5.5V
+85C 5.5V
+125C 5.5V
40C 2.7V
+25C 2.7V
+85C 2.7V
+125C 2.7V
40C 1.8V
+25C 1.8V
+85C 1.8V
+125C 1.8V
40C 1.0V
+25C 1.0V
+85C 1.0V
+125C 1.0V
0.50
40C 2.0V
40C 1.8V
40C 1.0V
0.75
1.00
+25C 2.0V
+25C 1.8V
+25C 1.0V
+85C 2.0V
+85C 1.8V
+85C 1.0V
+125C 2.0V
+125C 1.8V
+125C 1.0V
1.00
0
8
16
24
32
40
DAC Wiper Code
48
56
64
0
8
16
24
32
40
DAC Wiper Code
48
56
64
Analog Performance Specified for VDD ≥ 2.7V.
FIGURE 2-1:
INL vs. Code (00h to 3Fh)
and Temperature.
VDD = 5.5V, VREF = 5.5V, 2.7V, 1.8V, and 1.0V.
FIGURE 2-3:
INL vs. Code (00h to 3Fh)
and Temperature.
VDD = 2.0V, VREF = 2.0V, 1.8V, and 1.0V.
Typical Device
1.00
0.75
0.75
0.50
0.50
0.25
0.25
INL (LSb)
INL (LSb)
Typical Device
1.00
0.00
0.25
0.00
0.25
0.50
0.50
40C 2.7V
40C 1.8V
40C 1.0V
0.75
+25C 2.7V
+25C 1.8V
+25C 1.0V
+85C 2.7V
+85C 1.8V
+85C 1.0V
+125C 2.7V
+125C 1.8V
+125C 1.0V
0.75
1.00
40C 1.6V
40C 1.0V
+25C 1.6V
+25C 1.0V
+85C 1.6V
+85C 1.0V
+125C 1.6V
+125C 1.0V
1.00
0
8
16
24
32
40
DAC Wiper Code
48
56
64
0
8
16
24
32
40
DAC Wiper Code
48
56
64
Analog Performance Specified for VDD ≥ 2.7V.
FIGURE 2-2:
INL vs. Code (00h to 3Fh)
and Temperature.
VDD = 2.7V, VREF = 2.7V, 1.8V, and 1.0V.
 2012 Microchip Technology Inc.
FIGURE 2-4:
INL vs. Code (00h to 3Fh)
and Temperature.
VDD = 1.8V, VREF = 1.6V, and 1.0V.
DS25154A-page 11
MCP47A1
Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF.
Typical Device
Typical Device
0.50
0.50
40C 5.5V
40C 2.7V
40C 1.8V
40C 1.0V
+85C 5.5V
+85C 2.7V
+85C 1.8V
+85C 1.0V
+125C 5.5V
+125C 2.7V
+125C 1.8V
+125C 1.0V
40C 2.0V
40C 1.8V
40C 1.0V
+25C 2.0V
+25C 1.8V
+25C 1.0V
+85C 2.0V
+85C 1.8V
+85C 1.0V
+125C 2.0V
+125C 1.8V
+125C 1.0V
0.25
DNL (LSb)
DNL (LSb)
0.25
+25C 5.5V
+25C 2.7V
+25C 1.8V
+25C 1.0V
0.00
0.25
0.00
0.25
0.50
0.50
0
8
16
24
32
40
DAC Wiper Code
48
56
64
0
8
16
24
32
40
DAC Wiper Code
48
56
64
Analog Performance Specified for VDD ≥ 2.7V.
FIGURE 2-5:
DNL vs. Code (00h to 3Fh)
and Temperature.
VDD = 5.5V, VREF = 5.5V, 2.7V, 1.8V, and 1.0V.
FIGURE 2-7:
DNL vs. Code (00h to 3Fh)
and Temperature.
VDD = 2.0V, VREF = 2.0V, 1.8V, and 1.0V.
Typical Device
Typical Device
0.50
0.50
40C 2.7V
40C 1.8V
40C 1.0V
+25C 2.7V
+25C 1.8V
+25C 1.0V
+85C 2.7V
+85C 1.8V
+85C 1.0V
40C 1.6V
40C 1.0V
+125C 2.7V
+125C 1.8V
+125C 1.0V
+85C 1.6V
+85C 1.0V
+125C 1.6V
+125C 1.0V
0.25
DNL (LSb)
DNL (LSb)
0.25
+25C 1.6V
+25C 1.0V
0.00
0.25
0.00
0.25
0.50
0.50
0
8
16
24
32
40
DAC Wiper Code
48
56
64
0
8
16
24
32
40
DAC Wiper Code
48
56
64
Analog Performance Specified for VDD ≥ 2.7V.
FIGURE 2-6:
DNL vs. Code (00h to 3Fh)
and Temperature.
VDD = 2.7V, VREF = 2.7V, 1.8V, and 1.0V.
DS25154A-page 12
FIGURE 2-8:
DNL vs. Code (00h to 3Fh)
and Temperature.
VDD = 1.8V, VREF = 1.6V, and 1.0V.
 2012 Microchip Technology Inc.
MCP47A1
Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF.
Typical Device
Typical Device
0.00
0.00
0.20
Fulll Scale Error (LSb)
Fulll Scale Error (LSb)
0.20
0.40
0.60
When VREF =V
WhenV
= VDD
FSE 5.5V
FSE 2.7V
0.80
0.40
0.60
0.80
1.00
1.20
FSE 1.8V
FSE 1.0V
FSE 2.0V
FSE 1.8V
FSE 1.0V
1.40
1.00
1.60
40
20
0
20
40
60
Temperature (°C)
80
100
120
40
20
0
20
40
60
Temperature (°C)
80
100
120
Analog Performance Specified for VDD ≥ 2.7V.
FIGURE 2-9:
Full Scale Error (FSE) vs.
Temperature.
VDD = 5.5V, VREF = 5.5V, 2.7V, 1.8V, and 1.0V.
FIGURE 2-11:
Full Scale Error (FSE) vs.
Temperature.
VDD = 2.0V, VREF = 2.0V, 1.8V, and 1.0V.
Typical Device
0.00
0.20
1.00
Fulll Scale Error (LSb)
Fulll Scale Error (LSb)
Typical Device
0.00
0.40
0.60
WhenVREF =VDD
0.80
2.00
3.00
4.00
FSE 2.7V
FSE 1.6V
FSE 1.8V
FSE 1.0V
FSE 1.0V
1.00
5.00
40
20
0
20
40
60
Temperature (°C)
80
100
120
40
20
0
20
40
60
Temperature (°C)
80
100
120
Analog Performance Specified for VDD ≥ 2.7V.
FIGURE 2-10:
Full Scale Error (FSE) vs.
Temperature.
VDD = 2.7V, VREF = 2.7V, 1.8V, and 1.0V.
 2012 Microchip Technology Inc.
FIGURE 2-12:
Full Scale Error (FSE) vs.
Temperature.
VDD = 1.8V, VREF = 1.6V, and 1.0V.
DS25154A-page 13
MCP47A1
Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF.
Typical Device
Typical Device
1.00
1.00
ZSE 2.0V
ZSE 1.8V
ZSE 1.0V
ZSE 5.5V
ZSE 2.7V
0.80
ZSE 1.8V
Zero
o Scale Error (LSb)
Zero
o Scale Error (LSb)
0.80
ZSE 1.0V
0.60
0.40
0.20
0.60
0.40
0.20
0.00
0.00
40
20
0
20
40
60
Temperature (°C)
80
100
120
40
20
0
20
40
60
Temperature (°C)
80
100
120
Analog Performance Specified for VDD ≥ 2.7V.
FIGURE 2-13:
Zero Scale Error (ZSE) vs.
Temperature.
VDD = 5.5V, VREF = 5.5V, 2.7V, 1.8V, and 1.0V.
FIGURE 2-15:
Zero Scale Error (ZSE) vs.
Temperature.
VDD = 2.0V, VREF = 2.0V, 1.8V, and 1.0V.
Typical Device
Typical Device
1.00
ZSE 2.7V
ZSE 1.8V
ZSE 1.0V
ZSE 1.6V
ZSE 1.0V
0.80
Zero
o Scale Error (LSb)
0.80
Zero
o Scale Error (LSb)
1.00
0.60
0.40
0.20
0.60
0.40
0.20
0.00
0.00
40
20
0
20
40
60
Temperature (°C)
80
100
120
40
20
0
20
40
60
Temperature (°C)
80
100
120
Analog Performance Specified for VDD ≥ 2.7V.
FIGURE 2-14:
Zero Scale Error (ZSE) vs.
Temperature.
VDD = 2.7V, VREF = 2.7V, 1.8V, and 1.0V.
DS25154A-page 14
FIGURE 2-16:
Zero Scale Error (ZSE) vs.
Temperature.
VDD = 1.8V, VREF = 1.6V, and 1.0V.
 2012 Microchip Technology Inc.
MCP47A1
Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF.
Typical Device
Typical Device
1.00
1.00
0.50
40C 5.5V
+25C 5.5V
+85C 5.5V
+125C 5.5V
40C 2.7V
+25C 2.7V
+85C 2.7V
+125C 2.7V
40C 1.8V
+25C 1.8V
+85C 1.8V
+125C 1.8V
40C 1.0V
+25C 1.0V
+85C 1.0V
+125C 1.0V
0.25
0.00
0.25
0.50
WhenVREF =VDD
(code=64)
0.75
40C 2.0V
40C 1.8V
40C 1.0V
0.75
Total U
Unadjusted Error (LSb)
Total Unadjus
sted Error (LSb)
0.75
0.50
+25C 2.0V
+25C 1.8V
+25C 1.0V
+85C 2.0V
+85C 1.8V
+85C 1.0V
+125C 2.0V
+125C 1.8V
+125C 1.0V
0.25
0.00
0.25
0.50
0.75
1.00
1.25
1.00
1.50
0
8
16
24
32
40
48
56
64
0
8
16
DAC Wiper Code
24
32
40
48
56
64
DAC Wiper Code
Analog Performance Specified for VDD ≥ 2.7V.
FIGURE 2-17:
Total Unadjusted Error vs.
Code and Temperature.
VDD = 5.5V, VREF = 5.5V, 2.7V, 1.8V, and 1.0V.
FIGURE 2-19:
Total Unadjusted Error vs.
Code and Temperature.
VDD = 2.0V, VREF = 2.0V, 1.8V, and 1.0V.
Typical Device
Typical Device
1.00
1.00
Total U
Unadjusted Error (LSb)
+25C 2.7V
+25C 1.8V
+25C 1.0V
+85C 2.7V
+85C 1.8V
+85C 1.0V
+125C 2.7V
+125C 1.8V
+125C 1.0V
Total U
Unadjusted Error (LSb)
40C 2.7V
40C 1.8V
40C 1.0V
0.75
0.50
0.25
0.00
0.25
0.50
WhenVREF =VDD
(code=64)
0.75
1.00
40C 1.6V
+25C 1.6V
+85C 1.6V
+125C 1.6V
40C 1.0V
+25C 1.0V
+85C 1.0V
+125C 1.0V
0.00
1.00
2.00
WhenVREF =1.6V
(duetoOutputDriverlinearityatVDD =1.8V)
3.00
4.00
5.00
0
8
16
24
32
40
48
56
DAC Wiper Code
64
0
8
16
24
32
40
48
56
64
DAC Wiper Code
Analog Performance Specified for VDD ≥ 2.7V.
FIGURE 2-18:
Total Unadjusted Error vs.
Code and Temperature.
VDD = 2.7V, VREF = 2.7V, 1.8V, and 1.0V.
 2012 Microchip Technology Inc.
FIGURE 2-20:
Total Unadjusted Error vs.
Code and Temperature.
VDD = 1.8V, VREF = 1.6V, and 1.0V.
DS25154A-page 15
MCP47A1
Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF.
Typical Device
Typical Device
10.00
PPM/C 5.5V
PPM/C2.7V
PPM/C 1.8V
PPM/C 1.0V
8.00
6.00
PPM per °C
PPM p
per °C
4.00
2.00
0 00
0.00
2.00
4.00
6.00
8.00
10.00
0
8
16
24
32
40
DAC Wiper Code
48
56
85.00
80.00
75.00
70.00
65.00
60.00
55.00
50.00
45.00
40.00
35.00
30.00
25.00
20.00
15.00
10.00
5.00
0.00
5.00
10.00
64
PPM/C 2.0V
PPM/C 1.8V
PPM/C 1.0V
0
8
16
24
32
40
DAC Wiper Code
48
56
64
Analog Performance Specified for VDD ≥ 2.7V.
FIGURE 2-21:
VOUT Tempco vs. Code ( ( (
(VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) )
/ 165 ) * 1,000,000 ),
VDD = 5.5V, VREF = 5.5V, 2.7V, 1.8V, and 1.0V.
FIGURE 2-23:
VOUT Tempco vs. Code ( ( (
(VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) )
/ 165 ) * 1,000,000 ),
VDD = 2.0V, VREF = 2.0V, 1.8V, and 1.0V.
Typical Device
Typical Device
14.00
PPM/C 2.7V
PPM/C 1.8V
PPM/C 1.0V
12.00
10.00
6.00
PPM per °C
PPM per °C
8.00
4.00
2.00
0.00
2.00
4.00
6.00
8.00
10.00
0
8
16
24
32
40
DAC Wiper Code
48
56
64
350
330
310
290
270
250
230
210
190
170
150
130
110
90
70
50
30
10
10
PPM/C 1.8V
PPM/C 1.0V
0
8
16
24
32
40
DAC Wiper Code
48
56
64
Analog Performance Specified for VDD ≥ 2.7V.
FIGURE 2-22:
VOUT Tempco vs. Code ( ( (
(VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) )
/ 165 ) * 1,000,000 ),
VDD = 2.7V, VREF = 2.7V, 1.8V, and 1.0V.
DS25154A-page 16
FIGURE 2-24:
VOUT Tempco vs. Code ( ( (
(VOUT(+125C) - VOUT(-40C) ) / VOUT(+25C,Code=FS) )
/ 165 ) * 1,000,000 ),
VDD = 1.8V, VREF = 1.6V, and 1.0V.
 2012 Microchip Technology Inc.
MCP47A1
Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF.
Typical Device
1.0
VIL 5.5V
VIL 2.7V
VIL 1.8V
VIH 5.5V
VIH 2.7V
VIH 1.8V
200
400kHz 5.5V
400kHz 3.3V
400kHz 2.7V
400kHz 1.8V
100kHz 5.5V
100kHz 3.3V
100kHz 2.7V
100kHz 1.8V
180
160
0.6
Cu
urrent (uA)
Vo
oltage / VDD
0.8
Typical Device
220
0.4
0.2
140
120
100
80
60
0.0
40
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
FIGURE 2-25:
VIH / VIL Threshold of
SDA/SCL Inputs vs. Temperature and VDD.
VOL 5.5V
VOL 2.7V
VOL 1.8V
0.4
0
20
40
60
Temperature (C)
80
100
120
Typical Device
220
200
0.3
Static 5.5V
Static 3.3V
Static 2.7V
Static 1.8V
180
160
0.2
Cu
urrent (uA)
Voltage
V
(V)
-20
FIGURE 2-27:
Interface Active Current
(IDD) vs. SCL Frequency (fSCL) and Temperature
VDD = 1.8V, 2.7V and 5.5V,
VREF = 1.0V and VDD. (no load on VOUT).
Typical Device
0.5
-40
0.1
0.0
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
140
120
100
80
60
40
FIGURE 2-26:
Temperature.
VOL (SDA) vs. VDD and
-40
-20
0
20
40
60
Temperature (C)
80
100
120
FIGURE 2-28:
Interface Inactive Current
(STATIC) vs. Temperature and VDD.
VDD = 1.8V, 2.7V and 5.5V, VREF = 1.0V and
VDD. (no load on VOUT, SCL = SDA = VDD).
 2012 Microchip Technology Inc.
DS25154A-page 17
MCP47A1
Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF.
Typical Device
5
Typical Device
5
Code = 40h
4
4
3
3
VOUT (V)
VOUT (V)
Code = 00h
2
1
Code = 40h
2
1
0
0
0
1000
FIGURE 2-29:
VDD = 5.0V.
2000
3000
ISOURCE/SINK (mA)
4000
0
5000
VOUT vs. Resistive Load.
4
6
8
ISOURCE/SINK (mA)
10
12
14
FIGURE 2-31:
VOUT vs. Source / Sink
Current. VDD = 5.0V.
Typical Device
2.7
2
Typical Device
2.7
Code = 40h
Code = 00h
1.8
VOUT (V)
VOUT (V)
1.8
Code = 40h
0.9
0.9
0.0
0.0
0
1000
FIGURE 2-30:
VDD = 2.7V.
DS25154A-page 18
2000
3000
ISOURCE/SINK (mA)
4000
5000
VOUT vs. Resistive Load.
0
2
4
6
8
ISOURCE/SINK (mA)
10
12
14
FIGURE 2-32:
VOUT vs. Source / Sink
Current. VDD = 2.7V.
 2012 Microchip Technology Inc.
MCP47A1
Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF.
Typical Device
0.78
VOUT 5.5V
VOUT 2.7V
0.77
VOUT (V)
0.76
0.75
0.74
0.73
0.72
-40
-20
0
20
40
60
Temperature (C)
FIGURE 2-33:
Temperature.
80
100 120
VOUT Accuracy vs. VDD and
Typical Device
23000
RVREF5.5V
RVREF 2.7V
RVREF 1.8V
22000
Cu
urrent (uA)
21000
20000
19000
18000
17000
-40
-20
0
20 40 60
Temperature (°C)
80
100 120
Analog Performance Specified for VDD ≥ 2.7V.
FIGURE 2-34:
and Temperature.
RVREF Resistances vs. VDD
Typical Device
3.00
0.00
3.00
6.00
dB
9.00
12.00
15.00
18.00
21.00
FullScale VREF=2.7V
MidScaleVREF=2.7V
QuarterScaleVREF=2.7V
24.00
27.00
FullScaleVREF=5.5V
MidScaleVREF=5.5V
QuarterScaleVREF=5.5V
30.00
1
10
100
1000
Frequency (kHz)
FIGURE 2-35:
-3dB Bandwidth vs
Frequency, VDD = 5.5V.
 2012 Microchip Technology Inc.
DS25154A-page 19
MCP47A1
Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF.
FIGURE 2-36:
Zero-Scale to Full-Scale
Settling Time (00h to 40h),
VDD = 5.0V, VREF = 5.0V, RL = 5k, CL = 200 pF
(Time scale = 2 µs / div).
FIGURE 2-38:
Half-Scale Settling Time
(10h to 30h),
VDD = 5.0V, VREF = 5.0V, RL = 5k, CL = 200 pF.
(Time scale = 2 µs / div)
FIGURE 2-37:
Full-Scale to Zero-Scale
Settling Time (40h to 00h),
VDD = 5.0V, VREF = 5.0V, RL = 5k, CL = 200 pF
(Time scale = 2 µs / div).
FIGURE 2-39:
Half-Scale Settling Time
(30h to 10h),
VDD = 5.0V, VREF = 5.0V, RL = 5k, CL = 200 pF
(Time scale = 2 µs / div).
DS25154A-page 20
 2012 Microchip Technology Inc.
MCP47A1
Note: Unless otherwise indicated, TA = +25°C, VDD = VREF = 5V, VSS = 0V, RL = 5 k, CL = 1 nF.
2.1
Test Circuit
VIN
4.0V
(peak to
peak)
VDD
VREF
W
+
VOUT
-
1.0V DC
FIGURE 2-41:
Test.
-3 db Gain vs. Frequency
FIGURE 2-40:
Digital Feedthrough
(SCL signal coupling to VOUT pin);
VDD = 5.0V, VREF = 5.0V, FSCL = 100 kHz,
VOUT = 20h (VOUT Voltage Scale = 20 mV/div,
Time scale = 2 µs / div).
 2012 Microchip Technology Inc.
DS25154A-page 21
MCP47A1
NOTES:
DS25154A-page 22
 2012 Microchip Technology Inc.
MCP47A1
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follow.
TABLE 3-1:
PINOUT DESCRIPTION FOR THE MCP47A1
Pin
Name
Package
SC70-6
Pin
Type
Buffer
Type
VDD
1
P
—
Positive Power Supply Input
VSS
2
P
—
Ground
SCL
3
I/O
ST (OD)
I2C Serial Clock pin
SDA
4
I/O
ST (OD)
I2C Serial Data pin
VOUT
5
I/O
A
Output voltage
VREF
6
I/O
A
Reference Voltage for VOUT output
Function
Legend: A = Analog input
I = Input
3.1
ST (OD) = Schmitt Trigger with Open Drain
O = Output
I/O = Input/Output
Positive Power Supply Input (VDD)
3.5
P = Power
Analog Output Voltage Pin (VOUT)
The VDD pin is the device’s positive power supply input.
The input power supply is relative to VSS and can range
from 1.8V to 5.5V. A decoupling capacitor on VDD
(to VSS) is recommended to achieve maximum
performance. Analog specifications are tested from
2.7V.
VOUT can swing from approximately VZS (= VSS) to VFS
(= VREF). In normal mode, the DC impedance of the
output pin is about 1 . See Section 7.0 “Output
Buffer” for more information.
3.2
3.6
Ground (VSS)
The VSS pin is the device ground reference.
3.3
I2C Serial Clock (SCL)
The SCL pin is the serial clock pin of the I2C interface.
The MCP47A1 acts only as a slave and the SCL pin
accepts only external serial clocks. The SCL pin is an
open-drain output. Refer to Section 5.0 “Serial
Interface - I2C Module” for more details of I2C Serial
Interface communication.
3.4
VOUT is the DAC analog output pin. The DAC output
has an output amplifier.
Voltage Reference Pin (VREF)
This pin is the external voltage reference input. The
VREF pin signal is unbuffered so the reference voltage
must have the current capability not to drop its voltage
when connected to the internal resistor ladder circuit
(20 k typical). See Section 6.0 “Resistor Network”
for more information.
I2C Serial Data (SDA)
The SDA pin is the serial data pin of the I2C interface.
The SDA pin has a Schmitt trigger input and an
open-drain output. Refer to Section 5.0 “Serial
Interface - I2C Module” for more details of I2C Serial
Interface communication.
 2012 Microchip Technology Inc.
DS25154A-page 23
MCP47A1
NOTES:
DS25154A-page 24
 2012 Microchip Technology Inc.
MCP47A1
4.0
GENERAL OVERVIEW
VREF
The MCP47A1 device is a general purpose DAC
intended to be used in applications where a programmable voltage output with moderate bandwidth is
desired.
A
RFS
Applications generally suited for the MCP47A1 devices
include:
RS
• Set point or offset trimming
• Sensor calibration
• Cost-sensitive mechanical trim pot replacement
RS
•
•
•
•
POR/BOR Operation
Serial Interface - I2C Module
Resistor Network
Output Buffer
The POR/BOR operation is discussed in this section
and the I2C and Resistor Network operation are
described in their own sections. The commands are
discussed in Section 5.3, Serial Commands.
Figure 4-1 shows a block diagram for the resistive
network of the device. An external pin, called VREF, is
the DAC’s reference voltage. The resistance from the
VREF pin to ground is typically 20 k. The reference
voltage connected to the VREF pin needs to support this
resistive load.
This resistor network functions as a windowed voltage
divider. This means that the VOUT pin’s voltage range is
from approximately VSS to approximately VREF.
RW (1)
Goes to Output
Buffer’s input
RAB
The MCP47A1 has four main functional blocks. These
are:
RW (1)
W
RW (1)
RS
RW (1)
Analog Switch Mux
RZS
B
+
Op Amp
-
VOUT
Note 1: The wiper resistance is tap dependent.
That is, each tap selection resistance
has a small variation.
2: The RFS and RZS resistances are
determined by the analog switches that
connect the resistor network to the other
circuitry.
FIGURE 4-1:
Resistor Network and
Output Buffer Block Diagram.
 2012 Microchip Technology Inc.
DS25154A-page 25
MCP47A1
4.1
POR/BOR Operation
4.1.2
BROWN-OUT RESET
The Power-on Reset is the case where the device has
power applied to it from VSS. The Brown-out Reset
occurs when a device had power applied to it, and that
power (voltage) drops below the specified range.
When the device powers down, the device VDD will
cross the VPOR/VBOR voltage (VBOR < 1.8V). Once the
VDD voltage decreases below the VPOR/VBOR voltage,
the following happens:
The device’s RAM retention voltage (VRAM) is lower
than the POR/BOR voltage trip point (VPOR/VBOR).
This ensures that when the device Power-on Reset
occurs, the logic can retain default values that are
loaded. The maximum VPOR/VBOR voltage is less than
1.8V. When VPOR/VBOR < VDD < 1.8V, the DACs’ electrical performance may not meet the data sheet
specifications.
• Serial Interface is disabled
As the voltage recovers above the VPOR/VBOR voltage,
see Section 4.1.1 “Power-on Reset”.
Table 4-2 shows the DAC’s level of functionality across
the entire VDD range, while Figure 4-2 illustrates the
Power-up and Brown-out functionality.
Serial commands not completed due to a Brown-out
condition may cause the memory location to become
corrupted.
4.1.1
4.1.3
POWER-ON RESET
When the device powers up, the device VDD will cross
the VPOR/VBOR voltage. Once the VDD voltage crosses
the VPOR/VBOR voltage, the following happens:
• Volatile Serial Shift Register / Wiper register is
loaded with the default values (see Table 4-1)
• The device is capable of digital operation
Note:
At voltages below VDD(MIN), the electrical
performance of the I2C interface may not
meet the data sheet specifications
TABLE 4-1:
DEFAULT POR WIPER
SETTING SELECTION
Default POR
Wiper Setting
Serial Shift
Register (SSR)
Wiper Register
Mid-scale
20h
20h
TABLE 4-2:
VDD Level
If the VDD voltage decreases below the VRAM voltage,
the following happens:
• Volatile Serial Shift Register (SSR) and Wiper
register may become corrupted
WIPER REGISTER (RAM)
The Wiper Register is 7-bit volatile memory that starts
functioning at the RAM retention voltage (VRAM). The
Wiper Register will be loaded with the default wiper
value when VDD rises above the VPOR/VBOR voltage.
4.1.4
DEVICE CURRENTS
The current of the device can be classified into two
modes of the device operation. These are:
• Serial Interface Inactive (Static Operation)
• Serial Interface Active
Static Operation occurs when a Stop condition is
received. Static Operation is exited when a Start
condition is received.
DEVICE FUNCTIONALITY AT EACH VDD REGION (Note 1)
Serial
Interface
VOUT
DAC Register Setting
Comment
VDD < VTH
Ignored
“Unknown”
Pulled Low
VTH < VDD < VBOR Ignored
VBOR  VDD < 1.8V “Unknown” Operational with reduced
electrical specifications
1.8V  VDD  5.5V Accepted Operational
Unknown
Unknown
DAC Register loaded with
POR/BOR value
DAC Register determines Meets the data sheet
Serial Value
specifications
Note 1: For system voltages below the minimum operating voltage, it is recommended to use a voltage supervisor
to hold the system in reset. This will ensure that MCP47x1 commands are not attempted out of the operating range of the device.
DS25154A-page 26
 2012 Microchip Technology Inc.
MCP47A1
Normal Operation Range
VDD
Outside Specified
AC/DC Range
Normal Operation Range
1.8V
VPOR/BOR
VRAM
VSS
Below Minimum Operating Voltage
Device’s Serial
VBOR delay
Interface is
“Not Operational” Wiper forced to default POR/BOR setting
FIGURE 4-2:
Power-up and Brown-out.
 2012 Microchip Technology Inc.
DS25154A-page 27
MCP47A1
NOTES:
DS25154A-page 28
 2012 Microchip Technology Inc.
MCP47A1
5.0
SERIAL INTERFACE I2C MODULE
5.1
A 2-wire I2C serial protocol is used to write or read the
DAC’s wiper register. The I2C protocol utilizes the SCL
input pin and SDA input/output pin.
The I2C serial interface supports the following features:
• Slave mode of operation
• 7-bit addressing
• The following clock rate modes are supported:
- Standard mode, bit rates up to 100 kb/s
- Fast mode, bit rates up to 400 kb/s
• Support Multi-Master Applications
The serial clock is generated by the Master.
The I2C Module is compatible with the NXP I2C
specification (# UM10204). Only the field types, field
lengths, timings, etc. of a frame are defined. The frame
content defines the behavior of the device. The frame
content for the MCP47A1 device is defined in this section of the data sheet.
Figure 5-1 shows a typical I2C bus configuration.
Single I2C Bus Configuration
Device 1
Device n
Host
Controller
Device 2
FIGURE 5-1:
Configurations.
I2C specifications require active low, passive high
functionality on devices interfacing to the bus. Since
devices may be operating on separate power supply
sources, ESD clamping diodes are not permitted. The
specification recommends using open drain transistors
tied to VSS (common) with a pull-up resistor. The
specification makes some general recommendations
on the size of this pull-up, but does not specify the
exact value since bus speeds and bus capacitance
impacts the pull-up value for optimum system
performance.
Common pull-up values range from 1 k to a maximum
of ~10 k. Power sensitive applications tend to choose
higher values to minimize current losses during
communication but these applications also typically
utilize lower VDD.
The SDA and SCL float (are not driving) when the
device is powered down.
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. When these pins are an output, there is a
slew rate control of the pin that is independent of device
frequency.
5.1.1
Device 3
Device 4
I2C I/O Considerations
SLOPE CONTROL
The device implements slope control on the SDA
output. The slope control is defined by the fast mode
specifications.
For Fast (FS) mode, the device has spike suppression
and Schmidt trigger inputs on the SDA and SCL pins.
Typical Application I2C Bus
Refer to Section 2.0 “Typical Performance Curves”,
AC/DC Electrical Characteristics table for detailed input
threshold and timing specifications.
 2012 Microchip Technology Inc.
DS25154A-page 29
MCP47A1
5.2
I2C Bit Definitions
If the Slave Address is not valid, the Slave Device will
issue a Not A (A). The A bit will have the SDA signal
high.
I2C bit definitions include:
•
•
•
•
•
•
Start Bit
Data Bit
Acknowledge (A) Bit
Repeated Start Bit
Stop Bit
Clock Stretching
If an error condition occurs (such as an A instead of A)
then a START bit must be issued to reset the command
state machine.
TABLE 5-1:
Acknowledge
Bit Response
Event
Figure 5-8 shows the waveform for these states.
5.2.1
START BIT
The Start bit (see Figure 5-2) indicates the beginning of
a data transfer sequence. The Start bit is defined as the
SDA signal falling when the SCL signal is “High”.
General Call
A
Slave Address
valid
A
Slave Address
not valid
A
Bus Collision
N.A.
2nd Bit
1st Bit
SDA
SCL
S
FIGURE 5-2:
5.2.2
Start Bit.
5.2.4
DATA BIT
The SDA signal may change state while the SCL signal
is Low. While the SCL signal is High, the SDA signal
MUST be stable (see Figure 5-3).
2nd Bit
1st Bit
SDA
SCL
FIGURE 5-3:
5.2.3
8
FIGURE 5-4:
REPEATED START BIT
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is “High”.
ACKNOWLEDGE (A) BIT
SCL
I2C Module Resets,
or a “Don’t Care” if
the collision occurs
on the Masters
“Start bit”.
Note 1: A bus collision during the Repeated Start
condition occurs if:
Data Bit.
D0
Comment
The Repeated Start bit (see Figure 5-5) indicates
the current Master Device wishes to continue
communicating with the current Slave Device without
releasing the I2C bus. The Repeated Start condition is
the same as the Start condition, except that the
Repeated Start bit follows a Start bit (with the Data bits
+ A bit) and not a Stop bit.
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
The A bit (see Figure 5-4) is a response from the Slave
device to the Master device. Depending on the context
of the transfer sequence, the A bit may indicate
different things. Typically the Slave device will supply
an A response after the Start bit and 8 “data” bits have
been received. The A bit will have the SDA signal low.
SDA
MCP47A1 A / A RESPONSES
A
SDA
1st Bit
9
Acknowledge Waveform.
SCL
Sr = Repeated Start
FIGURE 5-5:
Waveform.
DS25154A-page 30
Repeat Start Condition
 2012 Microchip Technology Inc.
MCP47A1
5.2.5
STOP BIT
5.2.7
If any part of the I2C transmission does not meet the
command format, it is aborted. This can be intentionally
accomplished with a START or STOP condition. This is
done so that noisy transmissions (usually an extra
START or STOP condition) are aborted before they
corrupt the device.
The Stop bit (see Figure 5-6) indicates the end of the
I2C Data Transfer Sequence. The Stop bit is defined as
the SDA signal rising when the SCL signal is “High”.
A Stop bit resets the I2C interface of the other devices.
SDA A / A
5.2.8
SCL
5.2.6
IGNORING AN I2C TRANSMISSION
AND “FALLING OFF” THE BUS
The MCP47A1 expects to receive entire, valid I2C commands and will assume any command not defined as a
valid command is due to a bus corruption, and will enter
a passive high condition on the SDA signal. All signals
will be ignored until the next valid START condition and
CONTROL BYTE are received.
P
FIGURE 5-6:
Transmit Mode.
ABORTING A TRANSMISSION
Stop Condition Receive or
CLOCK STRETCHING
“Clock Stretching” is something that the secondary
device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP47A1 will not stretch the clock signal (SCL)
since memory read accesses occur fast enough.
SDA
SCL
S
FIGURE 5-7:
1st 2nd 3rd 4th 5th 6th 7th 8th A/A 1st 2nd 3rd 4th 5th 6th 7th 8th A/A
Bit Bit Bit Bit Bit Bit Bit Bit
Bit Bit Bit Bit Bit Bit Bit Bit
P
Typical 16-bit I2C Waveform Format.
SDA
SCL
START
Condition
FIGURE 5-8:
Data allowed
to change
Data or
A valid
STOP
Condition
I2C Data States and Bit Sequence.
 2012 Microchip Technology Inc.
DS25154A-page 31
MCP47A1
5.2.9
I2C COMMAND PROTOCOL
TABLE 5-2:
The MCP47A1 is a slave I2C device which supports 7bit slave addressing. The slave address contains seven
fixed bits. Figure 5-9 shows the control byte format.
5.2.9.1
Control Byte (Slave Address)
The Control Byte is always preceded by a START
condition. The Control Byte contains the slave address
consisting of seven fixed bits and the R/W bit. Figure 59 shows the control byte format and Table 5-2 shows
the I2C address for the devices.
I2C Address
Binary
Hex (1) Code Comment
MCP47A1
‘0101110’ 0x5C
A0
‘0111110’ 0x7C
A1
Note 1: The LSb of the 8-bit hex code is the I2C
Read/Write (R/W) bit. This hex value has
a R/W bit = “0” (write). If the R/W bit
reflected a read, these values would be
0x5D and 0x7D.
Device
Note 1: The MCP47A1 device supports two different I2C address (A0 and A1). This allows
two MCP47A1 devices on the same I2C
bus.
Slave Address
S A6 A5 A4 A3 A2 A1 A0 R/W
“0” “1” “0” “1” “1” “1” “0”
A/A
5.2.9.2
Start
bit
Hardware Address Pins
The MCP47A1 does not support hardware address
bits.
R/W bit
R/W = 0 = write
R/W = 1 = read
A bit (controlled by slave device)
A = 0 = Slave Device Acknowledges byte
A = 1 = Slave Device does not Acknowledge byte
FIGURE 5-9:
I2C Control Byte.
DEVICE I2C ADDRESS
Slave Address Bits in the
5.2.10
GENERAL CALL
The General Call is a method that the Master device
can communicate with all other Slave devices.
The MCP47A1 devices do not respond to General Call
address and commands, and therefore the
communications are Not Acknowledged.
Second Byte
S 0 0 0 0
0 0 0 0 A
General Call Address
X X X X X X X 0 A P
“7-bit Command”
Reserved 7-bit Commands (By I2C Specification - NXP specification # UM10204, Ver. 03 16 January 2007)
“0000 011”b - Reset and write programmable part of slave address by hardware
“0000 010”b - Write programmable part of slave address by hardware
“0000 000”b - NOT Allowed
The Following is a “Hardware General Call” Format
Second Byte
S 0 0 0 0
0 0 0 0 A
General Call Address
FIGURE 5-10:
DS25154A-page 32
X X X X X X
“7-bit Command”
n occurrences of (Data + A / A)
X
1
A X X X X X X X X
A P
This indicates a “Hardware General Call”.
MCP47A1 will ignore this byte and
all following bytes (and A), until
a Stop bit (P) is encountered.
General Call Formats.
 2012 Microchip Technology Inc.
MCP47A1
5.3
Serial Commands
The MCP47A1 devices support two serial commands.
These commands are:
• Write Operation
• Read Operations
The I2C command formats have been defined to
support the SMBus version 2.0 Write Byte/Word
Protocol formats and Read Byte/Word Protocol
formats. The SMBus specification that defines this
operation is Section 5 of the Version 2.0 document
(August 3, 2000).
This protocol format may be convenient for customers
using library routines for the I2C bus, where all they
need to do is specify the command (read, write, ...) with
the Device Address, the Register Address, and the
Data.
5.3.1
WRITE OPERATION
The write operation requires the START condition,
Control Byte, Acknowledge, Command Code,
Acknowledge, Data Byte, Acknowledge and STOP (or
RESTART) condition. The Control (Slave Address)
Byte requires the R/W bit equal to a logic zero (R/W =
“0”) to generate a write sequence. The MCP47A1 is
responsible for generating the Acknowledge (A) bits.
Data is written to the MCP47A1 after every byte
transfer (during the A bit). If a STOP or RESTART
condition is generated during a data transfer (before
the A bit), the data will not be written to MCP47A1.
Data bytes may be written after each Acknowledge.
The command is terminated once a Stop (P) condition
occurs. Refer to Figure 5-11 for the single byte write
sequence and Figure 5-12 for the generic (multi-byte)
write sequence. For a single byte write, the master
sends a STOP or RESTART condition after the 1st data
byte is sent.
5.3.2
READ OPERATIONS
The read operation requires the START condition,
Control Byte, Acknowledge, Command Code,
Acknowledge, Restart Condition, Control Byte,
Acknowledge, Data Byte, the master generating the
A and STOP (or RESTART) condition. The first Control
Byte requires the R/W bit equal to a logic zero (R/W =
“0”) to write the Command Code, while the second
Control Byte requires the R/W bit equal to a logic one
(R/W = “1”) to generate a read sequence. The
MCP47A1 will A the Slave Address Byte and A all the
Data Bytes. The I2C Master will A the Slave Address
Byte and the last Data Byte. If there are multiple Data
Bytes, the I2C Master will A all Data Bytes except the
last Data Byte (which it will A).
The MCP47A1 maintains control of the SDA signal until
all data bits have been clocked out.
The command is terminated once a Stop (P) or Restart
(S) condition occurs. Refer to Figure 5-14 for the read
command sequence. For a single read, the master
sends a STOP or RESTART condition after the 1st data
byte (and A bit) is sent from the slave.
The MSb of each Data Byte is always a “0”, since the
wiper register is only 7-bits wide.
Figure 5-15 shows the I2C read communication
behavior of the Master Device and the MCP47A1
device and the resultant I2C bus values.
Note:
A command code with a non-zero value
will cause the data not to be read from the
wiper register
The MSb of each Data Byte is a don’t care, since the
wiper register is only 7-bits wide.
The command is terminated once a Stop (P) or Restart
(S) condition occurs.
Figure 5-13 shows the I2C write communication
behavior of the Master Device and the MCP47A1
device and the resultant I2C bus values.
Note:
A command code with a non-zero value
will cause the data not to be written to the
wiper register
 2012 Microchip Technology Inc.
DS25154A-page 33
MCP47A1
Fixed
Address
S 0 1 0 1
1
Read/Write bit (“0” = Write)
1 0
0 A
0 0
Slave Address Byte (1)
0 0
0
0
0 0
STOP bit
A X D6 D5 D4 D3 D2 D1 D0 A P
Command Code
Data Byte
Legend
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
R/W = Read/Write bit
D6:D0 = Data bits
Note 1: Example using Slave Address Option A0 (5Ch).
FIGURE 5-11:
I2C Single Byte Write Command Format.
Fixed
Address
S 0 1 0 1
1
Read/Write bit (“0” = Write)
1 1
0 A
Slave Address Byte (1)
0 0
0 0
0
0
0 0
Command Code
A X D6 D5 D4 D3 D2 D1 D0 A
Data Byte
STOP bit
X D6 D5 D4 D3 D2 D1 D0 A X D6 D5 D4 D3 D2 D1 D0 A P
Data Byte
Data Byte
Legend
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
R/W = Read/Write bit
D6:D0 = Data bits
Note 1: Example using Slave Address Option A0 (5Ch).
FIGURE 5-12:
DS25154A-page 34
I2C Write Command Format.
 2012 Microchip Technology Inc.
MCP47A1
Write 1 Byte with Command Code = 00h
S Slave Address
Master
R A
/ C
W K Command Code
A
C
K P
S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 d d d d d d d 1 P
MCP47A1
I2C Bus
A
C
K Data Byte
0
0
0
S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 d d d d d d d 0 P
Write 2 Byte with Command Code = 00h
S Slave Address
Master
A
C
K Data Byte
0
0
0
S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 d d d d d d d 0
Data Byte
Master
A
C
K P
0 d d d d d d d 1 P
MCP47A1
0
I2C Bus
FIGURE 5-13:
A
C
K
S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 d d d d d d d 1
MCP47A1
I2C Bus
R A
/ C
W K Command Code
0 d d d d d d d 0 P
I2C Write Communication Behavior.
 2012 Microchip Technology Inc.
DS25154A-page 35
MCP47A1
Read/Write bit (“0” = Write)
S 0 1
0
1
1
1 0 0 A
0
0
Slave Address Byte (3)
0 0
0
0
0 0 A
Command Code
STOP bit
Read/Write bit (“1” = Read)
S 0 1
0 1
1
1
0 1 A
0 D6 D5 D4 D3 D2 D1 D0 A(2) P
Slave Address Byte (3)
Legend
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
R/W = Read/Write bit
D6:D0 = Data bits
Data Byte
Note 1:
Master Device is responsible for ACK / NACK signal. If a NACK signal occurs, the MCP47A1 will abort this transfer
and release the bus.
2:
The Master Device will Not ACK, and the MCP47A1 will release the bus so the Master Device can generate a Stop or
Repeated Start condition.
3:
Example using Slave Address Option A0 (5Ch).
2
FIGURE 5-14:
I C Read Command Format.
Read 1 Byte with Command Code = 00h
S Slave Address
Master
R A
/ C
W K Command Code
R A
/ C
WK
S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 S 0 1 0 1 1 1 0 1 1
MCP47A1
I2C Bus
A
C R
K S Slave Address
0
0
0
S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 S 0 1 0 1 1 1 0 1 0
Data Byte
Master
A
C
K P
1 P
MCP47A1
0 d d d d d d d 1
I2C Bus
0 d d d d d d d 1 P
Read 2 Byte with Command Code = 00h
S Slave Address
Master
MCP47A1
I2C Bus
R A
/ C
W K Command Code
A
C R
K S Slave Address
R A
/ C
WK
S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 S 0 1 0 1 1 1 0 1 1
0
0
0
S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 S 0 1 0 1 1 1 0 1 0
Data Byte
Master
A
C
K Data Byte
A
C
K P
0
1 P
MCP47A1
0 d d d d d d d 1 0 d d d d d d d 1
I2C Bus
0 d d d d d d d 0 0 d d d d d d d 1 P
FIGURE 5-15:
DS25154A-page 36
I2C Read Communication Behavior.
 2012 Microchip Technology Inc.
MCP47A1
6.0
RESISTOR NETWORK
The Resistor Network is made up of an RAB resistor
ladder. The RAB resistor has a typical resistance of
20 k. Figure 6-1 shows a block diagram for the
resistor network and output buffer. The resistance from
the VREF pin to ground is referred to as RVREF.
The 7-bit I2C Data Byte (00h - 7Fh) is decoded to the 6bit wiper value (00h - 40h). Section 6.3 describes the
Serial Shift buffer to Wiper register decoding.
6.1
RVREF Resistance
RVREF resistance is the resistance from the VREF pin to
ground and is the RAB resistances. Equation 6-1 shows
how to calculate RVREF.
6.1.1
VREF PIN CURRENT (IVREF)
The current into the VREF pin is dependent on the voltage on the VREF pin (VREF) and the RVREF resistance.
The VREF pin’s voltage source current capability should
support a resistive load that is the minimum RVREF
resistance.
EQUATION 6-1:
RVREF =
CALCULATING RVREF
(VREF)
(IVREF)
VREF is the voltage on the VREF pin.
IVREF is the current into the VREF pin.
6.2
RAB Resistor Ladder
The RAB resistor ladder is a digital potentiometer in a
voltage divider configuration. The RAB resistor ladder
has 64 RS resistors in series. This resistor ladder has
65 wiper taps which allow wiper connectivity to the
bottom (terminal B), Zero-Scale, and the top (terminal
A), Full-Scale, of the resistor ladder (see Figure 6-1).
With an even number of RS resistors in the RAB ladder,
when the wiper is at the Mid-Scale value, VOUT equals
VREF / 2. The RAB resistance also includes the RFS and
RZS resistances (see Section 6.2.2). The RAB (and RS)
resistance has small variations over voltage and
temperature. The typical RAB resistance is 10k .
6.2.1
THE WIPER
The value in the volatile wiper register selects which
analog switch to close, connecting the W terminal to
the selected node of the resistor ladder. The Wiper register value is derived from the Serial Shift Register
value (see Section 6.3).
Any variation of the wiper resistance does not effect the
voltage at the W terminal, and therefore the input of the
output buffer.
6.2.2
RFS AND RZS RESISTORS
The RFS and RZS resistances are artifacts of the RAB
resistor implementation. These resistors are included
in the block diagram to help better model the actual
device operation. Equation 6-2 shows how to estimate
the RS, RFS, and RZS resistances, based on the
measured voltages of VREF, VFS, and VZS and the
measured current IVREF.
EQUATION 6-2:
RFS =
RZS =
RS =
ESTIMATING RS, RFS,
AND RZS
VREF
IVREF
VZS
IVREF
VS
IVREF
Where:
( VFS - VZS )
VS =
64
VFS is the VOUT voltage when the wiper code is at
full-scale.
VZS is the VOUT voltage when the wiper code is at
zero-scale.
 2012 Microchip Technology Inc.
DS25154A-page 37
MCP47A1
VREF
A
RFS
N = 64
(40h)
RS
64 * RS
RAB / RVREF
RS
N = 63
(3Fh)
N = 62
(3Eh)
RS
RW (1)
RW (1)
RW (1)
W
+
Op Amp
N=1
(01h)
RS
N=0
(00h)
RW (1)
RW (1)
Analog
Mux
RZS
B
VOUT
Output Buffer
(Section 7.0)
Wiper Value
Resistor Network (Section 6.0)
Note 1: The wiper resistance is tap dependent. That is, each tap selection resistance has a
small variation.
FIGURE 6-1:
DS25154A-page 38
Resistor Network and Output Buffer Block Diagram.
 2012 Microchip Technology Inc.
MCP47A1
6.3
Serial Buffer to Wiper Register
Decode
The I2C’s Data Byte is 8-bits, where only the lower 7bits are implemented. This register is called the Serial
Shift Register (SSR). The Wiper register supports
addressing of 65 taps (6-bit resolution). Table 6-1
shows the decoding of the Serial Shift Register to the
Wiper Register value.
Note 1: The I2C Write and Read commands
access the value in the Serial Shift Register (SSR).
2: The MSb of the I2C Data Byte is ignored
and not loaded into the SSR. A write of
C0h, will result in the same VOUT voltage
as a write of 40h (mid-scale). A subsequent read command (of the SSR) will
result in a value of 40h.
3: The 7-bit SSR value is decoded to a 6-bit
(65 taps) value that controls the wiper’s
position.
TABLE 6-1:
I2C Write
Data
00h
01h or 81h
02h or 82h
SERIAL SHIFT REGISTER
VALUE TO WIPER VALUE
Wiper
Comment
SSR(1)
Value(2)
00h
01h
02h
:
20h
00h
Wiper Register at
Zero Scale,
VOUT = VSS
01h
02h
:
20h
:
Mid-Scale (POR
value),
VOUT = (1/2) * VREF
:
:
:
3Eh or BEh 3Eh
3Eh
Wiper Register =
SSR - 20h
3Fh or BFh
3Fh
3Fh
Wiper Register =
SSR - 20h
40h - 7Fh or 40h 40h
Wiper Register at
C0h - FFh
7Fh
Full Scale,
VOUT = VREF
Note 1: The Serial Shift Register (SSR) is 7-bits
wide and holds the value written from the
I2C Write command. An I2C Read command will read the value in this register.
20h or A0h
6.4
Resistor Variations
(Voltage and Temperature)
The RAB resistors are implemented to have minimal
variations (by design). Any variations should occur
uniformly on all the resistor elements, so the resistor’s
elements will track each other over temperature and
process variations.
The variation of the resistive elements over the operating voltage range is also minimal. Therefore the VREF
resistance (RVREF) of the device has minimal variation
due to operating voltage.
Since the VOUT pin’s voltage is ratiometric, and the
resistive elements change uniformly over temperature,
process, and operating voltage variations. Minimal
variation should be seen on the VOUT pin’s voltage.
6.5
POR Value
A POR/BOR event will load the volatile Serial Shift
Register (and therefore Wiper register) with the default
value. Table 6-2 shows the default values offered.
TABLE 6-2:
Device
MCP47A1
POR/BOR SETTINGS
Setting
Mid-scale
Register Value (1)
SSR
Wiper
20h or A0h
20h
Note 1: Custom POR/BOR Wiper Setting options
are available; contact the local Microchip
Sales Office for additional information.
Custom options have NRE and minimum
volume requirements.
2: The Wiper value is the value that controls
the resistor ladder’s wiper position.
 2012 Microchip Technology Inc.
DS25154A-page 39
MCP47A1
NOTES:
DS25154A-page 40
 2012 Microchip Technology Inc.
MCP47A1
7.0
OUTPUT BUFFER
7.1.1
As the device powers up, the VOUT pin will float to an
unknown value. When the device’s VDD is above the
transistor threshold voltage of the device, the output
will start being pulled low. After the VDD is above the
POR/BOR trip point (VBOR/VPOR), the resistor network’s wiper will be loaded with the POR value (20h,
which is midscale). The output voltage of the buffer
(VOUT) may not be within specification until the device
VDD is at 2.7V. The outputs’ slew rate and settling time
must also be taken into account.
OUTPUT VOLTAGE
The volatile DAC Register’s value controls the analog
VOUT voltage. The volatile Wiper Register’s value is
unsigned binary. The formula for the output voltage is
given in Equation 7-1.
EQUATION 7-1:
CALCULATING OUTPUT
VOLTAGE (VOUT)
VOUT = VZS + (N * VS)
When RFS = RZS = 0 : VZS = 0V
7.1
Output Buffer / VOUT Operation
The DAC output is buffered with a low power and
precision output amplifier (op amp). This amplifier
provides a rail-to-rail output with low offset voltage and
low noise. The amplifier’s output can drive the resistive
and capacitive loads without oscillation. The amplifier
provides a maximum load current which is enough for
most programmable voltage reference applications.
Figure 7-1 shows a block diagram.
Note 1: The load resistance must stay higher than
5 k for the stable and expected analog
output (to meet electrical specifications).
Refer to:
•
•
Section 1.0 “Electrical Characteristics” for the specifications of
the output amplifier.
Section 7.3 “Driving Resistive
and Capacitive Loads” for additional design information.
VFS = VREF
VZS is the VOUT voltage when the wiper code = 00h.
N = wiper code = 0 to 64;
The Serial Shift Register’s value will be latched on the
falling edge of the acknowledge pulse of the write
command’s last byte. Then the VOUT voltage will start
driving to the new value.
The following events update the analog voltage output
(VOUT):
• Power-On-Reset.
• Falling edge of the acknowledge pulse of the last
write command byte.
7.1.2
STEP VOLTAGE (VS)
The Step voltage is dependent on the device resolution
(64 RS) and the output voltage range (VZS to VFS).
Equation 7-2 shows the calculation for the step resistance.
EQUATION 7-2:
Gain =1x
VS =
VW
FIGURE 7-1:
Diagram.
Op
Amp
VOUT
Output Buffer Block
 2012 Microchip Technology Inc.
VS CALCULATION
(VFS - VZS)
64
VFS is the VOUT voltage when the wiper code is at
full-scale.
VZS is the VOUT voltage when the wiper code is at
zero-scale.
Table 7-1 shows the calculated VOUT voltages for the
given volatile Wiper Register value. These calculations
are based on different VREF voltage values (1.5V, 3.3V,
and 5.0V) with an assumption that RFS = RZS = 0 .
DS25154A-page 41
MCP47A1
TABLE 7-1:
THEORETICAL DAC OUTPUT VALUES
VOUT ( 1)
Wiper Value
Hex
Dec
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Note 1:
Ratio
0.0000
0.0156
0.0313
0.0469
0.0625
0.0781
0.0938
0.1094
0.1250
0.1406
0.1563
0.1719
0.1875
0.2031
0.2188
0.2344
0.2500
0.2656
0.2813
0.2969
0.3125
0.3281
0.3438
0.3594
0.3750
0.3906
0.4063
0.4219
0.4375
0.4531
0.4688
0.4844
VOUT ( 1)
Wiper Value
VREF
1.5
3.3
5.0
Hex
Dec
0.0000
0.0234
0.0469
0.0703
0.0938
0.1172
0.1406
0.1641
0.1875
0.2109
0.2344
0.2578
0.2813
0.3047
0.3281
0.3516
0.3575
0.3984
0.4219
0.4453
0.4688
0.4922
0.5156
0.5391
0.5625
0.5859
0.6094
0.6328
0.6563
0.6797
0.7031
0.7266
0.0000
0.0516
0.1031
0.1547
0.2063
0.2578
0.3094
0.3609
0.4125
0.4641
0.5156
0.5672
0.6188
0.6703
0.7219
0.7734
0.8250
0.8766
0.9281
0.9797
1.0313
1.0828
1.1344
1.1859
1.2375
1.2891
1.3406
1.3922
1.4438
1.4953
1.5469
1.5984
0.0000
0.0781
0.1563
0.2344
0.3125
0.3906
0.4688
0.5469
0.6250
0.7031
0.7813
0.8594
0.9375
1.0156
1.0938
1.1719
1.2500
1.3281
1.4063
1.4844
1.5625
1.6406
1.7188
1.7969
1.8750
1.9531
2.0313
2.1094
2.1875
2.2656
2.3438
2.4219
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Ratio
0.5000
0.5156
0.5313
0.5469
0.5625
0.5781
0.5938
0.6094
0.6250
0.6406
0.6563
0.6719
0.6875
0.7031
0.7188
0.7344
0.7500
0.7656
0.7813
0.7969
0.8125
0.8281
0.8438
0.8594
0.8750
0.8906
0.9063
0.9219
0.9375
0.9531
0.9688
0.9844
1.0000
VREF
1.5
0.7500
0.7734
0.7969
0.8203
0.8438
0.8672
0.8906
0.9141
0.9375
0.9609
0.9844
1.0078
1.0313
1.0547
1.0781
1.1016
1.1250
1.1484
1.1719
1.1953
1.2188
1.2422
1.2656
1.2891
1.3125
1.3359
1.3594
1.3828
1.4063
1.4297
1.4531
1.4766
1.5000
3.3
1.6500
1.7016
1.7531
1.8047
1.8563
1.9078
1.9594
2.0109
2.0625
2.1141
2.1656
2.2172
2.2688
2.3203
2.3719
2.4234
2.4750
2.5266
2.5781
2.6297
2.6813
2.7328
2.7844
2.8359
2.8875
2.9391
2.9906
3.0422
3.0938
3.1453
3.1969
3.2484
3.3000
5.0
2.5000
2.5781
2.6563
2.7344
2.8125
2.8906
2.9688
3.0469
3.1250
3.2031
3.2813
3.3594
3.4375
3.5156
3.5938
3.6719
3.7500
3.8281
3.9063
3.9844
4.0625
4.1406
4.2188
4.2969
4.3750
4.4531
4.5313
4.6094
4.6875
4.7656
4.8438
4.9219
5.0000
VOUT voltages based on RFS and RZS = 0 .
DS25154A-page 42
 2012 Microchip Technology Inc.
MCP47A1
7.1.3
AMPLIFIER INPUT VOLTAGE (VW)
To ensure that the amplifier is operating in its linear
range, the voltage (VW) into the output amplifier’s input
has requirements that must be met.
For device VDD voltages  2.7V, the amplifier is in the
linear region for all VREF voltages ( 1.0V) and DAC
register codes.
For device VDD voltages < 2.7V, there will be a voltage
where the amplifier output is no longer linear with the
amplifier input voltage (VW). This is shown in Figure 220, where VDD = 1.8V and the VREF = 1.6V. Higher
DAC register codes are the first to encounter the
nonlinearity of the output buffer. The nonlinearity is also
influenced by the temperature of operation.
Figure 7-2 shows the trend of the amplifier linearity
based on the device VDD / VREF voltages and the input
voltage to the amplifier. The trend will also be affected
by device temperature. VNL is the voltage where the
amplifier’s output becomes nonlinear. While the VW
voltage is less than the VNL voltage, the amplifier’s output is linear. Once the device VDD has been lowered to
where the amplifier’s nonlinear range increases, the
two methods to keep VW < VNL are:
1.
2.
Figure 7-3 shows the equations for solving for VOUT
voltage, the VREF voltage, or the maximum DAC
Register code, based on knowing the requirements for
two of these variables. For VDD voltages below the
specified analog performance voltage (2.7V), the
calibration of the device could be done to ensure VOUT
voltage is not driven into the output amplifier nonlinear
region via the DAC Register value / VREF voltage.
Using the measured VNL voltage as the VOUT voltage
will allow you to balance your selection of the VREF
voltage and maximum DAC Code. The DAC Register
code of 64 is the full-scale code.
VOUT = VREF *
VREF =
DAC Code =
DAC Code
64
64 * VOUT
DAC Code
64 * VOUT
VREF
FIGURE 7-3:
Solving for VOUT, VREF, or
DAC Register Code.
Lower the VREF voltage
Decrease the DAC Register code
Both methods reduce the maximum usable output
voltage.
VDD /
VREF
VDD = 5.5V
VDD = 1.8V
VW
Ideal
Actual
(Based on device
VDD and temperature)
VDD / VREF
0
VOUT
FIGURE 7-2:
Amplifier Input (VW) to
Amplifier Output (VOUT) General Characteristics
(VREF = VDD).
 2012 Microchip Technology Inc.
DS25154A-page 43
MCP47A1
7.2
Output Slew Rate
Figure 7-4 shows an example of the slew rate of the
VOUT pin. The slew rate can be affected by the
characteristics of the circuit connected to the VOUT pin.
VOUT(B)
Wiper = A
Wiper = B
Time
Slew Rate =
FIGURE 7-4:
7.2.1
| VOUT(B) - VOUT(A) |
T
VOUT Pin Slew Rate.
SMALL CAPACITIVE LOAD
With a small capacitive load, the output buffer’s current
is not affected by the capacitive load (CL). But still, the
VOUT pin’s voltage is not a step transition from one
output value (wiper code value) to the next output
value. The change of the VOUT voltage is limited by the
output buffer’s characteristics, so the VOUT pin voltage
will have a slope from the old voltage to the new
voltage. This slope is fixed for the output buffer, and is
referred to as the buffer slew rate (SRBUF).
7.2.2
Driving Resistive and Capacitive
Loads
The VOUT pin can drive up to 100 pF of capacitive load
in parallel with a 5 k resistive load (to meet electrical
specifications). Figure 2-29 shows the VOUT vs.
Resistive Load.
VOUT drops slowly as the load resistance decreases
after about 3.5 k . It is recommended to use a load
with RL greater than 5 k.
VOUT
VOUT(A)
7.3
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response with overshoot and ringing in the step
response. That is, since the VOUT pin’s voltage does
not quickly follow the buffer’s input voltage (due to the
large capacitive load), the output buffer will overshoot
the desired target voltage. Once the driver detects this
overshoot, it compensates by forcing it to a voltage
below the target. This causes voltage ringing on the
VOUT pin.
So, when driving large capacitive loads with the output
buffer, a small series resistor (RISO) at the output (see
Figure 7-5) improves the output buffer’s stability (feedback loop’s phase margin) by making the output load
resistive at higher frequencies. The bandwidth will be
generally lower than the bandwidth with no capacitive
load.
LARGE CAPACITIVE LOAD
With a larger capacitive load, the slew rate is determined by two factors:
VW
• The output buffer’s short circuit current (ISC)
• The VOUT pin’s external load
IOUT cannot exceed the output buffer’s short circuit
current (ISC), which fixes the output buffer slew rate
(SRBUF). The voltage on the capacitive load (CL), VCL,
changes at a rate proportional to IOUT, which fixes a
capacitive load slew rate (SRCL).
So the VCL voltage slew rate is limited to the slower of
the output buffer’s internally set slew rate (SRBUF) and
the capacitive load slew rate (SRCL).
Op
Amp
VOUT
VCL
RISO
RL
CL
FIGURE 7-5:
Circuit to Stabilize Output
Buffer for Large Capacitive Loads (CL).
The RISO resistor value for your circuit needs to be
selected. The resulting frequency response peaking
and step response overshoot for this RISO resistor
value should be verified on the bench. Modify the
RISO’s resistance value until the output characteristics
meet your requirements.
A method to evaluate the system’s performance is to
inject a step voltage on the VREF pin and observe the
VOUT pin’s characteristics.
Note:
DS25154A-page 44
Additional insight into circuit design for
driving capacitive loads can be found in
AN884 “Driving Capacitive Loads With Op
Amps” (DS00884).
 2012 Microchip Technology Inc.
MCP47A1
7.4
Output Errors
TABLE 7-2:
The output error is caused by two factors. These are:
CALCULATION COMPARISON
Example Theoretical
Delta
20,180
—
RVREF
• Characteristics of the Resistor Network
• Characteristics of the Output Buffer
Figure 7-6 shows the components of the error on the
output voltage. The first part of the error is from the
resistor ladder and the RFS and RZS resistances. The
second part is due to the output buffer’s input offset
characteristics.
RFS
100
0
100
RZS
80
0
80
R1 + 64*RS +
R2
30,000
30,180
- 180
R1, RAB, R2
10,000
10,060
- 60
VREF
The RFS and RZS resistances affect the voltage
between VZS and VFS. The larger that RFS + RZS is, the
smaller that the step voltage (VS) will be (from the
theoretical step voltage). The increase in the RFS and
RZS resistances also effects the Full Scale Error (FSE),
Zero Scale Error (ZSE), and gain error.
5.00 V
3.3267 V
3.3333 V
- 6.6 mV
VZS
1.6700 V
1.6667 V
+ 3.3 mV
VS
25.88 mV
26.04 mV
- 0.16 mV
VREF
1.5V
0.9980 V
VFS
Table 7-2 compares theoretical resistor network voltages for full scale and zero scale, where RFS = RZS =
0 , to an example where RFS and RZS and non-zero.
The voltage calculations show cases of VREF = 5.0V
and VREF = 1.5V. Figure 2-34 shows RVREF, RFS, and
RZS resistances VDD.
—
VFS
—
1.0000 V
- 2.0 mV
VZS
0.5010 V
0.5000 V
+ 1.0 mV
VS
7.766 mV
7.813 mV
- 0.047mV
Note 1: RVREF = R1 + RAB + R2 ,
RAB = RFS + 64*RS + RZS.
VS = (VFS - VZS) / 64
So, as the voltage reference (VREF) decreases, the
Step voltages (VS) decrease. At a low VREF voltage, the
step voltage approaches the magnitude of the output
buffer’s input offset voltage (design target of ± 4.5 mV).
So, for low VREF voltages, the output buffer errors have
greater influence on the VOUT voltage.
Theoretical VFS ( VREF )
( RFS  0 )
VREF
RAB = 64*RS
VOUT(FS)
VFS-RL
(Due to RFS  0)
Variations due to Output Buffer’s
Input Offset voltage and Buffer’s Impedance / Load
VZS-RL
(Due to RZS  0)
(VFS - VZS)
Step Voltage (VS) =
VOUT(ZS)
64
* VREF
When:
RFS = RZS = 0 .
VSS
Theoretical VZS ( VSS )
( RZS  0 )
VS = VREF / 64
VREF
5.0V
VS
2.7V
78.125mV 42.19mV
1.8V
1.5V
1.0V
28.13mV 23.44mV 15.63mV
when RFS = RZS = 0 .
FIGURE 7-6:
Output Voltage (VOUT) Error.
 2012 Microchip Technology Inc.
DS25154A-page 45
MCP47A1
NOTES:
DS25154A-page 46
 2012 Microchip Technology Inc.
MCP47A1
8.0
APPLICATIONS EXAMPLES
The MCP47A1 family of devices are general purpose,
single-channel voltage output DACs for various
applications where a precision operation with low
power is needed.
The MCP47A1 devices are rail-to-rail output DACs
designed to operate with a VDD range of 1.8V to 5.5V.
The internal output op amplifier is robust enough to
drive common, small-signal loads directly, thus
eliminating the cost and size of external buffers for
most applications.
Applications generally suited for the devices are:
•
•
•
•
Set Point or Offset Trimming
Sensor Calibration
Portable Instrumentation (Battery Powered)
Motor Control
Application examples include:
DC Set Point or Calibration
Decreasing Output Step Size
Building a “Window” DAC
Selectable Gain and Offset Bipolar Voltage
Output
• Building Programmable Current Source
• Serial Interface Communication Times
• Software I2C Interface Reset Sequence
•
•
•
•
In the design of a system with the MCP47A1 devices,
the following considerations should be taken into
account:
• Power Supply Considerations (Noise)
• PCB Area Requirements
• Connecting to I2C BUS using Pull-Up
Resistors
8.1
DC Set Point or Calibration
A common application for the devices is a
digitally-controlled set point and/or calibration of
variable parameters, such as sensor offset or slope.
For example, the MCP47A1 provides 64 output steps
over the voltage reference range. If voltage reference is
1.65V, the LSb size is 1.65V / 64, or ~ 25.78 mV.
Applications that need accurate detection of an input
threshold event often need several sources of error
eliminated. Use of comparators and operational
amplifiers (op amps) with low offset and gain error can
help achieve the desired accuracy, but in many
applications, the input source variation is beyond the
designer’s control. If the entire system can be
calibrated after assembly in a controlled environment
(like factory test), these sources of error are minimized,
if not entirely eliminated. Figure 8-1 illustrates this
example circuit. Equation 8-1 shows a quick estimation
of the wiper value given the desired voltage trip (VTRIP)
point.
VREF VDD
VCC+
VSENSE
MCP47A1
Comp.
VTRIP
C1
VOUT
VO
VCC–
I2C™
2-wire
FIGURE 8-1:
Calibration.
Set Point or Threshold
EQUATION 8-1:
ESTIMATING THE WIPER
VALUE (N) FROM THE
DESIRED VTRIP
VTRIP = VOUT = (N * VS)
N =
( VTRIP - VREF )
VS
Where: VS = VREF / 64
Note: Calculation does not take into account RFS
and RZS resistors of the DAC’s resistor ladder (see
Section 7.1 for additional information).
 2012 Microchip Technology Inc.
DS25154A-page 47
MCP47A1
8.1.1
DECREASING OUTPUT STEP SIZE
Due to the step voltage and output range of the
MCP47A1, it may be desirable to reduce the step
voltage while also modifying the range of the output. A
common method to achieve this smaller step size is a
voltage divider on the DAC’s output. Figure 8-2
illustrates this concept. Equation 8-2 shows a quick
estimation of the wiper value given the desired voltage
trip (VTRIP) point.
For example, if R1 = R2, then the VTRIP voltage range
is from VSS to 1/2 * VREF. Also at the VTRIP node, the
step voltage is 1/2 the step voltage at the VOUT node.
A bypass capacitor on the output of the voltage divider
plays a critical function in attenuating the output noise
of the DAC and the induced noise from the
environment.
VREF VDD
VCC+
R1
MCP47A1
VOUT
I2C™
2-wire
When calibrating a set point or threshold of a sensor,
typically only a small portion of the DAC output range is
utilized. If the LSb size is adequate enough to meet the
application’s accuracy needs, the unused range is
sacrificed without consequences. If greater accuracy is
needed, then the output range will need to be reduced
to increase the resolution around the desired threshold.
If the threshold is not near VREF, 2 • VREF, or VSS then
creating a “window” around the threshold has several
advantages. One simple method to create this
“window” is to use a voltage divider network with a
pull-up and pull-down resistor. Figure 8-3 and Figure 84 illustrate this concept.
VCC+
Comp.
VTRIP
C1
R3
R1
VTRIP Comp.
MCP47A1
VCC–
VOUT AND VTRIP
ESTIMATIONS
VOUT
VO
VCC–
VCC–
FIGURE 8-3:
DAC.
Single-Supply “Window”
EQUATION 8-3:
VOUT AND VTRIP
ESTIMATIONS
VS = VREF / 64
VOUT = N * VS
R2
VTRIP = VOUT * R + R
1
2
VS = VREF / 64
VOUT * R23 + V23 * R1
R1 + R23
VTRIP =
The VOUT voltage can also be scaled by a
resistor from the VREF pin to the system
reference voltage. Care should be taken
with this implementation due to the ± 20%
variation to the 20k typical resistance
from the VREF pin to ground (RVREF). This
variation in resistance directly effects the
actual VOUT voltage.
C1
R2
I2C™
2-wire
VOUT = N * VS
Note:
VCC+
RSENSE
VREF VDD
FIGURE 8-2:
Example Circuit Of Set Point
or Threshold Calibration.
EQUATION 8-2:
BUILDING A “WINDOW” DAC
VO
VSENSE
R2
8.1.2
Thevenin
Equivalent
R23 =
R2 * R3
R2 + R3
V23 =
(VCC+ * R2) * (VCC- * R3)
R2 + R3
R1
VOUT
VTRIP
R23
V23
DS25154A-page 48
 2012 Microchip Technology Inc.
MCP47A1
8.2
Selectable Gain and Offset Bipolar
Voltage Output
In some applications, control of the output range is
desirable. Figure 8-4 shows a circuit using a DAC
device to achieve a bipolar or single-supply application.
This circuit is typically used for linearizing a sensor
whose slope and offset varies. Depending on the output range desired, resistor R4 or resistor R5 may not be
required. Equation 8-4 shows the calculation of the
Gain, while Equation 8-5 shows the calculation of the
VO voltage.
This circuit can be simplified if the window range is
limited (by removing either the R4 or R5 resistor).
Figure 8-5 shows a circuit for the case where the R5
resistor is removed. Resistors R1 and R2 control the
gain, while resistors R3 and R4 shift the DAC's output
to a selected offset. Equation 8-6 shows the calculation
of the VO voltage.
Note:
R4 can be tied to VDD, instead of VSS, if a
higher offset is desired.
VCC+
VREF VDD
MCP47A1
VO
C1
R4
R2
R1
EQUATION 8-5:
R2
VIN
BIPOLAR “WINDOW” DAC
CALCULATIONS
R1
VOA+ =
V45 =
R45 =
VS =
VO
C1
R4
VCC–
2
I C™
2-wire
R2
VIN
Gain Adjust
(VCC+ • R4) + (VCC- • R5)
R4 + R5
R4 • R5
R4 + R5
(1)
VREF
192
SIMPLIFIED BIPOLAR
“WINDOW” DAC
CALCULATIONS
VO = VOA+ • ( 1 +
VOA+ = VOUT • (
VCC+
VOUT
)
R3 + R45
VREF VDD
VOA+
R1
(VOUT • R45) + (V45 • R3)
EQUATION 8-6:
FIGURE 8-4:
Bipolar Voltage Source with
Selectable Gain and Offset Circuit.
MCP47A1
R1
R2
) - VIN • (
Offset Adjust
Note: Capacitor C1 is recommended (0.1uF typical)
R3
R2
VO = VOA+ • ( 1 +
Note 1: VOUT calculation does not take into
account RFS and RZS resistors of the DAC’s
resistor ladder (see Section 7.1 for additional
information).
VCC–
VCC–
GAIN CALCULATION
If desired Gain = 0.5, and R1 is selected as 20 k
then R2 would need to be 10 k .
VCC+
VOA+
VOUT
I2C™
2-wire
Gain =
VOUT = N * VS
R5
R3
EQUATION 8-4:
R2
R1
) - VIN • (
R4
R3 + R4
R2
R1
)
)
VOUT = N * VS
Note 1: VOUT calculation does not take into
account RFS and RZS resistors of the DAC’s
resistor ladder (see Section 7.1 for additional
information).
R1
Note: Capacitor C1 is recommended (0.1uF typical)
FIGURE 8-5:
Simplified Bipolar Voltage
Source with Selectable Gain and Offset Circuit.
 2012 Microchip Technology Inc.
DS25154A-page 49
MCP47A1
8.3
Building Programmable Current
Source
8.4
Figure 8-6 shows an example of building a
programmable current source using a voltage follower.
The current sensor resistor is used to convert the DAC
voltage output into a digitally-selectable current source.
The smaller RSENSE is, the less power is dissipated
across it. However, this also reduces the resolution that
the current can be controlled.
VDD
(or VREF)
VREF
Serial Interface Communication
Times
Table 8-1 shows time for each I2C serial interface
command as well as the effective data update rate that
can be supported by the digital interface (based on the
two I2C serial interface frequencies). The continuous
write command allows a higher data update frequency
since for the fixed overhead more bytes are
transferred. The Serial Interface performance, along
with the VOUT output performance (such as slew rate),
would be used to determine the application’s volatile
DAC register update rate.
VDD
Load
VCC+
VOUT
IL
MCP47A1
Ib
VCC–
I2C™
2-wire
IL
I b = ----
RSENSE

V OUT

I L = ---------------  ------------R sense  + 1
where Common-Emitter Current Gain
FIGURE 8-6:
Source.
TABLE 8-1:
Digitally-Controlled Current
SERIAL INTERFACE TIMES / FREQUENCIES
Command
Time (µs)
Example
Command
Write Single Byte
Write Continuous Bytes
Read Byte
Note 1:
2:
# of Serial
# Bytes
# of Serial
Interface bits(1) Transferred Interface bits
Effective Data Update
Frequency (kHz) (2)
100kHz
400kHz
100kHz
400kHz
29
1
29
290.0
72.5
3.4
13.8
20 + N * 9
5
65
650.0
162.5
7.7
30.8
39
1
39
390.0
97.5
2.6
10.3
Includes the Start or Stop bits.
This is the command frequency multiplied by the number of bytes transferred.
DS25154A-page 50
 2012 Microchip Technology Inc.
MCP47A1
Software I2C Interface Reset
Sequence
8.5
Note:
This technique should be supported by
any I2C compliant device. The 24XXXX
I2C Serial EEPROM devices support this
technique, which is documented in
AN1028.
At times, it may become necessary to perform a
Software Reset Sequence to ensure the MCP47A1
device is in a correct and known I2C Interface state.
This technique only resets the I2C state machine.
This is useful if the MCP47A1 device powers up in an
incorrect state (due to excessive bus noise, etc), or if
the Master Device is reset during communication.
Figure 8-7 shows the communication sequence to
software reset the device.
S
‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’
Start
bit
FIGURE 8-7:
Format.
S
P
Nine bits of ‘1’
Start bit
Stop bit
Software Reset Sequence
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device. In this mode, the device is monitoring
the data bus in Receive mode and can detect if the
Start bit forces an internal Reset.
 2012 Microchip Technology Inc.
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP47A1 is driving an A bit on
the I2C bus, or is in output mode (from a Read
command) and is driving a data bit of ‘0’ onto the I2C
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP47A1 holding the bus
low. By sending out nine ‘1’ bits, it is ensured that the
device will see an A bit (the Master Device does not
drive the I2C bus low to acknowledge the data sent by
the MCP47A1), which also forces the MCP47A1 to
reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP47A1, AND then as the Master Device returns
to normal operation and issues a Start condition, while
the MCP47A1 is issuing an Acknowledge. In this case,
if the 2nd Start bit is not sent (and the Stop bit was sent)
the MCP47A1 could initiate a write cycle.
Note:
The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP47A1.
The Stop bit terminates the current I2C bus activity. The
MCP47A1 waits to detect the next Start condition.
This sequence does not effect any other I2C devices
which may be on the bus, as they should disregard this
as an invalid command.
DS25154A-page 51
MCP47A1
VDD
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP47A1’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are suggested. Particularly harsh environments may
require shielding of critical signals.
The device’s power sources (VDD and VREF) should be
as clean as possible. Any noise induced on the VDD
and VREF signals can affect the DAC performance.
Separate digital and analog ground planes are
recommended.
VREF
VOUT
FIGURE 8-8:
Connections.
Note:
Breadboards and wire-wrapped boards
are not recommended.
DS25154A-page 52
SDA
VSS
Typical Microcontroller
Optional
Analog
C4
C5
VREF
Optional
Output
C1 C2
C3
VDD 1
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close to the device power pin (VDD) as possible (within
4 mm).
Figure 8-9 shows an example of using two bypass
capacitors (a 10 µF tantalum capacitor and a 0.1 µF
ceramic capacitor) in parallel on the VDD line. These
capacitors should be placed as close to the VDD pin as
possible (within 4 mm). If the application circuit has
separate digital and analog power supplies, the VDD
and VSS pins of the device should reside on the analog
plane.
SCL
VSS
Typical applications require a bypass capacitor in order
to filter high-frequency noise on the VDD and VREF signals. The noise can be induced onto the power supply’s
traces or as a result of changes on the DAC output. The
bypass capacitor helps to minimize the effect of these
noise sources on signal integrity. Figure 8-8 illustrates
an appropriate bypass strategy.
Separate digital and analog ground planes are
recommended. In this case, the VSS pin and the ground
pins of the VDD capacitors should be terminated to the
analog ground plane and VDD and VSS should reside
on the analog plane.
0.1 µF
0.1 µF
PICmicro®
Microcontroller
POWER SUPPLY
CONSIDERATIONS (NOISE)
VDD
MCP47A1
8.6.1
Design Considerations
VSS
2
SCL 3
MCP47A1
8.6
6 VREF
5
4
VDD
VOUT
SDA
R1
R2
To MCU
R1 and R2 are I2C pull-up resistors:
R1 and R2:
5 k - 10 k for fSCL = 100 kHz to 400 kHz
C1:
0.1 µF capacitor
Ceramic
C2:
10 µF capacitor
Tantalum
C3:
~ 0.1 µF
Optional to reduce noise
in VOUT pin.
C4:
0.1 µF capacitor
Ceramic
C5:
10 µF capacitor
Tantalum
FIGURE 8-9:
Example MCP47A1 Circuit.
 2012 Microchip Technology Inc.
MCP47A1
8.6.2
PCB AREA REQUIREMENTS
8.6.4
In some applications, PCB area is a criteria for device
selection. Table 8-2 shows the typical package
dimensions and area for the different package options.
PACKAGE FOOTPRINT (1)
Package
Package Footprint
Pins
Dimensions (mm)
6
Type
Code
Length
Width
Area (mm2)
TABLE 8-2:
SC70
LT
3.10
3.20
9.92
Note 1: Does not include recommended Land
Pattern dimensions. Dimensions are Max
values.
8.6.3
PINOUT/FOOTPRINT
COMPATIBILITY
CONNECTING TO I2C BUS USING
PULL-UP RESISTORS
The SCL and SDA pins of the MCP47A1 devices are
open-drain configurations. These pins require a pull-up
resistor as shown in Figure 8-9.
The pull-up resistor values (R1 and R2) for SCL and
SDA pins depend on the operating speed (standard,
fast, and high speed) and loading capacitance of the
I2C bus line. A higher value of the pull-up resistor
consumes less power, but increases the signal
transition time (higher RC time constant) on the bus
line. Therefore, it can limit the bus operating speed.
The lower resistor value, on the other hand, consumes
higher power, but allows higher operating speed. If the
bus line has higher capacitance due to long metal
traces or multiple device connections to the bus line, a
smaller pull-up resistor is needed to compensate the
long RC time constant. The pull-up resistor is typically
chosen between 1 kand 10 kranges for standard
and fast modes.
The MCP47A1 has a pinout and footprint compatibility
to the MCP40D18 and MCP4018 devices.
8.6.4.1
The MCP40D18/MCP4018’s W pin is analogous to the
MCP47A1’s VOUT pin, while the MCP40D18/
MCP4018’s A pin is analogous to the MCP47A1’s VREF
pin. The MCP40D18 and MCP47A1 share the same
I2C command protocol structure.
The user can test the presence of the device on the I2C
bus line using a simple I2C command. This test can be
achieved by checking an acknowledge response from
the device after sending a read or write command.
Figure 8-10 shows an example with a read command.
The steps are:
a)
b)
c)
Device Connection Test
Set the R/W bit “High” in the device’s address
byte.
Check the ACK bit of the address byte.
If the device acknowledges (ACK = 0) the
command, then the device is connected,
otherwise it is not connected.
Send Stop bit.
Address Byte
SDA
Start
Bit
1
2
3
1
1 0
4
5
6
7
8
1 A2 A1 A0 1
9
ACK
SCL
Stop
Bit
Device Code Address bits
R/W
Device
Response
FIGURE 8-10:
 2012 Microchip Technology Inc.
I2C Bus Connection Test.
DS25154A-page 53
MCP47A1
NOTES:
DS25154A-page 54
 2012 Microchip Technology Inc.
MCP47A1
9.0
DEVELOPMENT SUPPORT
9.1
Evaluation/Demonstration Boards
Note:
The MCP47A1 devices do not have a dedicated
evaluation or demonstration board. Figure 9-1 shows
the component connections to make an evaluation
board using the SC70EV Bond Out PCB (order #
SC70EV). This will allow the MCP47A1’s capabilities to
be evaluated with the PICkit™ Serial Analyzer (order #
DV164122).
0
VDD
Since the SC70EV is a generic board, the
noise immunity of the board will not be
optimal. If noise immunity is a requirement, then a you will need to develop a
custom PCB for the MCP47A1. This PCB
would need to use good layout techniques
to reduce noise coupling.
1.0 µF
VREF (1)
0.1 µF
VSS
VOUT
0
CL & RL
4.7 k
4.7 k
SDA
47A1
SCL
Required components
Recommended components for noise filtering
Optional I2C bus pull up resistors (value may need to be adjusted for your system)
Optional VOUT loading components (stacked), CL = 1 nF max and RL = 5 k max
Note 1: The VREF pin (P8) will need to be connected to a reference voltage source (such as VDD).
FIGURE 9-1:
SC70EV Bond Out PCB – Top Layer and Silk-Screen.
 2012 Microchip Technology Inc.
DS25154A-page 55
MCP47A1
9.2
Technical Documentation
Several additional technical documents are available to
assist you in your design and development. These
technical documents include Application Notes,
Technical Briefs, and Design Guides. Table 9-1 shows
some of these documents.
TABLE 9-1:
Application
Note Number
TECHNICAL DOCUMENTATION
Title
Literature #
AN1326
Using DAC for LDMOS Amplifier Bias Control Applications
DS01326
—
Signal Chain Design Guide
DS21825
—
Analog Solutions for Automotive Applications Design Guide
DS01005
DS25154A-page 56
 2012 Microchip Technology Inc.
MCP47A1
10.0
PACKAGING INFORMATION
10.1
Package Marking Information
6-Lead SC-70
Example
BANN
Part Number
Code
Part Number
Code
MCP47A1T-A0E/LT
BANN
MCP47A1T-A1E/LT
BCNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2012 Microchip Technology Inc.
DS25154A-page 57
MCP47A1
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS25154A-page 58
 2012 Microchip Technology Inc.
MCP47A1
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2012 Microchip Technology Inc.
DS25154A-page 59
MCP47A1
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS25154A-page 60
 2012 Microchip Technology Inc.
MCP47A1
APPENDIX A:
REVISION HISTORY
Revision A (August 2012)
• Original Release of this Document.
 2012 Microchip Technology Inc.
DS25154A-page 61
MCP47A1
APPENDIX B:
B.1
TERMINOLOGY
B.4
Resolution
The resolution is the number of DAC output states that
divide the full-scale range. For the 6-bit DAC, the
resolution is 26, meaning the DAC code ranges from 0
to 64.
B.2
Least Significant Bit (LSb)
Normally, this is thought of as the ideal voltage
difference between two successive codes. This bit has
the smallest value or weight of all bits in the register.
For a given output voltage range, which is typically the
voltage between the Full-Scale voltage and the ZeroScale voltage (VOUT(FS) - VOUT(ZS)), it is divided by the
resolution of the device (Equation B-1).
EQUATION B-1:
LSb VOLTAGE
CALCULATION
Monotonic Operation
Monotonic operation means that the device’s output
voltage (VOUT) increases with every one code step
(LSb) change (from terminal B to terminal A). The VOUT
voltage (VW voltage) is the sum of all the Step voltages
plus the voltage at Zero-Scale (VZS). The Zero-Scale
voltage is dependent on the resistance between the tap
0 point and the B Terminal.
VS64
0x40
0x3E
Wiper Code
EQUATION B-2:
FSE =
Figure 2-12
for
FSE
FULL SCALE ERROR
VIDEAL(@FS) - VOUT(@FS)
VLSb
Where:
FSE is expressed in LSb
VOUT(@FS) is the VOUT voltage when the DAC
register code is at Full-scale.
VIDEAL(@FS) is the ideal output voltage when the
DAC register code is at Full-scale.
Zero-Scale Error (ZSE)
The Zero-Scale Error (ZSE) is the difference between
the ideal and measured VOUT voltage with the Wiper
position set to its minimum (Wiper code = 00h); see
Figure B-3. The Zero-Scale Error is the same as the
Offset Error for this case (Wiper code = 00h).
Equation B-3 shows how to calculate the zero scale
error.
See Figure 2-13 through
characterization graphs.
EQUATION B-3:
ZSE =
Figure 2-16
for
ZSE
ZERO SCALE ERROR
VOUT(@ZS)
VLSb
VS63
0x3F
Where:
FSE is expressed in LSb
VOUT(@ZS) is the VOUT voltage when the DAC
register code is at Zero-scale.
VLSb is the delta voltage of one DAC register code
step (such as code 20h to code 21h).
VS3
0x03
VS1
0x02
VS0
0x01
0x00
See Figure 2-9 through
characterization graphs.
B.5
2N = 64 (MCP47A1)
B.3
The Full-Scale Error (FSE) is the difference between
the ideal and measured DAC output voltage with the
Wiper’s position set to its maximum (Wiper code =
40h); see Figure B-3. Full-scale error may also be
thought of as the sum of the offset error plus gain error.
VLSb is the delta voltage of one DAC register code
step (such as code 20h to code 21h).
VOUT(FS) - VOUT(ZS)
2N
VLSb =
Full-Scale Error (FSE)
VW
n=?
(@ tap) V =
VSn + VZS(@ Tap 0)
W
n=0
Voltage (VW ~= VOUT)
FIGURE B-1:
DS25154A-page 62
VW (VOUT).
 2012 Microchip Technology Inc.
MCP47A1
B.6
Total Unadjusted Error
B.9
The Total Unadjusted Error is the difference between
the ideal and measured VOUT voltage. Typically,
calibration of the output voltage is implemented to
improve system performance.
Total Unadjusted Error can be calculated, see
Equation B-4.
EQUATION B-4:
VIDEAL =
VLSb =
ErrorLSb =
TOTAL UNADJUSTED
ERROR (LSb)
VREF
* DAC Code
The Gain error (see Figure B-3) is the difference
between the actual full-scale output voltage, from the
ideal output voltage of the DAC transfer curve. The
gain error is calculated after nullifying the offset error,
or full scale error minus the offset error.
The gain error indicates how well the slope of the actual
transfer function matches the slope of the ideal transfer
function. The gain error is usually expressed as percent
of full-scale range (% of FSR) or in LSb. The gain error
is not calibrated at the factory and most of the gain error
is contributed by the output buffer (op amp) saturation.
64
VREF
Actual Transfer Function
64
Full-Scale
Error
VIDEAL - VMEASURED
VLSb
Where:
VREF is the voltage on the VREF pin.
VMEASURED is the VOUT voltage for the same DAC
register code as VIDEAL is calculated.
See Figure 2-17 through Figure 2-20
Unadjusted Error characterization graphs.
B.7
Gain Error
for
Gain Error
Analog
Output
Actual Transfer Function
after Offset Error is removed
Total
Ideal Transfer Function
Zero-Scale
Error
Offset Error
The Offset error (see Figure B-2) is the deviation from
zero voltage output when the volatile DAC Register
value = 00h (zero scale voltage). This error affects all
codes by the same amount. The offset error can be
calibrated by software in application circuits.
Actual Transfer Function
0
DAC Input Code
FIGURE B-3:
GAIN ERROR AND FULLSCALE ERROR EXAMPLE.
B.10
Gain Error Drift
The Gain error drift is the variation in gain error due to
a change in ambient temperature. The gain error drift is
typically expressed in ppm/oC.
Analog
Output
Ideal Transfer Function
Offset
Error
(ZSE)
0
FIGURE B-2:
B.8
DAC Input Code
OFFSET ERROR.
Offset Error Drift
The Offset error drift is the variation in offset error due
to a change in ambient temperature. The offset error
drift is typically expressed in ppm/oC.
 2012 Microchip Technology Inc.
DS25154A-page 63
MCP47A1
B.11
Integral Nonlinearity (INL)
The Integral Nonlinearity (INL) error is the maximum
deviation of an actual transfer function from an ideal
transfer function (straight line).
In the MCP47A1, INL is calculated using two end
points. The points used are Zero-Scale (00h) and FullScale - 1 (3Fh). INL can be expressed as a percentage
of full scale range (FSR) or in a fraction of an LSb. INL
is also called relative accuracy. Equation B-5 shows
how to calculate the INL error in LSb and Figure B-4
shows an example of INL accuracy.
INL error for these devices is the maximum deviation
between an actual code transition point and its
corresponding ideal transition point after offset and
gain errors have been removed. These endpoints are
from 0x00 to 0x40 for the MCP47A1. Refer to Figure B4.
Positive INL means higher VOUT voltage than ideal.
Negative INL means lower VOUT voltage than ideal.
See Figure 2-1 through Figure 2-4 for INL characterization graphs.
EQUATION B-5:
INLLSb =
The Differential Nonlinearity (DNL) error (see Figure B5) is the measure of step size between codes in actual
transfer function. The ideal step size between codes is
1 LSb. A DNL error of zero would imply that every code
is exactly 1 LSb wide. If the DNL error is less than
1 LSb, the DAC guarantees monotonic output and no
missing codes. The DNL error between any two
adjacent codes is calculated as follows:
DNL error is the measure of variations in code widths
from the ideal code width. A DNL error of zero would
imply that every code is exactly 1 LSb wide.
See Figure 2-5 through Figure 2-8 for DNL characterization graphs.
EQUATION B-6:
DNLLSb =
VS =
VS
V(Code=63) - VZS
63
110
101
Wiper 100
Code
011
010
V(Code=63) - VZS
63
Ideal transfer
function
Wide code, > 1 LSb
001
Actual
transfer
function
000
Narrow code < 1 LSb
VOUT Output Voltage
100
010
VS
Actual
transfer
function
101
011
VS - ( V(Code = n) - V(Code = n-1) )
111
INL < 0
Wiper
Code
DNL ERROR
VOUT - VIDEAL
111
110
Differential Nonlinearity (DNL)
INL ERROR
VIDEAL = VZS + ( VS * DAC Code )
VS =
B.12
FIGURE B-5:
DNL ACCURACY.
Ideal transfer
function
001
000
INL < 0
VOUT Output Voltage
FIGURE B-4:
DS25154A-page 64
INL ACCURACY.
 2012 Microchip Technology Inc.
MCP47A1
B.13
Settling Time
The Settling time is the time delay required for the VOUT
voltage to settle into its new output value. This time is
measured from the start of code transition, to when the
VOUT voltage is within the specified accuracy.
In the MCP47A1, the settling time is a measure of the
time delay until the VOUT voltage reaches within 0.5
LSb of its final value, when the volatile DAC Register
changes from 40h to 50h.
See Figure 2-36 through Figure 2-39 for Settling Time
oscilloscope screen captures.
B.14
Major-Code Transition Glitch
Major-code transition glitch is the impulse energy
injected into the DAC analog output when the code in
the DAC register changes state. It is normally specified
as the area of the glitch in nV-Sec, and is measured
when the digital code is changed by 1 LSb at the major
carry transition (Example: Wiper code changes from
“011111” to “100000”, or from “100000” to
“011111”).
B.15
Digital Feedthrough
The Digital feedthrough is the glitch that appears at the
analog output caused by coupling from the digital input
pins of the device. The area of the glitch is expressed
in nV-Sec, and is measured with a full scale change
(Example: all 0s to all 1s and vice versa) on the digital
input pins. The digital feedthrough is measured when
the DAC is not being written to the output register.
 2012 Microchip Technology Inc.
B.16
Power-Supply Rejection Ratio
(PSRR)
PSRR indicates how the output of the DAC is affected
by changes in the supply voltage. PSRR is the ratio of
the change in VOUT to a change in VDD for full-scale
output of the DAC. The VOUT is measured while the
VDD is varied +/- 10%, and expressed in dB or µV/V.
B.17
Ratiometric Temperature
Coefficient
The ratiometric temperature coefficient quantifies the
error in the ratio of the resistor setting (Resistance from
VREF pin to Wiper position (RVREF-W) and the Wiper
position to Ground (RW-VSS) due to temperature drift.
This error also includes the drift of the output driver
over temperature. This is typically the critical error
when using a DAC.
See Figure 2-21 through Figure 2-24 for Tempco
characterization graphs.
B.18
Absolute Temperature Coefficient
The absolute temperature coefficient quantifies the
error in the end-to-end output voltage (Nominal output
voltage VOUT) due to temperature drift. For a DAC, this
error is typically not an issue, due to the ratiometric
aspect of the output.
DS25154A-page 65
MCP47A1
NOTES:
DS25154A-page 66
 2012 Microchip Technology Inc.
MCP47A1
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
XXX
/XX
I2C Slave Temperature Package
Address
Range
6-bit Single DAC with I2C interface
(Tape and Reel)
Device:
MCP47A1T:
I2C Slave Address
A0 = 5Ch
A1 = 7Ch
Temperature
Range:
E
Package:
LT = Plastic Small Outline Transistor
(SC70), 6-lead
Examples:
a)
MCP47A1T-A0E/LT:
b)
MCP47A1T-A1E/LT:
6-bit DAC,
SC70-6,
Address = 5Ch,
Tape and Reel
6-bit DAC,
SC70-6,
Address = 7Ch,
Tape and Reel
= -40°C to +125°C
 2012 Microchip Technology Inc.
DS25154A-page 67
MCP47A1
NOTES:
DS25154A-page 68
 2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
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Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
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MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
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Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
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TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated
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All other trademarks mentioned herein are property of their
respective companies.
© 2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-491-6
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2012 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
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are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
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and manufacture of development systems is ISO 9001:2000 certified.
DS25154A-page 69
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