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Designing A High-Frequency, Higher-Power Buck/Boost
Converter for Multi-Cell Input Configurations Using Si9168
Nitin Kalje
The Si9168 is a high-frequency synchronous dc-to-dc
controller designed for higher-power buck or boost conversion
applications in end products running off 2-cell Lithium Ion or
6-cell NiCd or NiMH battery packs. Like the lower-power
Si9167, the Si9168 is capable of operating at up to 2 MHz while
offering the flexibility to choose the optimum drivers for higher
current handling. Its high-frequency operation, strong totem
pole drivers, selectable PWM/PSM operation modes,
integrated under-voltage lockout, and soft-start features make
the Si9168 suitable for 1-A to 10-A conversion applications. A
synchronization feature allows designers to use multiple
Si9168s for a complete power management system, where
size and cost are a prime importance. The Si9168 is designed
to promote efficient use of battery energy and to allow the use
of smaller form factors, thanks to better heat dissipation and
thereby lower operating junction temperature of power
management components.
The features and functions of the Si9168 are described in
detail in the product data sheet. The following section provides
design guidelines for the creation of buck and boost dc-to-dc
converters using the Si9168.
Oscillator Frequency—Choosing ROSC
The oscillator function is implemented with an RS flip-flop, an
inverter, an internal capacitor, a temperature-compensated
current source, and an external resistor. The oscillator ramp is
generated by charging the internal capacitor with a constant
current source. This current is mirrored from the current in
ROSC. The capacitor is charged from 0.5 V to a 1-V threshold,
where it is discharged at a faster rate and the flip-flop is reset
for the next cycle. The lower the value of Rosc, the higher the
charging current and the higher the oscillator frequency. The
oscillator is guaranteed to operate within 20% with a 1%
ROSC for the 200-kHz to 2-MHz frequency range. Refer to
Figure 2 to set the oscillator frequency.
VOUT
5-12.6 V
VIN
5-10 V
VIN
5-10 V
VS
VDD
VDD
DH
VOUT
1.3–10 V
DL
BOOST/BUCK
PGND
PWM/PSM
PWM/PSM
SD
DH
SD
SYNC
VS
DL
BOOST/BUCK PGND
SYNC
ROSC
VOUT
ROSC
VOUT
VREF
FB
VREF
FB
GND
COMP
GND
COMP
Si9168BQ
Buck Mode
Document Number: 71116
25-Feb-00
Si9168BQ
Boost Mode
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VDD
SD
Positive Supply
Reference
1.3 V
Soft-Start
Timer
UVLO
Threshold
Generator
POR
Bias
Generator
System Monitor
VREF
VO
FB
COMP
VS
PWM
Modulator
1.0 V
Ramp
SYNC
PWMIN
0.5 V
DH
PWMIN
Oscillator
PWM/PFM
Select
ROSC
COSC
Drivers
PSMIN
PSMIN
DL
PSM
Modulator
PWM/PSM
PGND
Negative Return
and
Substrate
MODE
GND
FIGURE 1.
Synchronization
Frequency (kHz)
10000
The internal single-shot circuit resets the flip-flop at the
low-going edge of the external synchronization pulse. The
external clock driving the synchronization pin does not get
loaded because of the low input capacitance seen at the
synchronous pin. At every cycle, the low-going external clock
pulse would end the positive ramp and start the next cycle.
Obviously, the external clock frequency needs to be at least
20% higher than the internal oscillator frequency for reliable
synchronization. In addition, the minimum low pulse width
must be 50 nS, while the fall time should not exceed 50 nS
(refer to Figure 3). Figure 4 shows the synchronization
achieved with the external clock running at 1.2 times the
internal oscillator frequency.
1000
100
10
100
1000
ROSC (k)
FIGURE 2. Frequency Setting
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Sync
90%
Oscillator
Single Shot
50%
10%
tLOW 50 nsec
tr, tf 50 nsec
Rosc
FIGURE 3. Synch Pulse Width
Duty Cycle
In PWM mode, the controller operates at a fixed frequency
determined by ROSC. The duty cycle in buck or boost mode is
a function of the difference in the input and output voltage
levels, with the maximum duty ratio at a minimum input line.
At 2 MHz, the duty cycle in buck mode increases gradually up
to a typical level of 80% before jumping instantaneously to
100%. At this time, the upper switch is continuously in the on
state and the converter functions as a low dropout regulator.
The difference between the input and output voltages is equal
to the resistive drop in the upper MOSFET switch, the inductor,
and the printed circuit board (pcb) traces. Since the fixed
break-before-make (BBM) time causes this sudden jump, the
maximum duty cycle the converter can attain before going into
LDO mode will increase at lower switching frequencies.
Ch1 – External Clock (5 V/div)
Ch4 – Drive Output (5 V/div)
FOSC (Internal) – 825 kHz
FCLOCK (External) – 1 MHz
FIGURE 4. Synchronization
Document Number: 71116
25-Feb-00
In boost mode, the same phenomenon is observed when the
duty cycle needs to be reduced down to 0%. The decrease will
be gradual from 75% to 5% and abrupt from 5% to 0%. The
maximum duty cycle in boost mode is limited in order to provide
a fixed off-state time for an inductor to discharge before the
next cycle. Obviously, the maximum achievable duty cycle is
inversely proportional to the switching frequency of the
converter. Refer to Figure 5 and Figure 6 for typical maximum
duty cycles at selected operating frequencies.
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Before selecting the operating frequency, ensure that the
maximum duty cycle required at the minimum input and
maximum output voltages and loads is less than or equal to the
maximum provided by the Si9168. Refer equations 1 and 2 to
calculate the maximum operating duty cycle at the rated load.
D MAX–BUCK +
VOUT_MAX ) V ESR ) VTRACE
V IN_MIN–r DS_p
I OUT
(1)
D MAX – BOOST +
V OUT_MAX ) VESR ) V TRACE ) r DS_p
I IN – VIN_MIN
V OUT_MAX ) IIN ǒr DS_p – r DS_nǓ
(2)
Where,
VESR,VTRACE = dc voltage drop across inductor ESR, PCB
traces (V)
rDS_p, rDS_n = on-resistance of p- or n- channel MOSFET at an
operating junction temperature ()
VIN_MIN, VOUT_MAX = extreme minimum input and maximum
output voltage (V)
IIN, IOUT = input supply and output load currents (A)
MOSFET Selection
Synchronous rectification is used to achieve the best possible
efficiency at moderate to high load currents. A moderate to
high load can be defined as the value at which the total voltage
drop across the synch switch is less than the forward voltage
drop of the Schottky rectifier, which otherwise is used in
asynchronous dc-dc converter. At lower loads, the switching
losses of the synchronous switch can outweigh the dc losses.
Under such circumstances, the Si9168 operates in pulse
skipping mode, where it shuts off the synchronous switch
driver and allows the parallel Schottky diode to conduct.
Selection criteria for the power MOSFET include
on-resistance (rDS(on)), total gate charge(Qg), rise/fall time
(tr /tf) and gate threshold (VGS(th)).
MOSFET on-resistance is inversely proportional to the
number of cells or the channel width, while the gate
capacitance increases with the channel width. The product of
the gate charge and on-resistance is thus a figure of merit, with
a lower number signifying better performance. Vishay offers a
wide range of PWM-optimized MOSFETs using Trench
technology to provide the lowest product of on-resistance
times gate charge. Lower gate charge is needed to reduce CV2
as well as cross conduction losses by reducing the rise and fall
times for a given peak gate current drive. This is critical
especially when operating at a higher input voltages. It is also
recommended to use a high gate threshold (4.5-V) MOSFET
to reduce the CV2 losses further. One good approach to
selecting the appropriate level of on-resistance is to calculate
the dc and total switching power losses at a load level where
the converter will be operating most of the time and then
choose a MOSFET with dc losses equal to or less than 40%
of the total dc and switching losses combined. Refer to
equations 3 through 10 to estimate the MOSFET dc (Pdc) and
switching (Psw) power losses in buck and boost converters at
a nominal line and load.
Max Duty Cycle vs. Frequency (Buck Mode)
Max Duty Cycle vs. Frequency (Boost Mode)
98
74
VIN = 7.2 V
% Max Duty Cycle
% Max Duty Cycle
66
90
86
82
78
58
54
46
600
800 1000 1200 1400 1600 1800 2000 2200
Frequency (kHz)
FIGURE 5.
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62
50
74
70
400
VIN = 7.2 V
70
94
42
400
600
800 1000 1200 1400 1600 1800 2000 2200
Frequency (kHz)
FIGURE 6.
Document Number: 71116
25-Feb-00
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Vishay Siliconix
Once the dc and switching losses are determined, make sure
that the MOSFET package can handle the power dissipation
without the junction temperature going above 125_C in
worst-case line/load and ambient temperature conditions.
Buck Converter
P sw–n + Q gn
V in
Fsw
(3)
Diode Selection
P dc–n + 1.4
I rms–n
P sw–P + Q gp
Vin
P dc–p + 1.4
I rms–p
r DS(on)_n
Fsw )
V in
(4)
I pk
ǒtr ) tfǓ
fsw
(5)
2
(6)
r DS(on)_p
Boost Converter
P sw–n + Q gn
Vo
P dc–n + 1.4
I rms–n
P sw–P + Q gp
Vin
P dc–p + 1.4
I rms–p
f sw )
Vo
ǒt r ) t f Ǔ
I in
(7)
2
r DS(on)_n
fsw
r DS(on)_p
(8)
In PSM operation, the synchronous switch (n-channel in buck
configurations and p-channel in boost configurations) is
switched off to reduce switching losses. The circuit works as
a non-synchronous buck or boost converter, where the diode
freewheels during the off cycle. The operating frequency in
PSM is kept relatively low to reduce switching losses, which
means that dc losses can become significant if the parasitic
body diode is used as a free wheeling diode. The use of a low
forward drop Schottky diode is thus recommended to achieve
good efficiency results in PSM operation.
The other reason the parasitic body diode cannot be used as
a freewheeling diode is its dynamic behavior, the effect of
which becomes more significant during high frequency PWM
operation. Break before make is internally set at about 40 nS,
to avoid any possible shoot-through during the transition time.
The MOSFET internal body diode, being a silicon p-n junction
diode, can experience a significant reverse recovery minority
carrier charge if used to conduct in the forward direction during
the BBM period. The result is almost the same as
shoot-through without BBM and the losses are proportional to
the operating frequency. At the operating frequencies above 1
MHz, these could reduce efficiency significantly.
The Schottky should be chosen such that at a maximum peak
inductor current, the forward drop is less than the forward
breakdown of internal body diode. Figure 7 and 8 shows the
practical waveforms explaining the BBM.
(9)
(10)
Where,
rDS(on)_p, rDS(on)_n = on-resistance of the p- or n-channel
MOSFET at 25_C junction temperature ()
Qgn, Qgp = specified total gate charge for n-, p-channel
switches at VIN (C)
tr , tf = rise/fall time of respective switches (sec)
Irms-n, Irms-p = RMS currents in n-/p-channel switches (A) (see
Appendix)
Document Number: 71116
25-Feb-00
Ch1 – DH (p-channel Drive Output) (5 V/div)
Ch4 – DL (n-channel Drive Output) (5 V/div)
FIGURE 7. Break Before Make (N-channel turn on)
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ESR +
DV ESR
DI
C OUT +
1
DV C
ƪ2F1
1
2
ƫ
DI
2
sw
Output Ripple DVp–p + DV ESR ) DV C
Boost
Refer to Application Note AN715 to determine the required
inductance for a continuous conduction mode boost
conversion.
Ch1 – DH (p-channel Drive Output) (5 V/div)
LMIN +
V2IN
2
Fsw
D
V OUT
h
I OUT_MIN
Ch4 – DL (n-channel Drive Output) (5 V/div)
FIGURE 8. Break Before Make (P-channel turn on)
Inductor and Capacitor
Proper inductor and capacitor values should be chosen to
achieve the specified input/output ripple, for a selected
operating frequency. For a converter, operating at near
one-megahertz switching frequency, the low ESR ceramic
capacitors with values as low as 10 mF are good enough to
achieve 10-mVp-p ripple/noise at the output. The inductor
value determines the ripple current(DI) in the inductor and
output capacitor, for given input/output voltages and switching
frequency. The total peak-to-peak output ripple is contributed
by the DVESR, caused by the ESR of the ouptut capacitor and
the DVC, caused by the loss of charges from the output
capacitor. Equal contribution of ripple voltage from the ESR
and capacitance can be assumed for high frequency
converters using the low ESR ceramic capacitors.
Buck
In a boost converter, entire load current is supplied by the
output capacitor when the main switch is ON. Obviously, the
output capacitance required to support the load is quite high,
especially at a higher duty cycle. Moreover, the output
capacitor ESR needs to be low enough for minimum voltage
drop across it, while supporting the load. Use the following
equation to calculate the output capacitor, for a specified ripple
performance.
DV ESR
DI
I OUT
+
DV C
ESR +
C OUT
D MAX
Fsw
Output Ripple DVp–p + DV ESR ) DV C
Where,
LMIN = inductance required to remain in continuous conduction
mode operation (H)
DMAX = maximum duty cycle at minimum VIN
h = converter efficiency
Refer to equation 11 in appendix to calculate the inductance
value for a DI = 0.2 IOUT. The capacitor value and ESR for
output capacitor are estimated using the following equation:
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IOUT_MIN = minimum output current for continuous conduction
mode (A)
Document Number: 71116
25-Feb-00
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Use the following equations to calculate dc, peak, and rms values of currents in the n- and p-channel switches in buck or boost
converter designs.
Ipk
DI
Idc
IP–CH (Buck), IN–CH (Boost)
Ipk
Idc
IN–CH (Buck), IP–CH (Boost)
DI
IINDUCTOR (Buck, Boost)
FIGURE 9. Current Waveform (Buck, Boost)
Buck Converter
Boost Converter
DI +
DI +
D+
ǒVin * VOǓ
L
D
D+
f sw
1.05 V O
Vin
(2)
V in
f sw
D
L
(4)
1.1 ǒV o * VinǓ
Vo
I dc + Iin * DI
2
I pk + Iin * DI
2
I dc + Io * DI
2
I pk + Io ) DI
2
I rms_p +
ǸǒI
2 dc
) I2 pk ) Idc
I pkǓ 1–D
3
I rms_n +
ǸǒI
2 dc
) I2 pk ) Idc
I pkǓ D
3
Where,
I rms*p +
ǸǒI
2 dc
) I 2pk ) I dc
IpkǓ D
3
I rms*n +
ǸǒI
2 dc
) I 2pk ) I dc
IpkǓ I * D
3
Document Number: 71116
25-Feb-00
(3)
DI = Peak-to-Peak ripple current (A)
D = Converter Duty Cycle
Idc, Ipk = Refer to Figure 9
IL = Inductor Current (A)
Irms – P, Irms – n = RMS current thru P, N-channel switch (A)
fsw = Converter switching frequency (Hz)
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VIN
5-10 V
6, 7
Q1B
5
C1
22 mF
16 V
R1*
51 W
Si6803DQ
R9*
5.6 W
1
2
DL
NC
3 PGND
DH
4
5
6
SD
C5
0.1 mF
VOUT
SYNC
VDD
GND
R5
75 kW
C9
0.1 mF
Q1A
C2
10 mF
10 V
C3
0.1 mF
COM
2, 3
Si6803DQ
13
12
R2
200 W
11
R3
22 kW
10
9
FB
C8
0.1 mF
Si9168BQ
C6
1 nF
4
14
VREF
8 COMP
8.2 kW
15
PWM/PSM
7 R
OSC
R6
16
VS
MODE
8
1
D1
MBR0520T1
R8*
5.6 W
U1
VOUT
3.6 V
1.5 A
L1, 4.7 mH
IHLP2525
COM
C7
56 pF
PWM/PSM to VIN for PWM mode;
PWM/PSM to GND for PSM mode.
C4
330 pF
SD to VIN for converter enable mode;
SD to GND for shutdown mode.
R4
12.4 kW
* = Optional
FIGURE 10. 1.5A Buck Regulator using the Si9168BQ
3
VIN
5-10 V
Q1B
R1*
51 W
R9*
2.7 W
COM
U1
1
2
MODE
VS
DL
NC
3 PGND
DH
4
5
6
SD
PWM/PSM
VOUT
SYNC
VDD
GND
7 R
OSC
R6
C5
0.1 mF
R5
75 kW
8.2 kW
C6
1nF
VREF
8 COMP
FB
Si9168BQ
C7
56 pF
R8*
2.7 W
Si9801DY
7, 8
5, 6
16
15
C9
0.1 mF
2
14
Q1A
VOUT
3.6 V
2.5 A
L1, 1.5 mH
IHLP2525
D1
B130LB
C1
22 mF
16 V
4
C2
22 mF
16 V
C3
0.1 mF
COM
1
Si9801DY
13
12
R2
200 W
11
R3
22 kW
10
9
C8
0.1 mF
PWM/PSM to VIN for PWM mode;
PWM/PSM to GND for PSM mode.
SD to VIN for converter enable mode;
SD to GND for shutdown mode.
C4
330 pF
R4
12.4 kW
* = Optional
FIGURE 11. 2.5A Buck Regulator Using the Si9168BQ
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Document Number: 71116
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VIN
5-7.2 V
C1
10 mF
16 V
COM
R1*
51 W
L1, 1.5 mH
IHLP2525
Q2
Si3442DV
1, 2, 5, 6
Q1
5, 6, 7, 8
SI9803DY
3
D1
B130LB
4
U1
1
MODE
VS
DL
NC
3 PGND
DH
2
4
SD
5
6
PWM/PSM
VOUT
SYNC
VDD
GND
7 R
OSC
C5
0.1 mF
R5
75 kW
R6
8 COMP
4.7 kW
C6
5.6 nF
VOUT
7.2 V
2.5 A
4
VREF
FB
1, 2, 3
16
15
C2
47 mF
16 V
14
C3
0.1 mF
13
COM
12
11
10
9
R2
1 kW
C8
0.1 mF
R3
56.2 kW
C4
560 pF
Si9168BQ
C7
220 pF
R4
12.4 kW
PWM/PSM to VIN for PWM mode;
PWM/PSM to GND for PSM mode.
SD to VIN for converter enable mode;
SD to GND for shutdown mode.
* = Optional
FIGURE 12. 7.2-VO/2.5-A Boost Regulator Application
Document Number: 71116
25-Feb-00
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100
Efficiency —Buck, VOUT = 3.6 V
100
Efficiency —Boost, VOUT = 7.2 V
PSM = 5 VIN
90
PWM = 5 VIN
80
PWM = 7.2 VIN
PSM = 7.2 VIN
PWM = 8.4 VIN
70
Efficiency (%)
Efficiency (%)
90
PWM = 5.4 VIN
PSM = 5.4 VIN
PWM = 6.0 VIN
80
PSM = 6.0 VIN
PSM = 7.0 VIN
PWM = 7.0 VIN
70
PSM = 8.4 VIN
60
50
10
60
100
1000
10000
50
10
100
1000
Load Current (mA)
Load Current (mA)
FIGURE 13. Efficiency—1.5-A Buck Converter
FIGURE 14. Efficiency—Boost Converter
10000
VIN = 7.2 V, VO = 3.6 V
Slew Rate – 1A/msec
Ch 3 – Load (1A/div)
Ch4 – Output (200 mV/div)
VIN = 7.2 V, VO = 3.6 V
Slew Rate – 1A/msec
Ch 3 – Load (100 mA/div)
Ch4 – Output (100 mV/div)
FIGURE 15. Dynamic Load Response Buck Converter – PWM
FIGURE 16. Dynamic Load Response Buck Converter – PSM
VIN = 5.4 V, VOUT = 7.2 V
Slew Rate – 1A/msec
Ch 3 – Load (1A/div)
Ch4 – Output (200 mV/div)
VIN = 5.4 V, VOUT = 7.2 V
Slew Rate – 1A/msec
Ch 3 – Load (200 mA/div)
Ch4 – Output (50 mV/div)
FIGURE 17. Dynamic Load Response Boost Converter – PWM
FIGURE 18. Dynamic Load Response Boost Converter – PSM
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Document Number: 71116
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