CN0276: High Performance, 10-Bit to 16-Bit Resolver-to-Digital Converter PDF

Circuit Note
CN-0276
Devices Connected/Referenced
Circuits from the Lab™ reference circuits are engineered and
tested for quick and easy system integration to help solve today’s
analog, mixed-signal, and RF design challenges. For more
information and/or support, visit www.analog.com/CN0276.
AD2S1210
Variable Resolution, 10-Bit to 16-Bit R/D
Converter with Reference Oscillator
AD8397
Rail-to-Rail, High Output Current Amplifier
ADG1611/
ADG1612
1 Ω On Resistance, ±5 V, +12 V, +5 V, and
+3.3 V Quad SPST Switches
ADM6328
Ultralow Power, 3-Lead, SOT-23
Microprocessor Reset Circuits
ADP7104
20 V, 500 mA, Low Noise, CMOS LDO
AD8692/
AD8694
Low Cost, Low Noise, Dual/Quad CMOS,
RRO Op Amps
High Performance, 10-Bit to 16-Bit Resolver-to-Digital Converter
EVALUATION AND DESIGN SUPPORT
CIRCUIT FUNCTION AND BENEFITS
Circuit Evaluation Boards
CN-0276 Circuit Evaluation Board (EVAL-CN0276-SDPZ)
System Demonstration Platform (EVAL-SDP-CB1Z)
Design and Integration Files
Schematics, Layout Files, Bill of Materials
The circuit shown in Figure 1 is a complete high performance
resolver-to-digital (RDC) circuit that accurately measures
angular position and velocity in automotive, avionics, and
critical industrial applications where high reliability is required
over a wide temperature range.
THIRD ORDER BUTTERWORTH
LOW PASS FILTER
3.3V
5V
5V
5V
VDRIVE DVDD
1
AD8692
2
AVDD
VCC
1
AD8397
2
v(t) = A sinωt
RESOLVER
R1
S2
EXC
1
AD8397
2
1
AD8692
2
θ
v(t)
EXC
S4
R2
AD2S1210
VREFOUT
S1
VREF
2.5V
5V
5V
SIN
S3
1
AD8694
4
1
AD8694
4
1
AD8694
4
1
AD8694
4
1
AD8694
4
1
AD8694
4
1
AD8694
4
1
AD8694
4
SIN
COS
COSLO
DGND
COS
10793-001
SINLO
AGND
THIRD ORDER BUTTERWORTH
LOW PASS FILTER
Figure 1. High Performance Resolver-to-Digital (RDC) Circuit. Simplified Schematic: All Components, Connections, and Decoupling Not Shown
Rev. 0
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engineers. Standard engineering practices have been employed in the design and construction of
each circuit, and their function and performance have been tested and verified in a lab environment at
room temperature. However, you are solely responsible for testing the circuit and determining its
suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices
be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause
whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page)
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CN-0276
Circuit Note
The circuit has an innovative resolver rotor driver circuit that
has two modes of operation: high performance and low power.
In the high performance state, the system operates on a single
12 V supply and can supply 6.4 V rms (18 V p-p) to the resolver.
In the low power state, the system operates on a single 6 V supply
and can supply 3.2 V rms (9.2 V p-p) to the resolver, with less
than 100 mA of current consumption. Active filtering is provided
in both the driver and receiver to minimize the effects of
quantization noise.
quantization noise and distortion. For this reason, the dual
AD8692 op amp is configured as a third-order active Butterworth
filter in order to reduce the noise of the drive signals. Similarly,
the SIN and COS receiver circuits use two quad AD8694 op
amps as an active noise filter.
Signal Chain Design
These factors must be considered in the design of the signal chain:
•
The maximum tracking rate of the RDC is 3125 rps in the 10bit mode (resolution = 21 arc min) and 156.25 rps in the 16-bit
mode (resolution = 19.8 arc sec).
•
•
CIRCUIT DESCRIPTION
•
The signal chain must be designed with care to consider not
only amplitude and frequency, but also phase shift and stability.
In addition, the resolver rotor winding impedance has both a
resistive and an inductive component.
•
•
•
The AD2S1210 RDC excitation signal range is 2 kHz to 20 kHz
and can be set in increments of 250 Hz. Most resolvers are
specified at a fixed excitation fequency, typically around 10 kHz.
Different resolvers have difference phase shifts that must also be
considered in the signal chain design.
The excitation signal is applied to the resolver rotor winding
which is a non-ideal inductor and has a typical resistive component
of 50 Ω to 200 Ω and a reactive component of 0 Ω to 200 Ω. For
example, the impedance of the Tamagawa TS2620N21E11 resolver
used in the circuit of Figure 1 is 70 Ω + j100 Ω at 10 kHz.
Typical excitation voltages can be as high as 20 V p-p (7.1 V rms),
so both maximum current and maximum power consumption
of the resolver driver must be considered. The AD8397 was
chosen for the circuit because of its wide supply range (24 V),
high output current (310 mA peak into 32 Ω on ±12 V supplies),
rail-to-rail output voltage, and low thermal resistance package
(θJA = 47.2°C/W for the 8-pin SOIC EP package).
The excitation output signals from the AD2S1210 are generated
from an internal DAC that produces a certain amount of
•
•
•
•
AD2S1210 excitation signal output range : 3.2 V min,
3.6 V typical, 4.0 V max
AD8692 output voltage range: 0.29 V to 4.6 V with
+5 V supply
AD8397 output voltage range: 0.18 V to 5.87 V with
+6 V supply.
AD8397 output voltage range: 0.35 V to 11.7 V with
+12 V supply
Resolver(TS2620N21E11) transformation ratio: 0.5
Resolver(TS2620N21E11) phase shift: 0°
AD8694 output voltage range: 0.37 V to 4.6 V with +5 V
supply
AD2S1210 input differential p-p signal range (SIN,
COS) is 2.3 V min, 3.15 V typ, 4.0 V max
Resolver output SIN, COS loads should be equal.
Resolver output loads should be at least 20 times the
resolver output impedance
Total signal chain phase shift range: n × 180° − 44° ≤ φ
≤ n × 180° + 44°, n is an integer.
Resolver Excitation Filter and Driver Circuits
The AD2S1210 excitation signal filter and power amplifier circuit
are shown in Figure 2. Careful attention must be paid to the gain
and signal levels at each point in the chain so that the AD8397
output driver does not saturate for the maximum excitation (EXE)
of 4.0 V p-p from the AD2S1210. Note that because the resolver
is driven differentially there are two identical channels as shown
in Figure 2 corresponding to the true and complementary EXE
outputs, respectively.
Rev. 0 | Page 2 of 10
Circuit Note
CN-0276
R1
20kΩ
C1
56pF
+5V
EXE/EXE FROM
AD2S1210
3.2V p-p MIN
3.6V p-p TYP
4.0V p-p MAX
R2
20kΩ
C2
470pF
R3
2
6.2kΩ
VREF 3
2.5V
8
1
U1A
4 AD8692
R4
3
4
TO RESOLVER
ROTOR WINDING, R1
1
820Ω
2
C3
2.2nF
U2A
8 AD8397
VCC
3-POLE BUTTERWORTH FILTER
G = –1, FC = 88kHz
R7
3.3kΩ
R6
750Ω
S1
G = 1.28, VCC = 6V:
4.10V p-p MIN
4.60V p-p TYP
5.12V p-p MAX
C4
2.7nF
G1 = 1.28 (S1 OPEN)
G2 = 2.49 (S1 CLOSED)
10793-002
ADG1612
R5
910Ω
G = 2.49, VCC = 12V:
8.0V p-p MIN
9.0V p-p TYP
10.0V p-p MAX
Figure 2. Excitation Driver and Filter Circuit (All Connections and Decoupling Not Shown)
0
−10
−20
GAIN (dB)
−40
The ADG1612 has a typical on-resistance of less than 1 Ω and is
ideal for the gain switch. However, because the off capacitance of
the switch is typically 72 pF, it should not be connected directly
to the input of the op amp. Note that in the circuit it connects
R6 to ground, and when off, the capacitance has minimum
effect on performance.
The AD8692 is configured as a multiple feedback (MFB) third
order Butterworth lowpass filter. It should have a phase shift in
range of 180° ± 15°. The design procedure is described in
Chapter 8 of Linear Circuit Design Handbook. It is important
to select the proper op amp for this filter, and as a general rule,
the gain-bandwidth product of the op amp should be at least 20
times the –3dB cutoff frequency of the active filter. In this case,
the cutoff frequency is 88 kHz, and the gain-bandwidth product
of the AD8692 is 10 MHz, which is 113 times the cutoff
frequency. Because the AD8692 is a CMOS op amp, the input
bias current is low, and will not significantly affect the dc
characteristics of the filter.The input capacitance is 7.5 pF which
minimizes the effect on cutoff frequency for the capacitor
values chosen in the filter design.
−30
−50
−60
1
10
100
FREQUENCY (kHz)
1000
10793-003
The dc gain of the AD8692 filter circuit is −1. For the high
performance mode (S1 closed), the gain of the AD8397 driver
stage is set for 2.5 (2.49 using actual available resistor values) so
that a 4.0 V p-p EXE input produces a 10 V p-p output when
using a 12 V supply. This allows 1 V headroom from either rail
at the output of the AD8397. For the low power mode (S1 open),
the gain is set for 1.28 so that a 4.0 V p-p EXE input produces a
5.12 V p-p output when using a 6 V supply.
Figure 3. AD8692 Third-Order Low Pass Filter Response
The filter is very effective in reducing the noise on the excitation
signals driving the resolver. Figure 4 shows the 10 kHz EXE
signal measured directly at the output of the AD2S1210. Figure
5 shows the signal measured at C3 (input to AD8397) and the
effectiveness of the filter in removing the noise.
The AD8397 power amplifier can be configured with a gain of
1.28 (low gain mode) and 2.49 (high gain). Phase shift at
10 kHz in the low gain mode is −1.9°, and phase shift in the
high gain mode is −5.2°.
The AD8692 third order low pass filter transfer function is
shown in Figure 3.
Rev. 0 | Page 3 of 10
10793-004
The −3dB cutoff frequency of the filter is 88 kHz, the phase
shift is −13° at 10 kHz, and the dc gain is 1 at 10 kHz.
Figure 4. Signal Measured on the EXC Pin of the AD2S1210
10793-007
Circuit Note
10793-005
CN-0276
Figure 5. Signal Measured on C3 (Input to the AD8397 Driver)
Figure 7. Signal at the Resolver Input When Using High Performance Mode
Resolver SIN/COS Receiver Circuit and Filter
Figures 6 and 7 show the output of the AD8397 measured at
one input to the resolver for the low power mode (Figure 6) and
the high performance mode (Figure 7). Note that these signals
are measured on one side of the resolver input, and the actual
differential signal applied to the resolver has twice the
amplitude.
10793-006
Figure 8 shows the receiver circuit that includes a third order
Butterworth filter and a programmable gain stage. When the
driver circuit is in the high performance mode (VCC = 12 V),
S1 is open, and the overall gain is 0.35. The input drive to the
resolver is 18 V p-p (differential), and the SIN/COS outputs are
9 V p-p differential because the resolver transformation ratio is
0.5. The 9 V p-p differential is 4.5 V p-p single-ended, and
when multiplied by the 0.35 gain factor, yields 1.58 V p-p
(3.16 V p-p differential) which is the optimum input voltage for
the SIN/COS inputs of the AD2S1210. Similarly, in the low
power mode S1 is closed, and the overall gain is 0.7 which again
provides an optimum input signal level for the SIN/COS inputs
of the AD2S1210.
Figure 6. Signal at the Resolver Input When Using Low Power Mode
C1
120pF
R2
22kΩ
S1
R5
VCC = 6V:
2.05V p-p MIN
2.30V p-p TYP
2.56V p-p MAX
2
VCC = 6V:
S1 CLOSED
G1 = –1.63
+5V
8
R6
1
27kΩ
VCC = 12V:
S1 OPEN
G1 = –0.81
+5V
27kΩ
ADG1611
VCC = 12V:
4.0V p-p MIN
4.5V p-p TYP
5.0V p-p MAX
C1
680pF
R4
VREF
2.5V
3
U1A
11 AD8694
R7
1.2kΩ
C3
3.9nF
2
4
1
4.7kΩ
VREF
2.5V
3
TO AD2S1210
SIN/COS INPUTS
U2A
11
AD8694
AD2S1210 SIN/COS INPUT SPECIFICATIONS:
1.15V p-p MIN, 1.6V p-p TYP, 2.0V p-p MAX
(DIFFERENTIAL INPUT IS 2× THESE VALUES)
G = 0.35, VCC = 12V:
1.40V p-p MIN
1.58V p-p TYP
1.75V p-p MAX
G = 0.70, VCC = 6V:
1.43V p-p MIN
1.61V p-p TYP
1.80V p-p MAX
Figure 8. Resolver Receiver Circuit (Simplified Schematic: All Connections and Decoupling Not Shown)
Rev. 0 | Page 4 of 10
10793-008
SIN/COS OUTPUTS
FROM RESOLVER
R1
2kΩ
Circuit Note
CN-0276
In addition to providing the gain adjustment, the receiver
circuit also acts as a third order Butterworth filter with a cutoff
frequency of 63 kHz and a phase shift of −18.6° at 10 kHz.
Figure 12 shows that the total phase shift between the AD2S1210
EXC pin (CH1 yellow) to the SIN input pin (CH2 blue) is approximately 40° which is below the maximum design value of 44°.
The frequency response of the filter in the low gain and high
gain modes is shown in Figure 9 and Figure 10, respectively.
–10
−20
GAIN (dB)
−30
−40
−50
−60
−80
1
10
100
FREQUENCY (kHz)
1000
10793-009
10793-012
−70
Figure 12. Phase Shift Between the AD2S1210 EXC and SIN Pins
Automatic Mode Detection Circuit
Figure 9. Resolver Receiver Circuit, Low Gain Transfer Function
The reset circuit shown in Figure 13 uses the ADM6328 microprocessor reset circuit to determine the gain in the driver and
receiver based on the value of the VCC voltage. The threshold
voltage is set so that if VCC is greater than 11.5 V, the circuit
switches to the high performance mode. If VCC is less than 11.5 V,
the circuit switches to the low power mode.
0
−10
−30
Because the ADM6328 consumes only 1 µA it can use the high
impedance R1/R3 resistor divider output as its power supply
without significant voltage drop.
−40
VCC
−50
+5V
1
10
100
FREQUENCY (kHz)
1000
10793-010
R1
1.6kΩ
−60
R2
100kΩ
OUTPUT
VIN
R3
390Ω
Figure 10. Resolver Receiver Circuit, High Gain Transfer Function
The voltage at the SIN/COS inputs of the AD2S1210 is shown
in Figure 11, and is 1.64 V p-p (3.28 V p-p differential).
3
2
VCC
RESET
ADM6328-22
GND
1
10793-013
GAIN (dB)
−20
Figure 13. VCC Detection Circuit
The ADM6328 has an open drain output, and resistor R2 acts as
a pull-up. This ensures that the output swing is independent of
the VCC input. The ADM6328 power supply voltage is given by:
VIN = VCC ×
R3
R1 + R3
10793-011
The circuit uses the ADM6328-22 that has a typical threshold
voltage of 2.2 V, and a maximum of 2.25 V. The maximum VCC
threshold voltage is 11.5 V, therefore:
Figure 11. Signal on the AD2S1210 Sine and Cosine Inputs
R1
R3
=
11.5 V
– 1 = 4.1
2.25 V
Resistors R1 and R3 are chosen to be 1.6 kΩ and 390 Ω,
respectively, giving a ratio of 4.102.
Rev. 0 | Page 5 of 10
CN-0276
Circuit Note
Because of the relatively low impedance of the resolver and the
large VCC voltage, it is important to know the power dissipated
in the AD8397 driver amplifier to make sure the maximum
power dissipation specification is not exceeded. The maximum
power that can be safely dissipated by the AD8397 is limited by
the associated rise in junction temperature.
these calculations neglect the op amp quiescent current and
consider only the current due to the excitation current. The
equivalent circuit for these calculations is shown in Figure 14.
v(t) = A sinωt
1
AD8397
2
The power dissipated in the amplifier, PAMP, is calculated by
subtracting the power dissipated in the load, PLOAD, from the
power supplied by the power supply PSUPPLY:
i1(t)
–VCC/2
–VCC/2
i1(t)
IPEAK
0
0
i2(t)
Figure 14. Equivalent Circuit for Calculating Power Supply Current
The peak current from the supply is:
I PEAK =
A
|Z |
I AVG =
The equivalent load impedance of the resolver rotor winding is
equal to:
I PEAK
π
=
A
π |Z |
Because this current must be supplied by each rail,
Z = R + jXL, where XL = ωL
The magnitude of the impedance is:
R2 + X L
PSUPPLY = 2 × VCC × I AVG =
2 × VCC × A
2
v(t) = A sinωt
The rms voltage applied to Z is
PAMP = PSUPPLY – PLOAD =
2 × VCC × A
V = A/√2
The rms current through Z is given by:
4 × VCC × A – πA 2 ×
PAMP =
V
|Z |
I=
(A/ 2 )
P LOAD = V × I cos θ =
π |Z|
A2 ×
–
R
|Z|
2|Z |
R
|Z |
2π | Z |
When using Tamagawa TS2620N21E11 resolver, the impedance
is 70 Ω+j100 Ω at 10 kHz. In the high performance state (VCC
= 12 V, A = 10 V), the AD8397 power dissipation is 390 mW
using the derived equation.
|Z|
R
A2 ×
π |Z |
We can now calculate PAMP:
The signal applied to the rotor winding is
I=
1
AD8397
2
XL
Because the signal applied to the load is a sine wave, each
supply must supply a half-wave rectified sine wave current to
the load. The average current is equal to IPEAK/π.
PAMP = PSUPPLY − PLOAD
| Z |=
R
i2(t)
The junction temperature rise can be calculated from the
ambient temperature (TA), the package thermal resistance (θJA),
and the amplifier power dissipation (PAMP):
The circuit uses the AD8397ARDZ that is housed in an 8-pin
SOIC package with exposed pad (EP), and θJA = 47.2°C/W.
i2(t)
i1(t)
The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 150°C. Temporarily
exceeding this limit may cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package.
T J = T A + P AMP × θ JA
VCC/2
VCC/2
10793-014
Resolver Driver Power Amplifier Power Dissipation
The thermal resistance to ambient, θJA, is 47.2°C/W for the
AD8397 (EP package), and therefore the junction temperature
rise above ambient is 47.2°C/W × 0.39W = 18.4°.
|Z|
2|Z |
Where cosθ = power factor = R
|Z |
The power supplied by the power supplies is calculated by first
calculating the average current from the supplies. Note that
Rev. 0 | Page 6 of 10
Circuit Note
CN-0276
Power Supplies
10000
9000
8000
7000
OCCURRENCES
The entire circuit operates on either an external VCC of +6 V or
+12 V, depending on the mode. The 5 V supply for the circuits
is developed using a 5 V, 500 mA ADP7104-5 low dropout
regulator (LDO). A 3.3 V ADP7104-3.3 is used to develop the
3.3 V supply. Details of the power circuits can be found in the
complete schematic included in the CN0276 Design Support
Package (www.analog.com/CN0276-DesignSupport).
5000
4000
3000
PCB Design and Layout Considerations
2000
Even at the lower frequencies associated with the RDC circuits,
poor layout can lead to poor performance. For instance,
although the resolver operates with a 10 kHz excitation signal,
the AD2S1210 operates on an 8.192 MHz clock; therefore it
must be treated as a high speed device with respect to layout,
grounding, and decoupling. Tutorials MT-031 and MT-101
cover these topics in detail.
A good method to measure the overall system noise in the circuit is
to apply a fixed position to the resolver and generate a histogram of
the output codes. This test should be performed with the hysteresis
function disabled. The following Figures show the AD2S1210
output histogram of codes for the 10-bit, 12-bit, 14-bit, and 16bit angular accuracy modes. In each case, the full 16-bits of the
RDC are used in generating the histogram, and the circuit is
placed in the high performance mode with VCC = +12 V.
10000
58C7
58C8
58C9
58CA
58CB
AD2S1210 OUTPUT CODE
10793-016
0
Figure 16. Histogram of Output Codes, 10,000 Samples, Hysteresis
Disabled,12-Bit Angular Accuracy Mode, 16-Bit ADC Resolution
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
16A0
16A1
16A2
16A3
16A4
AD2S1210 OUTPUT CODE
10793-017
System Performance Results
1000
OCCURRENCES
A design support package is available for the CN-0276, including
complete schematic, PADs and Gerber layout files, and bill of
materials. This is located at http://www.analog.com/CN0276DesignSupport.
Figure 17. Histogram of Output Codes, 10,000 Samples, Hysteresis Disabled,
14-Bit Angular Accuracy Mode, 16-Bit ADC Resolution
9000
10000
8000
9000
7000
8000
6000
7000
OCCURRENCES
5000
4000
3000
2000
6000
5000
4000
3000
1000
58C4
58C5
58C6
58C7
58C8
AD2S1210 OUTPUT CODE
10793-015
2000
0
1000
0
55CD
Figure 15. Histogram of Output Codes, 10,000 Samples, Hysteresis
Disabled,10-Bit Angular Accuracy Mode, 16-Bit ADC Resolution
55CE
55CF
55D0
55D1
AD2S1210 OUTPUT CODE
10793-018
OCCURRENCES
6000
Figure 18. Histogram of Output Codes, 10,000 Samples, Hysteresis
Disabled,16-Bit Angular Accuracy Mode, 16-Bit ADC Resolution
The histograms show that the AD2S1210 with a low pass filter
on the driver and receiver circuit can be achieve high angular
resolution in all modes.
Rev. 0 | Page 7 of 10
CN-0276
Circuit Note
COMMON VARIATIONS
CIRCUIT EVALUATION AND TEST
The CN-0276 circuit can used for various types of resolver. For
the best performance, the designer should adjust the passive
components appropriately. The basic principles in adapting the
circuit to different resolvers are:
This circuit uses the EVAL-CN0276-SDPZ circuit board and the
EVAL-SDP-CB1Z SDP-B system demonstration platform
controller board. The two boards have 120-pin mating
connectors, allowing for the quick setup and evaluation of the
performance of the circuit. The EVAL-CN0276-SDPZ contains
the circuit to be evaluated, and the EVAL-SDP-CB1Z (SDP-B)
is used with the CN-0276 Evaluation Software to exchange the
data from the EVAL-CN0276-SDPZ.
2.
3.
Ensure that each amplifier output remains within the
allowable voltage range.
Ensure that none of the components are subjected to
overvoltage. For example, I the resolver output voltage
is too high for the ADG1611 switch, a resistor can be
added in series with the input to the circuit shown in
Figure 8.
Ensure that the total signal chain phase shift remains
within the range: n × 180° − 44° ≤ φ ≤ n × 180° + 44°,
where n is an integer.
Equipment Needed
The following equipment is needed:
•
•
•
•
•
•
•
In some applications, a capacitor is added in parallel with the
primary winding of the resolver, and the value chosen so that it
resonates with the resolver inductance at the frequency of
operation. This makes the load appear resistive. For example,
the resolver used in the circuit has a reactance of 100 Ω at
10 kHz, corresponding to an inductor value of 1.6 mH. A
160 nF capacitor placed in parallel with the primary causes the
load to be approximately 70 Ω, the real part of the impedance.
A PC with a USB port and Windows® 7 or later
The EVAL-CN0276-SDPZ circuit board
The EVAL-SDP-CB1Z SDP-B controller board
The CN-0276 Evaluation Software
A 6 V/1 A bench supply
A 12 V/1 A bench supply
Tamagawa TS2620N21E11 Resolver
Getting Started
Load the evaluation software by placing the CN-0276
Evaluation Software into the CD drive of the PC. Using My
Computer, locate the drive that contains the evaluation
software. Further details regarding the software operation can
be found in the CN0276 Software User Guide.
However, at higher frequencies that are still within the bandwidth
of the op amp, the op amp may oscillate because of the
capacitive load. The op amp must be carefully compensated in
this application so that it maintains stability over its entire
bandwidth.
Functional Block Diagram
A functional block diagram of the test setup is shown in Figure 19.
6V/1A
OR
12V/1A
COM
1
USB
J4
6
TS2620N21E11
+12V OR +6V
2
θ
PC
J3
J1
120
CON A
EVAL-CN0276-SDPZ BOARD
Figure 19. Functional Diagram of Test Setup
Rev. 0 | Page 8 of 10
EVAL-SDP-CB1Z
SDP-B BOARD
10793-019
1.
Circuit Note
CN-0276
Setup
Connect the 120-pin connector on the EVAL-CN0276-SDPZ
circuit board to the CON A connector on the EVAL-SDP-CB1Z
controller board (SDP-B). Use nylon hardware to firmly secure
the two boards, using the holes provided at the ends of the 120pin connectors. With power to the supply off, connect a 6 V or
12 V power supply to the VCC and GND pins on the board.
Connect the USB cable supplied with the SDP-B board to the
USB port on the PC. Do not connect the USB cable to the MiniUSB connector on the SDP-B board at this time. Connect the
resolver TS2620N21E11 to the J3 of EVAL-CN0276-SDPZ
circuit board.
Test
When USB communications are established, the EVAL-SDPCB1Z can send, receive, and capture parallel data from the
EVAL-CN0276-SDPZ.
10793-021
Apply power to the 6 V or 12 V supply connected to the EVALCN0276-SDPZ. Launch the evaluation software and connect
the USB cable from the PC to the mini-USB connector on the
EVAL-SDP-CB1Z.
Figure 21. Photo of EVAL-CN0276-SDPZ PCB
Connectivity for Prototype Development
Figure 20 shows a screen shot of the software output display
when using the circuit to measure position and velocity.
Figure 21 shows a photo of the EVAL-CN0276-SDPZ evaluation
board.
Information and details regarding test setup and calibration,
and how to use the evaluation software for data capture can be
found in the CN-0276 Software User Guide.
The EVAL-CN0276-SDPZ evaluation board is designed to use
the EVAL-SDP-CB1Z SDP-B board; however, any
microprocessor can be used to interface to the SPI port of the
AD2S1210 (the user should set SOE pin low to active SPI
interface). In order for another controller to be used with the
EVAL-CN0276-SDPZ evaluation board, software must be
developed by a third party.
10793-020
There are existing interposer boards that can be used to
interface to the Altera and Xilinx field programmable gate
arrays (FPGAs). The BeMicro SDK board from Altera can be
used with the BeMicro SDK/SDP interposer using Nios Drivers.
Any Xilinx evaluation board that features the FMC connector
can be used with the FMC-SDP Interposer board.
Figure 20. Screenshot of Software Output Window
Rev. 0 | Page 9 of 10
CN-0276
Circuit Note
LEARN MORE
Data Sheets and Evaluation Boards
CN-0276 Design Support Package:
http://www.analog.com/CN0276-DesignSupport
CN-0276 Circuit Evaluation Board (EVAL-CN0276-SDPZ)
Mark Thomas, Dynamic Characteristics of Tracking Converters,
Application Note AN-264, Analog Devices.
AD2S1210 Data Sheet
System Demonstration Platform (EVAL-SDP-CB1Z)
John Gasking, Resolver-to-Digital Conversion, Application Note
AN-263, Analog Devices.
Dennis Fu, Digital Resolver Integration, Application Note AN234, Analog Devices.
Dennis Fu, Circuit Applications of the AD2S90 Resolver-toDigital Converter, Application Note AN-230, Analog
Devices.
MT-030 Tutorial, Resolver-to-Digital Converters, Analog
Devices.
AD8397 Data Sheet
ADG1611/ADG1612 Data Sheet
ADM6328 Data Sheet
ADP7104 Data Sheet
AD8692/AD8694 Data Sheet
REVISION HISTORY
11/13—Revision 0: Initial Version
MT-031 Tutorial, Grounding Techniques, Analog Devices.
MT-101 Tutorial, Decoupling Techniques, Analog Devices.
(Continued from first page) Circuits from the Lab circuits are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you
may use the Circuits from the Lab circuits in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by
application or use of the Circuits from the Lab circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the Lab circuits are supplied
"as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular
purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. Analog Devices
reserves the right to change any Circuits from the Lab circuits at any time without notice but is under no obligation to do so.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
CN10793-0-11/13(0)
Rev. 0 | Page 10 of 10
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