AN-1063 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Oversampling Technique to Improve ADXL345 Output Resolution by Tomoaki Tsuzuki and Christopher Fisher INTRODUCTION ADXL345 IMPLEMENTATION The Analog Devices, Inc., ADXL345 is a 3-axis accelerometer with a digital interface and a built-in analog-to-digital converter (ADC). With a high resolution of 3.9 mg/LSB in all g-ranges (±2 g, ±4 g, ±8 g, and ±16 g), the resolution of the ADXL345 is suitable for most applications. In applications where greater resolution is required, oversampling techniques can be used to improve the resolution of the ADXL345. This application note explains how to increase the resolution of the ADXL345 by leveraging the first-in, first-out (FIFO) buffer of the ADXL345. ADXL345 is a 3-axis accelerometer with a digital interface. It has a 13-bit ADC and a 32-level FIFO (for each axis) output buffer with a powerful interrupt system. It can generate an interrupt signal when a specified number of data sets is stored in the FIFO. The output data rate of the ADC can be configured by writing to the appropriate register. OVERSAMPLING THEORY Output Data Rate Setting Analog-to-digital conversion is the first step to the digital signal processing of the acceleration signal from an accelerometer. For an accelerometer with an analog output, the accelerometer signal is digitized by an external ADC, where the resolution depends on the application requirements and designer selection. In contrast to an analog output accelerometer, a digital output accelerometer like the ADXL345 has an internal ADC, and its resolution is fixed by sensor design. When using the oversampling technique with the ADXL345, the user must first determine the oversampling factor. Select an oversampling factor based on the level of the resolution improvement required. Choose an oversampling factor of 4 when the required resolution improvement is 1 LSB and an oversampling factor of 16 when 2 LSBs of resolution are required. Next, the output data rate of the sensor can be selected based on the required data rate. For example, if the data rate required from the application is 12.5 Hz and the required improvement in resolution is 1 LSB, the ADXL345 data rate should be configured as 50 Hz (12.5 Hz × 4). The output data rate can be set in the BW_RATE register. Oversampling is a technique to increase resolution by sampling the analog signal at a much higher rate than that required when not using oversampling. In conjunction with digital filtering and decimation, it results in a higher resolution. Even with digital output accelerometers in which the ADC resolution is fixed, acceleration can be measured at a higher resolution by using this technique. The theory behind oversampling is that the total quantization noise in an oversampled signal is the same as the signal sampled at the original rate, but the total quantization noise is spread over a wider bandwidth. The oversampled signal can then be filtered at the original bandwidth and the total quantization noise is reduced. With the total noise reduced, the signal can be resolved into finer steps while maintaining the original signal-to-noise ratio (SNR). Table 1 shows the oversampling factor, which defines how the output data rate of the ADXL345 is higher compared to the data rate required from an application. For a 2×, or 1 LSB, improvement in resolution, the oversampling factor must be 4. A 4×, or 2 LSB, improvement in resolution requires an oversampling factor of 16. The ADXL345 is suitable for this oversampling technique because of the FIFO configurable output data rate and flexible interrupt system. FIFO Setting The FIFO should be configured to generate an interrupt when the number of data sets stored in the FIFO equals the value of the oversampling factor. This type of interrupt is called watermark (WM) interrupt. The FIFO should also be used either in FIFO mode or in stream mode (see the ADXL345 data sheet for more information). The amount of data required to generate WM and FIFO operation can be set by the FIFO_CTL register. The INT_ENABLE register enables the WM interrupt. The INT_MAP register controls if the WM interrupt is assigned to the INT1 or INT2 pin. For additional details beyond what is covered in this application note on using the FIFO, refer to the ADXL345 data sheet or AN-1025 Application Note, Utilization of the First In, First Out (FIFO) Buffer in Analog Devices, Inc. Digital Accelerometers. Data Format Table 1. Oversampling Factor and Resolution Improvements Oversampling Factor 4 16 SNR Improvement 6 12 Resolution Improvement in Number of Bits 1.0 2.0 ADXL345 data can be read by accessing data registers that consist of two bytes for each axis. When using right-justified data with ±2 g mode, acceleration data is represented as shown in Table 2 (10-bit data field with extended sign bits represented in twos complement format). Rev. 0 | Page 1 of 2 AN-1063 Application Note Data Processing in Microprocessor NOISE CONSIDERATION The ADXL345 is configured to generate the WM interrupt at the required data rate from the application. The processor reads multiple data based on the oversampling factor corresponding to the WM interrupt. Data must then be digitally filtered and decimated to acquire the required resolution data. A simple and effective way to filter and decimate is by averaging. Add all the data read from the ADXL345 and divide it by 2 or 4 for an improvement of 1 LSB or 2 LSBs, respectively, in resolution. (Divide the data by 2 when oversampling factor is 4, and divide the data by 4 when oversampling factor is 16.) Oversampling only improves quantization error of the ADC. The output noise of ADXL345 can be calculated from the noise density and the performance of the digital filter used for oversampling. The noise of the ADXL345 is white noise, which has the same amount of power at every frequency. Output noise can be calculated using the following equation: Output noise (g rms) = √(Noise Density (g/√(Hz))2 × Filter gain (dB) × پf (Hz)) In the case of a moving average (16× oversampling for an improvement of 2 LSBs) where the output data rate is 100 Hz, Figure 1 shows the gain response of the filter. Figure 2 shows the timing diagram of oversampling when the output data rate of the ADXL345 is 200 Hz and the watermark interrupt is generated after 16 sets of data are stored in the FIFO. Table 3 shows an example of how data is treated in the processor with an oversampling factor of 4. 0 –10 Data1 is 256 LSBs at 3.9 mg/LSB resolution. It is interpreted as 1000 mg. Data2 is 257 LSBs and ~1004 mg, and so on. When all four data are summed and divided by 2, the data becomes 512 LSBs, which is interpreted as 1000 mg at 1.95 mg/LSB resolution. This shows a 1 LSB improvement in resolution. GAIN (dB) –20 –30 –40 Care should be taken that the ADXL345 data is twos complement. When dividing negative numbers, shifting data may cause the result to not be consistent with actual data. –60 0 5 10 15 30 20 25 FREQUENCY (Hz) 35 40 50 45 08859-001 –50 Figure 1. Gain Response of Moving Average Filter Table 2. Data Format of ADXL345 (±2 g, Right Justified)1 D7 Sign 1 D6 Sign 0x33 (X)/0x35 (Y)/0x37 (Z) D5 D4 D3 D2 Sign Sign Sign Sign D1 D9 D0 D8 D7 D7 D6 D6 0x32 (X)/0x34 (Y)/0x36 (Z) D5 D4 D3 D2 D5 D4 D3 D2 D1 D1 D0 D0 The DATA_FORMAT register is used to configure the ADXL345 dynamic range and data format. 80ms (16 SETS OF DATA × 5ms) ADXL345 DATA ACQUISITION DATA ACQUISITION (16 SETS OF DATA) DATA ACQUISITION (16 SETS OF DATA) MICROCONTROLLER OPERATION READ DATA DATA PROCESS READ DATA 08859-002 VOLTAGE OF INTx PIN WITH WM DATA PROCESS Figure 2. Timing Diagram of Oversampling Technique Table 3. Data Format in Oversampling Process Data1 (256 LSBs) Data2 (257 LSBs) Data3 (255 LSBs) Data4 (256 LSBs) Sum of Data1 to Data4 Divide the Sum by 2 (512 LSBs) D15 0 0 0 0 0 0 D14 0 0 0 0 0 0 D13 0 0 0 0 0 0 D12 0 0 0 0 0 0 D11 0 0 0 0 0 0 D10 0 0 0 0 1 0 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN08859-0-3/10(0) Rev. 0 | Page 2 of 2 D9 0 0 0 0 0 1 D8 1 1 0 1 0 0 D7 0 0 1 0 0 0 D6 0 0 1 0 0 0 D5 0 0 1 0 0 0 D4 0 0 1 0 0 0 D3 0 0 1 0 0 0 D2 0 0 1 0 0 0 D1 0 0 1 0 0 0 D0 0 1 1 0 0 0