CY8CKIT-050 PSoC® 5LP Development Kit Guide Doc. # 001-65816 Rev. *G Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): +1.408.943.2600 http://www.cypress.com Copyrights Copyrights © Cypress Semiconductor Corporation, 2011-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. PSoC Creator™ is a trademark, and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Flash Code Protection Cypress products meet the specifications contained in their particular Cypress PSoC datasheets. Cypress believes that its family of PSoC products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as ‘unbreakable’. Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 2 Contents 1. Introduction 1.1 1.2 1.3 1.4 1.5 Kit Contents .................................................................................................................5 PSoC Creator ..............................................................................................................5 Additional Learning Resources....................................................................................6 1.3.1 Beginner Resources.........................................................................................6 1.3.2 Engineers Looking for More .............................................................................6 1.3.3 Learning from Peers.........................................................................................6 1.3.4 More Code Examples.......................................................................................6 Document History ........................................................................................................8 Documentation Conventions .......................................................................................8 2. Getting Started 2.1 2.2 2.3 2.4 2.5 11 Programming PSoC 5LP Device ...............................................................................11 4. Hardware 4.1 4.2 9 DVD Installation ...........................................................................................................9 Install Hardware.........................................................................................................10 Install Software ..........................................................................................................10 Uninstall Software......................................................................................................10 Verify Kit Version .......................................................................................................10 3. Kit Operation 3.1 5 14 System Block Diagram ..............................................................................................14 Functional Description ...............................................................................................15 4.2.1 Power Supply .................................................................................................15 4.2.1.1 Power Supply Jumper Settings........................................................16 4.2.1.2 Grounding Scheme ..........................................................................17 4.2.1.3 Low-Power Functionality..................................................................17 4.2.1.4 AC/DC Adaptor Specifications .........................................................18 4.2.1.5 Battery Specifications ......................................................................18 4.2.2 Programming Interface...................................................................................18 4.2.2.1 Onboard Programming Interface .....................................................19 4.2.2.2 JTAG/SWD Programming................................................................19 4.2.3 USB Communication......................................................................................20 4.2.4 Boost Convertor .............................................................................................21 4.2.5 32-kHz and 24-MHz Crystal ...........................................................................21 4.2.6 Protection Circuit............................................................................................21 4.2.6.1 Functional Description .....................................................................22 4.2.7 PSoC 5LP Development Kit Expansion Ports ................................................23 4.2.7.1 Port D...............................................................................................23 4.2.7.2 Port E ...............................................................................................25 4.2.8 RS-232 Interface ............................................................................................26 CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 3 Contents 4.2.9 Prototyping Area ............................................................................................26 4.2.10 Character LCD ...............................................................................................27 4.2.11 CapSense Sensors ........................................................................................28 5. Code Examples 5.1 5.2 5.3 5.4 5.5 5.6 5.7 A. Appendix A.1 A.2 A.3 A.4 30 Introduction ................................................................................................................30 5.1.1 Programming the Code Examples .................................................................30 Project: VoltageDisplay_SAR_ADC...........................................................................31 5.2.1 Project Description .........................................................................................31 5.2.2 Hardware Connections...................................................................................31 5.2.3 SAR ADC Configuration.................................................................................31 5.2.4 Verify Output ..................................................................................................32 Project: VoltageDisplay_DelSigADC .........................................................................32 5.3.1 Project Description .........................................................................................32 5.3.2 Hardware Connections...................................................................................32 5.3.3 DelSig ADC Configuration..............................................................................33 5.3.4 Verify Output ..................................................................................................34 Project: IntensityLED .................................................................................................35 5.4.1 Project Description .........................................................................................35 5.4.2 Hardware Connections...................................................................................35 5.4.3 Verify Output ..................................................................................................35 Project: LowPowerDemo ...........................................................................................35 5.5.1 Project Description .........................................................................................35 5.5.2 Hardware Connections...................................................................................35 5.5.3 Verify Output ..................................................................................................36 Project: CapSense.....................................................................................................37 5.6.1 Project Description .........................................................................................37 5.6.2 Hardware Connections...................................................................................37 5.6.3 Verify Output ..................................................................................................37 Project: ADC_DAC ....................................................................................................38 5.7.1 Project Description .........................................................................................38 5.7.2 Hardware Connections...................................................................................38 5.7.3 Verify Output ..................................................................................................38 40 Schematic ..................................................................................................................40 Board Layout .............................................................................................................46 A.2.1 PDC-09356 Top .............................................................................................46 A.2.2 PDC-09356 Power .........................................................................................47 A.2.3 PDC-09356 Ground .......................................................................................48 A.2.4 PDC-09356 Bottom ........................................................................................49 Bill of Materials (BOM) ...............................................................................................50 Pin Assignment Table ................................................................................................55 CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 4 1. Introduction Thank you for your interest in the CY8CKIT-050 PSoC® 5LP Development Kit. This kit allows you to develop precision analog and low-power designs using PSoC 5LP. You can design your own projects with PSoC Creator™ or alter the sample projects provided with this kit. The CY8CKIT-050 PSoC 5LP Development Kit is based on the PSoC 5LP family of devices. PSoC 5LP is a Programmable System-on-Chip™ platform for 8-bit, 16-bit, and 32-bit applications. It combines precision analog and digital logic with a high-performance CPU. With PSoC, you can create the exact combination of peripherals and integrated proprietary IP to meet your application requirements. 1.1 Kit Contents The PSoC 5LP Development Kit contains: ■ Development board ■ Kit DVD ■ Quick start guide ■ USB A to mini-B cable ■ 3.3-V LCD module Inspect the contents of the kit; if you find any part missing, contact your nearest Cypress sales office for help. 1.2 PSoC Creator Cypress's PSoC Creator software is a state-of-the-art, easy-to-use integrated development environment (IDE) that introduces a hardware and software design environment based on classic schematic entry and revolutionary embedded design methodology. With PSoC Creator, you can: ■ Create and share user-defined, custom peripherals using hierarchical schematic design. ■ Automatically place and route select components and integrate simple glue logic, normally located in discrete muxes. ■ Trade off hardware and software design considerations allowing you to focus on what matters and getting to market faster. PSoC Creator also enables you to tap into an entire tools ecosystem with integrated compiler tool chains, RTOS solutions, and production programmers to support both PSoC 3 and PSoC 5LP. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 5 Introduction 1.3 Additional Learning Resources Visit http://www.cypress.com/go/psoc5 for additional learning resources in the form of datasheets, application notes, and technical reference manual. 1.3.1 Beginner Resources AN77759 - Getting Started with PSoC 5 PSoC Creator Training 1.3.2 Engineers Looking for More AN54460 - PSoC 3, PSoC 4, and PSoC 5LP Interrupts AN52705 - PSoC 3 and PSoC 5LP - Getting Started with DMA AN52701 - PSoC 3 and PSoC 5LP - Getting Started with Controller Area Network (CAN) AN54439 - PSoC 3 and PSoC 5LP External Crystal Oscillators AN52927 - PSoC 3 and PSoC 5LP - Segment LCD Direct Drive Cypress continually strives to provide the best support. Click here to view a growing list of application notes for PSoC 3, PSoC 4, and PSoC 5LP. 1.3.3 Learning from Peers Cypress Developer Community Forums 1.3.4 More Code Examples PSoC Creator provides several example projects that make code development fast and easy. To access these example projects, click on Find Example Project… under the Example and Kits section in the Start Page of PSoC Creator or navigate to File > Open > Example Project… Figure 1-1. Find Example Project CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 6 Introduction The Find Example Project section has various filters that help you locate the most relevant project. PSoC Creator provides several starter designs. These designs highlight features that are unique to PSoC devices. They allow you to create a design with various components, instead of creating an empty design; the code is also provided. To use a starter design for your project, navigate to File > New > Project and select the design required. Figure 1-2. New Project The example projects and starter designs are designed for the CY8CKIT-001 PSoC Development Kit. However, these projects can be converted for use with the CY8CKIT-030 PSoC 3 Development Kit or CY8CKIT-050 PSoC 5LP Development Kit by following the procedure in the knowledge base article Migrating Project from CY8CKIT-001 to CY8CKIT-030 or CY8CKIT-050. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 7 Introduction 1.4 Document History Revision 1.5 PDF Creation Date Origin of Change Description of Change ** 03/01/2011 PVKV Initial version of kit guide *A 04/28/2011 RKAD Updated Schematic *B 12/15/2011 RKAD Added sections 4.2.1.4 and 4.2.1.5. Added Pin Assignment table in the Appendix. Updated bill of materials. Content updates throughout the document *C 05/15/2012 SASH Updated the Additional Resources section *D 06/18/2012 SASH Updated DVD Installation on page 9. *E 11/09/2012 SASH Updated images and content. *F 07/12/2013 SASH Added another item to the Warnings list in section 4.2.1.1. Updates for PSoC Creator 2.2. *G 08/22/2013 SASH Updated Figure 1-1, Figure 1-2, Figure 2-1, Figure 5-4, and Figure 5-5. Updated Install Software on page 10. Added note in Verify Output on page 35. Updated to PSoC Creator 3.0. Documentation Conventions Table 1-1. Document Conventions for Guides Convention Usage Courier New Displays file locations, user entered text, and source code: C:\ ...cd\icc\ Italics Displays file names and reference documentation: Read about the sourcefile.hex file in the PSoC Designer User Guide. [Bracketed, Bold] Displays keyboard commands in procedures: [Enter] or [Ctrl] [C] File > Open Represents menu paths: File > Open > New Project Bold Displays commands, menu paths, and icon names in procedures: Click the File icon and then click Open. Times New Roman Displays an equation: 2+2=4 Text in gray boxes Describes cautions or unique functionality of the product. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 8 2. Getting Started This chapter describes how to install and configure the PSoC 5LP Development Kit. Kit Operation chapter on page 11 describes the kit operation. It explains how to program a PSoC 5LP device with PSoC Programmer and use the kit with the help of a code example. To reprogram the PSoC device with PSoC Creator, see the installation instructions for PSoC Creator. Hardware chapter on page 14 details the hardware operation. Code Examples chapter on page 30 provides instructions to create a simple code example. The Appendix on page 40 provides the Schematic on page 40 and Bill of Materials (BOM) on page 50 associated with the PSoC 5LP Development Kit. 2.1 DVD Installation Follow these steps to install the PSoC 5LP Development Kit software: 1. Insert the kit DVD into the DVD drive of your PC. The DVD is designed to auto-run and the kit menu appears. Figure 2-1. Kit Menu Note If auto-run does not execute, double-click cyautorun.exe on the root directory of the DVD. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 9 Getting Started Figure 2-2. DVD Root Directory After the installation is complete, the kit contents are available at the following location: <Install_Directory>\Cypress\PSoC 5LP Development Kit\<version> 2.2 Install Hardware No hardware installation is required for this kit. 2.3 Install Software When installing the PSoC 5LP Development Kit, the installer checks if your system has the required software. These include PSoC Creator, PSoC Programmer, Windows Installer, .NET, and Keil Complier. If these applications are not installed, the installer installs them in your PC before installing the kit. If Acrobat Reader application is not installed in your PC, then the installer provides the link to install the same and this does not prevent kit installation. Note that Adobe reader is required to view the kit documents. Install the following software from the kit DVD: 2.4 ■ PSoC Creator 3.0 or later ■ PSoC Programmer 3.19.1 or later Note When installing PSoC Programmer, select Typical on the Installation Type page. ■ Code examples (provided in the Firmware folder) Uninstall Software The software can be uninstalled using one of the following methods: 2.5 ■ Go to Start > Control Panel > Add or Remove Programs; select the Remove button. ■ Go to Start > All Programs > Cypress > Cypress Update Manager > Cypress Update Manager; select the Uninstall button. ■ Insert the installation DVD and click Install PSoC 5LP Development Kit button. In the CyInstaller for PSoC 5LP Development Kit 2.1 window, select Remove from the Installation Type drop-down menu. Follow the instructions to uninstall. Verify Kit Version To know the kit revision, look for the white sticker on the bottom left, on the reverse of the kit box. If the revision reads CY8CKIT-050B, then, you own the latest version. To upgrade CY8CKIT-050/CY8CKIT-050A to CY8CKIT-050B, you can purchase our latest kits at http://www.cypress.com/go/CY8CKIT-050. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 10 3. Kit Operation The code examples in the PSoC 5LP Development Kit help you develop precision analog applications using the PSoC 5LP family of devices. The board also has hooks to enable low-power measurements for low-power application development and evaluation. 3.1 Programming PSoC 5LP Device The default programming interface for the board is a USB-based onboard programming interface. To program the device, plug the USB cable to the programming USB connector J1, as shown in Figure 3-1. Figure 3-1. Connect USB Cable to J1 When plugged in, the board enumerates as DVKProg5. After enumeration, initiate, build, and then program using PSoC Creator. When using onboard programming, it is not necessary to power the board from the 12-V or 9-V DC supply or a battery. You can use the USB power to the programming section. If the board is already powered from another source, plugging in the programming USB does not damage the board. The PSoC 5LP device on the board can also be programmed using a MiniProg3 (CY8CKIT-002). To use MiniProg3 for programming, use the connector J3 on the board, as shown in Figure 3-2. Note The MiniProg3 (CY8CKIT-002) is not part of the PSoC 5LP Development Kit contents. It can be purchased from the Cypress Online Store. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 11 Kit Operation Figure 3-2. Connect MiniProg3 With the MiniProg3, programming is similar to the onboard programmer; however, the setup enumerates as a MiniProg3. The Select Debug Target window may be displayed, as shown in the following figure. Figure 3-3. Select Debug Target Click Port Acquire. The window appears as follows. Click Connect to start programming. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 12 Kit Operation Figure 3-4. Click Connect CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 13 4. 4.1 Hardware System Block Diagram The PSoC 5LP Development Kit has the following sections: ■ Power supply system ■ Programming interface ■ USB communications ■ Boost convertor ■ PSoC 5LP and related circuitry ■ 32-kHz crystal ■ 24-MHz crystal ■ Port E (analog performance port) and port D (CapSense® or generic port) ■ RS-232 communications interface ■ Prototyping area ■ Character LCD interface ■ CapSense buttons and sliders Note P0[2] is connected to the SAR bypass capacitor C40, which can be selected by shorting jumper J43. P0[4] is connected to the SAR bypass capacitor C55, which can be selected by shorting jumper J44. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 14 Hardware Figure 4-1. PSoC 5LP Development Kit Details Communication USB Power Adapter Boost Converter 9-V Battery Input 10-Pin JTAG/SWD/SWO Debug and Prog Header On-board Programming USB 10-Pin MiniTrace Connector 32-kHz Crystal 24-MHz Crystal Port D (CapSense/ Miscellaneous Port) Port E (Analog Port) Reset Button Variable Resistor/ Potentiometer CapSense RS-232 Interface Character LCD Interface 4.2 Functional Description 4.2.1 Power Supply Prototyping Area Switches/LEDs The power supply system on this board is versatile; input supply can be from the following sources: ■ 9-V or 12-V wall wart supply using connector J4 ■ 9-V battery connector using connectors BH1 and BH2 ■ USB power from communications section using connector J2 ■ USB power from the onboard programming section using connector J1 ■ Power from JTAG/SWD programming interface using connector J3 ■ Power through boost convertor that uses the input test points VBAT and GND CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 15 Hardware The board power domain has five rails: ■ Vin rail: This is where the input of the onboard regulators are connected. This domain is powered through protection diodes. ■ 5-V rail: This is the output of the 5-V regulator U2. The rail has a fixed 5-V output regardless of jumper settings. The voltage in this rail can be less than 5 V only when the board is powered by the USB. This 5-V rail powers the circuits that require fixed 5-V supply. ■ 3.3-V rail: This is the output of the 3.3-V regulator U4. This rail remains 3.3 V regardless of jumper settings or power source changes. It powers the circuits requiring fixed 3.3-V supply such as the onboard programming section. ■ Vddd rail: This rail provides power to the digital supply for the PSoC device. It can be derived from either the 5-V or 3.3-V rail. The selection is made using J10 (3-pin jumper). ■ Vdda rail: This rail provides power to the analog supply of the PSoC device. It is the output of a low-noise regulator U1. The regulator is a variable output voltage and can be either 3.3 V or 5 V. This is done by changing the position on J11 (3-pin jumper). The following block diagram shows the structure of the power system on the board. Figure 4-2. Power System Structure USB Programming USB Communication Power 3.3 V 5V Vin 3.3-V Regulator Vddd Selection (J10) 9-V Battery 5V 5-V Regulator 12-V/9-V Wall wart 4.2.1.1 5-V/3.3-V Analog Regulator Vddd Vdda Selection (J11) Vdda Power Supply Jumper Settings Figure 4-3. Jumper Settings CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 16 Hardware Two jumpers govern the power rails on the board. J10 is responsible for the selection of Vddd (digital power) and J11 selects the VADJ of Vdda (analog power). The jumper settings for each power scheme are as follows. Powering Scheme Jumper Settings Vdda = 5 V, Vddd = 5 V J10 in 5-V setting and J11 in 5-V setting. Vdda = 3.3 V, Vddd = 3.3 V J10 in 3.3-V setting and J11 in 3.3-V setting. Vdda = 5 V, Vddd = 3.3 V J10 in 3.3-V setting and J11 in 5-V setting. Vdda = 3.3 V, Vddd = 5 V Can be achieved, but is an invalid condition because the PSoC 5LP silicon performance cannot be guaranteed. Warning: 4.2.1.2 ■ The PSoC device performance is guaranteed when Vdda is greater than or equal to Vddd. Failure to meet this condition can have implications on the silicon performance. ■ When USB power is used, ensure a 3.3-V setting on both analog and digital supplies. This is because the 5-V rail of the USB power is not accurate and is not recommended. ■ If separate analog and digital power supplies are used, the analog supply ramp rate may be slower than that of the digital supply. This may cause I/Os to be in an indeterminate state until the power supplies stabilize. Grounding Scheme The board design considers analog designs as major target applications. Therefore, the grounding scheme in the board is unique to ensure precision analog performance. The board has three types of ground: ■ GND - This is the universal ground where all the regulators are referred. Both Vssd and Vssa connect to this ground through a star connection. ■ Vssd - This is the digital ground and covers the digital circuitry on the board, such as RS-232 and LCD. ■ Vssa - This is the analog ground and covers the grounding for analog circuitry present on the board, such as the reference block. When creating custom circuitry in the prototyping area provided on the board, remember to use the Vssa for the sensitive analog circuits and Vssd for the digital ones. Port E on the board is the designated analog expansion connector. This connector brings out ports 0, 3, and 4, which are the best performing analog ports on PSoC 3 and PSoC 5 devices. Port E has two types of grounds. One is the analog ground (GND_A in the silkscreen, Vssa in the schematic), which connects directly to the analog ground on the board. The other ground, known as GND, is used for the digital and high-current circuitry on the expansion board. This differentiation on the connector grounds helps the expansion board designer to separate the analog and digital ground on any high-precision analog boards being designed for port E. 4.2.1.3 Low-Power Functionality The kit also facilitates application development, which requires low power consumption. Low-power functions require a power measurement capability, also available in this kit. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 17 Hardware The analog supply is connected to the device through the 0- resistor (R23). By removing this resistor and connecting an ammeter in series using the test points, Vdda_p and Vdda, you can measure the analog power used by the system. The digital supply can be monitored by removing the connection on jumper J10 and connecting an ammeter in place of the short. This allows to measure the digital power used by the system. The board provides the ability to measure analog and digital power separately. To measure power at a single point, rather than at analog and digital separately, remove resistor R23 to disconnect the analog regulator from powering the Vdda and short Vdda and Vddd through R30. The net power can now be measured at jumper J10 similar to the digital power measurement. To switch repeatedly between R23 and R30, moving around the 0- resistors can be discomforting. Hence, a J38 (unpopulated) is provided to populate a male 3-pin header and have a shorting jumper in the place of R23/R30. While measuring device power, make the following changes in the board to avoid leakage through other components that are connected to the device power rails. 4.2.1.4 ■ Disconnect the RS-232 power by disconnecting R58. An additional jumper capability is available as J37 if you populate it with a 2-pin male header. ■ Disconnect the potentiometer by disconnecting J30. ■ Ground the boost pins if boost operation is not used by populating R1, R28, and R29. Also make sure R25 and R31 are not populated. AC/DC Adaptor Specifications Use adaptors with the following specifications: ■ Input voltage: 100 to 240 VAC, 50 Hz to 60 Hz, 1A ■ Output voltage: 12 VDC, 1A ■ Power output: 12 W ■ Polarization: Positive center ■ Certification: CE certified Some recommended part numbers include EPSA120100U-P5P-EJ (CUI Inc.) and LTE12W-S2 (Li Tone Electronics Co. Ltd). 4.2.1.5 Battery Specifications Use batteries with the following specifications: ■ Battery size: 6LR61 (9 V) ■ Output voltage: 9 VDC ■ Type: Non-rechargeable alkaline consumer batteries ■ RoHS status: RoHS compliant ■ Lead free status: Pb-free Some recommended part numbers include 6LR61XWA/1SB (Panasonic), MN1604 (Duracell), and 6LR61 (Energizer). 4.2.2 Programming Interface This kit allows programming in two modes: ■ Using the onboard programming interface ■ Using the JTAG/SWD programming interface with a MiniProg3 CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 18 Hardware 4.2.2.1 Onboard Programming Interface The onboard programmer interfaces with your PC through a USB connector, as shown in Figure 4-4. Figure 4-4. Onboard Programming Interface When the USB programming is plugged into the PC, it enumerates as DVKProg5 and you can use the normal programming interface from PSoC Creator to program this board through the onboard programmer. A 0- resistor R9 is provided on the board to disconnect power to the onboard programmer. 4.2.2.2 JTAG/SWD Programming Apart from the onboard programming interface, the board also provides the option of using the MiniProg3. This interface is much faster than the onboard program interface. The JTAG/SWD programming is done through the 10-pin connector, J3. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 19 Hardware Figure 4-5. JTAG/SWD Programming The JTAG/SWD programming using J3 requires the MiniProg3 programmer, which can be purchased from http://www.cypress.com/go/CY8CKIT-002. Note While using MiniProg3, only the Reset mode is supported with this kit. 4.2.3 USB Communication The board has a USB communications interface that uses the connector, as shown in Figure 4-6. The USB connector connects to the D+ and D– lines on the PSoC to enable development of USB applications using the board. This USB interface can also supply power to the board, as discussed in Power Supply on page 15. Figure 4-6. USB Interface CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 20 Hardware 4.2.4 Boost Convertor The PSoC 5LP device has the unique capability of working from a voltage supply as low as 0.5 V. This is possible using the boost convertor. The boost convertor uses an external inductor and a diode. These components are prepopulated on the board. Figure 4-7 shows the boost convertor. To enable the boost convertor functionality, make the following hardware changes on the board. ■ Populate resistors R25, R27 (populated by default), R29, and R31 with 0- resistors. Note See the Bill of Materials (BOM) on page 50 for the manufacturer part number. ■ Ensure that R1 and R28 are not populated After making these changes, you can configure the project to create a boost convertor-based design. The input power supply to the boost convertor must be provided through the test points marked Vbat and GND. Figure 4-7. Boost Converter 4.2.5 32-kHz and 24-MHz Crystal PSoC 5LP has an on-chip real time clock (RTC), which can function in sleep. This requires an external 32-kHz crystal, which is provided on the board to facilitate RTC-based designs. The PSoC 5LP also has an external MHz crystal option in applications where the IMO tolerance is not satisfactory. In these applications, the board has a 24-MHz crystal to provide an accurate main oscillator. 4.2.6 Protection Circuit A reverse-voltage and over-voltage protection circuit is added to the expansion port on the 5-V and 3.3-V lines. The protection circuit consists of two P-channel MOSFET on the power line, allowing the current to flow from input to output depending on the voltages applied at the external board connector. Figure 4-8 and Figure 4-9 are protection circuits placed between EBK and the onboard components on the 5-V and 3.3-V lines. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 21 Hardware Figure 4-8. Schematic for Protection Circuit on 5-V Power Line Figure 4-9. Schematic for Protection Circuit on 3.3-V Power Line 4.2.6.1 Functional Description The protection circuit will protect from a maximum over-voltage or reverse-voltage of 12 V. The cutoff voltage on the 5-V line is 5.7 V and on the 3.3-V line is 3.6 V. This means, if you apply more than this voltage level from the external board connector side, the p-MOS Q5 will turn off, thus protecting PSoC and other onboard components. The current consumption of these protection circuits is less than 6 mA. When voltage from the external connector is between 1.8 V and 3.3 V, the p-MOS Q4 conducts. Because the voltage across R16 is less than the threshold voltage (Vth) of p-MOS Q6, it will turn off and the p-MOS Q5 conducts, allowing voltage supply to the DVK. When the external power supply exceeds 3.3 V, the p-MOS Q5 starts conducting. This eventually turns off p-MOS Q6 at 3.6 V, protecting the DVK from over-voltage. When a reverse voltage is applied across the protection circuit from the external connector side, Q4 P-MOS will turn off, thus protecting the components on the board from reverse voltage. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 22 Hardware If you are using the regulator power supply from the board to power the external modules, both the P-MOS Q4 and Q5 will always be in the On state, allowing the flow of current with a maximum of 22 mV drop across the circuit when the current consumed by the external module is 150 mA. Note The working of protection circuit on the 3.3-V and 5-V lines is as described. For the purpose of explanation, the annotation of 3.3-V protection circuitry (Figure 4-9) is used. 4.2.7 PSoC 5LP Development Kit Expansion Ports The PSoC 5LP Development Kit has two expansion ports, port D and port E, each with their own unique features. 4.2.7.1 Port D This is the miscellaneous port designed to handle CapSense-based application boards and digital application boards. The signal routing to this port adheres to the stringent requirements needed to provide good performance CapSense. This port can also be used for other functions and expansion board kits (EBKs). This port is not designed for precision analog performance. The pins on the port are functionally compatible to port B of the PSoC Development Kit. Any project made to function on port B of the PSoC Development Kit can be easily ported over to port D on this board. A caveat to this is that there is no opamp available on this port; therefore, opamp-based designs are not recommended for use on this port. The following figure shows the pin mapping for the port. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 23 Hardware Figure 4-10. Port D CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 24 Hardware 4.2.7.2 Port E This is the analog port on the kit and has special layout considerations. It also brings out all analog resources such as dedicated opamps to a single connect. Therefore, this port is ideal for precision analog design development. This port is functionally compatible to port A of the PSoC Development Kit and it is easy to port an application developed on port A. This port has two types of grounds, CGND1 and CGND2. The two grounds are connected to the GND on the board, but are provided for expansion boards designed for analog performance. The expansion boards have an analog and digital ground. The two grounds on this port help to keep it distinct even on this board until it reaches the GND plane. Figure 4-11. Port E CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 25 Hardware 4.2.8 RS-232 Interface The board has an RS-232 transceiver for designs using RS-232 (UART). The RS-232 section power can be disconnected through a single resistor R58. This is useful for low-power designs. Figure 4-12. RS-232 Interface 4.2.9 Prototyping Area The prototyping area on the board has two complete ports of the device for simple custom circuit development. The ports in the area are port 0 and port 3, which bring out the four dedicated opamp pins on the device. Therefore, these ports can be used with the prototyping area to create simple yet elegant analog designs. It also brings SIOs such as port 12[4], port 12[5], port 12[6], and port 12[7] and GPIOs such as port P6[0] and port P6[6]. Power and ground connections are available close to the prototyping space for convenience. The area also has four LEDs and two switches for applications development. The two switches on the board are hard-wired to port 15[5] and port 6[1]. Two LEDs out of the four are hard-wired to port 6[2] and port 6[3] and the other two are brought out on pads closer to the prototyping area. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 26 Hardware Figure 4-13. Prototyping Area This area also comprises of a potentiometer to be used for analog system development work. The potentiometer connects from Vdda, which is a noise-free supply and is hence capable of being used for low-noise analog applications. The potentiometer output is available on P6[5] and VR on header P6 in the prototyping area. 4.2.10 Character LCD The kit has a character LCD module, which goes into the character LCD header, P8. The LCD runs on a 3.3-V supply and can function regardless of the voltage on which PSoC is powered. A 0- resistor setting is available on the LCD section (R71/72), making it possible to convert it to a 3.3-V LCD. CAUTION When the resistor is shifted to support a 5-V LCD module, plugging in a 3.3-V LCD module into the board can damage the LCD module. Figure 4-14. Pin 1 Indication CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 27 Hardware Figure 4-15. LCD Connected on P8 Connector 4.2.11 CapSense Sensors The board layout considers the special requirements for CapSense. It has two CapSense buttons and a five-element CapSense slider. The CapSense buttons are connected to pins P5[6] and P5[5]. The slider elements are connected to pins P5[0:4]. The Cmod (modulation capacitor) is connected to pin P6[4] and an optional Rb (bleeder resistor) is available on P15[4]. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 28 Hardware Figure 4-16. CapSense Sensors CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 29 5. 5.1 Code Examples Introduction All the code examples of this kit are for CY8C5868AXI-LP035 device. To access code examples described in this section, open the PSoC Creator Start Page. For additional code examples, visit http://www.cypress.com. Figure 5-1. PSoC Creator Start Page 5.1.1 Programming the Code Examples Follow these steps to open and program code examples: 1. Click on a code example from Kits on the PSoC Creator Start Page. 2. Create a folder in the desired location and click OK. 3. The project opens in PSoC Creator and is saved to that folder. 4. Build the code example to generate the hex file. 5. To program, connect the board to a computer using the USB cable connected to port J1, as described in Onboard Programming Interface on page 19. The board is detected as DVKProg5 6. Click Debug > Program. 7. The programming window opens up. If the silicon is not yet acquired, select the DVKProg5 and click on the Connect button. 8. The silicon is acquired and is shown in a tree structure below the DVKProg5. 9. Click OK to exit the window and start programming. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 30 Code Examples 5.2 Project: VoltageDisplay_SAR_ADC 5.2.1 Project Description This example code measures an analog voltage controlled by the potentiometer. The code uses the internal SAR ADC configured for a 12-bit operation; the ADC range is 0 to Vdda. The results are displayed on the character LCD module. Note The PSoC 5LP Development Kit is factory-programmed with this example. 5.2.2 Hardware Connections The example requires the character LCD on P8. Because it uses the potentiometer, the jumper POT_PWR should be in place. This connects the potentiometer to the Vdda. 5.2.3 SAR ADC Configuration To view or configure the SAR ADC component, double-click the component in the TopDesign.cysch file. Figure 5-2. SAR ADC Configuration The SAR ADC is configured as follows: ■ Free-running mode of operation is selected because the ADC scans only one channel continuously. ■ Conversion rate is set to 100 ksps. The code waits for each sample, processes it, and displays the result on the LCD. ■ Range is set to Vssa to Vdda in single-ended mode because the potentiometer output is a singleended signal that can go from 0 to Vdda. Therefore, at 12-bit resolution, the ADC will resolve in steps of Vdda/212. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 31 Code Examples ■ 5.2.4 Voltage reference should be set to Vdda/2 supply voltage when input range is set to ‘Vssa to Vdda’. It is set to 1.65 V here, because by default, Vdda jumper setting on the board is set to 3.3 V. If J11 is changed to select 5 V, then this parameter should be changed to 2.5 V accordingly. Verify Output Build and program the code example, and reset the device. The LCD shows the voltage reading corresponding to the voltage on the potentiometer. Figure 5-3 demonstrates the functionality. When you turn the potentiometer, the voltage value changes. You can also verify the voltage on the potentiometer using a precision multimeter. Note The potentiometer connects to a differential ADC, which works in single-ended mode. This means the ADC input is measured against internal Vssa. Any offset in the measurement can be positive or negative. This can result in a small offset voltage even when the potentiometer is zero. Figure 5-3. Voltage Display using SAR ADC 5.3 Project: VoltageDisplay_DelSigADC 5.3.1 Project Description This example code measures a simple analog voltage controlled by the potentiometer. The code uses the internal Del-Sig ADC configured for a 20-bit operation; the ADC range is 0 to Vdda. The voltage measurement resolution is in microvolts. The results are displayed on the character LCD module. 5.3.2 Hardware Connections The example requires the character LCD on P8. Because it uses the potentiometer, the jumper POT_PWR should be in place. This connects the potentiometer to the Vdda. Move jumper J10 and J11 to position 2-3, this will set Vdda to 5 V. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 32 Code Examples 5.3.3 DelSig ADC Configuration To view or configure the Delsig ADC component, double-click the component in the TopDesign.cysch file. Figure 5-4. Delta-Sigma ADC Configuration To configure the Del-Sig ADC: ■ Select the continuous mode of operation because the ADC scans only one channel. ■ Set the conversion rate to 187 samples/sec, which is the maximum sample rate possible at 20-bit resolution. ■ Set the range from Vssa to Vdda in single-ended mode because the potentiometer output is a single-ended signal that can go from 0 to Vdda. Therefore, at 20-bit resolution, the ADC will resolve in steps of Vdda/220. Note Internal Vdda/3 reference option is not available in the current PSoC 5LP silicon. In this project, Vdda = 5 V. The project will not work if Vdda = 3.3 V, because it needs Vdda/3 reference for DelSig ADC. To set Vdda to 5 V, in the VoltageDisplay_DelSigADC.cydwr window of PSoC Creator, click on the System tab, go to the Operating Conditions option. Set Vdda to 5 V. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 33 Code Examples Figure 5-5. Operating Conditions Option 5.3.4 Verify Output Build and program the code example, and reset the device. The LCD shows the voltage reading corresponding to the voltage on the potentiometer. Figure 5-6 demonstrates the functionality. When you turn the potentiometer, the voltage value changes. You can also verify the voltage on the potentiometer using a precision multimeter. Notes ■ ■ The potentiometer connects to a differential ADC, which works in single-ended mode. This means the ADC input is measured against internal Vssa. Any offset in the measurement can be positive or negative. This can result in a small offset voltage even when the potentiometer is zero. Move jumper J10 and J11 back to position 1-2 after verifying the output. The LCD displays negative voltages when the POT is at 0th position. Figure 5-6. Voltage Display using Del-Sig ADC CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 34 Code Examples 5.4 Project: IntensityLED 5.4.1 Project Description This example code uses a pulse-width modulator (PWM) to illuminate an LED. When the pulse width of the PWM varies, the LED brightness changes. By continuously varying the pulse width of the PWM, the example code makes an LED go from low brightness to a high brightness and back. 5.4.2 Hardware Connections No hardware connections are required for this project, because all the connections are hard-wired to specific pins on the board. 5.4.3 Verify Output When the example code is built and programmed into the device, reset the device by pressing the Reset button or power cycling the board. The project output is LED3 glowing with a brightness control that changes with time (see Figure 5-7). Note If the CY8CKIT-050 is programmed with any other code example involving LCD display prior to programming the IntensityLED.hex file, the LCD display continues to display the output of previous project as the LCD component is not handled in the IntensityLED project. The LCD display gets cleared by power cycling the board. Figure 5-7. Verify Output - Code Example 5.5 Project: LowPowerDemo 5.5.1 Project Description This code example demonstrates the low-power functionality of PSoC 5LP. The project implements an RTC based code, which goes to sleep and wakes up on the basis of switch inputs. The RTC uses an accurate 32-kHz clock generated using the external crystal provided on the board. When there is a key press, the device is put to sleep while the RTC is kept active. 5.5.2 Hardware Connections The project requires a 3.3 V LCD to view the time display. No extra connections are required for project functionality. To make low-power measurements using this project, implement the changes proposed in Low-Power Functionality on page 17. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 35 Code Examples 5.5.3 Verify Output In normal operation, the project displays the time starting from 00:00:00 when SW2 is pressed. Normal mode is indicated by LED3 in ON state. When you press the SW2 button again, the device is put to sleep. Sleep mode is indicated by LED3 in OFF state. If an ammeter is connected to measure the system current (see Low-Power Functionality on page 17 for details), a system current of less than 2 µA is displayed. The device wakes up when SW2 is pressed again and displays the time on the LCD. The following figures show the output display. Figure 5-8. PSoC 5LP in Active Mode Figure 5-9. PSoC 5LP in Sleep Mode CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 36 Code Examples 5.6 Project: CapSense 5.6.1 Project Description This code example provides a platform to build CapSense-based projects using PSoC 5LP. The example uses two CapSense buttons and one five-element slider provided on the board. Each capacitive sensor on the board is scanned using the Cypress CSD algorithm. The buttons are pretuned in the example code to take care of factors such as board parasitic. 5.6.2 Hardware Connections This project uses the LCD for display; therefore, ensure that it is plugged into the port. No specific hardware connections are required for this project because all connections are hard-wired on the board. 5.6.3 Verify Output Build and program the code example, and reset the device. The LCD displays the status of the two buttons as On/Off. The LCD also shows the slider touch position as a percentage. When you touch a button, the LCD displays ON; when you remove the finger from the button, the LCD displays OFF. When the slider is touched, the corresponding finger position is displayed as a percentage on the LCD. Figure 5-10. CapSense Slider CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 37 Code Examples Figure 5-11. CapSense Button 5.7 Project: ADC_DAC 5.7.1 Project Description This project demonstrates sine wave generation by using an 8-bit DAC and DMA. The sine wave period is based on the current value of the ADC value of the potentiometer. The firmware reads the voltage output by the board potentiometer and displays the raw counts on the LCD. An 8-bit DAC outputs a table generated sine wave to an LED using DMA at a frequency proportional to the ADC count. 5.7.2 Hardware Connections For this example, the character LCD must be installed on P8. The example uses the potentiometer; therefore, the jumper POT_PWR should also be in place. This jumper connects the potentiometer to the Vdda. 5.7.3 Verify Output Build and program the code example, and reset the device to view the ADC output displayed on the LCD. LED4 is an AC signal output whose period is based on the ADC. Turning the potentiometer results in LCD value change. This also results in change in the period of the sine wave fed into LED4. When the potentiometer changes, the blinking rate of LED4 changes. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 38 Code Examples Figure 5-12. ADC Output CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 39 Schematic Power Supply NO LOAD TP4 RED V5.0 5.0V/1A LDO U2 3 3216 R24 AP1117D50G TO-252 VIN + 2 VOUT 2 C143216 + D-64 2 9V Battery Terminals 10 uFd 16v GND 1 TP3 RED NO LOAD VSSD GND V3.3 R26 ZERO V5.0 0805 SS12-E3/61T GND LM1117MPX-3.3 2 VOUT GND 4 TAB 3216 U4 + C15 10 uFd 16v VDDA GND + C5 GND GND1 GND2 nSHDN 4 Byp VDDA GND VSSD 1 1 VSSB ZERO NO LOAD VSSA VSSD 1 NO LOAD 1 VDDD R11 1K 3 2 1 0805 0805 1 2 3 VSSA LED Green D5 R57 J38 V5.0 V3.3 VSSA 2 2 Note: Load R30 when either Analog and Digital regulator required 1 2 3 + C13 330 ohm 0805 ZERO NO LOAD 2 3216 2 R15 GND 1 0805 1 0805 R13 3.74K V5.0 VDDD R30 2 R12 3.16K SENSE 3 6 7 GND 0.1 uFd C17 2 SENSE 5 10 uFd 16v 1 1 OUT 3 2 SENSE 1 SEL3V3 IN 0603 3216 2 8 BAT 9V MALE VDDA_P LT1763CS8 VDDA_P RED VDDD VDDA VSSD SEL3V3 2 U1 1 NEG2 NEG1 NEG3 9V 0402 BH1 5V/3.3V/0.5A LDO 0603 GND 2 1 3 R23 ZERO 0805 BAT 9V FEMALE J33 2 3.3V/0.8A LDO 1 VIN 1 + C2 10 uFd 16v 10 uFd 16v 3216 SOT-223 1 1 3 2 1 3 POS2 POS1 POS3 BH2 C4 D4 1 POWER JACK P-5 0805 ZERO 2 VIN SS12-E3/61T 1 1 J4 D-64 10 uFd 16v D3 1 2 3 2 GND +9V/+12V, 1A 3 2 1 A.1 Appendix VSSD VSSA J11 3 2 1 A. J10 Note: For 5V: J11-3 to J11-2, J10-3 to J10-2 For 3.3V: J11-2 to J11-1, J10-2 to J10-1 For 5V Analog,3.3V Digital: J11-3 to J11-2, J10-2 to J10-1 Note: Load R25, R29 and R31 for operating the device on Boost Internal Boost Regulator VDDD Ind VDDA R31 NO LOAD 0805 R25 NO LOAD L1 Vboost 0805 R29 NO LOAD VBAT TP2 RED 0805 VBAT D6 1 R27 ZERO SOT23 7032 2 0805 22 uH 0805 0402 GND GND 0.1 uFd 1210 C6 22 uFd 10V C22 22 uFd 10V TP1 BLACK GND 1210 GND C23 0805 C3 R1 NO LOAD ZHCS 0402 0.1 uFd R28 NO LOAD VSSB Note: Load R1,R28 and Un-Load R27 for low power application CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 40 0603 VCCd C42 1.0 uFd 0603 C55 1.0 uFd 1 1 NO LOAD 1 1 2 C40 0.1 uFd 0402 VDDA 0603 VSSA 0603 C54 1.0 uFd VSSA VCCa C37 C36 1.0 uFd 0.1 uFd 0402 1 2 C38 0402 0.1 uFd VSSA VSSD 32.768KHz XTAL P12[1] P12[0] P3[7] P3[6] Y2 1 2 3 4 5 P3[0] P3[1] P3[2] P3[3] P3[4] P3[5] 1 1 C25 0603 22 pFd 2 J16 1 0603 P1[6] P1[7] P12[6] P12[7] P5[4] P5[5] P5[6] P5[7] DP_P DM_P J43 P0[3] P0[2] P0[1] P0[0] P4[1] P4[0] P12[3] P12[2] 0603 VDDD R36 R39 ZERO VSSA 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 TP5 NO LOAD 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDDio0 P0_3 P0_2 P0_1 P0_0 P4_1 P4_0 SIO_P12_3 SIO_P12_2 VSSd VDDa VSSa VCCa NC8 NC7 NC6 NC5 NC4 NC3 P15_3 P15_2 SIO, I2C1_SDA P12_1 SIO, I2C1_SCL P12_0 P3_7 P3_6 CY8C5868AXI-LP035 TQFP100 VSSD VDDA 1 1 PIN HDR NO LOAD 1 VSSD VSSB /XRES P5[0] P5[1] P5[2] P5[3] SWDIO SWDCK P1[2] SWO TDI P1[5] P2_5 P2_6 P2_7 P12_4 I2C0_SCL, SIO P12_5 I2C0_SDA, SIO P6_4 P6_5 P6_6 P6_7 VSSb Ind Vboost Vbat VSSd XRES P5_0 P5_1 P5_2 P5_3 P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 J8 2 Ind Vboost VBAT 1 VDDio2 P2_4 P2_3 P2_2 P2_1 P2_0 P15_5 P15_4 P6_3 P6_2 P6_1 P6_0 VDDd VSSd VCCd P4_7 P4_6 P4_5 P4_4 P4_3 P4_2 P0_7 P0_6 P0_5 P0_4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 J12 1 PIN HDR 1 PIN HDR NO LOAD NO LOAD J22 VDDio1 P1_6 P1_7 P12_6_SIO P12_7_SIO P5_4 P5_5 P5_6 P5_7 P15_6 DP P15_7 DM VDDd VSSd VCCd NC1 NC2 P15_0 P15_1 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 VDDio3 0603 NO LOAD 2200 pFd Cmod 2 1 0805 VSSD 0603 R2 3K R8 NO LOAD 1.5K P2[5] P2[6] P2[7] P12[4] P12[5] P6[4] P6[5] P6[6] C39 P6[7] 1 1 U7 VSSD P4[7] P4[6] P4[5] P4[4] P4[3] P4[2] P0[7] P0[6] P0[5] P0[4] P2[4] P2[3] P2[2] P2[1] P2[0] P15[5] P15[4] P6[3] P6[2] P6[1] P6[0] 0.1 uFd VBUS2 R38 2.2K J26 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 C43 0402 1 PIN HDR VDDA 0603 1 1 PIN HDR NO LOAD P15[4] Rbleed 1 C44 1.0 uFd VDDD VSSD J25 J42 1 PIN HDR NO LOAD 0402 ZERO 1 J41 1 PIN HDR NO LOAD VSSA C41 0.1 uFd VCCa 1 0603 R47 VCCd 1 VDDD VDDD J44 1 2 1 1 2 1 Appendix C27 22 pFd NO LOAD 1 PIN HDR VSSA VDDA VSSA 1 2 C34 0402 0.1 uFd DP 1 DM 1 1 PIN HDR NO LOAD VCCd 0603 0603 1 0603 22E R33 2 2 22E R32 ZERO J18 VDDD 0402 VSSD C29 C33 0.1 uFd 1.0 uFd 0603 C35 0.1 uFd 0402 Y3 24 MHz Crystal 1 C31 22 pFd 0402 C30 22 pFd 0402 C26 0.1 uFd VSSA 0402 VSSD R35 ZERO VSSD CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G PSoC 5 VSSA Note: Place De-Caps near to the Chip 41 Appendix C7 0402 C18 0402 0.1 uFd C12 0402 0.1 uFd C20 2 VDDD 9 8 D11 1 10K 54 44 29 30 31 NO LOAD 6 7 3V3_FX12P GND U3 VCC 8-SOIC 1 2 R5 2.2K 0805 4 5 XTALOUT WAKEUP# CTL0/FLAGA CTL1/FLAGB CTL2/FLAGC 4 15 16 5 SCL SDA 45 46 47 48 49 50 51 52 SWD/SWV/JTAG VSSD VDDD J40 1 3 5 7 9 /XRES 1 TV1 P2[3] P2[4] P2[5] P2[6] P2[7] 2 4 6 8 10 50MIL KEYED SMD VSSD 10-PIN TRACE HEADER SWDIO SWDCK SWO VBUS1 R21 39K 1% GND GND P3[0] P3[1] P3[2] P3[3] P3[4] P3[5] P3[6] P3[7] 8 7 6 5 4 3 2 1 P4 RECP 8X1 SW1 LED1 1A 1B /XRES VDDD 2 R62 1 1 J5 330 ohm 2 1 0805 0805 LED Red LED2 J30 LED2 1 2 2 1 R61 330 ohm 1 2 1 R60 330 ohm 1 2 1 R59 330 ohm 1 2 0805 P6[5] LED Red LED3 R56 2 1A 1B SW2 2A 2B 1A 1B P6[1] SW PUSHBUTTON 2A 2B VSSA SW PUSHBUTTON VSSD 1 PIN HDR VSSD VDDD VDDA J14 1 VSSA1 PIN HDR 1 J35 1 J27 NO LOAD J7 1 1 J28 J6 1 1 NO LOAD VSSA NO LOAD P5[6] P5[5] P5[4] P5[3] CSB1 CapSense R48 0603 0603 0603 0603 0603 CapSense Linear Slider 5 Seg CSS1 ZERO ZERO CSB2 CapSense CapSense Button and Slider VSSA VSSD 1 PIN HDR 1 PIN HDR P5[2] P5[0] P5[1] 0603 VSSD 1 PIN HDR 1 PIN HDR 1 PIN HDR VSSD R54 1 SW3 R49 R50 R51 R52 R53 1 VSSD P6[5] LED1 LED2 0603 LED Red V5.0 V3.3 8 7 6 5 4 3 2 1 1 ZERO 2 ZERO 3 ZERO 4 ZERO 5 ZERO 8 7 6 5 4 3 2 1 0805 1 10K R55 VSSA NO LOAD P15[5] Note: Load R56 for high precision analog NO LOAD J36 1 1 to disconnect Capacitive Sensors 1 2 1 C45 P6[3] 1 LED Red LED4 + 1 3216 0805 2 Note: Un-Load R48 - R54 VDDA P6 0805 0805 10K P6[5] 10 uFd 16v P6[2] 3 NO LOAD 0805 1 2 VSSD 1 1 PIN HDR 1 VDDA 2A 2B SW PUSHBUTTON P3 RECP 8X1 LED1 Breadboard Prototype Area 8 7 6 5 4 3 2 1 P0[0] P0[1] P0[2] P0[3] P0[4] P0[5] P0[6] P0[7] 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 GND J50 R22 62K 1% 1 14 57 26 28 53 56 12 41 FX2LP Programmer FIRMWARE UPDATE REQUIRED FOR USB BACKVOLTAGE COMPLIANCE. 0603 6 10 2 CP GND3 GND4 GND5 GND6 GND1 GND2 AGND1 AGND2 GND 24LC00/SN 8-SOIC 18 19 20 21 22 23 24 25 PD0/FD8 PD1/FD9 PD2/FD10 PD3/FD11 PD4/FD12 PD5/FD13 PD6/FD14 PD7/FD15 RDY0/SLRD RDY1/SLWR 1 2 3 7 SDA 6 33 34 35 36 37 38 39 40 PB0/FD0 PB1/FD1 PB2/FD2 PB3/FD3 PB4/FD4 PB5/FD5 PB6/FD6 PB7/FD7 CLKOUT SWDIO SWDCK SWO TDI /XRES 2 4 6 8 10 50MIL KEYED SMD PA0/nINT0 PA1/nINT1 PA2/SLOE PA3/WU2 PA4/FIFOADR0 PA5/FIFOADR1 U5 PA6/PKTEND PA7/FLAGD CY7C68013A-56LTXC IFCLK 0.1 uFd VSSD 0603 NC1 NC2 NC3 NC4 GND R6 2.2K 0402 SCL 0402 0402 0.01 uFd 8 13 TV-20R TV2 1 TP2 1 1 0402 0402 2 D-64 D-64 2 D-64 2 R17 J9 100K 2 C8 DMINUS DPLUS 3V3_FX12P USB MINI B 1 RESET# 0402 RESERVED D9 1 D10 1 D+ D- AVCC1 AVCC2 C1 2 42 1 3 5 7 9 GND 1 3 7 GND J3 1 Y1 24 MHz XTALIN 0.1 uFd VBUS1 R3 3 2 11 32 C16 0402 VCC1 VCC2 C11 2.2 uFd 6.3V 0402 0.1 uFd 1 2 3 4 5 VBUS DM DP ID GND R9 ZERO 17 27 43 55 VBUS1 2 C19 0402 GND S1 S2 PLACE ONE CAP PER EACH VCC ON U5. 0.1 uFd VCC3 VCC4 VCC5 VCC6 D-64 2 D-64 0603 R14 100K 1% J1 S3 S4 C10 0402 0.1 uFd 1 1 PLACE C11 AND C16 CLOSE CLOSE TO U5-3 AND U5-7. 1 1 SS12-E3/61T SS12-E3/61T D2 8 9 0402 V3.3 V5.0 VBUS1 2 D8 C21 0.1 uFd GND 3V3_FX12P VIN 0402 0.1 uFd 8 7 6 5 4 3 2 1 1 1 VSSA VSSD 8 7 6 5 4 3 2 1 J31 J34 1 J29 J32 1 1 1 VDDA 1 1 VDDD P6[6] P6[0] P12[7] P12[6] P12[5] P12[4] VDDD VSSD P9 RECP 8X1 CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 42 Appendix GND CGND1 Use Separate Track for CGND1 to GND P1 P3[6] P3[4] P3[2] P3[0] J23 1 1 P0[6] P0[4] P0[2] P0[0] NO LOAD J20 1 1 P4[6] P4[4] P4[2] P4[0] NO LOAD J17 1 1 NO LOAD J13 1 P12[2] SCL P12[0] 1 V5.0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 P3[7] P3[5] P3[3] P3[1] Expansion Connectors P2 J15 P0[7] P0[5] P0[3] P0[1] 1 1 P2[6] P2[4] P2[2] P2[0] NO LOAD J19 P4[7] P4[5] P4[3] P4[1] 1 1 P5[6] P5[4] P5[2] P5[0] NO LOAD J21 P12[3] P12[1] SDA VSSA V3.3 1 NO LOAD J24 VIN 1 P12[2] SCL P12[0] V5.0 1 1 NO LOAD 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 P1[6] TDI P1[2] SWDIO 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 P1[7] P1[5] SWO SWDCK P2[7] P2[5] P2[3] P2[1] P5[7] P5[5] P5[3] P5[1] P12[3] P12[1] SDA V3.3 VIN NO LOAD 20x2 RECP RA 20x2 RECP RA CGND1 CGND1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Port E (Analog EBK Connector) VSSD VSSD Port D (Misc Connector) VDDA NO LOAD J39 1 R73 ZERO 1 VREF 2 P0[3] LM4140 NO LOAD VIN VREF 6 VREF NO LOAD 1 R34 ZERO C24 1.0 uFd NO LOAD 1 R37 ZERO 2 0603 NC 5 3216 C32 + C28 VSSA 0402 0.1 uFd VSSA 1 4 7 8 GND GND1 GND2 GND3 EN 10 uFd 16v 0805 3 2 P3[2] 0805 1 0805 U6 2 VSSA Voltage Reference CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 43 Appendix Note: Load R72 for 5V operation, Load R71 for 3.3V operation LCD Display VLCD D1 0E 0805 C53 1 0402 D-64 2 VBUS2 2 VBUS2 D-64 D131 LCD MODULE 2 D121 2 D-64 D-64 D14 1 DM DP 2 0.1 uFd VSSD P8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND VCC VO RS R/nW EN D0 D1 D2 D3 D4 D5 D6 D7 A USB MinB 1 2 0402 2 1 2 100 ohm R68 10K R69 VSSD 10K R40 10K 0402 R41 10K 0402 R42 10K 0402 R43 10K 0402 R44 10K 0402 R45 10K 0402 R46 K LCD HEADER W/O BACKLIGHT 0402 C9 R71 1 NO LOAD 100K R4 1 0E 0805 2 R67 10K NO LOAD 1 2 R72 1 1 SS12-E3/61T 1 VBUS 2 DM 3 DP 4 ID 5 GND USB MINI B 3 V5.0 D-64 2 6 7 8 9 S3 S4 S1 S2 J2 V3.3 0603 D7 VLCD 0603 VIN SS12-E3/61T V5.0 P2[0] P2[1] P2[2] P2[3] P2[4] P2[5] P2[6] 0402 VLCD 0.01 uFd VSSD VSSD R70 0805 NO LOAD NO LOAD 1 2 RTS RX CTS TX C2+ C51 0402 0.1 uFd C47 0402 0.1 uFd 1 VSSD C50 5 14 13 DB9 FEMALE 7 8 RTS CTS 0402 16 C1+ 0.1 uFd TX RX C46 0402 C2- C1- TR1OUT TR1IN RX1IN RX1OUT TR2OUT TR2IN RX2IN RX2OUT 0.1 uFd 3 R64 ZERO 11 12 R63 1 R65 1 10 9 SERIAL_TX 100 ohm 2 SERIAL_RX 100 ohm 2 SERIAL_RTS 0805 VSSD VCC U8 4 C48 + 0805 10 10 ohm P7 3216 0603 11 0805 R58 5 9 4 8 3 7 2 6 1 10 uFd 16v 1 2 J37 1 2 Note: Un-Load R58 to disconnect RS-232 Power VDDD R66 ZERO SERIAL_CTS C49 0402 V+ MAX3232CDR 0.1 uFd V- 6 C52 15 1 2 3 4 GND 0603 2 P5 SERIAL_RX SERIAL_TX SERIAL_CTS SERIAL_RTS 0402 0.1 uFd 4x1 RECP RS 232 VSSD CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 44 Appendix R74 ZERO NO LOAD R75 0805 0805 PMOS( DMP3098L-7) V5.0 V3.3_EXT PMOS( DMP3098L-7) Q4 Q3 Q2 PMOS( DMP3098L-7) D15 R10 1K ohm PMOS( DMP3098L-7) PMOS( DMP3098L-7) R7 220 ohm V3.3 Q5 R16 442 ohm Vz=1.8V(BZT52C2V0-7-F) Q1 Vz=4.3V(PTZTE254,SOD-106) V5.0_EXT ZERO NO LOAD Q6 PMOS( DMP3098L-7) D16 R18 1K ohm Protection Circuits CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 45 Appendix A.2 Board Layout A.2.1 PDC-09356 Top CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 46 Appendix A.2.2 PDC-09356 Power CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 47 Appendix A.2.3 PDC-09356 Ground CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 48 Appendix A.2.4 PDC-09356 Bottom CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 49 Appendix A.3 Bill of Materials (BOM) Item Qty Reference Value Description Manufacturer Manufacturer Part No. PCB Cypress PDC-09356 1 1 BH1 BAT 9V MALE BATTERY HOLDER 9V Male PC MT Keystone Electronics 593 2 1 BH2 BAT 9V FEMALE BATTERY HOLDER 9V Female PC MT Keystone Electronics 594 3 9 C2,C4,C5,C13,C 14,C15,C28,C45, 10 uFd 16v C46 CAP 10UF 16V TANTALUM 10% 3216 AVX TAJA106K016R 4 2 C6,C22 CAP CER 22UF 10V 10% X5R Kemet 1210 C1210C226K8PACTU 5 29 C7,C10,C12,C16, C17,C18,C19,C2 0,C21,C26,C32,C 33,C34,C35,C36, 0.1 uFd C38,C40,C41,C4 3,C47,C48,C49,C 50,C51,C52, C53, C1, C3, C23 CAP .1UF 16V CERAMIC Y5V Panasonic 0402 ECG ECJ-0EF1C104Z 6 2 C8,C9 0.01 uFd CAP 10000PF 16V CERAMIC 0402 SMD Panasonic ECG ECJ-0EB1C103K 7 1 C11 2.2 uFd CAP CER 2.2UF 6.3V 20% X5R 0402 Panasonic ECG ECJ-0EB0J225M 8 4 C29,C37,C42,C4 1.0 uFd 4 CAP CERAMIC 1.0UF 25V X5R 0603 10% Taiyo Yuden TMK107BJ105KA-T 9 2 C25, C27 22pF CAP, CER, 22 pF, 50V, 5%, COG, 0603, SMD Panasonic ECG ECJ-0EC1H220J 10 1 C39 2200 pFd SMD/SMT 0805 2200pF 50volts C0G 5% Murata GRM2165C1H222JA0 1D 11 2 C54,C55 1.0 uFd CAP CERAMIC 1.0UF 25V X5R 0603 10% Taiyo Yuden TMK107BJ105KA-T 12 6 D1,D2,D3,D4, D7, D8 SS12-E3/61T DIODE SCHOTTKY 20V 1A SMA Vishay/General Semiconductor SS12-E3/61T 13 1 D5 LED Green LED GREEN CLEAR 0805 SMD Chicago Miniature CMD17-21VGC/TR8 14 1 D6 ZHCS DIODE SCHOTTKY 40V 1.0A SOT23-3 Zetex ZHCS1000TA 15 6 D9, D10, D11, D12, D13, D14 ESD diode SUPPRESSOR ESD 5VDC 0603 SMD Bourns Inc. CG0603MLC-05LE 16 1 D15 4.3V zener diode DIODE ZENER 4.3V 1W SOD- Rohm SemiconPTZTE254.3B 106 ductor 17 1 D16 2.0V Zener Diode DIODE ZENER 2V 500MW SOD-123 Diodes Inc BZT52C2V0-7-F 18 2 J1,J2 USB MINI B CONN USB MINI B SMT RIGHT ANGLE TYCO 1734035-2 19 2 J3, J40 50MIL KEYED SMD CONN HEADER 10 PIN 50MIL Samtec KEYED SMD FTSH-105-01-L-DV-K 20 1 J4 POWER JACK P-5 CONN JACK POWER 2.1mm PCB RA CUI PJ-102A 21 1 J50 Breadboard BREADBOARD 17x5x2 3M 923273-I 22 uFd CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 50 Appendix Item Qty Reference Value BLACK TEST POINT Description Manufacturer TEST POINT PC MINI .040"D Black Keystone Electronics Manufacturer Part No. 22 5 TP1, J26, J27, J35, J28 23 4 LED1,LED2,LED LED Red 3,LED4 LED RED CLEAR 0805 SMD Rohm SemiconSML-210LTT86 ductor 24 1 L1 22 uH INDUCTOR SHIELD PWR 22UH 7032 TDK Corporation 25 2 P1,P2 20x2 RECP RA CONN FMALE 40POS DL .100 Sullins ElectronPPPC202LJBN-RC R/A GOLD ics Corp. 26 1 P7 DB9 FEMALE CONN DB9 FMALE VERT PRESSFIT SLD 27 1 P8 LCD HEADER W/ CONN RECEPT 16POS .100 O BACKLIGHT VERT AU 28 4 P3,P4,P6,P9 RECP 8X1 29 6 P-MOS, 30V 3.8A Q1,Q2,Q3,Q4,Q5 MOSFET P-CH 30V 3.8A SOT23 in Protec,Q6 SOT23-3 tion circuit 30 1 R7 RES 220 OHM 1/ 10W 1% 0603 SMD 31 1 R16 32 2 R3,R4 33 6 R9,R23,R24,R26, ZERO R27,R71 RES 0.0 OHM 1/10W 5% 0805 Panasonic-ECG ERJ-6GEY0R00V SMD 34 2 R5,R6 2.2K RES 2.2K OHM 1/16W 5% 0402 SMD 35 3 R11,R10,R18 1K RES 1.0K OHM 1/8W 5% 0805 Panasonic SMD ECG ERJ-6GEYJ102V 36 1 R12 3.16K RES 3.16K OHM 1/10W .5% 0603 SMD Yageo RT0603DRD073K16L 37 1 R13 3.74K RES 3.74K OHM 1/10W 1% 0603 SMD Panasonic ECG ERJ-3EKF3741V 38 1 R14 100K RES 100K OHM 1/10W 1% 0603 SMD Yageo RC0603FR-07100KL 39 5 R15,R59,R60,R6 330 ohm 1,R62 RES 330 OHM 1/10W 5% 0805 Panasonic SMD ECG ERJ-6GEYJ331V 40 8 R17,R40,R41,R4 2,R43,R44,R45,R 10K 46 RES 10K OHM 1/16W 5% 0402 SMD Stackpole Electronics Inc RMCF 1/16S 10K 5% R 41 13 R35,R36,R39,R4 7,R48,R49,R50,R ZERO 51,R52,R53,R54, R64,R66 RES ZERO OHM 1/16W 5% 0603 SMD Panasonic ECG ERJ-3GEY0R00V 42 2 R32,R33 22E RES 22 OHM 1/16W 1% 0603 Panasonic SMD ECG ERJ-3EKF22R0V 43 2 R63,R65 100 ohm RES 100 OHM 1/8W 5% 0805 Rohm SMD MCR10EZHJ101 Norcomp Inc. 5001 SLF7032T-220MR962-PF 191-009-223R001 Tyco Electronics 1-534237-4 CONN RECT 8POS .100 VERT 3M 929850-01-08-RA Diodes Inc DMP3098L-7 Panasonic - ECG ERJ3EKF2200V YES RES 442 OHM 1/ 10W 1% 0603 SMD Panasonic - ECG ERJ3EKF4420V YES 100K RES 100K OHM 1/16W 5% 0402 SMD Panasonic ECG ERJ-2GEJ104X CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G Panasonic ECG ERJ-2GEJ222X 51 Appendix Item Qty Reference Value Description Manufacturer Manufacturer Part No. 44 1 R56 POT 10K POT 10K OHM 1/8W CARB VERTICAL 45 1 R58 10E RES 10 OHM 1/8W 5% 0805 SMD 46 1 R68 100 ohm RES 100 OHM 1/16W 5% 0603 Panasonic SMD ECG ERJ-3GEYJ101V 47 1 R69 10K RES 10K OHM 1/16W 5% 0603 SMD Panasonic ECG ERJ-3GEYJ103V 48 3 SW1,SW2,SW3 SW PUSHBUTTON LT SWITCH 6MM 160GF H=2.5MM SMD Panasonic ECG EVQ-Q2P02W 49 1 U1 LT1763CS8 IC LDO REG LOW NOISE ADJ Linear Technol8-SOIC ogy LT1763CS8#PBF 50 1 U2 AP1117D50G IC REG LDO 1.0A 5.0V TO252 Diodes Inc AP1117D50G-13 51 1 U3 24LC00/SN IC EEPROM 128BIT 400KHZ 8SOIC Microchip Technology 24LC00/SN 52 1 U4 LM1117MPX-3.3 IC REG 3.3V 800MA LDO SOT-223 National Semiconductor LM1117IMP-3.3/ NOPB 53 1 U5 CY7C68013A56LTXC IC, FX2 HIGH-SPEED USB Cypress SemiPERIPHERAL CONTROLLER conductor QFN56 54 1 U7 CY8C5868AXILP035 TQFP100 PSoC 5 Mixed-Signal Array Cypress Semiconductor CY8C5868AXI-LP035 55 1 U8 MAX3232CDR IC 3-5.5V LINE DRVR/RCVR 16-SOIC Texas Insturments MAX3232IDR 56 1 Y1 24 MHz CER RESONATOR 24.0 MHz SMD Murata CSTCW24M0X53-R0 57 1 Y2 32.768KHz XTAL CRYSTAL 32.768 KHZ CYL 12.5PF CFS308 Citizen America CFS308Corporation 32.768KDZF-UB 58 1 Y3 24 MHz Crystal CRYSTAL 24.000MHZ 20PF SMD ECS Inc ECS-240-20-5PX-TR 59 3 J8,J33, TP2 RED TEST POINT TEST POINT PC MINI .040"D RED Keystone Electronics 5000 60 1 R38 2.2K RES 2.2KOHM 1/16W 2700PPM 5%0603 Panasonic ECG ERA-V27J222V 61 2 J10,J11 3p_jumper CONN HEADER VERT SGL 3POS GOLD 3M 961103-6404-AR 62 3 J30,J43,J44 2p_jumper CONN HEADER VERT SGL 2POS GOLD 3M 961102-6404-AR 63 1 NA 3.3V LCD Module 16POS w/16 pin header installed 3.3V LCD Module 16POS w/16 Lumex pin header installed LCM-S01602DTR/A-3 64 1 NA 16 pin header CONN HEADER VERT SGL 16POS GOLD 3M 961116-6404-AR 65 1 R21 39K RES 39.0K OHM 1/10W 1% 0603 SMD Rohm SemiconMCR03EZPFX3902 ductor 66 1 R22 62K RES 62.0K OHM 1/10W 1% 0603 SMD Rohm SemiconMCR03EZPFX6202 ductor 67 2 C30,C31 22pF CAP, CER, 22 pF, 50V, 5%, COG, 0603, SMD Panasonic ECG CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G CTS Electrocomponents 296UD103B1N Stackpole Electronics Inc RMCF 1/10 10 5% R CY7C68013A56LTXC ECJ-1VC1H220J 52 Appendix Item Qty Reference Value Description Manufacturer Manufacturer Part No. 68 1 P5 4x1 RECP CONN RECEPT 4POS .100 VERT GOLD 69 1 J31, J32, J29, J34 4x1 RECP CONN RECEPT 4POS .100 VERT GOLD 3M 929850-01-04-RA 1.0 uFd CAP CERAMIC 1.0UF 25V X5R 0603 10% Taiyo Yuden TMK107BJ105KA-T 3M 929850-01-04-RA No Load Components 70 1 C24 71 11 J5,J6,J12,J14,J1 8,J22,J25,TP3,T RED P4,J16,J39 TEST POINT PC MINI .040"D RED Keystone Electronics 5000 72 2 J7,J36 BLACK TEST POINT PC MINI .040"D Black Keystone Electronics 5001 73 1 TP5 WHITE TEST POINT PC MINI .040"D WHITE Keystone Electronics 5002 74 1 R67 10K POT 10K OHM 1/4" SQ CERM Bourns Inc. SL ST 75 12 R30,R34,R57,R7 2,R25,R31,R70,R ZERO 37,R29, R73,R74,R75 RES 0.0 OHM 1/10W 5% 0805 Panasonic-ECG ERJ-6GEY0R00V SMD 76 1 R55 10K TRIMPOT 10K OHM 4MM TOP Bourns Inc. ADJ SMD 77 2 R1,R28, ZERO RES ZERO OHM 1/10W 5% 0603 SMD Panasonic ECG ERJ-3GEY0R00V 78 1 U6 LM4140 IC REF PREC VOLT MICROPWR 8-SOIC National Semiconductor LM4140ACM-1.0/ NOPB 79 1 R8 1.5K RES 1.5KOHM 1/10W 1500PPM 5%0805 Panasonic ECG ERA-S15J152V 80 1 R2 3K RES 1/10W 3K OHM 0.1% 0805 Stackpole Electronics Inc RNC 20 T9 3K 0.1% R 81 1 J38 3p_jumper CONN HEADER VERT SGL 3POS GOLD 3M 961103-6404-AR 82 1 J37 2p_jumper CONN HEADER VERT SGL 2POS GOLD 3M 961102-6404-AR 83 2 CSB1,CSB2 CapSense CapSense Button Cypress CapSense Linear Slider 5 Seg CapSense Slider Cypress 84 1 CSS1 85 11 J9,J13,J15,J17,J 19,J20,J21,J23,J PADS 24,J41,J42 PADS 86 2 TV1,TV2 PADS PADS 3362P-1-103LF 3214W-1-103E Install On Bottom of PCB As Close To Corners As Possible 87 5 BUMPER CLEAR .500X.23" Richco Plastic RBS-3R SQUARE Co CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 53 Appendix Item Qty Reference Value Description Manufacturer Manufacturer Part No. Special Jumper Installation Instructions 88 1 J30 Install jumper across pins 1 and 2 Rectangular Connectors MINI JUMPER GF 13.5 CLOSE TYPE BLACK Kobiconn 151-8030-E 89 2 J10, J11 Install jumper across pins 1 and 2 Rectangular Connectors MINI JUMPER GF 13.5 CLOSE TYPE BLACK Kobiconn 151-8030-E 90 2 J43,J44 Install jumper across pins 1 and 2 Rectangular Connectors MINI JUMPER GF 13.5 CLOSE TYPE BLACK Kobiconn 151-8030-E External Assembly 91 2 Install 3.3V label 3.3V label as per assembly spec 92 2 4-40 X 5 +13 Brass Spacer Stud with Nut Spacer and nut for RS232 Connector P7 CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 54 Appendix A.4 Port Port 0 Pin Assignment Table Pin Pin Name Description 71 P0[0] Connected to pin 18 on port E 72 P0[1] Connected to pin 17 on port E 73 P0[2] 74 P0[3] 76 P0[4] 77 P0[5] 1. Connected to pin 16 on port E 2. Connected to SAR bypass capacitor C54 that can be selected by shorting jumper J43 Connected to two points: 1. Voltage reference chip* 2. Connected to pin 15 on port E 1. Connected to pin 14 on port E 2. Connected to SAR bypass capacitor C55 that can be selected by shorting jumper J44 Connected to pin 13 on port E 78 P0[6] Connected to pin 12 on port E 79 P0[7] Connected to pin 11 on port E P1[0] Connected to three points: 1. Connected to pin 2 on programming header J3 2. Connected to pin 45 on U5 3. Connected to pin 8 (SWDIO) on port D 21 P1[1] Connected to three points: 1. Connected to pin 4 on programming header 2. Connected to pin 56 on U5 3. Connected to pin 7 (SWDCK) on port D 22 P1[2] Connected to pin 6 on port D 23 P1[3] Connected to three points: 1. Connected to pin 6 on programming header 2. Connected to pin 47 on U5 3. Connected to pin 5 (SWO) on port D 24 P1[4] Connected to two points: 1. Connected to pin 8 on programming header 2. Connected to pin 4 (TDI) on port D 25 P1[5] Connected to pin 3 on port D 27 P1[6] Connected to pin 2 on port D 28 P1[7] Connected to pin 1 on port D 20 Port 1 CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 55 Appendix Port Pin Pin Name 95 P2[0] Connected to two points: 1. Connected to LCD module 2. Connected to pin 18 on port D 96 P2[1] Connected to two points: 1. Connected to LCD module 2. Connected to pin 17 on port D 97 P2[2] Connected to two points: 1. Connected to LCD module 2. Connected to pin 16 on port D P2[3] Connected to three points: 1. Connected to pin 2 on trace header J40 2. Connected to LCD module 3. Connected to pin 15 on port D P2[4] Connected to three points: 1. Connected to pin 4 on trace header J40 2. Connected to LCD module 3. Connected to pin 14 on port D P2[5] Connected to three points: 1. Connected to pin 6 on trace header J40 2. Connected to LCD module 3. Connected to pin 13 on port D P2[6] Connected to three points: 1. Connected to pin 8 on trace header J40 2. Connected to LCD module 3. Connected to pin 12 on port D 3 P2[7] Connected to three points: 1. Connected to pin 10 on trace header J40 2. Connected to LCD module 3. Connected to pin 11 on port D 44 P3[0] Connected to pin 8 on port E 45 P3[1] Connected to pin 7 on port E 46 P3[2] Connected to two points: 1. Voltage reference chip* 2. Connected to pin 6 on port E 47 P3[3] Connected to pin 5 on port E 48 P3[4] Connected to pin 4 on port E 49 P3[5] Connected to pin 3 on port E 51 P3[6] Connected to pin 2 on port E 52 P3[7] Connected to pin 1 on port E 69 P4[0] Connected to pin 28 on port E 70 P4[1] Connected to pin 27 on port E 80 P4[2] Connected to pin 26 on port E 81 P4[3] Connected to pin 25 on port E 82 P4[4] Connected to pin 24 on port E 83 P4[5] Connected to pin 23 on port E 84 P4[6] Connected to pin 22 on port E 85 P4[7] Connected to pin 21 on port E 98 Port 2 99 1 2 Port 3 Port 4 Description CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 56 Appendix Port Port 5 Port 6 Port 12 Pin Pin Name Description 16 P5[0] Connected to two points: 1. Connected to CapSense slider segment 2. Connected to pin 28 on port D 17 P5[1] Connected to two points: 1. Connected to CapSense slider segment 2. Connected to pin 27 on port D 18 P5[2] Connected to two points: 1. Connected to CapSense slider segment 2. Connected to pin 26 on port D 19 P5[3] Connected to two points: 1. Connected to CapSense slider segment 2. Connected to pin 25 on port D 31 P5[4] Connected to two points: 1. Connected to CapSense slider segment 2. Connected to pin 24 on port D 32 P5[5] Connected to two points: 1. Connected to CapSense button CSB1 2. Connected to pin 23 on port D 33 P5[6] Connected to two points: 1. Connected to CapSense button CSB2 2. Connected to pin 22 on port D 34 P5[7] Connected to pin 21 on port D 89 P6[0] Connected to pin 5 on P9 90 P6[1] Connected to SW2 push button 91 P6[2] Connected to LED3 92 P6[3] Connected to LED4 6 P6[4] Connected to CapSense Modulation Capacitor CMOD 7 P6[5] Connected to two points: 1. Connected to VR POT 2. Connected to pin 5 on P6 8 P6[6] Connected to pin 6 on P9 9 P6[7] Unused/No Connect 53 P12[0] Connected to pin 34 (SCL) on port D and port E 54 P12[1] Connected to pin 33 (SDA) on port D and port E 67 P12[2] Connected to pin 32 on port D and port E 68 P12[3] Connected to pin 31 on port D and port E 4 P12[4] Connected to pin 1 on P9 5 P12[5] Connected to pin 2 on P9 29 P12[6] Connected to pin 3 on P9 30 P12[7] Connected to pin 4 on P9 CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 57 Appendix Port Port 15 Other pins Pin Pin Name Description 42 P15[0] Connected to 24-MHz crystal 43 P15[1] Connected to 24-MHz crystal 55 P15[2] Connected to 32-kHz crystal 56 P15[3] Connected to 32-kHz crystal 93 P15[4] Connected to Rbleed resistor 94 P15[5] Connected to SW3 push button 35 P15[6] Connected to USB D+ 36 P15[7] Connected to USB D– 13 Vbat Connected to Vbat 12 Vboost Connected to Vboost 63 VCCa Connected to VCCa 39 VCCd Connected to VCCd 86 VCCd Connected to VCCd 65 VDDa Connected to VDDa 37 VDDd Connected to VDDd 88 VDDd Connected to VDDd 75 VDDio0 Connected to VDDio0 26 VDDio1 Connected to VDDio1 100 VDDio2 Connected to VDDio2 50 VDDio3 Connected to VDDio3 64 VSSa Connected to GND 10 VSSb Connected to GND 14 VSSd Connected to GND 38 VSSd Connected to GND 66 VSSd Connected to GND 87 VSSd Connected to GND 15 XRES Connected to three points: 1. Connected to pin 10 on J3 2. Connected to SW1 3. Connected to pin 20 on U5 11 Ind Connected to inductor 40 NC1 Unused/No Connect 41 NC2 Unused/No Connect 57 NC3 Unused/No Connect 58 NC4 Unused/No Connect 59 NC5 Unused/No Connect 60 NC6 Unused/No Connect 61 NC7 Unused/No Connect 62 NC8 Unused/No Connect Note* To enable voltage reference, populate the resistors R34, R37, R73, and low dropout voltage reference IC LM4140. See the “Bill of Materials (BOM)” on page 50 for component details. CY8CKIT-050 PSoC 5LP Development Kit Guide, Doc. # 001-65816 Rev. *G 58