Datasheet

SC186
4A Synchronous
Step-Down Regulator
POWER MANAGEMENT
Features
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Description
Input Voltage Range — 2.9 to 5.5V
Output Voltage Range — 0.8V to 3.3V
Output Current — up to 4A
Ultra-Small Footprint — <1mm Height Solution
Switching Frequency — 1.5MHz
Automatic Power Save Mode
Efficiency Up to 95%
Low Output Noise Across Load Range
Excellent Transient Response
Start Up into Pre-Bias Output
Duty-Cycle Low Dropout Operation — 100%
Shutdown Current — <1µA
Externally Programmable Soft Start Time
Power Good indicator
Input Under-Voltage Lockout
Output Over-Voltage, Current Limit Protection
Over-Temperature Protection
Thermally Enhanced 3 x 3 x 0.6 (mm)
MLPQ-UT16 package
Temperature Range — -40 to +85°C
Lead-free, Halogen free, and RoHS/WEEE compliant
Applications
The SC186 is a 4A synchronous step-down regulator
designed to operate with an input voltage range of 2.9V
to 5.5V. The device offers fifteen pre-determined output
voltages via four control pins programmable from 0.8 to
3.3 Volts. The control pins allow for on-the-fly voltage
changes, enabling system designers to implement
dynamic power savings. The device is also capable of
adjusting output voltage via an external resistor divider.
The SC186 is optimized for maximum efficiency over a
wide range of load currents. During full load operation,
the device operates in PWM mode with fixed 1.5MHz
oscillator frequency, allowing the use of small surface
mount external components. As the load decreases, the
regulator will transition into Power Save mode maintaining high efficiency.
Connecting the control pins to logic low forces the device
into shutdown mode reducing the supply current to less
than 1μA. Connecting any of the control pins to logic high
enables the converter and sets the output voltage according to Table 1. Other features include under-voltage
lockout, programmable soft-start to limit in-rush current,
power good indicator, over-temperature protection, and
output short circuit protection.
The SC186 is available in a thermally-enhanced, 3 x 3 x 0.6
(mm) MLPQ-UT16 package.
Routers and Network Cards
 LCD TV
 Office Automation
 Printers

Typical Application Circuit
V IN
LX
PVIN
C IN
22µF
R P GOOD
100kΩ
R A V IN
1Ω
C A V IN
0.1µF
SC186
AVIN
VOU T
SS
C T L0
PGOOD
C T L0
PGN D
C T L1
C T L1
AGN D
C T L2
C T L2
C T L3
C T L3
Revision 2.1
L
1.0µH
V OU T
C OU T
47µF
CSS
10nF
© 2016 Semtech Corporation
SC186
16
LX
PGND
13
12
PGND
2
11
PGND
A V IN
3
10
VOUT
CTL0
4
9
SS
T O P V IE W
5
6
7
8
PGOOD
T
C T L3
AGND
14
C T L2
1
15
C T L1
P V IN
Ordering Information
LX
P V IN
Pin Configuration
3 x 3 x 0.6 (mm) MLPQ-UT16
θJA = 40°C/W; θJC = 7°C/W
Marking Information
186
yyw w
xxxx
yyww = Date Code
XXXX = Semtech Lot number
Device
Package
SC186ULTRT(1)(2)
3 x 3 x 0.6 (mm) MLPQ-UT16
SC186EVB(5)
Evaluation Board
Notes:
(1) Available in tape and reel only. A reel contains 3,000 devices.
(2) Device is lead-free, Halogen free, and RoHS/WEEE compliant.
Table 1 – Output Voltage Settings
CTL3
CTL2
CTL1
CTL0
Output Voltage
0
0
0
0
Shutdown
0
0
0
1
0.8
0
0
1
0
1.00
0
0
1
1
1.025
0
1
0
0
1.05
0
1
0
1
1.20
0
1
1
0
1.25
0
1
1
1
1.30
1
0
0
0
1.50
1
0
0
1
1.80
1
0
1
0
2.20
1
0
1
1
2.50
1
1
0
0
2.60
1
1
0
1
2.80
1
1
1
0
3.00
1
1
1
1
3.30
SC186
Absolute Maximum Ratings
Recommended Operating Conditions
PVIN and AVIN Supply Voltages (V) . . . . . . . . . -0.3 to +6.0
PVIN and AVIN Supply (V) . . . . . . . . . . . . . . . . . . 2.9 to +5.5
LX (V) (1). . . . . . . . . . . . . . . . . . . . . . . -0.3 to PVIN +0.3V, 6V Max
Maximum Output Current (A). . . . . . . . . . . . . . . . . . . . . . . 4.0
VOUT (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to AVIN + 0.3
Input Capacitor (µF)... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CTLx pins (V). . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to AVIN + 0.3
Output Capacitor (µF). . . . . . . . . . . . . . . . . . . . . 47 or 2 x 22
VOUT Short Circuit Duration. . . . . . . . . . . . . . . . Continuous
Output Inductor (µH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0
ESD Protection Level(2) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal Information
Thermal Resistance, Junction to Ambient(3) (°C/W) . . . . 40
Thermal Resistance, Junction to Case (°C/W) . . . . . . . . . . . 7
Operating Junction Temperature (°C). . . . . . . . -40 to +125
Maximum Junction Temperature (°C). . . . . . . . . . . . . . . +150
Storage Temperature Range (°C) . . . . . . . . . . . . -65 to +150
Peak IR Reflow Temperature (10s to 30s) (°C) . . . . . . . +260
Exceeding the absolute maximum ratings may result in permanent damage to the device and/or device malfunction. Operation outside of the
parameters specified in the Electrical Characteristics section is not recommended.
Notes:
(1) Due to parasitic board inductance, the transient LX pin voltage at the point of measurement may appear larger than that which exists on silicon. The device is
designed to tolerate the short duration transient voltages that will appear on the LX pin due to the deadtime diode conduction, for inductor currents up to the
current limit setting of the device.
(2) Tested according to JEDEC standard JESD22-A114-B.
(3) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Unless specified: PVIN = AVIN = 5.0V, VOUT = 1.50V, CIN = 22µF, COUT = 2 x 22µF; L = 1.0µH; -40°C≤ TJ ≤ +125 °C; Unless otherwise noted typical values are TA = +25 °C.
Parameter
Under-Voltage Lockout
Symbol
Conditions
Min
Typ
Max
Units
Rising AVIN, PVIN=AVIN
2.70
2.80
2.90
V
UVLO
Hysteresis
Output Voltage Tolerance(1)
300
ΔVOUT
PVIN= AVIN= 2.9 to 5.5V; IOUT=1A
-1.5
ILIMIT
Peak LX current
5.0
IQ
IOUT = 0A
100
ISHDN
CTL3-0 = AGND
1
High Side Switch Resistance(2)
RDSON_P
ILX= 100mA, TJ= 25 °C
50
Low Side Switch Resistance(2)
RDSON_N
ILX= -100mA, TJ= 25 °C
35
PVIN= AVIN= 5.5V; LX= 0V; CTL3-0 = AGND
1
Current Limit
Supply Current
Shutdown Current
LX Leakage Current(2)
Load Regulation
ILK(LX)
ΔVLOAD-REG
6.0
mV
+1.5
%
7.0
A
µA
10
µA
mΩ
10
µA
PVIN= AVIN= 5.5V; LX= 5.0V; CTL3-0 = AGND
PVIN= AVIN= 5.0V, IOUT=800mA to 4A
-20
-1
±0.3
%
SC186
Electrical Characteristics (continued)
Parameter
Symbol
Oscillator Frequency
fOSC
Soft-Start Charging Current(2)
ISS
Typ
Max
Units
1.275
1.500
1.725
MHz
µA
1
A
10
Ω
VOUT rising
90
%
Asserted
2
ms
PGOOD= Low
20
µs
tEN_DLY
From CTLX Input High to SS starts rising
50
µs
ICTLx
CTLX =AVIN or AGND
ICL_HOLD
Impedence of PGOOD Low
RPGOOD_LO
PGOOD Threshold
VPG_TH
PGOOD Delay
VPG_DLY
CTLX Input Current(2)
Min
+5
Foldback Holding Current
CTLX Delay
Conditions
CTLX Input High Threshold
VCTLx_HI
CTLX Input Low Threshold
VCTLX_LO
Average LX Current
-2.0
2.0
1.2
V
115
0.4
V
120
%
VOUT Over Voltage Protection
VOVP
Thermal Shutdown Temperature
TSD
160
°C
TSD_HYS
10
°C
Thermal Shutdown Hysteresis
110
µA
Notes:
(1) The “Output Voltage Tolerance” includes output voltage accuracy, voltage drift over temperature and the line regulation.
(2) A negative current means the current flows into the pin and a positive current means the current flows out from the pin.
SC186
Pin Descriptions
Pin #
Pin Name
Pin Function
1, 16
PVIN
Input supply voltage for the converter power stage
2
AGND
Ground connection for the internal circuitry — AGND needs to be connected to PGND directly.
3
AVIN
Power supply for the internal circuitry — AVIN is required to be connected to PVIN through an R-C filter of 1Ω
and 100nF.
4, 5, 6, 7
CTLx
Control bit — see Table 1 for decoding. These pins have 500kΩ internal pull-down resistors which are switched
in circuit whenever CTLx is low or when the part is in under-voltage lockout.
8
PGOOD
Power good indicator — when the output voltage reaches the PGOOD threshold, this pin will be open-drain
(after the PGOOD delay), otherwise, it is pulled low internally.
9
SS
Soft Start — Connect a soft-start capacitor to program the soft start time. There is a 5µA charging current
flowing out of the pin.
10
VOUT
Output voltage sense pin
11,12,13
PGND
Ground connection for converter power stage
14,15
LX
T
Thermal Pad
Switching node — connect an inductor between this pin and the output capacitor.
Thermal pad for heat sinking purposes — recommend to connect to PGND. It is not connected internally.
SC186
Block Diagram
A V IN
C u rre n t A m p
C
P V IN
C o n tro l
L o g ic
A
LX
B
PGND
3
P lim it A m p
O scilla to r a n d
S lo p e G e n e ra to r
VOUT
10
CTL0
4
CTL1
5
CTL2
6
CTL3
7
V o lta g e
S e le ct
E rro r A m p
PW M
C om p
500m V
R ef
P G O O D D e te cto r
D e la y
9
2
8
SS
AGND
PGOOD
NO TES:
A = P in s 1 4 ,1 5
B = P in s 1 1 , 1 2 , 1 3
C = 1, 16
SC186
Typical Characteristics
Circuit Conditions: CIN = 22µF/6.3V, COUT = 2 x 22µF/6.3V, CSS = 10nF. Unless otherwise noted, L = 1.0µH (TOKO: FDV0530S-1R0).
Efficiency
100
TA = 25 °C
V IN = 5 V ; V O U T = 3 .3 V
95
Efficiency (%)
90
85
V IN = 5 V ; V O U T = 1 .5 V
V IN = 3 .3 V ; V O U T = 1 .5 V
80
75
70
65
60
0
0 .1
Output current (A)
1.0
1 0.0
Total Loss
2 .0
V IN = 3.3 V ; V O U T = 1.5 V
1600
V IN = 5 V ; V O U T = 3 .3 V
Loss (mW)
1200
800
TA = 25 °C
1 .5
Regulation (%)
2000
Load Regulation
TA = 25 °C
V IN = 5 V ; V O U T = 1 .5 V
V IN = 3 .3 V ; V O U T = 1 .5 V
1 .0
V IN = 5V ; V O U T = 3 .3V
0 .5
V IN = 5 V ; V O U T = 1 .5 V
400
0
0
0
0.5
1.5
2 .0
2 .5
Output current (A)
1 .0
3 .5
3 .0
4 .0
-0.5
0
RDS(ON) Variation vs. Input Voltage
35
I LX = ±1 0 0m A , T A = 2 5 °C
20
1 .5
2
2 .5
Output current (A)
3
3 .5
4
4 .5
I LX = ±100m A , T A = 25 °C
15
25
10
20
P -C h a n n e l
Variation (%)
Variation (%)
1
RDS(ON) Variation vs. Temperature
30
15
10
5
0
P -C hannel
-5
5
N -C h a n n e l
-10
0
N -C hannel
-15
-5
-1 0
0 .5
2 .5
3 .0
3 .5
4 .0
4 .5
Input Voltage (V)
5 .0
5 .5
-20
-40
-15
35
10
Ambient Temperature (°C)
60
85
SC186
Typical Characteristics (continued)
Circuit Conditions: CIN = 22µF/6.3V, COUT = 2 x 22µF/6.3V, CSS = 10nF. Unless otherwise noted, L = 1.0µH (TOKO: FDV0530S-1R0).
Output Voltage Ripple (VOUT=1.5V)
Output Voltage Ripple (VOUT=1.5V)
VIN = 5V, = IOUT = 0
VIN = 3.3V, = IOUT = 0
VOUT (50mV/div)
VOUT (50mV/div)
VIN (2V/div)
VIN (2V/div)
LX (2V/div)
LX (2V/div)
ISW (1A/div)
ISW (1A/div)
Time (500n������
s�����
/div)
Time (500n������
s�����
/div)
Output Voltage Ripple (VOUT=1.5V) @ Full Load
Output Voltage Ripple (VOUT=1.5V) @ Full Load
VIN = 3.3V, = IOUT = 4A
VIN = 5V, = IOUT = 4A
VOUT (10mV/div)
VOUT (10mV/div)
IL (1A/div)
IL (1A/div)
VIN (2V/div)
VIN (2V/div)
LX (1V/div)
LX (1V/div)
Time (500n������
s�����
/div)
Time (500n������
s�����
/div)
SC186
Typical Characteristics (continued)
Circuit Conditions: CIN = 22µF/6.3V, COUT = 2 x 22µF/6.3V, CSS = 10nF. Unless otherwise noted, L = 1.0µH (TOKO: FDV0530S-1R0).
Output Voltage Ripple (VOUT = 3.3V) @ No Load
Output Voltage Ripple (VOUT = 3.3V) @ Full Load
VIN = 5V, = IOUT = 4A; VOUT = 3.3V
VIN = 5V, = IOUT = 0; VOUT = 3.3V
VOUT (20mV/div)
VOUT (50mV/div)
VIN (2V/div)
VIN (2V/div)
LX (2V/div)
ISW (1A/div)
LX (2V/div)
ISW (1A/div)
Time (500n������
s�����
/div)
Time (500n������
s�����
/div)
Start Up (CTLX) — Full Load
Start Up (CTLX) — No Load
VIN = 5V, = IOUT = 0; VOUT = 1.5V
VIN = 5V, = IOUT = 4A; VOUT = 1.5V
VCTLx (5V/div)
VCTLx (5V/div)
PGOOD (5V/div)
PGOOD (5V/div)
VOUT (1V/div)
VOUT (1V/div)
IOUT (5A/div)
IOUT (5A/div)
Time (500µ������
s�����
/div)
Time (500µ������
s�����
/div)
SC186
Typical Characteristics (continued)
Circuit Conditions: CIN = 22µF/6.3V, COUT = 2 x 22µF/6.3V, CSS = 10nF. Unless otherwise noted, L = 1.0µH (TOKO: FDV0530S-1R0).
Start Up (CTLX) — Full Load
Start Up (CTLX) — No Load
VIN = 5V, = IOUT = 0; VOUT = 3.3V
VIN = 5V, = IOUT = 0; VOUT = 3.3V
VCTLx (5V/div)
VCTLx (5V/div)
PGOOD (5V/div)
PGOOD (5V/div)
VOUT (2V/div)
VOUT (2V/div)
IOUT (5A/div)
IOUT (5A/div)
Time (500µ������
s�����
/div)
Start Up into Pre-Biased Output (VOUT=1.5V)
Time (500µ������
s�����
/div)
Start Up into Pre-Biased Output (VOUT=3.3V)
VCTLx (5V/div)
VCTLx (5V/div)
PGOOD (5V/div)
PGOOD (5V/div)
VOUT (1V/div)
VOUT (2V/div)
IOUT (5A/div)
IOUT (5A/div)
Time (500µ������
s�����
/div)
Time (500µ������
s�����
/div)
Start Up into Output Short Circuit
VIN = 5V
LX (5V/div)
VOUT (500mV/div)
VSS (1V/div)
ILX (2A/div)
Time (1m������
s�����
/div)
10
SC186
Typical Characteristics (continued)
Circuit Conditions: CIN = 22µF/6.3V, COUT = 2 x 22µF/6.3V, CSS = 10nF. Unless otherwise noted, L = 1.0µH (TOKO: FDV0530S-1R0).
Recovery from Short Circuit
Output Short Circuit
VIN = 5V; VOUT = 1.5V
VIN = 5V; VOUT = 1.5V
VCTLx (5V/div)
VCTLx (5V/div)
PGOOD (5V/div)
VOUT (1V/div)
PGOOD (5V/div)
VOUT (1V/div)
IOUT (5V/div)
IOUT (2V/div)
Time (20µ������
s�����
/div)
Time (20µ������
s�����
/div)
Output Short Circuit
Recovery from Short Circuit
VIN = 5V; VOUT = 3.3V
VIN = 5V; VOUT = 3.3V
VCTLx (5V/div)
VCTLx (5V/div)
PGOOD (5V/div)
VOUT (2V/div)
PGOOD (5V/div)
VOUT (2V/div)
IOUT (2V/div)
IOUT (5V/div)
Time (20µ������
s�����
/div)
Time (20µ������
s�����
/div)
Transient Response (VOUT=1.5V, ISTEP=2A)
Transient Response (VOUT=3.3V, ISTEP=2A)
VIN = 5V; IOUT = 1A to 3A to 1A
VIN = 5V; IOUT = 1A to 3A to 1A
VOUT (100mV/div)
VOUT (100mV/div)
IOUT (1A/div)
IOUT (1A/div)
Time (20µ������
s�����
/div)
Time (20µ������
s�����
/div)
11
SC186
Typical Characteristics (continued)
Circuit Conditions: CIN = 22µF/6.3V, COUT = 2 x 22µF/6.3V, CSS = 10nF. Unless otherwise noted, L = 1.0µH (TOKO: FDV0530S-1R0).
Transient Response (VOUT=1.5V, ISTEP=3A)
Transient Response (VOUT=3.3V, ISTEP=3A)
VOUT = 5V; IOUT = 0A to 3A to 0A
VIN = 5V; IOUT = 0A to 3A to 0A
VID Transition — Full Load
VID Transition — No Load
VIN = 5V; VOUT = 1.5V to 1.8V to 1.5V
VIN = 5V; VOUT = 1.5V to 1.8V to 1.5V
VOUT (200mV/div)
VOUT (200mV/div)
IOUT (2A/div)
IOUT (2A/div)
Time (400m������
s�����
/div)
Time (100m������
s�����
/div)
12
SC186
Applications Information
Detailed Description
The SC186 is a synchronous step-down PWM (Pulse Width
Modulated) DC-DC converter utilizing a 1.5MHz fixed-frequency voltage mode architecture. The device is designed
to operate in fixed-frequency PWM mode and will enter
PSAVE (power save) mode at light loads to maximize efficiency. The switching frequency is chosen to minimize the
size of the external inductor and capacitors while maintaining high efficiency.
Operation
During normal operation, the PMOS MOSFET is activated
on each rising edge of the internal oscillator. The period is
set by the onboard oscillator when in PWM mode. The
device has an internal synchronous NMOS rectifier and
does not require a Schottky diode on the LX pin. The
device operates as a buck converter in PWM mode with a
fixed frequency of 1.5MHz at medium to high loads. At
light loads the part will enter PSAVE mode to maximize
efficiency.
If the output load current increases enough to cause VOUT
to decrease below the PSAVE exit threshold (VOUT - 4%),
the device automatically exits PSAVE and operates in continuous PWM mode. Note that the PSAVE high and low
threshold levels are both set at or above VOUT to minimize
undershoot when the SC186 exits PSAVE. Figure 1 illustrates the transitions from PWM mode to PSAVE mode and
back to PWM mode.
L oa d
D e m an d
(IOUT )
V OUT +2%
VOUT
BURST
V O U T -4%
Power Save Mode Operation
When the load current decreases below the PSAVE threshold, PWM switching stops and the device automatically
enters PSAVE mode. This threshold varies depending upon
the input voltage and output voltage setting, optimizing
efficiency for all possible load currents. While in PSAVE
mode, output voltage regulation is controlled by a series of
bursts in switching. During a burst, the inductor current is
limited to a peak value which controls the on-time of the
PMOS switch. After reaching this peak, the PMOS switch is
disabled and the inductor current is forced to near 0mA.
Switching bursts continue until the output voltage climbs
to VOUT +2% or until the PSAVE current limit is reached.
Switching is then stopped to eliminate switching losses,
enhancing overall efficiency. Switching resumes when the
output voltage reaches the lower threshold of VOUT and
continues until the upper threshold again is reached. Note
that the output voltage is regulated hysteretically while in
PSAVE mode between VOUT and VOUT + 2%. The period and
duty cycle while in PSAVE mode are solely determined by
VIN and VOUT until PWM mode resumes. This can result in the
switching frequency being much lower than the PWM
mode frequency.
OFF
VLX
P W M M od e at
M e diu m / H ig h
L oa d
PSAVE
E X IT
P S A V E M od e at
L igh t L oa d
T im e
P W M M od e at
M e diu m / H ig h
Lo a d
Figure 1 — Transitions between PWM and PSAVE Modes
Protection Features
The SC186 provides the following protection features:
•
•
•
•
Current Limit
Over-Voltage Protection
Soft-Start Operation
Thermal Shutdown
Current Limit & OCP
The internal PMOS power device in the switching stage is
protected by a current limit feature. If the inductor current
is above the PMOS current limit for 16 consecutive cycles,
the part enters foldback current limit mode and the output
current is limited to the current limit holding current
(ICL_HOLD) which is approximately 1A. Under this condition,
the output voltage will be the product of ICL_HOLD and the
13
SC186
Applications Information (continued)
load resistance. When the load presented falls below the
current limit holding level, the output will charge to the
upper PSAVE voltage threshold and return to normal
operation. The SC186 is capable of sustaining an indefinite short circuit without damage. During the soft start, if
current limit has occurred before the SS voltage has
reached 400mV, the part enters foldback current limit
mode. Foldback current limit mode will be disabled during
soft-start after the SS voltage is higher than 400mV.
L
V IN
C IN
22µF
R A V IN -1Ω
R P GOOD
100k Ω
C A V IN
0.1µF
PVIN
SC186
AVIN
R FB 1
C FF
C OU T
VOU T
R FB 2
10k Ω
PGOOD
C T L0
Enable
V OU T
LX
SSA
C T L1
PGN D
C T L2
AGN D
R FB 1 = (V OU T -1)
x R FB 2
for C T LX = 0010
(1.0V)
CSS
10nF
C T L3
Over-Voltage Protection
In the event of a 15% over-voltage on the output, the
PWM drive is disabled with the LX pin floating. Switching
does not resume until the output voltage falls below the
nominal VOUT regulation voltage.
Programmable Output Voltage
The SC186 has fifteen pre-determined output voltage
values which can be individually selected by programming the CTL input pins (see Table 1 — Output Voltage
Settings). Each CTL pin has an active 500kΩ internal pulldown resistor. The 500kΩ resistor is switched in circuit
whenever the CTL input voltage is below the input threshold, or when the part is in under voltage lockout. It is
recommended to tie all high CTL pins together and use an
external pull-up resistor to AVIN if there is no enable signal
or if the enable input is an open drain/collector signal. The
CTL pins may be driven by a microprocessor to allow
dynamic voltage adjustment for systems that reduce the
supply voltage when entering sleep states. Avoid all zeros
being present on the CTL pins when changing programmable output voltages as this would disable the device.
SC186 is also capable of regulating a different (higher)
output voltage, which is not shown in the Table 1, via an
external resistor divider. There will be a typical 2μA current
flowing into the VOUT pin. The typical schematic for an
adjustable output voltage option from the standard 1.0V
with CTLx=[0010], is shown in Figure 2. RFB1 and RFB2 are
used to adjust the desired output voltage. If the RFB2
current is such that the 2μA VOUT pin current can be
ignored, then RFB1 can be found using the next equation.
RFB2 needs to be low enough in value for the current
through the resistor chain to be at least 20μA in order to
ignore the VOUT pin current.
Figure 2 — Output Voltage Programming
R FB1
VOUT VOSTD
u R FB2
VOSTD
where VOSTD is the pre-determined output voltage via the
CTL pins.
CFF is needed to maintain good transient response performance. The correct value of CFF can be found using the
following equation.
CFF [nF]
2 .5 u
VOUT 0.52
VOSTD
u(
)
R FB1 [k:] u VOUT VOSTD VOSTD 0.5
To simplify the design, it is recommended to program the
desired output voltage from a standard 1.0V as shown in
Figure 2 with a proper CFF calculated from Equation 2. For
programming the output voltage from other standard
voltages, RFB1, RFB2 and CFF need to be adjusted to conform
to the previous equations.
Shut Down
When all CTL pins are low, the device will run in shutdown
mode, drawing less than 1μA from the input power supply.
The internal switches and band-gap voltage will be immediately turned off.
Thermal Shutdown
The device has a thermal shutdown feature to protect the
SC186 if the junction temperature exceeds 160°C. During
thermal shutdown, the on-chip power devices are disabled, floating the LX output. When the temperature
drops by 10°C, it will initiate a soft start cycle to resume
normal operation.
14
SC186
Applications Information (continued)
Under-Voltage Lockout
Under-Voltage Lockout (UVLO) is enabled when the input
voltage drops below the UVLO threshold. This prevents
the device from entering an ambiguous state in which
regulation cannot be maintained. Hysteresis of approximately 300mV is included to prevent chattering near the
threshold. When the AVIN voltage rises back to the turnon threshold and CTL X is high, the soft-start mode is
resumed.
Power Good
The power good (PGOOD) is an open-drain output. When
the output voltage drops below 10% of nominal voltage,
the PGOOD pin is pulled low after a 20μs delay. During
start-up, PGOOD will be asserted 2ms (typ.) after the
output voltage reaches 90% of the final regulation voltage.
The faults of over voltage, fold-back current limit mode
and thermal shutdown will force PGOOD low after a 20µs
delay. When recovering from a fault, PGOOD will be
asserted 1.8ms (typ.) after Vout reaches 90% of the final
regulation voltage.
Soft-Start
The soft-start mode is activated after AVIN reaches it’s
UVLO voltage threshold and CTLX is set high to enable the
part. A thermal shutdown event will also activate the soft
start sequence. The soft-start mode controls the slew-rate
of the output voltage during start-up thus limiting in-rush
current on the input supply. During start-up, the reference
voltage for the error amplifier is clamped by the voltage
on the SS pin. The output voltage slew rate during softstart is determined by the value of the external capacitor
connected to the SS pin and the internal 5µA charging
current. The device requires a minimum soft-start time
from enable to final regulation in the order of 200µs,
including the 50µs enable delay. As a result the soft start
capacitor, Css, should be higher than 1.5nF. During start
up, the chip operates in forced PWM mode.
multiplied by the on-resistance of the internal PMOS
switch and the DC-resistance of the inductor when PMOS
switch is on continuously.
Output L-C filter Selection
SC186 has fixed internal loop-gain compensation. It
is optimized for X5R or X7R ceramic output capacitors
and an output L-C filter corner frequency of less
than 34kHz. The output L-C corner frequency can be
determined by Equation 2.
1
fC
2S
L u C OUT
In general, the inductor is chosen to set the inductor ripple
current to approximately 30% of the maximum output
current. It is recommended to use a typical inductor value
of 1μH to 2.2μH with output ceramic capacitors of 44μF or
higher capacitance. Lower inductance should be considered in applications where faster transient response is
required. More output capacitance will reduce the output
deviation for a particular load transient. When using low
inductance, the maximum peak inductor current at any
condition (normal operation and start up) can not exceed
5A which is the guaranteed minimum current limit. The
saturation current rating of the inductor needs to be at
least larger than the peak inductor current which is the
maximum output current plus half of inductor ripple
current.
100% Duty-Cycle Operation
SC186 is capable of operating at 100% duty-cycle. When
the difference between the input voltage and output
voltage is less than the minimum dropout voltage, the
PMOS switch is completely on, operating in 100% dutycycle. The minimum dropout voltage is the output current
15
SC186
Applications Information (continued)
PCB Layout Considerations
The layout diagram in Figure 3 shows a recommended
top-layer PCB for the SC186 and supporting components.
Figure 4 shows the bottom layer for this PCB. Fundamental
layout rules must be followed since the layout is critical for
achieving the performance specified in the Electrical
Characteristics table. Poor layout can degrade the performance of the DC-DC converter and can contribute to EMI
problems, ground bounce, and resistive voltage losses.
Poor regulation and instability can result.
The following guidelines are recommended when developing a PCB layout:
1. The input capacitor, CIN should be placed as close to
the PVIN and PGND pins as possible. This capacitor
provides a low impedance loop for the pulsed currents
present at the buck converter’s input. Use short wide
traces to connect as closely to the IC as possible.
This will minimize EMI and input voltage ripple by
localizing the high frequency current pulses.
2. Keep the LX pin traces as short as possible to minimize
pickup of high frequency switching edges to other
parts of the circuit. COUT and L should be connected as
close as possible between the LX and PGND pins, with
a direct return to the PGND pin from COUT.
3. Route the output voltage feedback/sense path away
from the inductor and LX node to minimize noise and
magnetic interference.
4. Use a ground plane referenced to the SC186 PGND
pin. Use several vias to connect to the component
side ground to further reduce noise and interference
on sensitive circuit nodes.
5. If possible, minimize the resistance from the VOUT
and PGND pins to the load. This will reduce the
voltage drop on the ground plane and improve the
load regulation. And it will also improve the overall
efficiency by reducing the copper losses on the output
and ground planes.
Figure 3 — Recommended PCB Layout (Top Layer)
Figure 4 — Bottom Layer Detail (Top View)
16
SC186
Outline Drawing – 3x3 MLPQ-UT16
A
D
B
P IN 1
IN D IC A T O R
(L A S E R M A R K )
D IM
E
A2
A
a aa C
C
A1
S E A T IN G
P LA N E
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
D IM E N S IO N S
IN C H E S
M ILL IM E T E R S
M IN N O M M A X M IN N O M M A X
.024
.002
(.006)
.007 .009 .012
.114 .118 .122
.061 .067 .071
.114 .118 .122
.061 .067 .071
.020 B S C
.012 .016 .020
16
.003
.004
.020
.000
0.60
0.05
(0.152)
0.18 0.23 0.30
2.90 3.00 3.10
1.55 1.70 1.80
2.90 3.00 3.10
1.55 1.70 1.80
0.50 B S C
0.30 0.40 0.50
16
0.08
0.10
0.50
0.00
D1
e /2
L xN
E /2
E1
2
1
N
e
b xN
D /2
b bb
C A B
NOTES:
1.
C O N T R O L LIN G D IM E N S IO N S A R E IN M IL LIM E T E R S (A N G L E S IN D E G R E E S ).
2.
C O P L A N A R IT Y A P P L IE S T O T H E E X P O S E D P A D A S W E LL A S T H E T E R M IN A LS .
3.
D A P IS 1.90 x 1 .9 0m m .
Land Pattern – 3x3 MLPQ-UT16
H
R
D IM
(C )
K
G
Y
X
P
Z
C
G
H
K
P
R
X
Y
Z
D IM E N S IO N S
IN C H E S
M IL LIM E T E R S
(.1 14)
.083
.067
.067
.020
.006
.012
.031
.146
(2 .90)
2 .10
1 .70
1 .70
0 .50
0 .15
0 .30
0 .80
3 .70
NOTES:
1.
C O N T R O L LIN G D IM E N S IO N S A R E IN M IL LIM E T E R S (A N G L E S IN D E G R E E S ).
2.
T H IS LA N D P A T T E R N IS F O R R E F E R E N C E P U R P O S E S O N LY .
C O N S U LT Y O U R M A N U F A C T U R IN G G R O U P T O E N S U R E Y O U R
C O M P A N Y 'S M A N U F A C T U R IN G G U ID E LIN E S A R E M E T .
3 . T H E R M A L V IA S IN T H E L A N D P A T T E R N O F T H E E X P O S E D P A D
S H A LL B E C O N N E C T E D T O A S Y S T E M G R O U N D P LA N E .
F A ILU R E T O D O S O M A Y C O M P R O M IS E T H E T H E R M A L A N D /O R
F U N C T IO N A L P E R F O R M A N C E O F T H E D E V IC E .
17
SC186
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18
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