CN0247: 12-Bit ,1 MSPS, Single-Supply, Low Power Data Acquisition System PDF

Circuit Note
CN-0247
Devices Connected/Referenced
Circuits from the Lab® reference designs are engineered and
tested for quick and easy system integration to help solve today’s
analog, mixed-signal, and RF design challenges. For more
information and/or support, visit www.analog.com/CN0247.
AD7091R
Ultralow Power, 12-Bit, 1 MSPS Analog-toDigital Converter
AD8031
2.7 V, 800 μA, 80 MHz Rail-to-Rail
I/O Single Amplifier
12-Bit ,1 MSPS, Single-Supply, Low Power Data Acquisition System
The low power consumption and small package size of the
selected components makes this combination an industryleading solution for portable battery-operated systems where
power dissipation, cost, and size play a critical role.
EVALUATION AND DESIGN SUPPORT
Circuit Evaluation Boards
AD7091R Evaluation Board (EVAL-AD7091RSDZ)
System Demonstration Platform (EVAL-SDP-CB1Z)
Design and Integration Files
Schematics, Layout Files, Bill of Materials
The AD7091R requires typically only 350 μA of supply current
on the VDD pin at 3 V, which is significantly lower than any
competitive ADC offering currently available in the market.
This translates to ~1 mW typical power dissipation.
CIRCUIT FUNCTION AND BENEFITS
The circuit shown in Figure 1 is an ultralow, power data
acquisition system using the AD7091R 12-bit, 1 MSPS SAR
ADC and an AD8031 op amp driver with a total circuit power
dissipation of less than 5 mW on a single 3 V supply.
AD8031
SUPPLY
DECOUPLING
The AD8031 requires only 800 μA of supply current, that results
in 2.4 mW typical power dissipation at 3 V supply, making the
total power dissipation of the system less than 5 mW when
sampling at 1 MSPS with a 10 kHz analog input signal.
OPTIONAL
INPUT
PROTECTION
3V
3V
3V
10µF
WITH BUSY
INDICATION
VDRIVE
VDRIVE
10µF
100nF
100nF
100kΩ
100nF
VIN
VDD
1µF
0V TO 2.5V
+VS
AD8031
–VS
51Ω
SDO
SCLK
AD7091R
3V
ANALOG
INPUT
VDRIVE
REGCAP
CS
CONVST
VIN GND
4.7nF
SYSTEM
DEMONSTRATION
PLATFORM
(SDP)
REFIN/REFOUT
2.2µF
RC FILTER
10264-001
10µF
Figure 1. 12-Bit, 1 MSPS Low Power ADC with Driver (Simplified Schematic: All Connections Not Shown)
Rev. B
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CN-0247
Circuit Note
CIRCUIT DESCRIPTION
To maximize performance, most SAR ADCs require a suitable
input buffer for the analog signal. The buffer isolates the source
from the transients generated on the ADC input when the internal
track-and-hold switch goes from hold to track. The buffer driving
the ADC must recover from this transient and settle to the required
accuracy within the acquisition time of the ADC. This is particularly
important in applications where the signal source has high source
impedance and where low distortion and a high signal-to-noise
ratio is important. Selecting the proper buffer op amp is therefore
a critical part of the design process.
The AD7091R is a 12-bit, fast, ultralow power, single-supply ADC
with an internal 2.5 V reference. The part can be operated from
a 2.7 V to 5.25 V supply. The AD7091R is capable of throughput
rates of 1 MSPS. At a sampling rate of 1 MSPS, the total power
dissipation of the AD7091R with a 10 kHz input signal is
approximately 2.3 mW.
This power figure can be reduced in applications where 1 MSPS
sampling frequency is not necessary because the AD7091R power
scales with the throughput, as shown in Table 1.
To further reduce power dissipation of the system, reduce the
throughput rate of the converter. Table 1 shows the typical power
vs. throughput for the AD7091R at 3 V when operating in
normal mode.
input is needed, the AD8031 requires an additional negative
supply (see Tutorial MT-035).
Figure 1 shows the simplified schematic for the circuit. Well
decouple the IC power supply pins to ground using 100 nF and
10 µF ceramic capacitors. Position these capacitors as close as
possible to the supply pins of both ICs.
Take care to ensure that the analog input signal to the ADC does
not exceed the supply rails by more than 300 mV. If the signal
does exceed this level, the internal ESD protection diodes become
forward-biased and start conducting current into the substrate.
A diode can conduct a maximum current of 10 mA without
causing irreversible damage to the part. This can be prevented
by connecting a pair of Schottky diodes between VIN and the
supply rails of the AD7091R, as described in Tutorial MT-036).
The AD7091R contains an internal 2.5 V reference. Well decouple
the REFIN/REFOUT pin to achieve the specified performance. The
typical value for the REFIN/REFOUT capacitor is 2.2 µF. Note that
the internal reference voltage can be overdriven externally.
If an external reference voltage is used, the range must be between
2.7 V to VDD, and it must be connected to the REFIN/REFOUT pin.
A typical value for the regulator bypass (REGCAP) decoupling
capacitor is 1 µF.
The voltage applied to the VDRIVE input controls the logic level
voltage of the serial interface. Connect this pin to the supply voltage
of the logic family connected to the AD7091R digital outputs.
VDRIVE can be set in the 1.8 V to VDD range. Typical values for the
VDRIVE decoupling capacitors are 100 nF in parallel with 10 µF.
Table 1 shows the reduction in power consumption that is
achievable when power-down mode is activated. The powerdown mode is an extremely useful method to significantly reduce
power supply requirements when operating the AD7091R at
lower throughput rates.
If the busy indication function is required, connect a pull-up
resistor of 100 kΩ between the VDRIVE and the SDO pin.
The AD7091R is housed in a tiny, 3 mm × 2 mm, 10-lead LFCSP
or a 3 mm × 5 mm, 10-lead MSOP. Both packages offer
considerable space saving advantages over competitive solutions.
The AD8031 is a rail-to-rail input/output low power operational
amplifier and is an optimum drive amplifier for the AD7091R.
The AD8031 can operate from a 2.7 V to 12 V supply, which
allows both ICs to be driven from the same supply rail. The
AD8031 has an 80 MHz bandwidth, a 30 V/µs slew rate, and a
125 ns settling time to 0.1%.
When operating on a single supply, the output of the AD8031
can go to within 20 mV of the negative rail. If linearity to 0 V
The AD8031that is used to buffer analog input of the AD7091R
is configured as a unity gain buffer. A single-pole RC filter follows
the op amp output stage to reduce out-of-band noise. The cutoff
frequency of the RC filter is set to 660 kHz. However, depending on
the system throughput rate specification, this parameter can
vary. In systems where the AD7091R is not operated at maximum
throughput rate, the filter cutoff frequency can be reduced.
Depending on the analog signal input amplitude and offset,
the AD8031 operational amplifier can be configured to provide
gain, attenuation, and level shifting, to match the input signal
swing to the analog input range of the ADC.
Table 1. Typical Power vs. Throughput for the AD7091R at 3 V when Operating in Normal Mode
Mode
IDD
IDRIVE
IAMP (µA)
Total Current (µA)
Total Power (mW)
Power Down
550 nA
36 nA
766
767
2.3
Static (Power On, Input Grounded, No Clock)
21 µA
81 nA
766
787
2.4
Operating (Power On, 10 kHz Input, 1 MSPS Sampling)
368 µA
406 µA
766
1540
4.6
Operating (Power On, Input Grounded, 1 MSPS Sampling)
344 µA
35 µA
766
1145
3.4
Operating (Power On, Input Grounded, 1 kSPS Sampling)
57.8 µA
18.9 µA
766
843
2.5
Note that convert start pulse width = 20 ns when sampling, VDD = VDRIVE = 3 V.
Rev. B | Page 2 of 5
Circuit Note
CN-0247
Figure 4 displays the FFT data calculated for 8192 samples
captured at the 1 MSPS rate with an analog input frequency of
10 kHz. The SNR is 70.44 dBFS.
0.5
0
0.4
–20
0.3
–40
0.2
–60
0.1
0
–100
–120
–0.2
–140
1000
2000
3000
4000
–160
10264-002
0
ADC CODE
0
Figure 2. INL for Sampling Rate of 1 MSPS
500
The circuit must be constructed on a multilayer printed circuit
board (PCB) with a large area ground plane. Proper layout,
grounding, and decoupling techniques must be used to achieve
optimum performance (see Tutorial MT-031, Tutorial MT-101, and
the AD7091R evaluation board layout shown in the CN-0247
Design Support Package.
0.2
0.1
0
–0.1
1
1001
2001
ADC CODE
3001
Figure 3. DNL for Sampling Rate of 1 MSPS
4001
10264-003
–0.2
–0.3
250
FREQUENCY (kHz)
Figure 4. FFT of System, Input =10 kHz, Sampling Frequency = 1 MSPS
0.3
DNL ERROR (LSB)
–80
–0.1
–0.3
INPUT = 10kHz
SAMPLING RATE = 1MSPS
SNR = 70.44dBFS
10264-004
AMPLITUDE (dB)
INL ERROR (LSB)
Figure 2 and Figure 3 show the integral nonlinearity (INL) and
differential nonlinearity (DNL) plots for the circuit. Note that
the INL and DNL is less than ±1 LSB.
Values of the components surrounding the AD7091R and the
AD8031 can be modified to meet specific requirements of the
application and sensor. For example, the buffer can be configured
to provide gain and offset, and the cutoff frequency of the RC
filter can be changed depending on the sampling frequency and
input frequency.
A complete documentation package including schematics,
board layout, and bill of materials (BOM) can be found at
http://www.analog.com/CN0247-DesignSupport.
Rev. B | Page 3 of 5
CN-0247
Circuit Note
CIRCUIT EVALUATION AND TEST
Setup
The EVAL-AD7091RSDZ evaluation board is developed to
evaluate and test the AD7091R device with the circuitry described
in this circuit note. A detailed schematic and user instructions
are available in the EVAL-AD7091RSDZ documentation. A
functional block diagram of the test setup is shown in Figure 5.
Before connecting any hardware, ensure that the links on the
EVAL-AD7091RSDZ evaluation board are positioned as
follows:
•
•
•
•
Equipment Needed
The following equipment is required to test the circuit:
•
9V DC
POWER
SUPPLY
−
GND
Test
Refer to the evaluation board documentation for the complete
description on how to run the various tests contained in this
circuit note.
3V DC
POWER
SUPPLY
+
−
PC
+
USB
+9VIN
J2-2
J2-1
VDD
J1
J3-2
J3-1
VDRIVE
J5
VIN
SIGNAL
GENERATOR
120
EVAL-AD7091RSDZ
J4
EVAL-SDP-CB1Z
•
From this point, follow the evaluation board documentation to
connect the hardware and install the software.
10264-005
•
•
EVAL-AD7091RSDZ Evaluation Board (includes software
and 9 V dc wall wart power supply)
EVAL-SDP-CB1Z System Demonstration Platform Board
A low distortion signal generator, such as the Agilent
81150A or Audio Precision System Two 2322
A PC with an USB 2.0 Port running Windows® XP,
Windows Vista, or Windows 7 (32-Bit or 64-bit)
Power supplies: 9 V dc wall wart (included with evaluation
board, external 3 V dc supply at 50 mA)
CON A
•
LK1: Position A (selects the AD8031 as the input buffer)
LK2: Position A (connects the input at J5 to the input buffer)
LK5: Position A (enables external VDRIVE source)
LK6: Position B (enables external VDD source)
Figure 5. Functional Diagram of Test Setup
Rev. B | Page 4 of 5
Circuit Note
CN-0247
LEARN MORE
REVISION HISTORY
CN-0247 Design Support Package:
http://www.analog.com/CN0247-DesignSupport
12/13—Rev. A to Rev. B
Changes to Title ................................................................................. 1
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of"AGND" and "DGND", Analog Devices.
MT-035 Tutorial, Op Amp Inputs, Outputs, Single-Supply, and
Rail-to-Rail Issues, Analog Devices.
10/12—Rev. 0 to Rev. A
Deleted Common Variations Section ............................................. 3
4/12—Revision 0: Initial Version
MT-036 Tutorial, Op Amp Output Phase-Reversal and Input
Over-Voltage Protection, Analog Devices.
MT-101 Tutorial, Decoupling Techniques, Analog Devices.
Data Sheets and Evaluation Boards
AD7091R Data Sheet and Evaluation Board
System Demonstration Platform (EVAL-SDP-CB1Z)
AD8031 Data Sheet
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CN10264-0-12/13(B)
Rev. B | Page 5 of 5
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