AN-1319: Compensator Design for a Battery Charge/Discharge Unit Using the AD8450 or the AD8451 (Rev. 0) PDF

AN-1319
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Compensator Design for a Battery Charge/Discharge Unit
Using the AD8450 or the AD8451
by Sandro Herrera and Christopher Lang
INTRODUCTION
In response to the growing popularity of portable systems, the
demand for rechargeable batteries has increased exponentially.
The formation and testing of a rechargeable battery requires
multiple charge and discharge cycles, during which the current
and voltage of the battery must be precisely controlled. Accurately
controlling the charge and discharge process extends the life of
the battery and maximizes its capacity. Therefore, battery
formation and test systems require high precision analog front
ends and controllers to monitor and regulate the battery current
and terminal voltage.
Most battery formation and test systems implement the CC-CV
algorithm using high accuracy feedback loops that control the
battery current and voltage. To ensure high battery quality, the
feedback loops need to be stable and robust. This application
note describes how to design and implement the compensation
network for both the constant current and the constant voltage
feedback loops in a battery test or formation system using the
AD8450 or the AD8451 analog front end and controller.
Rechargeable batteries frequently require a constant currentconstant voltage (CC-CV) algorithm to charge or discharge
them. This algorithm forces a constant current into or out of the
battery until its voltage reaches a preset final value. At this point,
the system switches to constant voltage mode and provides the
necessary current to hold the battery voltage at this final value.
Rev. 0 | Page 1 of 20
AN-1319
Application Note
TABLE OF CONTENTS
Introduction ...................................................................................... 1
AD8450 and AD8451 Bandwidth Considerations..................... 14
Revision History ............................................................................... 2
Design Examples ............................................................................ 15
System Overview .............................................................................. 3
Constant Current Feedback Loop with a Type II
Compensator............................................................................... 15
AD8450 and AD8451 Overview................................................. 3
Power Converter Overview ......................................................... 4
Modeling ............................................................................................ 5
Battery ............................................................................................ 5
Linear Regulators.......................................................................... 5
Switching Power Converters ....................................................... 5
CC and CV Feedback Loops ....................................................... 6
Compensator Design........................................................................ 8
Constant Current Feedback Loop with a Type III
Compensator............................................................................... 16
Special Cases ................................................................................... 18
Crossover Frequency Before fPP2............................................... 18
Linear Regulators ....................................................................... 18
Steps for Compensating Linear Regulators ............................ 18
Conclusion....................................................................................... 20
Uncompensated System ............................................................... 8
Compensator Design Steps for the Synchronous Buck/Boost
Converter ....................................................................................... 8
REVISION HISTORY
12/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
Application Note
AN-1319
SYSTEM OVERVIEW
In a battery formation and test system, each charge/discharge
unit is comprised of three major components—an analog front
end, a controller, and a power converter. These components
form the CC and CV feedback loops that control the battery
voltage and current during the charge/discharge process.
AD8450 AND AD8451 OVERVIEW
The AD8450 and the AD8451 are precision analog front ends
and controllers for battery formation and test systems. The
analog front end of these devices includes a precision current
sense programmable gain instrumentation amplifier (PGIA) to
measure the battery current by means of an external shunt
resistor (RS in Figure 1) and a precision voltage sense
programmable gain difference amplifier (PGDA) to measure
the battery voltage.
The analog front end measures the battery voltage and current
and forms the feedback path of the CC and CV control loops
(see the Modeling section). The controller compares the
measured battery voltage and current to the target values and
generates the control signal for the power converter using the
CC-CV algorithm. The power converter generates the battery
current based on the applied control signal.
The controllers of the AD8450 and the AD8451 include two
feedback control loops—a constant current loop (CC) and a
constant voltage loop (CV)—which transition automatically
from CC to CV after the battery reaches the user defined target
voltage. The feedback loops are implemented by means of two
precision error amplifiers (A1 and A2 in Figure 1). These serve
as error amplifiers and external feedback networks that set the
frequency response of the CC and CV feedback loops. External
voltage references set the battery target current and target
voltage for the CC and CV feedback loops. A minimum output
selector circuit combines the outputs of the precision amplifiers
and implements the CC-CV algorithm of the controller.
Figure 1 shows a simplified charge/discharge unit in a battery
formation and test system using an AD8450 or an AD8451
analog front end and controller. In this configuration, the
power converter extracts power from a common dc voltage bus,
which can be shared by multiple charge/discharge units. The
shunt resistor (RS) converts the battery current (IBAT) into a
voltage across it (VRS) that is read by the AD8450 or the AD8451.
Note that the battery current IBAT is the output current of the
power converter. The battery voltage is read directly from the
battery terminals. In both measurements, Kelvin connections to
the shunt resistor and the battery terminals reduce errors due to
voltage drops in the wires. Voltage sources ISET and VSET set
the target current and voltage for the CC and CV feedback
loops, while the external compensation networks set the
frequency response of the controller.
The controllers of the AD8450 and the AD8451 can be operated
in either charge or discharge mode. These modes are selected by
switching the state of the MODE pin. Charge and discharge
modes use independent compensation networks for the CC and
CV loops, and the frequency response of these loops is set
independently in each mode.
VOUT
VIN
DC BUS
VCTRL
COMPENSATION
NETWORK
ISET
POWER
CONVERTER
IBAT
ISMEA
ISVP
SHUNT
RESISTOR
+
VRS
–
RS
ISET
IVE
VINT
PGIA
GIA
A1
ISVN
ANALOG
‘NOR’
CONSTANT CURRENT LOOP
VCTRL
1
BVPx
+
CONSTANT VOLTAGE LOOP
A2
GDA
MINIMUM
OUTPUT
SELECTOR
BVNx
MODE
BVMEA
VSET
VVE
VINT
AD8450/
AD8451
VSET
COMPENSATION
NETWORK
Figure 1. Simplified Charge/Discharge Unit in a Battery Formation and Test System
Rev. 0 | Page 3 of 20
12685-001
VBAT
–
PGDA
AN-1319
Application Note
IOUT = IBAT
R2
In contrast to linear regulators, switching power converters
achieve higher levels of efficiency under most conditions but
are more complex and more difficult to stabilize. However, due
to their increased efficiency, switching power converters are
gaining popularity, especially in high power battery formation
and test systems.
Figure 3 shows a simplified nonisolated synchronous
buck/boost switching converter. The control signal (VCTRL),
which is generated by the controller (AD8450 or AD8451), sets
the duty cycle of the MOSFET switches and the average value of
the voltage at Node VM, by means of the pulse width modulator
(PWM) of the converter (ADP1972). The inductor (LO) and
capacitor (CO) form an LC low-pass filter that averages the
voltage at Node VM to generate a low ripple output voltage (VOUT)
and output current (IBAT).
M1
VIN
VOUT
RS
VCTRL
Q1
BAT
TO PGIA
TO PGDA
R1
Figure 2. Charge Linear Regulator
VIN
DC POWER BUS
OR
RECYCLING BUS
M1
VM
LO
VOUT
IOUT = IBAT
RS
HV
MOSFET
DRIVER
DH
PL
ADP1972
M2
CO
BAT
VCTRL
TO PGIA
TO PGDA
12685-003
Two types of power converters are commonly used to charge
and discharge batteries—linear regulators and switching power
converters. Linear regulators are implemented as voltage
controlled voltage sources or voltage controlled current sources
using a pass transistor. The output current/voltage of these
regulators is proportional to their control voltage. While simple
to compensate and use, the efficiency of linear regulators tends
to be low if the battery voltage and the voltage of the dc bus
differ greatly. Figure 2 shows a simple implementation of a
charge linear regulator using a voltage controlled current source.
The nonisolated buck/boost converter is a bidirectional power
converter that enables energy recycling in the system. During
charge mode, the converter runs in buck mode, such that it
pulls current from the dc bus to charge the battery. In discharge
mode, the converter runs in boost mode, such that it pulls
current from the battery and feeds it to the dc bus. Therefore, in
boost mode, the energy stored in the battery is recaptured.
12685-002
POWER CONVERTER OVERVIEW
Figure 3. Nonisolated Synchronous Buck/Boost Converter Schematic System
Modeling
Rev. 0 | Page 4 of 20
Application Note
AN-1319
MODELING
Designing the compensator for the constant current and constant
voltage feedback loops requires linearized models for each of
the components in the loops. This section presents these models.
INDUCTOR
VCTRL
BATTERY
RL
VOUT
RS
TO PGIA
RB
TO PGDA
RC
LINEAR REGULATORS
The small signal model for a linear voltage controlled current
source is a transconductor with transconductance, GM (see
Figure 4). The transfer function for this block is
GM
I OUT
=
  s 1
VCTRL
VIN FOR BUCK
VRAMP (CHARGE) MODE
AV =
CAP
CO
VIN
FOR BOOST
VRAMP (DISCHARGE) MODE
Figure 5. Averaged Linearized Circuit for the Nonisolated Synchronous
Buck/Boost Converter
In buck (charge) mode, the buck/boost converter has the
averaged transfer function shown in Equation 1.
GPC(s) =
VOUT
VCTRL
=
V IN
V RAMP
×
RD (RC CO  s 1)
s2 CO  LO (RD  RC )  s (LO  RD  RC CO  RL CO (RD  RC )) RD  RL )
(1)
where RD is the load resistance of the converter (RB + RS).
where:
τ is the time constant of the block and models its finite bandwidth.
IOUT is the output current.
VCTRL is the input control voltage.
IOUT
12685-004
VCTRL
GM
AV =
12685-005
The small signal model for a battery is simply its internal
resistance, RB. While the battery can be modeled as the series
connection of the internal resistance and the storage capacitance,
at any frequency of interest, the impedance of this connection is
approximately RB. Therefore, for simplicity, the storage
capacitance is treated as a small signal short.
GPC(s) =
LO
AV
In boost (discharge) mode, the buck/boost converter has the
averaged transfer function shown in Equation 2.
GPC(s) =
VOUT
= − V IN
VCTRL
V RAMP
×
RD (RC CO  s 1)
s2 CO  LO (RD  RC )  s (LO  RD  RC CO  RL CO (RD  RC ))  RD  RL )
(2)
where RD is the load resistance of the converter (RB + RS).
Figure 4. Linear Voltage Controlled Current Source, Small Signal Model
SWITCHING POWER CONVERTERS
Figure 5 shows the averaged linearized circuit of the nonisolated
synchronous buck/boost converter. In this model circuit, the dc
voltage bus, the PWM, and the switches are modeled as a linear
amplifier with a voltage gain of AV. In buck (charge) mode, the
gain of the amplifier is VIN/VRAMP, where VIN is the voltage of the
dc bus and VRAMP is the peak-to-peak voltage of the PWM ramp
(4 V p-p in the ADP1972).
These equations show that the averaged linearized model of the
buck/boost converter is a second order system with two poles
and one zero. The two poles are generated by the LC filter, while
the zero is caused by the series resistance of the output capacitor.
Depending on the values of the circuit components, the transfer
functions may be overdamped or underdamped. In the
underdamped case, the poles are located at the resonant frequency
of the LC filter, while, in the overdamped case, the poles may
not be coincident. Figure 6 and Figure 7 show approximate
Bode plots of the buck/boost converter.
In boost (discharge) mode, the gain of the amplifier is −VIN/VRAMP.
The linearized circuit in Figure 5 includes the parasitic resistance
of the output inductor, RL, and the output capacitor, RC, of the
power converter because they affect the transfer function of the
converter.
Rev. 0 | Page 5 of 20
AN-1319
Application Note
GP(s)
fPP1
fPP2
POWER CONVERTER
COMPENSATOR
fPZ
VVSET
VCTRL
GC(s)
VOUT
GPC(s)
RB
RS + RB
VBAT
VBVMEA
–20dB/dec
GDA
–40dB/dec
12685-009
AD8450/
AD8451 PGDA
PLANT GP(s)
Figure 9. CV Loop Block Diagram for a Voltage Out Power Converter
12685-006
f
–20dB/dec
The loop gain transfer function for the CC loop with a voltage
out power converter is
Figure 6. Magnitude Bode Plot of the Linearized Model of the Nonisolated
Synchronous Buck/Boost Converter
fPP1
fPP2
RS
RS + RB
LCC(s) = GC(s) × GPC(s) × GIA ×
fPZ
(3)
where:
GC(s) is the transfer function of the compensator.
GPC(s) is the transfer function of the power converter.
GIA is the gain of the current sense instrumentation amplifier of
the AD8450 or the AD8451.
RS is the value of the current sense shunt resistor.
RB is the value of the internal resistance of the battery.
f
0°
–90°
Similarly, the loop gain transfer function for the CV loop is
–180°
12685-007
GP(s)
RB
RS + R B
LCV(s) = GC(s) × GPC(s) × GDA ×
(4)
where GDA is the gain of the voltage sense difference amplifier of
the AD8450 or the AD8451.
Figure 7. Phase Bode Plot of the Linearized Model of the Nonisolated
Synchronous Buck/Boost Converter
CC AND CV FEEDBACK LOOPS
Current Out Power Converters
Given the CC-CV algorithm, only one of the two feedback
loops can be in control of the power converter at any given
time. Therefore, the two feedback loops can be modeled
independently. These loops are modeled slightly differently
depending on the output variable of the power converter, that is,
if the power converter output variable is a voltage or a current.
For a current out power converter, like the linear regulator in
Figure 2, the CC and CV loops are modeled using the block
diagrams shown in Figure 10 and Figure 11.
POWER CONVERTER
COMPENSATOR
VISET
Voltage Out Power Converters
VCTRL
GC(s)
GPC(s)
IBAT
VISMEA
GIA
RS
AD8450/
AD8451 PGIA
SHUNT RESISTOR
12685-010
VRS
For a voltage out power converter, like the nonisolated
synchronous buck/boost power converter in Figure 3, the CC
and CV loops are modeled using the block diagrams shown in
Figure 8 and Figure 9.
PLANT GP(s)
Figure 10. CC Loop Block Diagram for a Current Out Power Converter
VISET
GC(s)
POWER CONVERTER
VOUT
VCTRL
GPC(s)
1
RS + RB
VVSET
VISMEA
VRS
RS
AD8450/
AD8451 PGIA
SHUNT RESISTOR
PLANT GP(s)
GC(s)
POWER CONVERTER
VCTRL
IBAT
GPC(s)
RB
VBAT
VBVMEA
12685-008
GIA
COMPENSATOR
IBAT
GDA
AD8450/
AD8451 PGDA
PLANT GP(s)
Figure 8. CC Loop Block Diagram for a Voltage Out Power Converter
Figure 11. CV Loop Block Diagram for a Current Out Power Converter
Rev. 0 | Page 6 of 20
12685-011
COMPENSATOR
Application Note
AN-1319
The loop gain transfer function for the CC loop with a current
out power converter is
LCC(s) = GC(s) × GPC(s) × RS × GIA
(5)
where:
GC(s) is the transfer function of the compensator.
GPC(s) is the transfer function of the power converter.
RS is the value of the current sense shunt resistor.
GIA is the gain of the current sense instrumentation amplifier of
the AD8450 or the AD8451.
Similarly, the loop gain transfer function for the CV loop is
LCV(s) = GC (s) × GPC(s) × RB × GDA
(6)
where GDA is the gain of the voltage sense difference amplifier of
the AD8450 or the AD8451, and RB is the value of the internal
resistance of the battery.
Rev. 0 | Page 7 of 20
AN-1319
Application Note
COMPENSATOR DESIGN
Step 2: Determine the Transfer Function of the
Uncompensated System, GP(s), and Calculate the
Location of the Poles and Zeros
The following steps establish the procedure to design the
compensator of the CC and CV loops using the AD8450 or
the AD8451:
1.
2.
3.
4.
5.
6.
7.
Gather the parameters of the power converter and the
analog front end (AD8450 or AD8451).
Determine the transfer function of the
uncompensated system, GP(s), and calculate the
location of the poles and zeros.
Determine the crossover frequency of the system.
Select the compensator type.
Select the compensator pole and zero locations.
Set the gain of the compensator at the crossover
frequency.
Calculate the compensator component values.
UNCOMPENSATED SYSTEM
When designing the compensator for a system, all the elements
in the feedback loop, excluding the compensator, form the
uncompensated system or plant. For the CC and CV loops, see
the uncompensated transfer functions, GP(s), in Table 1.
COMPENSATOR DESIGN STEPS FOR THE
SYNCHRONOUS BUCK/BOOST CONVERTER
Step 1: Gather the Parameters for the Power Converter
and the Analog Front End (AD8450 or AD8451)
The first step in designing the compensator for the CC and CV
feedback loops is to extract the relevant parameters of the
buck/boost converter and the analog front end of the AD8450
or the AD8451. These parameters include
•
•
•
•
•
•
•
•
•
•
•
•
LO, the output inductor of the converter
CO, the output capacitor of the converter
RL, the ESR of the output inductor
RC, the ESR of the output capacitor
RB, the ESR of the battery
RS, the value of the shunt resistor
RD, the load resistance (RS + RB) of the converter
fS, the switching frequency of the converter
VIN, the dc bus voltage
VRAMP, the ramp voltage
GIA, the PGIA gain of the AD8450 or the AD8451
GDA, the PGDA gain of the AD8450 or the AD8451
After gathering the parameters of the power converter and front
end of the AD8450 or the AD8451, determine the exact transfer
function of the uncompensated system or plant. Because the
nonisolated buck/boost converter is a voltage out power converter,
for the CC feedback loop, the transfer function of the plant is
GP-CC(s) =
(R + RB ) × (s × RC × CO + 1)
VIN
RS
× S
× GIA ×
(7)
a × s2 + b × s + c
RS + RB
VRAMP
where:
a = LO × CO × (RD + RC)
b = RD × RC × CO + LO + RL × CO × (RD + RC)
c = RD + R L
For the CV feedback loop, the transfer function of the plant is
GP-CV(s) =
(R + RB ) × (s × RC × CO + 1)
VIN
RB
× S
× GDA ×
(8)
a × s2 + b × s + c
VRAMP
RS + RB
where:
a = LO × CO × (RD + RC)
b = RD × RC × CO + LO + RL × CO × (RD + RC)
c = RD + R L
Due to the equivalent series resistance (ESR) of the output
capacitor of the converter, the transfer functions, GP(s), have a
zero at
fPZ =
1
2π × RC × CO
Due to the LC filter of the converter, the transfer functions,
GP(s), have two poles at
fPP1, fPP2 =
b ± b2 − 4 × a × c
2 × a × 2π
Constant Voltage
Voltage Out
GP−CC(s) = GPC(s) × GIA ×
RS
RS + RB
GP−CV(s) = GPC(s) × GDA ×
RB
RS + RB
(10)
Pole PP1 is the lower frequency pole, and it may be coincident with
Pole PP2, depending on the value of the b2 − 4 × a × c term.
Table 1. Summary of Uncompensated Systems
Converter/Loop
Constant Current
(9)
Current Out
GP−CC(s) = GPC(s) × GIA × RS
GP−CV(s) = GPC(s) × GDA × RB
Rev. 0 | Page 8 of 20
Application Note
AN-1319
Note that, unlike most buck/boost converters, it is not safe to
assume that the converter poles are at fPP1 = fPP2 = 1/√(LC). The
battery and the shunt resistor present a heavy load to the
converter that may move the converter poles away from 1/√(LC).
Step 3: Determine the Crossover Frequency of the System
Next, choose the crossover frequency of the system. To guarantee
the accuracy of the linearized averaged model of the power
converter, set the crossover frequency of the system to 10 times
lower than the switching frequency. See Equation 11.
fC =
fS
10
(11)
After selecting fC, verify that the frequencies of the slowest
converter pole (fPP1) are at least a decade lower than the
crossover frequency of the system. This requirement reduces
the adverse effects of the LC resonance near crossover.
Therefore, verify that
f
fPP1 ≤ C
10
(12)
If this condition is not met, consider increasing the switching
frequency, fS, or decreasing the frequency of the converter
poles, fPP1 and fPP2.
Note that, at a given gain for the PGIA and PGDA of the AD8450
or the AD8451, there exists a maximum frequency that the
analog front end can support. See the AD8450 and AD8451
Bandwidth Considerations section for the exact specifications.
Step 4: Select the Compensator Type
Depending on the location of fC, with respect to fPP1, fPP2, and fPZ,
select the appropriate compensator type. For the nonisolated
buck/boost converter, proportional integral (PI) Type II and
proportional integral derivative (PID) Type III compensators
are recommended. An integral Type I compensator may also be
used, but it is not recommended due to the low system bandwidths
it requires.
To maximize the open-loop gain of the CC and CV feedback
loops, and therefore the accuracy of the system, the compensator
must have a pole at the origin (the integral component of the
compensator). This pole at the origin adds a −90° phase shift to
the feedback loops, destabilizing them if their crossover frequency
is higher than the converter poles, that is, if fC > fPP1, fPP2. As a
result, in addition to adding a pole at the origin, the compensator
must provide a phase boost near the crossover frequency, fC.
The Type II compensator implements a pole at the origin, a zero
at a frequency below the crossover frequency of the system, and
a high frequency pole. This compensator is used when the
magnitude of the uncompensated system rolls off at −20 dB/dec
at the desired crossover frequency, fC. Figure 12, Figure 13, and
Figure 14 show the magnitude Bode plots of the uncompensated
system, GP(s), the Type II compensator, GC(s), and the
compensated system, L(s), respectively.
The Type III compensator implements a pole at the origin, two
zeros at frequencies below the crossover frequency of the
system, and two high frequency poles. This compensator is used
when the magnitude of the uncompensated system rolls off at
−40 dB/dec at the desired crossover frequency, fC. Figure 15,
Figure 16, and Figure 17 show the magnitude Bode plots of the
uncompensated system, GP(s), the Type III compensator, GC(s),
and the compensated system, L(s), respectively.
The high frequency poles of the Type II and Type III compensators
are usually placed at a frequency between fC and fS. These poles
help attenuate the output ripple of the power converter without
significantly affecting the phase margin of the compensated system.
Rev. 0 | Page 9 of 20
AN-1319
Application Note
GP(s)
GP(s)
–20dB/dec
–40dB/dec
–40dB/dec
–20dB/dec
fPZ
fC
f
fPP1
Figure 12. Magnitude Bode Plot of the Uncompensated System GP(s)
fPP2 fC fPZ
12685-015
fPP1,
fPP2
–20dB/dec
12685-012
f
Figure 15. Magnitude Bode Plot of the Uncompensated System GP(s)
GC(s)
GC(s)
–20dB/
dec
–20dB/dec
–20dB/dec
+20dB/dec
f
fC
fS
–20dB/dec
2
f
fPP2 fC
fPP1
Figure 13. Magnitude Bode Plot of the Type II Compensator GC(s)
12685-016
fPZ
12685-013
fPP1 fPP1,
fPP2
2
fS
fPZ
2
L(s)
Figure 16. Magnitude Bode Plot of the Type III Compensator GC(s)
–20dB/dec
L(s)
–20dB/dec
–40dB/dec
f
–20dB/dec
f
–40dB/dec
fC
fS
2
–40dB/dec
fPP1
Figure 14. Magnitude Bode Plot of the Compensated System L(S)
fPP2 fC fPZ
fS
2
12685-017
fPZ
12685-014
fPP1 fPP1,
fPP2
2
Figure 17. Magnitude Bode Plot of the Compensated System L(S)
Figure 12 through Figure 17 show that the selection between
the Type II and Type III compensator depends on where the
zero of the converter is located with respect to where the
crossover frequency of the feedback loops is located. Therefore,
the recommended rules for compensator type selection are
•
•
If fPZ × 3 ≤ fC, use a Type II compensator
If fPZ × 3 ≥ fC, use a Type III compensator
The Type II and Type III compensators are implemented using the
CC and CV error amplifiers of the AD8450 or the AD8451
(Amplifier A1 and Amplifier A2 in Figure 1). In charge mode, the
CC and CV feedback loops require inverting compensators to
maintain negative feedback because there are no inversions in the
loops. Figure 18 and Figure 19 show practical implementations of
inverting Type II and Type III compensators.
In discharge mode, the converter is operated in boost mode,
and the transfer function of the converter exhibits an inversion.
Despite this inversion, in discharge mode, the CC feedback loop
requires an inverting compensator because the MODE pin of
the AD8450 and the AD8451 changes the gain polarity of the
PGIA. However, because the gain polarity of the PGDA is not
altered by the MODE pin in discharge mode, the CV loop
requires a noninverting integrator. Figure 20 and Figure 21
show practical implementations of the noninverting Type II and
Type III compensators.
Note that if the same resistor and capacitor values are used in
the inverting and noninverting compensators, the transfer
functions of the compensators of a given type are identical,
except for the polarity of their dc gain.
Rev. 0 | Page 10 of 20
Application Note
AN-1319
C1
fCZ = min 

R2
C2
VINT
Figure 18. Inverting Type II Compensator
C3
fCP = fC × 5 =
C1
C2
VINT
Figure 19. Inverting Type III Compensator
C1
R3
C2
R1
VSET
Place the Type III compensator zeros at the same frequency of
the poles of the converter, such that they cancel each other out.
See Equation 15 and Equation 16.
BVMEA
R2
12685-020
C1
C2
Figure 20. Noninverting Type II Compensator
R3
VSET
R1
R2
R1
R2
fCZ1 = fPP1 =
1
× τ1
2π
(15)
fCZ2 = fPP1 =
1
× τ2
2π
(16)
Place the Type III compensator poles at fS/2 to attenuate the
switching ripple of the converter. If the power converter zero is
located near the crossover frequency, fC, place one of the
compensator poles at fPZ to cancel out the zero. This cancellation
prevents the zero of the converter from altering the magnitude
of the compensated system at fC. These restrictions place the
poles at
C3
C1
(14)
Type III Compensator Pole and Zero Locations
VINT
R1
fS
1
=
2
2π × τ2
Figure 12 through Figure 14 illustrate the suggested pole and
zero placements for the Type II compensator. The uncompensated
system magnitude Bode plot shows the magnitude of GP(s)
rolling off at −20 dB/dec at fC, because the zero of the converter
is at a frequency below the crossover frequency. Also, at fC, the
slope of the compensator is approximately 0; therefore, the loop
gain of the compensated system, L(s), crosses over with a slope
of −20 dB/dec, ensuring a stable system.
R2
12685-019
R1
ISMEA/
BVMEA
ISET/
VSET
R3
(13)
To limit phase margin degradation, place the pole of the
compensator at a frequency significantly higher than frequency
fC. Additionally, place the pole at a frequency below fS to
attenuate the switching ripple of the converter. These
constraints place the pole at
R1
12685-018
ISMEA/
BVMEA
ISET/
VSET
fC f PP1 
1
,
 =
2 
2π × τ1
 10
C2
VINT
BVMEA
fS
1

, f PZ  =
2π × τ3
2

fCP1 = min 

C1
R3
C3
12685-021
C2
fCP2 =
Figure 21. Noninverting Type III Compensator
Step 5: Choose the Compensator Pole and Zero Locations
The next step in compensating the CC and the CV feedback
loops is to choose the locations of the compensator poles and
zeros and to calculate their corresponding time constants.
Type II Compensator Pole and Zero Locations
Place the Type II compensator zero at a frequency significantly
below fC, such that the compensator pole at the origin induces
only a small phase shift at the crossover frequency. Additionally,
place the zero before the poles of the power converter to avoid a
−180° phase shift in the loop gain before the crossover frequency.
These two restrictions place the zero of the compensator at
fS
1
=
2
2π × τ4
(17)
(18)
Figure 15 through Figure 17 illustrate the suggested pole and
zero placements for the Type III compensator. The uncompensated
system Bode plot shows the magnitude of GP(s) rolling off at
−40 dB/dec at fC, because the zero of the converter is at a
frequency above the crossover frequency. Also, at fC, the slope of
the compensator is approximately +20 dB/dec; therefore, the
loop gain of the compensated system, L(s), crosses over with a
slope of −20 dB/dec, ensuring a stable system.
Rev. 0 | Page 11 of 20
AN-1319
Application Note
Step 6: Set the Gain of the Compensator at the Crossover
Frequency
The crossover frequency of the CC and CV feedback loops is
established by setting the gain of their compensator at the
crossover frequency. At fC, set the gain of the compensator to
the inverse of the gain of the uncompensated system.
GC ( fC ) =
1
GP ( fC )
The transfer functions of the noninverting compensators are
identical to the transfer functions of the inverting compensators,
except for the inversion, which is not present. The transfer
function of the noninverting Type II compensator is shown in
Equation 24. The transfer function of the noninverting Type III
compensator is shown in Equation 25.
GCII-NON-INV(s) = −GCII-INV(s) =
(19)
1  s  R2  C2 
 1  s  R2  C1  C2 


C1  C2 

For the CC feedback loop, the gain of the uncompensated
system at fC is
GP  fC  =
1
V  G  RS
= IN
×
GC ( fC )
V RAMP
2   f C  C O  RC 2  1
b  2   f C 2  c  a  2   f C 2 2
Note that the transfer functions of the compensators are only
dependent on impedance ratios; therefore, there is a degree of
freedom in the calculation of the component values. A practical
starting point is to select a reasonable value for C2 (such as 10 nF)
and then calculate the other values.
1
V  G  RB
= IN
×
GC ( fC )
VRAMP
Type II Component Values
(21)
After choosing the value for C2, the remaining component
values for the Type II compensator are calculated using
Equation 26 through Equation 28.
where:
a = LO × CO × (RD + RC)
b = RD + RC + CO + LO + RL + CO (RD + RC)
c = RD + R L
R2 =
1
C2
C1 = C2 ×
Step 7: Calculate the Compensator Component Values
Figure 18 through Figure 21 show practical implementations of the
inverting and noninverting Type II and Type III compensators. The
transfer function of the inverting Type II compensator is shown
in Equation 22. The transfer function of the inverting Type III
compensator is shown in Equation 23.
GCII−INV(s) = −
−
1  s  R2  C2  =
1
×
s  R1  C1  C2 
 1  s  R2  C1  C2 


C1  C2 

K 1  s  1
×
s
1  s  2
R1 =
τ1 =
1
2   f CZ
τ2 =
1
2   f CP
(22)
1
×
s  R1  R2   C2  C3 
1  s  R3  C2   1  s  R2  C1
 1  s  R3  C2  C3    1  s  C1  R1  R2 

 

C2  C3  
R1  R2 

K 1  s  1  1  s  2 
×
s
1  s  3  1  s  4 
(23)
Rev. 0 | Page 12 of 20
(26)
2
1   2
GP  fC 
1  j  2   f C  1

2   f C  C1  C2  1  j  2   f C   2
where:
GCIII−INV(s) = −
=−
(24)
1
×
s  R1  R2   C2  C3 
1  s  R3  C2   1  s  R2  C1
 1  s  R3  C2  C3    1  s  C1  R1  R2 

 

C2  C3  
R1  R2 

K 1  s  1  1  s  2 
=− ×
(25)
s
1  s  3  1  s  4 
(20)
For the CV feedback loop, the gain of the uncompensated
system at fC is
2   f C  CO  RC 2  1
b  2   f C 2  c  a 2   f C 2 2
K 1  s  1
×
s
1  s  2
GCIII-NON-INV(s) = −GCIII-INV(s) =
where:
a = LO × CO × (RD + RC)
b = RD + RC + CO + LO + RL + CO (RD + RC)
c = RD + R L
GP  fC  =
=−
1
×
s  R1  C1  C2 
(27)
(28)
Application Note
AN-1319
Type III Component Values
After choosing the value for C2, the remaining component
values for the Type III compensator are calculated similarly to
the Type II compensator, using Equation 29 through Equation 33.
R3 =
1
C2
C3 = C2 ×
C1 =
3
1   3
2
R2
R1 = R2 ×
R2 =
(29)
If any of the component values of the compensators are too
large or too small to be practical, the component values may be
scaled because the compensator transfer functions only depend
on impedance ratios. If necessary, adjust the component values
by scaling all the impedances equally, that is, scale all resistances
by a factor α and all capacitances by 1/α.
(30)
(31)
4
2   4
(32)
GP  f C  1  j  2  f C  1  1  j  2  f C  2 
 2 

2  f C  C2  C3  1  j  2  f C  3  1  j  2  f C  4  
 2   4 
where:
τ1 =
1
2   f CZ1
τ2 =
1
2   f CZ2
τ3 =
1
2  f CP1
τ4 =
1
2   f CP2
Rev. 0 | Page 13 of 20
(33)
AN-1319
Application Note
AD8450 AND AD8451 BANDWIDTH CONSIDERATIONS
The sense amplifiers of the AD8450 and the AD8451, the PGIA
and the PGDA, have finite bandwidths that are gain dependent.
These finite bandwidths impose an upper limit on the crossover
frequency of the CC and CV feedback loops. The recommended
upper limit for the crossover frequency of a loop is a tenth of
the bandwidth of the sense amplifier of the loop. Table 2
summarizes the recommended upper limit for the crossover
frequency of the CC and CV feedback loops of the AD8450.
Note that the AD8451 has one PGIA gain of 26 and one PGDA
gain of 0.8, as shown in Table 3.
If extra filtering is required, the bandwidths of the sense
amplifiers can be reduced by means of input filters. Note that
reducing the bandwidth of the sense amplifiers also reduces the
upper limit for the crossover frequency of the CC and CV
feedback loops.
Table 2. Recommended Maximum Crossover Frequency for
the CC and CV Feedback Loops of the AD8450
CC Feedback Loop
PGIA Gain Maximum CC fC
(kHz)
26
150
66
63
133
33
200
22
CV Feedback Loop
PGDA Gain Maximum CV fC
(kHz)
0.2
42
0.27
73
0.4
94
0.8
100
Table 3. Recommended Maximum Crossover Frequency for
the CC and CV Feedback Loops of the AD8451
CC Feedback Loop
PGIA Gain Maximum CC fC
(kHz)
26
150
Rev. 0 | Page 14 of 20
CV Feedback Loop
PGDA Gain Maximum CV fC
(kHz)
0.8
100
Application Note
AN-1319
DESIGN EXAMPLES
Step 3: Determine the Crossover Frequency of the System
CONSTANT CURRENT FEEDBACK LOOP WITH A
TYPE II COMPENSATOR
Step 1: Gather the Parameters of the Power Converter
and the Analog Front End (AD8450 or AD8451)
Table 4 shows the parameters of the power converter and analog
front end for this example.
Set the crossover frequency of the loop a decade below the
switching frequency, such that
fC = 10 kHz
Using Equation 11, verify that the crossover frequency is not
close to any potential resonance.
Table 4. Power Converter and Analog Front End Parameters
for the Type II Design Example
Parameter
LO
CO
RL
RC
RB
RS
fS
GIA
VIN
VRAMP
Value
150 μH
1000 μF
70 mΩ
50 mΩ
50 mΩ
20 mΩ
100 kHz
200
24 V
4V
fPP1 = 154 Hz < 1 kHz =
fC
10
Step 4: Select the Compensator Type
Select a Type II compensator because the crossover frequency of
the loop, fC, is located after the converter poles and after three
times the frequency of the converter zero.
Step 5: Select the Compensator Pole and Zero Locations
Using Equation 13 and Equation 14, the compensator pole and
zero are at
fCZ = 77 Hz
fCP = 50 kHz
Step 2: Calculate the Location of the Uncompensated
System Poles and Zeros
Step 6: Set the Gain of the Compensator at the Crossover
Frequency
After gathering the parameters of the power converter and the
front end of the AD8450 or the AD8451, determine the exact
transfer function of the uncompensated system or plant. Using
Equation 7 and Equation 8, the denominator coefficients of the
transfer function of the plant are
Using Equation 20, the magnitude of the uncompensated
system at fC is
GP ( f ) = 1.104
Step 7: Calculate the Compensator Component Values
Using Equation 26 through Equation 28, the component values
for the Type II compensator are
a = 1.8 × 10−8
b = 1.61 × 10−4
R1 = 22.3 kΩ
c = 1.4
Using Equation 9 and Equation 10, the power converter poles are at
fPP1 = 154 kHz
R2 = 20.6 kΩ
C1 = 154 pF
C2 = 100 nF
fPP2 = 1.28 kHz
The power converter zero is at
fPZ = 3.18 kHz
Rev. 0 | Page 15 of 20
AN-1319
Application Note
Figure 22, Figure 23, and Figure 24 show the magnitude Bode
plots of the uncompensated system, the compensator, and the
compensated system, respectively. As expected, the compensated
system crosses over with a slope of −20 dB/dec at fC = 10 kHz,
guaranteeing a stable system.
GP(s)
50
CONSTANT CURRENT FEEDBACK LOOP WITH A
TYPE III COMPENSATOR
Step 1: Gather the Parameters of the Power Converter
and the Analog Front End (AD8450 or AD8451)
Table 5 shows the parameters of the power converter and analog
front end for this example.
Table 5. Power Converter and Analog Front End Parameters
for Type III Design Example
40
30
20
10
0
–10
12685-022
–20
–30
–40
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
Figure 22. Magnitude Bode Plot of the Uncompensated System GP(s)
Parameter
LO
CO
RL
RC
RB
RS
fS
GIA
VIN
VRAMP
Value
150 μH
250 μF
70 mΩ
7.5 mΩ
50 mΩ
20 mΩ
100 kHz
200
24 V
4V
Step 2: Calculate the Location of the Uncompensated
System Poles and Zeros
GC(s)
20
After gathering the parameters of the power converter and front
end of the AD8450 or the AD8451, determine the exact transfer
function of the uncompensated system or plant. Using Equation 7
through Equation 8, the denominator coefficients of the transfer
function of the plant are
15
10
05
0
–05
a = 2.9 × 10−9
–10
b = 1.51 × 10−4
–15
c = 0.14
12685-023
–20
–25
–30
10
100
1k
10k
FREQUENCY (Hz)
100k
Using Equation 9 and Equation 10, the power converter poles are at
fPP1 = 150 Hz
1M
fPP2 = 8.15 kHz
Figure 23. Magnitude Bode Plot of the Type II Compensator GC(s)
The power converter zero is at
L(s)
fPZ = 85 kHz
80
60
Step 3: Determine the Crossover Frequency of the System
40
Set the crossover frequency of the loop a decade below the
switching frequency, such that
20
fC = 10 kHz
0
Using Equation 12, verify that the crossover frequency is not
close to any potential resonance.
–20
–40
fPP1 = 150 Hz < 1 kHz =
–80
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
12685-024
–60
Figure 24. Magnitude Bode Plot of the Compensated System L(S)
fC
10
Step 4: Select the Compensator Type
Select a Type III compensator because the crossover frequency
of the loop, fC, is located after the converter poles and before
three times the frequency of the converter zero.
Rev. 0 | Page 16 of 20
Application Note
AN-1319
Step 5: Select the Compensator Pole and Zero Locations
50
Using Equation 15 through Equation 18, the compensator zeros
are at
GP(s)
40
30
fCZ1 = 150 Hz
20
fCZ2 = 8.15 kHz
10
0
Because fS/2 < fPZ, the poles are located at
–10
fCP1 = fCP2 = 50 kHz
Step 6: Calculate the Plant Gain at Crossover
–30
Using Equation 20, the magnitude of the uncompensated
system at fC is
–40
12685-025
–20
–50
G P  f C  = 1.63
–60
10
Step 7: Calculate the Compensator Component Values
100
1k
10k
FREQUENCY (Hz)
100k
1M
Figure 25. Magnitude Bode Plot of the Uncompensated System GP(s)
Using Equation 29 through Equation 33, the component values
for the Type III Compensator are
20
R1 = 43 kΩ
15
R2 = 220 kΩ
10
R3 = 106 kΩ
5
C1 = 88.6 pF
0
C2 = 10 nF
GC(s)
–5
C3 = 30 pF
–10
–15
–20
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
12685-026
Figure 25, Figure 26, and Figure 27 show the magnitude Bode
plots of the uncompensated system, the compensator, and the
uncompensated system, respectively. As expected, the compensated
system crosses over with a slope of −20 dB/dec at fC = 10 kHz,
guaranteeing a stable system.
Figure 26. Magnitude Bode Plot of the Type III Compensator GC(s)
L(s)
80
60
40
20
0
–20
–40
12685-027
–60
–80
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
Figure 27. Magnitude Bode Plot of the Compensated System L(S)
Rev. 0 | Page 17 of 20
AN-1319
Application Note
SPECIAL CASES
CROSSOVER FREQUENCY BEFORE fPP2
Step 2: Determine the Crossover Frequency of the System
There may be cases where the desired crossover frequency
occurs between the two converter poles, fPP1 and fPP2. In these
cases, use a Type II compensator. To maintain a 65° phase
margin, use a Type II compensator if fPP1 < fC < fC × 3 < fPP2.
Choose the crossover frequency of the CC and CV feedback
loops to be at least five times lower than the bandwidth of the
linear regulator, as shown in Equation 37.
To calculate the pole and zero locations of the compensator and
the component values of the associated circuit, follow the same
steps described in the Compensator Design section.
LINEAR REGULATORS
Linear regulators are often used in low power battery testing
and formation systems due to their simplicity. Linear regulators
can be either voltage controlled voltage sources or voltage
controlled current sources. A linear voltage controlled current
source is modeled with the following transfer function:
GM
τ× s +1
(34)
where GM is the regulator transconductance, and the pole
models the regulator finite bandwidth. For frequencies
significantly below this pole, the power converter has a uniform
gain and approximately 0° of phase.
For the CC feedback loop, the transfer function of the
uncompensated system is
GP−CC(s) = GIA ×
GM
× RS
τ× s +1
(35)
Step 3: Calculate the Gain of the Compensator at the
Crossover Frequency
The crossover frequency of the CC and CV feedback loops is
established by setting the gain of their compensator at the
crossover frequency. At fC, set the gain of the compensator to
the inverse of the gain of the uncompensated system. See
Equation 38.
GC ( fC ) =
1
GP ( f C )
(38)
If fC is sufficiently lower than the bandwidth of the linear
regulator, for the CC feedback loop, the gain of the
uncompensated system is approximately
For the CV feedback loop, the gain of the uncompensated
system is approximately
Step 4: Choose the Compensator Type
(36)
Step 1: Gather the Parameters of the Uncompensated
System
The first step in designing the compensator for the CC and CV
feedback loops is to extract the relevant parameters of the linear
regulator and the analog front end of the AD8450 or the AD8451.
These parameters include
•
•
•
•
This condition minimizes the impact of the bandwidth of the
linear regulator on the stability of the feedback loops.
GP −CV ( fC ) = GDA × GM × RB
STEPS FOR COMPENSATING LINEAR REGULATORS
•
•
(37)
GP −CC ( fC ) = GIA × GM × RS
For the CV feedback loop, the transfer function of the
uncompensated system is
GM
× RB
GP−CV(s) = GDA ×
τ× s +1
1
2π × τ × 5
GM, the transconductance of the linear regulator
τ, the time constant of the linear regulator (bandwidth =
1/(2π × τ))
RB, the ESR of the battery
RS, the value of the shunt resistor
GIA, the PGIA gain of the AD8450 or the AD8451
GDA, the PGDA gain of the AD8450 or the AD8451
Because the phase shift of the uncompensated system at fC is
less than −25° (due to fC being five times less than the regulator
bandwidth), a Type I or integral compensator is appropriate.
Type I compensators implement a single pole at the origin and
have a −90° phase shift for all frequencies. Therefore, at the
crossover frequency, the phase of the loop is less than −125°,
guaranteeing a phase margin of at least 65°. The transfer
function for a Type I compensator is
GCI(s) = ±
K
s
(39)
In charge mode, the CC and CV feedback loops require
inverting compensators to maintain negative feedback. Figure 28
shows a practical implementation of an inverting Type I
compensator.
C
ISMEA/
BVMEA
R
VINT
ISET/
VSET
Figure 28. Inverting Type I Compensator
Rev. 0 | Page 18 of 20
12685-028
GLPC(s) =
fC ≤
Application Note
AN-1319
The transfer function of the inverting Type I compensator is
GCI-INV(s) = −
1
R ×C × s
For the CC feedback loop, this condition translates to
(40)
In discharge mode, the CC feedback loop requires an inverting
compensator, but the CV feedback loop requires a noninverting
compensator. Figure 29 shows a practical implementation of a
noninverting Type I compensator.
R × C × 2π × fC = GIA × GM × RS
For the CV feedback loop, this condition implies
R × C × 2π × fC = GDA × GM × RB
Therefore, for a given fC, the product of R and C is chosen such that
R×C=
C
VINT
R
12685-029
BVMEA
C
R=
The transfer function of the noninverting Type I compensator is
1
R ×C × s
(41)
The R and C values of the Type I compensators shown in Figure 28
and Figure 29 set the gain of the compensator at a given
frequency, as well as the crossover frequency of the CC and CV
feedback loops. The crossover frequency of the loops occurs
when
1
GC ( fC )
GIA × RS × GM
C × 2π × fC
(44)
For the CV feedback loop, use Equation 45.
Step 5: Calculate the Compensator Component Values
GP ( f C ) =
(43)
For the CC feedback loop, use Equation 44.
Figure 29. Noninverting Type I Compensator
GCI-NON-INV(s) =
fC × 2π
Because the transfer function of the Type I compensator depends
on the product of R and C, there is a degree of freedom in the
calculation of the component values. A practical starting point
is to select a reasonable value for C (such as 10 nF) and then
calculate the value of R to achieve the desired crossover frequency.
R
VSET
GP ( f C )
(42)
Rev. 0 | Page 19 of 20
R = GDA × RB × GM
C × 2π × fC
(45)
AN-1319
Application Note
CONCLUSION
This application note describes a methodology to design the
compensators of the CC and CV feedback loops present in a
battery formation and test system using the AD8450 or
the AD8451 analog front end and controller. The note presents
models for linear regulators and buck/boost power converters, a
step-by-step design procedure, and two specific design
examples. While the design procedure described in this
document always results in a stable system, the optimum
solution is not guaranteed. Further optimization of the suggested
designs can improve the response of the feedback loops.
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN12685-0-12/14(0)
Rev. 0 | Page 20 of 20
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