CN-0123: Automated Calibration Technique That Reduces the AD5360 16-Channel, 16-Bit DAC Offset Voltage to Less Than 1 mV PDF

Circuit Note
CN-0123
Devices Connected/Referenced
Circuit Designs Using Analog Devices Products
Apply these product pairings quickly and with confidence.
For more information and/or support call 1-800-AnalogD
(1-800-262-5643) or visit www.analog.com/circuit.
AD5360
16-Channel, 16-Bit Voltage-Output DAC
AD790
High Speed Precision Comparator
AD8597
Low Noise Amplifier
ADR435
5 V Ultralow Noise Voltage Reference
Automated Calibration Technique That Reduces the AD5360 16-Channel, 16-Bit DAC
Offset Voltage to Less Than 1 mV
CIRCUIT FUNCTION AND BENEFITS
CIRCUIT DESCRIPTION
The circuit described in this document and shown in Figure 1
provides a method of calibrating that removes an unknown
offset error. When using high precision, high resolution DACs
in industrial process control and instrumentation applications,
low offset is often a critical specification. The circuit uses builtin features of the AD5360 in conjunction with an external
comparator and an operational amplifier to determine if the
DAC output voltages are above or below a ground reference
signal. With the amount of offset known, the user can adjust the
codes sent to the DAC to null out the offset.
The AD5360 is a 16 channel, 16-bit digital to analog converter.
The nominal output range is ±10 V when used with a 5 V
reference. The AD5360 contains two offset DACs. Each offset
DAC is connected to a group of eight DACs and is used to
adjust the mid-scale point of the output span. For example, the
offset DAC can be programmed to change the output span from
±10 V to −8 V to +12 V, or other values as required by the
application.
INPUT
AND
SPECIAL
FUNCTION
REGISTERS
SERIAL
INTERFACE
DVCC
VSS
VDD
AD5360
+5V
–15V
+15V
DAC 0
REGISTER
DAC 0
VOUT0
DAC 1
REGISTER
DAC 1
VOUT1
DAC 14
REGISTER
DAC 14
VOUT14
DAC 15
REGISTER
DAC 15
VOUT15
GPIO
MUX
MON_OUT
VREF0 VREF1
GPIO
AGND DGND
+5V
+5V
+15V
1kΩ
+15V LATCH
ADR435
+5V
VLOGIC
+15V
510Ω
+VS
AD790
AD8597
100nF
–15V
–15V
08521-001
–VS
Figure 1. Autocalibration Circuit for AD5360 DAC That Reduces the Offset Voltage to Less Than 1 mV
(Simplified Schematic: Decoupling and All Connections Not Shown).
Rev.0
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CN-0123
Circuit Note
The AD5360 is factory trimmed to have a very low offset. The
trimming is done with the offset DAC at its default value, and
the offset error due to the offset DAC is effectively removed.
When the value of the offset DAC is changed from its default
value, however, its offset error affects the offset error of the
main DACs.
The circuit described here allows for the offset error of the main
DACs to be measured and calibrated out under those conditions.
The circuit relies on a general-purpose I/O pin and an on-chip
monitor multiplexer. The GPIO (general-purpose I/O) pin is set
as an input, and by reading the GPIO internal register, the logic
status of the GPIO pin is determined. The analog multiplexer is
programmable to connect any of the 16 DAC outputs to a single
pin, the MON_OUT pin. The multiplexer switches have a low
but finite on resistance, RON so that any current drawn from
MON_OUT creates a voltage drop across RON and, therefore, an
output error. To prevent this, MON_OUT is buffered by an
AD8597 low-noise amplifier. The low pass filter following the
amplifier reduces the amount of noise seen by the AD790 high
speed precision comparator and prevents false triggering.
The AD790 can be operated on ±15 V supplies, making it
compatible with the AD5360. The AD790 also requires an
additional +5 V VLOGIC supply when operating on ±15 V supplies.
In addition, the AD790 has a 15 V maximum differential input
voltage; therefore, it can tolerate the output voltages from the
AD5360 without attenuation. In Figure 1, the comparator output
is low if the channel offset is positive, indicating that the output
voltage must be reduced to remove the offset. The comparator
output is high if the channel offset is negative, indicating that
the output voltage must be increased to remove the offset.
To calibrate a DAC, the DAC channel is loaded with the digital
value, which should ideally provide a voltage equal to SIGGND
(that is, 0 V). In this example the DAC channel is assumed to
have a negative offset. Reading the GPIO register shows that the
comparator output is low, indicating that the input must be
incremented until the output toggles. As progressively higher
codes are written to the DAC input register, the GPIO register is
read until the comparator trips to the high state. The AD790 has
a maximum hysteresis band of 0.65 mV; therefore, reducing the
DAC code again allows a more accurate determination of the
DAC offset.
When comparator output trips back to the low state, SIGGND
is somewhere between those two codes. Due to the errors of the
components used in the circuit, there is typically a span of three
or four codes between comparator trip points. There is no way
to determine exactly which code gives the lowest offset output
using this method, but by picking a code that is the average of
the two trip point codes, the DAC channel offset is typically less
than 1 mV from SIGGND.
Excellent layout, grounding, and decoupling techniques must be
used to achieve the desired performance from the circuits
discussed in this note (see MT-031 Tutorial and MT-101 Tutorial).
As a minimum, a 4-layer PCB should be used with one ground
plane layer, one power plane layer, and two signal layers.
COMMON VARIATIONS
The AD5362 is an 8-channel version of the AD5360. The AD5361
and AD5363 are 14-bit versions of the AD5360 and AD5362,
respectively. The AD8599 is a dual version of the AD8597.
The circuit described here can be used with any of the AD536x
devices mentioned above. The reference can also be changed to
give different output ranges if required.
LEARN MORE
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of "AGND" and "DGND," Analog Devices.
MT-083 Tutorial, Comparators, Analog Devices.
MT-101 Tutorial, Decoupling Techniques, Analog Devices.
Data Sheets and Evaluation Boards
AD5360
AD5361
AD5362
AD5363
AD5360, AD5361, AD5362, AD5363 Evaluation Board
AD8597
AD790
ADR435
REVISION HISTORY
9/09—Revision 0: Initial Version
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CN08521-0-9/09(0)
Rev. 0 | Page 2 of 2
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