AN-1341: Using the AD8436 True RMS to DC Converter (Rev. 0) PDF

AN-1341
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Using the AD8436 True RMS to DC Converter
by James Staley
INTRODUCTION
The AD8436 from Analog Devices, Inc., is a complete true rms
measurement system on a chip. It offers designers the greatest
flexibility in meeting their application needs, combined with the
smallest overall footprint and lowest power available in an off
the shelf analog ac measurement front end.
The AD8436 is comprised of three completely independent
circuit blocks, as shown in Figure 1. The rail-to-rail field effect
transistor (FET) input amplifier, high dynamic range, true zero
rms computing core, and precision rail-to-rail output amplifier
facilitate measurement systems that operate from high impedance
voltage sources in the megohm range. In concert, these three
components of the AD8436 deliver highly accurate dc output
voltages equivalent to the rms value of applied input voltages at
levels near zero and, with appropriate input attenuation, well
above its maximum rated input voltage.
INPUT
BUFFER
(IBUF)
For applications in which the signal source is sensitive to loading
errors, or a boost in gain is required to amplify low level ac
signals, the integrated FET input amplifier matches real-world
signals to the converter core. There is no need for additional
components or space on already crowded printed circuit boards
(PCBs).
The precision dc output amplifier for driving low impedance
loads optimizes performance between the converter core and
the next stage. The output buffer is also configurable as a SallenKey or other active filter architecture, further reducing settling
time to levels not feasible in other analog or even digital rms to
dc solutions.
All of this functionality is available in RoHS compliant, 20-lead
LFCSPs and QSOPs.
VCC
OUTPUT
BUFFER
(OBUF)
RMS CORE
(RMS)
CCF
CAVG
100kΩ
SUM
RMS
RV-I
8kΩ
IGND
100kΩ
RMS CORE
VEE
+
RI-V
16kΩ
10pF
Figure 1. The Three Independent Circuits
OGND
OUT
Throughout this application note, components that are internal
to the AD8436, such as the RV-I and RI-V resistors, are denoted by
subscripted text. External components, such as the CAVG, CIN,
and CCF capacitors, are denoted by all capital letters to remain
consistent with evaluation boards.
IBUFGN
10kΩ
IBUFIN–
–
IBUFIN+
+
IBUFOUT
OBUFIN+
GENERAL DESCRIPTION
OBUFIN–
Referring to Figure 2, the heart of the AD8436 is a true zero, high
dynamic range, analog computing core. The design of this core
ensures continuous operation from ≤1 mV to 3 V voltage levels.
The AD8436 rms core features a higher dynamic range and faster,
more consistent response than previous Analog Devices rms to
dc converter products.
10kΩ
FET OP AMP
+
16kΩ
OBUFOUT
–
DC BUFFER
AD8436
12788-002
ERMS
12788-001
+
Figure 2. Functional Block Diagram of the AD8436 RMS to DC Converter
SCOPE
This application note is a how-to, in-depth exploration of
configuration options of the AD8436, while at the same time
striving for clarity. Feedback from engineers is incorporated
wherever possible and most of the circuits shown are verified
experimentally. Simulations or other forms of vaporware are
minimal. Many applications and ideas are inspired by email and
questions received from the many AD8436 users.
Rev. 0 | Page 1 of 16
AN-1341
Application Note
TABLE OF CONTENTS
Introduction ...................................................................................... 1
Using the Precision DC Output Buffer ......................................9
General Description ......................................................................... 1
Single Supply Operation ............................................................ 10
Scope .................................................................................................. 1
AC Current, Ground Fault, and 3-Phase Applications.............. 11
Revision History ............................................................................... 2
Measuring Hazardous Circuits ................................................. 11
Using the Core .................................................................................. 3
Using the RMS Pin ....................................................................... 3
Low Cost, 3-Phase Power Line Monitor—Optimizing Settling
Time ............................................................................................. 12
Basic AC-Coupled Trimming ..................................................... 3
Error Sources................................................................................... 15
DC Coupling the Input—Calibration and VOS Trim ............... 3
PCB Precautions ......................................................................... 16
SUM Pin......................................................................................... 4
Conclusion .................................................................................. 16
Capacitor Selection ...................................................................... 4
Related Links ............................................................................... 16
Output Connections—Core ........................................................ 6
Input and Output Op Amps ........................................................ 6
REVISION HISTORY
1/15—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Application Note
AN-1341
USING THE CORE
USING THE RMS PIN
BASIC AC-COUPLED TRIMMING
For those applications where cost and power consumption are the
primary concerns, only the core and two external capacitors
(excluding supply filtering) are required for basic ac-to-dc
conversion (see Figure 3 and the Single Supply Operation section).
Input voltages are typically ac-coupled to the RMS pin via a low
leakage capacitor (CIN), such as a metallized polyester or a good
quality tantalum capacitor. The applied voltage is converted to
current by the 8 kΩ resistor, RV-I, connected to the rms core. The
junction of RV-I and the core behaves somewhat like that of an op
amp configured as a summing amplifier, with some important
exceptions. For additional details, see the Capacitor Selection
section and the SUM Pin section where these differences are
explained. Because the thin film resistors, RV-I and RI-V, are ratio
matched and have ratiometric temperature characteristics, the
RMS pin is preferred as the input port for nearly all applications.
For external calibration, increase the value of the internal resistor,
RV-I, by inserting a low value metal film resistor between the signal
source and the RMS pin (200 Ω shown in Figure 4). Add a small
trimmer (RTRIM = 500 Ω in Figure 4) from the OGND pin to
ground. The AD8436 is calibrated by adjusting RTRIM with no
interaction with VOS.
VCC
CAVG
VCC
100kΩ
i
OUT
RV-I
8kΩ
RI-V
16kΩ
AD8436
VEE
VCC
i
100kΩ
(OPTIONAL)
Figure 4. Basic AC-Coupled Calibration
RMS
AC INPUT
VOLTAGE
DC COUPLING THE INPUT—CALIBRATION AND
VOS TRIM
OUT
RI-V
16kΩ
AD8436
VEE
VEE
OGND
RTRIM
500Ω
IGND
VEE
RV-I
8kΩ
OGND
VEE
CLPF
12788-003
CIN
RMS CORE
CLPF
12788-004
SIGNAL
SOURCE
100kΩ
(OPTIONAL)
200Ω RMS
CCF
SUM
100kΩ
RMS CORE
IGND
VEE
CIN
CCF
VCC
CCF
Figure 3. Minimum of Input/Output Connections (Emphasized Lines are the
Signal Path)
The input impedance at the RMS pin is the 8 kΩ voltage to current
conversion resistor (RV-I), referred to the IGND pin. If the input
is provided by a voltage source (that is, ZOUT = 0 Ω) the input
amplitude is unaffected by the relatively low 8 kΩ input resistance.
Capacitor CIN blocks dc current to and from the core, resulting
in negligibly small input referred offset voltages (for example,
VOS < ±10 μV). A high voltage capacitor is often used for the
CIN capacitor to help protect the AD8436 from hazardous voltages
such as ordinary household line voltages. Note that the FET input
buffer amplifier (IBUF) easily accommodates voltages from
nonzero resistive voltages sources, even those in the megohm
range. See the Input and Output Op Amps section for more
details.
When the input pin, RMS, of the AD8436 is dc-coupled to the
signal source, the combined dc and ac signals are processed as
ac + dc (see the SUM Pin—Multiple Input Characteristics section).
However, a small dc offset error (VOS) is created from minor dc
error sources in the core. The AD8436 is tested for VOS error in
production and guaranteed to data sheet specifications (<0.25 mV
for the B grade model and <0.5 mV for the A grade and J grade
models).
VCC
CAVG
CCF
CAVG
CCF
VCC
VCC
SUM
100kΩ
i
RMS CORE
RV-I
8kΩ
OUT
RI-V
16kΩ
AD8436
VEE
VCC
RVOST
500kΩ
(OPTIONAL)
VEE
RTRIM
200Ω RMS
AC + DC
INPUT
100kΩ
IGND
OGND
VEE
RVOSCS
499kΩ
RVOS
160Ω
12788-005
CAVG
VCC
SUM
VCC
CAVG
CCF
CAVG
Figure 5. Optional Input Connections for AC + DC Signals, Including Offset
Correction and Trim (VCC = +5 V, VEE = −5 V)
Rev. 0 | Page 3 of 16
AN-1341
Application Note
Figure 5 shows how to reduce any small VOS error by inserting a
small fixed resistor (RVOS = 160 Ω) in series with RI-V from the
OGND pin to ground. A current source consisting of the RVOST
trimmer with RVOSCS in series with the wiper is connected to
the OGND pin. The current source adds or subtracts a small
current nulling the offset current. Because the value of RI-V changes
with the addition of 160 Ω, Resistor RI-V must be compensated
with an external resistor connected between the RMS pin and the
signal source. A 200 Ω trimmer provides a more than adequate
trim range. To trim the device, remove any input signal and set
the dc output at the OUT pin to 0 V using RVOST. Next, apply a
300 mV, 1 kHz test signal to the 200 Ω trimmer and adjust for
300 mV dc at the OUT pin. If there is interaction between the
two adjustments, repeat the sequence until the desired result is
achieved.
SUM PIN
The SUM pin provides direct access to the rms core, effectively
altering the range of usable input voltages. Direct core access is
an optional feature unique to the AD8436.
For range shifting applications, increasing or decreasing RV-I
optimizes the desired errors over the default range inherent to
the embedded 8 kΩ value. Resistors with values less than the
internal 8 kΩ at the RMS pin increase the core input current;
the opposite result occurs with values greater than 8 kΩ. This
method of core scaling is a convenience, obviating external
attenuators or amplifiers. When combined with the adjustable
gain feature of the on-chip FET input amplifier and scalability
of the output voltage, low level voltages convert to greater current
levels without degrading settling time, as is the case when using
the RMS pin.
When using the SUM pin, one must consider temperature error
due to mismatch of the temperature coefficients of RV-I and RI-V.
The temperature coefficients of resistance (TCR) of the fabricated
silicon chromium (SiCr) resistors used in the AD8436 is <50 ppm.
If temperature drift error is important, use resistors with equal
TCRs. For low current applications, consider supplementing the
8 kΩ RV-I by adding just enough external resistance to equal the
desired value.
SUM Pin—Multiple Input Characteristics
Using separate V to I resistors, multiple voltages can be applied to
the SUM pin. However, unlike a typical op amp summing circuit
where the output is the arithmetic sum of input voltages, input
voltages applied to the SUM pin convert to the residual sum of
squares (RSS) of the input voltages. For two rms voltages, VRMS1 and
VRMS2,
VOUT  (VRMS1 )2  (VRMS2 )2
As an example, if one introduces a dc voltage of 100 mV to a
100 mV, 60 Hz ac voltage to the SUM pin, the dc component
does not generate an ac conversion offset at the output (that is,
200 mV). Rather, the result is 141 mV dc.
VOUT  (0.1 V ac)2  (0.1 V dc)2  0.141 V dc
Fortunately, there is a way to add fixed offset voltages to the
output of the AD8436, which is discussed in the DC Matching
Devices with Dissimilar Common-Mode Voltages section).
CAPACITOR SELECTION
External capacitors are required to decouple the input (CIN), to
compute the mean rms dc (CAVG), and for ripple suppression
(CLPF) at the OUT pin. Capacitor CLPF is also used when the
AD8436 is configured to yield the average rectified value. The
CAVG and CFILT capacitors, in conjunction with the internal 5 kΩ
and 16 kΩ charging resistors, directly control the settling time
of the converter. Capacitor CCF is a secondary averaging capacitor,
and forms the second pole of a passive RC low-pass filter. The
3 dB frequency of Capacitor CCF must be adjusted to no less than
3× the frequency of the primary pole frequency controlled by
CAVG.
Input Decoupling Capacitor (CIN)
Capacitor CIN connects to the V to I resistor to form a high-pass
filter, referred to IGND (common). The series attenuation of XC
approaches 0 Ω as the input frequency (f) approaches ∞. Or, to
put it another way, the capacitor value must increase to accommodate lower frequencies.
A very simple way to calculate the value of CIN is to express the
required error in ohms reactance as a percent of RV-I, and then
calculate the equivalent capacitance at the required frequency.
In this instance, where RV-I is 8 kΩ, the equivalent series resistor
for 1% error is RERR = 80 Ω and the minimum capacitor value is
CIN ≈ 1/ωRERR = 1/2π50 × 80 = 40 μF
The nearest standard value is 47 μF, in which case the capacitive
reactance is 68 Ω at 50 Hz, and the error is 0.85%.
Rev. 0 | Page 4 of 16
Application Note
AN-1341
100
Averaging Capacitor (CAVG)
Basic rms to dc conversion requires an external capacitor (CAVG)
for providing the mean (or average) value of rms. Use any of the
following three methods to select the value of the CAVG capacitor.
10
SEE TEXT
1
1.0%
0.1
5%
0.01
0.0001
0.1
1
10
100
1k
FREQUENCY (Hz)
10k
In terms of circuit topology, the averaging capacitor is placed
following the squaring and root extraction cell of the rms core.
Its sole function is to store enough charge from each of a succession
of the absolute value periods to develop a ripple free dc voltage.
The best way to visualize this function is to think of the filter
capacitor found in any dc power supply. Because the capacitor is
located within the implicit conversion feedback loop, the resulting
dc voltage constitutes the rms to dc conversion. For most applications requiring an rms result, the capacitor value needs only
to be large enough to average sufficient periods of the input
waveform to yield the maximum permissible error at the
frequency of interest.
CAVG (μF)
200/f
70/f
20/f
Method 3 (see Figure 6) is a graphical method displayed as a
log-log graph. The orange mark and dashed lines define the
point where the desired frequency (50 Hz) and value of CAVG
coincide on a log-log plot, whereas the blue diagonal line is the
error value (1%). Figure 6 is useful for selecting smaller averaging
capacitors for higher frequency applications.
µF
50
0.4
7µ
F
SEE
TEXT
1µ
F
F
2.2
µ
4.7
µ
10
µF
F
–0.5
22
µF
–1.0
CAVG = 0.22µF
–1.5
10
50 60
100
FREQUENCY (Hz)
Figure 7. Conversion Error vs. Frequency for Various Values of CAVG (Method 1)
Rev. 0 | Page 5 of 16
1k
12788-007
CONVERSION ERROR (%)
0
2
1M
Figure 6. CAVG vs. Frequency for Three Error Values (Method 3)
Table 1. CAVG vs. Frequency (f) Equations for Three RMS
Error Values (Method 2)
–2.0
100k
12788-006
0.001
Method 2 is an rms error expression from Table 1. Use one of
these three empirically derived expressions for a more precise
numerical result, then select the next higher standard value
capacitor.
RMS Error (%)
0.1
1
5
0.1%
CAVG (µF)
Method 1 is an easy graphical method shown in Figure 7. Simply
locate the desired frequency and error level on the horizontal
and vertical axes and draw lines from these points. Choose or
estimate the higher capacitor value where the lines intersect.
The orange marks and dashed lines are two examples where the
frequencies of interest are 50 Hz and 60 Hz, and the acceptable
error is 1%. The nearest standard capacitor value is 2.2 μF for
both examples.
AN-1341
Application Note
Low-Pass Filter Capacitor (CLPF)
The output impedance of the AD8436 is 16 kΩ referred to ground.
Residual ripple errors following rms conversion are most effectively
filtered at this point because the voltage source drive charges the
capacitor, CLPF, through a 5 kΩ resistor unaffected by drive
impedance. The output structure is a current source driving a
16 kΩ resistor that transforms to a voltage source with 16 kΩ
resistance. When a capacitor is connected to this point (in this
instance, the OUT pin) it becomes a low-pass filter referred to
ground. Experiments have shown that a combination of 10 μF for
the CAVG capacitor and 3.3 μF for the CLPF capacitor reduces the
ripple to <1 mV, peak-to-peak, for a 300 mV rms, 60 Hz sine
wave input waveform. Noise and settling time improve with the
output buffer configured as a two-pole, Sallen-Key low-pass
filter, as shown in the Low Cost, 3-Phase Power Line Monitor—
Optimizing Settling Time section.
Crest Factor Capacitor (CCF)
Crest factor errors are not an issue for most sinusoidal applications; however, such errors are important if low duty cycle
square waves or pulses are to be measured accurately.
Thanks to steady improvements in dielectrics, leading ceramic
capacitor manufacturers now offer high temperature surfacemount capacitors (150°C, size 1210) for the automotive market.
Capacitance values as high as 47 μF are available. Look for parts
with X8L dielectric and high temperature, usually automotive
and/or downhole petroleum drilling applications. These capacitors
are physically more stable, without the microphonic characteristics
exhibited by all other ceramic capacitor dielectrics.
Film capacitors are also suitable for averaging capacitor applications
and have shrunk in the past few years; however, many are not
suitable for reflow assembly. Users must beware of temperature
limitations of the application as well.
OUTPUT CONNECTIONS—CORE
Minimal Output Configuration
The product at the rms core output is in the form of a current at
nominally half of the input current and, in turn, converts to a
voltage generated across the 16 kΩ resistor, RI-V. The conversion is
expressed as follows:
For voltage, the conversion is expressed as
The CCF pin is a node connected to a tap on the 5 kΩ resistor that
charges the CAVG capacitor. Connecting a capacitor at this point
adds a pole to the rms low-pass filter. The exact value of the
CCF capacitor is not critical, but must be <10% of the value of
CAVG to ensure the two capacitors behave as a two-pole, RC lowpass filter. A 100 nF filter is used in the AD8436-EVALZ evaluation
board and is the default value used for most characterization data.
Capacitor Styles
RMS to dc converter data sheets recommend using high quality
capacitors for the CAVG capacitor, but say very little as to what
exactly is critical for the application. Legacy Analog Devices data
sheets recommend tantalum style capacitors, and these are still a
good choice, but today more options are available. The most critical
attributes of the averaging capacitor are dc leakage (terminal to
terminal resistance) and, to a lesser extent, dielectric absorption
(see Figure 30).
VOUT(DC) = eRMSIN
For current in amperes, the conversion is expressed as
IDCOUT = (IRMSIN/2) A
where IRMSIN = (eRMSIN/8 kΩ).
If the output voltage is applied directly to the following stage,
the output appears as a voltage source with 16 kΩ series resistance.
Using the RV-I and RI-V Resistors to Scale the AD8436 for
Higher or Lower Voltages
The effective range of the AD8436 is a factor of the input and
output currents. As an example, consider a nominal input voltage
of 300 mV (the specified trim voltage). If the input voltage of
interest is 600 mV, one can simply double the resistor values of
RV-I and RI-V to double the usable input voltage of the AD8436.
The effective range being a factor of the input and output currents
is a useful property of the AD8436 in instances where the AD8436
replaces an older rms to dc converter with higher signal levels.
It is important to remember that these properties are used to
shift the rms to dc voltage amplitudes. The dynamic range is
unaffected.
INPUT AND OUTPUT OP AMPS
Referring to Figure 2, the on-chip AD8436 input and output op
amps are designed to interface to the rms core. IBUF is a unity gain
FET input op amp with a pin-selectable option for 2× gain. The
output op amp is a precision bipolar dc amplifier with a 16 kΩ
current matching resistor in series with its noninverting input. By
adding a few resistors, users can configure either or both op amps
over a wide range of gain settings.
Rev. 0 | Page 6 of 16
Application Note
AN-1341
The high input impedance input buffer features a metal-oxide
semiconductor field effect transistor (MOSFET) input architecture,
with a pair of closely matched 10 kΩ resistors for 6 dB of pinselectable gain. The user has a choice of unity or 6 dB gain settings
by simple pin selection, or externally adjustable gain up to 40 dB
using a single external resistor.
The unity gain option is shown in Figure 8, whereas Figure 9
shows the pin connections for 6 dB gain. Note the external, 10 MΩ,
user supplied resistor required to bias the gate voltage, from the
IBUFIN+ pin to the IGND pin.
Embedded across the internal, 10 kΩ feedback resistor is a
small capacitor for noise reduction and stability. Figure 10 and
Figure 11 show the large signal and small signal bandwidth,
respectively, using the 0 dB and 6 dB on-board gain options.
15
12
eIN = 3.5mV rms
9
GAIN = 6dB
6
GAIN (dB)
FET Input Buffer—Internal Gain Options
3
GAIN = 0dB
0
–3
16
–6
IBUFV+
3
0.47µF
4
5
–9
(CORE)
–12
IBUFOUT
IBUFIN–
G=1
–15
100
IBUFIN+
10kΩ
10MΩ
11
12
6
Figure 8. AC-Coupled High Impedance Input Buffer Configured for Unity Gain
for LFCSP
16
IBUFV+
3
0.47µF
4
5
RMS
GAIN = 0dB
0
–3
–9
IBUFOUT
–12
G = 6dB
IBUFIN–
–15
IBUFIN+
100
10kΩ
10pF
IGND
12788-009
6
1k
10k
100k
FREQUENCY (Hz)
1M
5M
Figure 11. AD8436 FET Input Buffer Large Signal Bandwidth for Gain = 0 dB
and 6 dB
10kΩ
IBUFGN
3
–6
(CORE)
10MΩ
11
GAIN = 6dB
6
GAIN (dB)
NC = NO CONNECT
2
5M
eIN = 300mV rms
9
12788-008
NC
4.7µF
1M
15
10kΩ
IBUFGN
10k
100k
FREQUENCY (Hz)
Figure 10. AD8436 FET Input Buffer Small Signal Bandwidth for Both Internal
Gain Options
10pF
IGND
1k
12788-010
4.7µF
RMS
12788-011
2
Figure 9. AC-Coupled High Impedance Input Amplifier Configured for G = 6 dB for
LFCSP
Rev. 0 | Page 7 of 16
AN-1341
Application Note
Configuring IBUF for Input Gain Greater than 6 dB
50
The AD8436 can provide gain across a wide range of input voltages
and frequencies. A gain value of 10× or 100× extends the usable
range of measureable ac voltages down to the tens of microvolts.
Larger gain values require a single external resistor connected
from the IBUFIN− pin to ground. As with any op amp, the gain
conforms to the classic gain bandwidth (GBW) 20 dB/decade
relationship. The internal feedback resistor is 10 kΩ, laser trimmed
to 1% precision. For gains greater than 6 dB, calculate a new value
for the gain resistor, RG (see Figure 12), using a transposition of the
noninverting gain equation, G = RFB/RG + 1.
GAIN = 40dB
40
GAIN (dB)
30
–10
RMS
3
4
0.47µF
5
(CORE)
IBUFOUT
6dB < G < 40dB
IBUFIN–
IBUFIN+
10kΩ
10MΩ
11
10pF
IGND
10kΩ
6
A RESISTOR VALUE FOR 6dB TO 40dB GAIN
12788-012
IBUFGN
Figure 12. FET Input Buffer Configured for External Gain Adjustment for LFCSP
The bandwidth of the IBUF is more than sufficient for audio
and power applications. Table 2 shows five gain values and their
corresponding values of RG. Figure 13 shows the resulting
corresponding GBW plots.
Table 2. Setting the Gain of the Input Buffer
6
10
20
40
2
3.16
10
100
RG
(Calculated)
∞
10 kΩ
4.1625 kΩ
1.101 kΩ
101 Ω
RG,
Nearest
1%
Leave
open
10 kΩ
4.64 kΩ
1.1 kΩ
101 Ω
1k
100k
10k
FREQUENCY (Hz)
1M
5M
12788-013
eIN = 1mV rms
The salient feature of a FET input amplifier is the low impact of
loading on virtually any real life signal source. Many source
circuits utilize resistive dividers to scale high voltages such as
utility line or power supply to usable values for measurement
purposes. Digital multimeters (DMMs) and other range switching
instruments are good examples of such applications. A complete
description of all the possible variations in design of DMM front
ends is beyond the scope of this document; however, Figure 14
shows a schematic of a front end of such an instrument to illustrate
the essential characteristics. A high voltage capacitor (keep safety in
mind when selecting a component) protects against unexpected dc
voltages. Diode pairs and a small series resistor clamp overvoltages
to the supplies, protecting the low voltage rms to dc converter
input. Finally, a large resistor network with one or more taps serves
to reduce input voltages to within the useable range of the AD8436.
Finally, note that the 1 kΩ resistor in the array serves to refer the
input to the IGND pin.
OPTIONAL
HV
CAPACITOR
Measured 3 dB
Bandwidth (see
Figure 13)
2.82 MHz
1MΩ
16
IBUFV+
2
3
100kΩ
1.29 MHz
639 kHz
160 kHz
15 kHz
4
10kΩ
1kΩ
RMS
(CORE)
4.7µF
5
IBUFOUT
IBUFIN–
IBUFIN+
SELECTOR
SWITCH
10kΩ
11
10pF
IGND
10kΩ
IBUFGN
6
12788-014
2
4.7µF
Gain
(×)
1
GAIN = 0dB
Figure 13. Gain and Bandwidth Options for the FET Input Buffer for Five
Values of Gain
16
Gain
(dB)
0
GAIN = 6dB
–20
100
IBUFV+
1SELECT
GAIN = 10dB
10
0
10 4
RG =
G −1
RG1
GAIN = 20dB
20
Figure 14. Range Switching for the LFCSP AD8436 FET Input Buffer
Operation of the AD8436 with Very Low Input Voltages
The AD8436 converts input voltages less than 1 mV, but such
low voltages result in longer power-up settling. This behavior is
caused by the lower input current level available to charge the
CAVG capacitor to its operating bias voltage. The power-up time
for a 1 mV rms input signal is typically 30 sec and increases with
lower input voltages.
Rev. 0 | Page 8 of 16
Application Note
AN-1341
USING THE PRECISION DC OUTPUT BUFFER
Configuring the AD8436 Output Op Amp as a Unity Gain
Buffer
As shown in Figure 16, the AD8436 output buffer is a precision
bipolar op amp with very low dc offset voltage error. A 16 kΩ
resistor from the op amp output to the inverting input nulls any
offset voltage created by the bias current from the noninverting
input through RI-V, minimizing any offset voltage error.
VCC
CCF
VCC
IBUFGN
10pF
10kΩ
10kΩ
RMS IN
Configuring the AD8436 Precision Output Op Amp for
Gain
4.7µF
–
IBUFIN+
+
0.47µF
FET OP AMP
DC BUFFER
–
IBUFOUT
OBUFIN+
+
OBUFOUT
13
OBUFIN–
Figure 16. Precision DC Output Buffer Showing Cancellation of the CommonMode Bias Current Component of VOS
33µF
ROUT
16kΩ
100kΩ
VEE
IBUFIN–
ROUT
1.6kΩ
OGND
100kΩ
IBIAS
16kΩ
8
OBUFOUT
OUT
RMS CORE
16kΩ
OBUFIN–
12788-015
IGND
14
RI-V
16kΩ
OGND
RIN
8kΩ
12
AD8436
Figure 15. AD8436 Optimized for Low Voltage Input to Enhance the Turn On
It is further recommended to use the minimum necessary value of
averaging capacitor to meet the rms error requirement. Then, filter
any residual ripple by increasing the value of the CLPF capacitor.
For applications requiring additional post conversion drive
voltage, increase the gain of the output buffer by inserting a
totem pole network at the inverting input, as shown in Figure 17.
This configuration is useful when the input signal must first be
downscaled to avoid overdrive of the core or when an application
requires higher dc output. Ensure that the total load resistance
is greater than 500 Ω and the resistance of the totem pole gain
network is between 10 kΩ and 25 kΩ. Add additional resistance
at the noninverting input to compensate for the change in bias
current induced VOS resulting from the parallel combined
resistance of the output network.
Table 3 shows resistor values and gain results for 3× and 10× gain.
Combining a 5× increase in core input current with the built in
2× gain of the input buffer yields a total of 10× gain overall,
reducing the turn on settling time for a 1 mV input from
approximately 30 sec to <3 sec. Before using this method, note
that this method reduces the maximum usable input voltage,
resulting in a tradeoff when implementing this method.
CORE
OUT EIN RCOMP
9
OBUFIN+
12
RI–V
16kΩ
OGND
14
16kΩ
IBIAS
IBIAS
13
OBUFOUT EOUT
OBUFIN–
8
RLO
RHI
12788-017
CAVG
OBUFIN+
9
IBIAS
RIN
1.6kΩ SUM
RMS
OUT
CORE
3.3µF
12788-016
In core only applications where power-on delay is an issue, the
effect is mitigated by scaling RV-I and RI-V for more current. One
approach is to configure the input buffer for gain, thus increasing the core input current for the same applied input voltage.
Connecting external resistors to the SUM and OUT pins with
appropriately scaled values (less than 8 kΩ and 16 kΩ, respectively)
restores the overall gain to unity. Figure 15 shows a suitable
configuration with the input buffer configured for 6 dB gain and
matching values for the input and output resistors, RIN and ROUT,
to optimize temperature stability.
Figure 17. LFCSP AD8436 Precision DC Op Amp Buffer Configured for Greater
than Unity Gain
Table 3. External Resistor Values for 3× and 10× Gain
RHI (kΩ)
6.65
9.09
RLO (kΩ)
3.32
1
RCOMP (kΩ)
2.21
909
Gain,
(RHI/RLO) + 1
3.003×
10.09×
EIN (V)
3.3
0.3
EOUT (Calculated)
9.91
3.03
Rev. 0 | Page 9 of 16
EOUT (Measured)
9.91
3.03
Gain (Measured)
3.003
10.09
Error (%)
0.1
0.17
AN-1341
Application Note
DC Matching Devices with Dissimilar Common-Mode
Voltages
SINGLE SUPPLY OPERATION
The AD8436 is eminently usable with single-supply applications
such as handheld DMMs and other small portable instruments.
Input signals in these applications are typically referred to 0 V (that
is, electrical ground). A matched pair of 100 kΩ resistors connected
internally between VCC and VEE provides the midsupply dc
reference for the AD8436 circuitry and is user accessible at the
IGND pin. The inputs of the RMS and SUM pins are both referred
to IGND; however, an external resistor (10 MΩ is recommended)
is required between the IBUF+ pin and the IGND pin to bias the
FET op amp. A 10 μF decoupling capacitor between the IGND pin
and VEE (ground) is recommended.
Matching the AD8436 devices with dissimilar dc common-mode
input devices, such as analog-to-digital converters (ADCs) or
pulse-width modulators (PWMs), is not uncommon and requires
a means to shift the common-mode voltage of the output of the
AD8436 (see the block diagram in Figure 19).
VCC
PWM,
ADC
VCC
HIGH
VOLTAGE
AC INPUT
RMS
Minimal Input Connection
CAVG
VCC
IGND
RMS CORE
1/2 VCC
10µF
VEE
RMS
OUT1
RV-I
8kΩ
AD8436
RI-V
16Ω
OGND
12788-019
The most straightforward solution is to offset the AD8436 dc
output voltage with an offset enabled amplifier such as a differential
or instrumentation amplifier. Figure 20 shows a circuit diagram
with an AD8237 instrumentation amplifier configured as buffer
and level shifter between the AD8436 and the following device in
the signal path. The AD8237 is a low current, single-supply, rail-torail in-amp ideally suited for this application. Apply the required
offset voltage directly to the reference input and the AD8436
output to the noninverting input of the AD8237. Then, connect
the inverting input to ground. A single device accomplishes
buffering and level shifting and the input protection to the
AD8436 is unaffected.
CCF
VCC
VBIAS
Figure 19. Block Diagram of the AD8436 Driving an External Device
Requiring a Fixed DC Input Bias
CCF
SUM
1/2 VCC
CIN
VBIAS
VEE
VCC
i
OUT
AD8436
Figure 18 shows the basic ac input connection. The CIN capacitor
is necessary to isolate the ground referred ac input from the
midsupply IGND referred to the RMS pin.
CAVG
BIASED
INPUT
CIN
VEE
12788-018
VEE
1THE OUT PIN IS REFERRED TO GND REGARDLESS
OF SUPPLY VOLTAGE CONFIGURATION.
Figure 18. Basic Input Connections with Single Supply
+5V
CAVG
RIN
8kΩ
RTRIM
500Ω
VCC
CAVG
SUM
IGND
RMS
CORE
CLPF
10µF
RMS
IBUFOUT
OUT
OGND
+VS
AD8237
–IN
ROUT
16kΩ
IBUFIN+
BW
+IN
CLPF
IBUFIN–
0.1µF
VOUT
AD8436
VBIAS
100mV
205Ω
10kΩ
0.1µF
Figure 20. Schematic of AD8436 Configured for Single Supply and a Biased Output Load
Rev. 0 | Page 10 of 16
OUT
REF
–VS
VEE
IN
FB
+5V
12788-020
RIN
7.87kΩ
Application Note
AN-1341
AC CURRENT, GROUND FAULT, AND 3-PHASE APPLICATIONS
A common 60 W incandescent lamp serves as a useful current
load for bench experiments. A Tektronix current probe with
scope or power supply monitors current levels, and voltages are
measured with Agilent or Fluke secondary standard DMMs.
The load current for a 60 W bulb is nominally 0.5 A rms, and
the test bulb measured 0.499 A rms.
MEASURING HAZARDOUS CIRCUITS
Configuring a Current Transformer
Monolithic rms to dc converters such as the AD8436 are well
suited for current measurements using low cost toroidal current
transformers. Toroidal current transformers have existed for a
long time in a wide variety of current ranges from milliamperes
up to hundreds of amperes.
Detecting Ground Fault Current
The emergence of international stringent safety standards for ac
connected equipment is well known. In the USA, UL is a voluntary
association that tests electrical safety across a broad range of
industries and grants approvals which manufacturers apply to
their wares to ensure the buyer that the equipment they are
buying has been independently tested for safety.
Shaped like a donut, the transformer primary is one or more
turns through the center of a ferromagnetic core wrapped with
several hundred turns. The one or more passes of wire in series
with the load through the center hole of the toroid is the primary,
and the several hundred turns around the core are the secondary.
Figure 21 is a schematic of the toroidal current transformer
essentials.
FOR A CURRENT TRANSFORMER,
THE CURRENT CARRYING CONDUCTOR
IS THE PRIMARY, AND BEHAVES AS ONE TURN
The IEC is an international organization that establishes safety
standards for the European community and is recognized as the
gold standard for a host of safety and regulatory limitations.
THE SECONDARY IS WOUND
AROUND THE TOROIDAL
CORE, FOR EXAMPLE
1000 TURNS
IL
1000
One of these limits is leakage current, which is the ac line current
from any power supplies that can pass through the user when
the user is exposed to conductive components of the equipment.
Such current leakage is known as ground fault current (or residual
current in the European community) and can be lethal. Figure 22 is
a schematic of a ground fault current path. Note that ground fault
currents are too small to trip the primary protection device, yet
large enough to be lethal to human beings. Exterior house wiring in
the USA must be equipped with special circuit breakers known as
ground fault circuit interrupters (GFCI).
BURDEN
RESISTOR
12788-021
IL
RL
Figure 21. Toroidal Current Transformer Schematic
The AD8436 is the ideal interface for a current transformer
because the transformer secondary current must all flow through
the burden resistor for maximum accuracy, and the FET input
buffer introduces no shunt current path error. Figure 23 shows
the circuit of a bench setup for experimenting with current
transformers and how best to use them.
LEAKAGE CURRENT
(GROUND FAULT)
PATH
ENCLOSURE
The current transformer for the following experiment detects
current values down to the milliampere level, has a small center
hole (~7 mm), and is accurate to about 80% when used with a
1 kΩ burden resistor. The FET input buffer of the AD8436
introduces no current transformer loading errors and compensates
the transformer error with a single 2.4 kΩ external feedback
resistor for about 2 dB of gain.
LINE
NEUTRAL
Figure 22. Human Hazard Caused by a Ground Fault Current Path
V+
10µF
0.5A rms
0.47µF
IBUFIN+
0.1µF
CAVG
CCF
CIN
47µF
1kΩ
OBUFOUT
IBUFIN–
2.4kΩ
60W
LIGHT BULB
OPTIONAL
GAIN SET
Figure 23. Block Diagram of AD8436 Current Transformer Configuration
Rev. 0 | Page 11 of 16
0.5V DC
OGND
12788-022
TORROIDAL
CORE
LEAKAGE
PATH
12788-023
UTILITY
CONNECTION
LINE
CONNECTED
EQUIPMENT
AN-1341
Application Note
V+
22nF
CAVG
CT
SEC
AD8436
CORE
IH
1kΩ
HIGH
RETURN
IR
0.5A
NEON
LAMP
10MΩ
GATE
LEAK
RESISTOR
47nF
IGND
60W
LIGHT BULB
TEST
SWITCH
OUT
IBUFOUT
RMS
OGND
CIN
4.7µF
12788-024
LINE
CONNECTION
IBUFIN+
0.47µF
2mA
Figure 24. Ground Fault (Residual Current) Test Circuit with the AD8436 Configured as a Precision Full Wave Rectifier (Absolute Value Circuit)
The AD8436 is particularly useful if it becomes necessary to
measure or detect these small current values. A common technique
is to use a current transformer configured for differential current
detection using the source and return currents through the line
cord conductors. Under normal circumstances, the current to and
from a load are equal and any imbalance in the two are assumed
to be caused by current leakage. When a current transformer
device is wired for differential, a current appears when none are
expected, tripping an alarm. Figure 24 shows a bench experiment
testing using the AD8436 to detect ground fault currents.
Figure 25 is a scope shot of the waveforms of interest. Trace 1 is
the line voltage across the neon lamp, Trace 2 is the current through
the lamp, approximately 2 mA rms, and Trace 3 is the resulting
current transformer secondary voltage.
Note that the waveform is a string of transient responses that
capture the current transitions when the neon lamps conduct
and extinguish, and that the amplitudes are very small, about
2 mV, peak-to-peak, and symmetrical around 0 V. This waveform
only describes this particular experiment. The occurrence of
hazardous ground fault currents are typically unpredictable
because they are caused by component failure or other random
events. One solution to this issue is to rectify the pulses and use a
comparator with a fixed reference level to detect amplitudes. To
demonstrate this solution, the AD8436 is configured as a low
level absolute value circuit with superior detector characteristics
to create a monopolar pulse train of about 1 mV peak, as seen
in Trace 4 in Figure 25.
2
3
12788-025
A small difference current is generated by a neon lamp connected
around the toroid to imbalance the load currents through the
core center. The neon lamp behaves as a Zener clamp, with no
current flowing at low voltages and firing after about 90 V, after
which time a very small 2 mA rms current of flows. The small
magnitude of the current makes it somewhat difficult to detect.
1
4
CH1 100V BW
CH3 1.0mV
CH2 10.0mA
CH4 1.0mV
5.0ms
20.0kS/s
50.0µs/PT
Figure 25. Simulated GFI Experiment Test Circuit Waveforms (see Figure 24);
Trace 1: Neon Lamp Voltage; Trace 2: Neon Lamp Current; Trace 3: Current
Transformer Load Resistor Waveform; Trace 4: Output of AD8436 Applied to
Comparator Input
LOW COST, 3-PHASE POWER LINE MONITOR—
OPTIMIZING SETTLING TIME
An internal, high gain driver within the translinear feedback
loop design of the AD8436 helps stabilize the settling time across
its input dynamic range. The advantage is that the same rms
accuracy is achieved with smaller averaging capacitor values than
in the prior circuits, but with slightly more ripple. The ripple is
easily remedied with an external 2f low-pass filter with shorter time
constants. The result is converter applications requiring less overall
settling times to accomplish the same conversion accuracies.
Rev. 0 | Page 12 of 16
Application Note
AN-1341
Figure 26 (with thanks to the Analog Devices field application
staff) shows the phase relationship of a typical European 3-phase
power distribution waveform. High voltage rms measurements of
utility systems require a high voltage divider with a high input
impedance buffer to mitigate loading errors. Depending on the
number of phases in the system, one or more rms to dc converters
and low-pass filters are selected by a mux and their outputs are
converted to digital by sampling with a single ADC (see an example
of a multichannel measurement system at the top of Figure 27).
The mux and ADC continuously sample all phases well within
the period of a single 20 ms power line voltage period.
µ
325V
L2
L1
L3
3.3ms
60°
n÷3
6.6ms
120°
2n ÷ 3
10ms
180°
n
13.3ms
240°
4n ÷ 3
16.6ms
300°
5n ÷ 3
20ms
360°
2n
12788-026
–325V
However, a single rms to dc converter and low-pass filter are
feasible if less frequent data samples over an extended time
period are acceptable. Because utility frequencies are 50 Hz to
60 Hz (internationally), and several full cycles are required to
produce an rms value, relatively long sampling periods of 1 sec
become practical. Thus, a single rms to dc converter and lowpass filter can convert all three phases sequentially by sampling
every 0.33 sec, as shown in the bottom of Figure 27.
In this scenario, the 3-to-1 mux is placed ahead of the signal
path, followed by the AD8436. Each phase is selected by the mux,
whose common output is connected to the IBUFIN+ pin of the
AD8436. The FET buffer mitigates divider loading and drives
the rms to dc converters. Op amps with moderate bandwidths
(~15 MHz) function as two-pole, Sallen–Key low-pass filters
with a 3 dB frequency low enough to effectively filter any residual
100 Hz output ripple. Note the dramatic reduction in complexity
(and cost) when 3-phase data is collected with a single rms to dc
converter. Further savings are possible if the FET input buffers
can be configured as Sallen-Key filters; however, the bandwidth
may not be sufficient in certain instances.
Figure 26. European 50 Hz/3-Phase Utility
1000:1 HV
DIVIDER (×3)
M
325V
L1
L2
FET
RMS TO DC
BUFFER CONVERTERS
(3)
(3)
ACTIVE
FILTERS
(3)
MUX
(3:1)
L3
ADC
–325V
3.3ms
60°
n÷3
6.6ms
120°
2n ÷ 3
10ms
180°
n
13.3ms 16.6ms 20ms
240°
60°
360°
4n ÷ 3 6n ÷ 3
2n
1000:1 HV
DIVIDER (×3)
8 COMPONENTS SAVED BY USING AN
INPUT/OUTPUT MUX AND BUILT IN
OP AMPS OF THE AD8436
M
325V
L1
L2
L3
3:1 MUX
AD8436
(×1)
ADC
3.3ms
60°
n÷3
6.6ms
120°
2n ÷ 3
10ms
180°
n
12788-027
–325V
13.3ms 16.6ms 20ms
240°
60°
360°
4n ÷ 3 6n ÷ 3
2n
Figure 27. Comparison of Two Methods of Measuring 3-Phase Utility RMS Voltages Using the AD8436
Rev. 0 | Page 13 of 16
AN-1341
Application Note
Performance
Figure 28 is a record of test results of the AD8436 configured as
shown in the diagram of Figure 29, and using a burst signal to
emulate switched samples at the output of a multiplexer (for
example, the ADG1604). A 4.8 V dc supply powers the AD8436
and the input and outputs observed on a scope. The AD8436
output buffer is configured as a two-pole, 10 Hz, Sallen-Key lowpass filter, using 2 μF and 1.5 μF capacitors, and an external
8.01 kΩ resistor as shown in Figure 29 (the 16 kΩ input resistor
is internal to the device).
1
12788-029
2
4
The test waveform period is 1 sec (although this can be
substantially reduced), with a 16-cycle burst of 50 Hz cycles
(20 ms × 16 = 320 ms), of a 252 mV rms sine wave input.
CH1 500mV
CH2 100mV
CH4 2V
200ms
2.5kS/s
400µs/PT
Figure 28. Timing Measurements of the AD8436 Configured for 3-Phase
Conversion; Trace 1: Input Burst—16 Cycles, 20 ms per Cycle, 1 sec Period;
Trace 2: Output; Trace 3: Timing Reference—Burst Gate (Sync Output of
Function Generator)
Direct Connected Power Line Measurements
Line voltages can be measured with a suitable differential amplifier
configured with a step-down resistor network such as the AD628.
Although efficient in device count and cost, circuitry that is
directly connected in any way to power line sources is hazardous to
humans and can be used only in galvanically isolated applications.
See Technical Article MS-2405, Simple Circuit Measures the
RMS Value of an AC Power Line, for a complete description of
the line voltage measurements.
4.8V
3.3µF
NC
20
19
SUM CAVG
NC
1
2
DNC
NC
18
CCF
0.1µF
17
10µF
+
16
VCC IBUFV+
AD8436
OBUFV+
OBUFOUT
RMS
15
OUT
14
4.7µF
3
ADG1604
IBUFOUT
OBUFIN–
IBUFIN–
OBUFIN+
IBUFIN+
IGND
13
2µF
L2
4
0.47µF
L3
10MΩ
12
8.01kΩ
1.5µF
5
IBUFGN DNC OGND OUT
6
NC
NC
7
NC
8
9
11
VEE
10
0.1µF
NC = NO CONNECT
Figure 29. LFCSP AD8436 of High Impedance Input and Precision Output Buffers
Configured to Accommodate High Impedance Sources
and a Two-Pole, Sallen-Key Low-Pass Output Filter
Rev. 0 | Page 14 of 16
17228-028
L1
Application Note
AN-1341
ERROR SOURCES
Conversion Errors
The AD8436 is laser trimmed to data sheet specifications;
however, careful selection of capacitor styles and scrutiny in
PCB layout and assembly are worthwhile, especially for
accurate, low level rms to dc conversion levels.
CAVG Pin
Referring to Figure 30, parasitic impedance at the CAVG pin
and the capacitor style can both introduce small errors. Any
external current diverted from the output path by way of board
contamination or capacitor leakage lowers the converted output
voltage, introducing a correspondingly negative error. Specify PCB
handling procedures applicable for complementary metal-oxide
semiconductor (CMOS) devices.
Referring to Figure 31, the AD8436 output includes a few small
amplitude, ac and dc error components in addition to the desired
output. The ac error is twice the input frequency ripple voltage
following averaging, or filtering, at the output and is managed
by the judicious choice of the CAVG and CLPF capacitors at the
lowest expected operating frequency. Fixed dc errors are compensated by an external offset adjustment; nonlinearities are
compensated by external means, either by scaling or by calibration.
RMS VALUE
RMS ERROR
17228-031
V+
2f RIPPLE
MEASURED
RESULT
Figure 31. AD8436 Output Components
Referring to Figure 31, the small dc rms error represents the
difference between the true rms and the measured dc result.
Mathematically, the rms error approaches zero as the averaging
capacitor or the frequency values approach infinity. This theoretical
convergence is usually ignored as a practical matter, but the loglog representation is useful for sizing averaging capacitors for
higher frequency applications. Furthermore, for a higher operating
frequency (for example, 100 kHz), some input high-pass filtering
in the form of limiting the frequency response using ac coupling
may be practical.
OUT
IRMS
5kΩ
CAVG
V+
RI-V
16kΩ
CLPF
DIELECTRIC
ABSORPTION
CAVG
ILEAKAGE
V–
17228-030
CAVG NODE
IS SENSITIVE
TO LEAKAGE
Figure 30. Capacitor and Leakage Errors
CLPF Pin
Referring to Figure 30, the output of the AD8436 is a current
source driving the 16 kΩ resistor, RI-V. Capacitors used for lowpass filter applications must have good dielectric absorption
qualities; otherwise, error voltages following power-down or
temporarily zero level signals can occur. An equivalent error
circuit for dielectric absorption is shown in Figure 30.
In modern ADC or microcontroller applications, the ripple
error impact can be quite an issue depending on accuracy and
bit resolution. Low supply-voltage converters are quite common,
where the references are only 1 V. For a modest 10-bit converter,
the LSB weighting is 1 mV, and <500 μV ripple is required for
unambivalent sampling.
The dc errors consist of a fixed offset error, which can be calibrated
out. The other is caused by nonlinearity of the translinear approach
used for the AD8436. Fortunately, it is a very small error over a
very large dynamic range; however, if used over an extended
range, multiple calibration points may be desired. The core resistor
values are trimmed at 300 mV rms input using ±5 V supplies.
Rev. 0 | Page 15 of 16
AN-1341
Application Note
PCB PRECAUTIONS
CONCLUSION
Just a few simple steps can make a big difference in results after
selecting the many options offered by the AD8436. Printed
circuit and/or other physical properties are worth mentioning
here. Any AD8436 board designs need a dedicated ground layer,
and benefit from a power layer as well, even if the power layer
includes multiple power and signal traces. Empty space in the
top and bottom layers filled with copper further improves noise
performance. The IBUF of the AD8436 is a FET design, and the
LFCSP version of the AD8436 is particularly vulnerable to surface
leakage of the board. Fortunately, these effects are well known
in the industry and millions of MOSFET applications serve as
precedents. For the QSOP model, hand washing using appropriate
solvents can suffice; however, machine washing and drying is
most effective for the LFCSP model to remove residual salts and
flux contamination that may become trapped beneath the package.
PCB assembly houses are aware of these issues and are fully
equipped to deal with them.
The AD8436 offers substantial flexibility, performance, and cost
savings advantages over older rms to dc converters and over
converters employing various digital schemes. The applications
described herein and data reproduced offer solutions to real life
situations. Many were based on customer input and feedback.
RELATED LINKS
AD8436 Data Sheet
RMS to DC Converter Application Guide
Rarely Asked Questions (RAQs): Resistors in Analog Circuitry
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN12788-0-1/15(0)
Rev. 0 | Page 16 of 16
Similar pages