AN-793 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com ESD/Latch-Up Considerations with iCoupler Isolation Products by Rich Ghiorse INTRODUCTION Analog Devices, Inc., iCoupler® products offer an alternative isolation solution to optocouplers with superior integration, performance, and power consumption characteristics. An iCoupler isolation channel consists of CMOS input and output circuits and a chip scale transformer (see Figure 1). Because digital isolators employ CMOS technology, they can be vulnerable to latch-up or electrostatic discharge (ESD) damage during system-level ESD, surge voltage, fast transient, or other overvoltage conditions. This application note provides guidance for avoiding these problems. Examples are presented for various system-level test configurations showing mechanisms that may impact performance. For each example, recommended solutions are given. ESD, surge, burst, and fast transient events are facts of life in electronic applications. These events generally consist of high voltage, short duration spikes applied directly or indirectly to a device. These events arise from interaction of the device to realworld phenomena, such as human contact, ac line perturbations, lightning strikes, or common-mode voltage differences between system grounds. Component-level ESD testing is most useful in determining a device’s robustness to handling by humans and automated assembly equipment prior and during assembly into a system. Component-level ESD data is less useful in determining a device’s robustness within a system subjected to system-level ESD events. There are two reasons for this. • COMPONENTS vs. SYSTEMS • 05547-001 Simply put, a component is a single integrated device with interconnects while a system is a nonintegrated device built from several interconnected components. In almost all cases, the distinction between a component and a system is obvious. However, the differences between component and system tests may not be so obvious. Further, component specifications may not directly indicate how a device will perform in system-level testing. ESD testing is a good example of this. System- and component-level ESD testing have different objectives. Component-level testing seeks to address conditions typically endured during component handling and assembly. System-level testing seeks to address conditions typically endured during system operation. The specific conditions a component is subjected to during system-level testing can be a strong function of the board/ module/system design in which it resides. For example, long inductive traces between a system and component ground can actually impose a more severe voltage transient onto a component than is imposed on the system at the test point. Figure 1. Quad Isolator Rev. A | Page 1 of 8 AN-793 Application Note TABLE OF CONTENTS Introduction ...................................................................................... 1 Injected ESD Current ........................................................................5 Components vs. Systems ................................................................. 1 Inductive Coupling from ESD Current ..........................................6 Revision History ............................................................................... 2 IEC 61000-4-5 Surge Testing ...........................................................7 Test Results ........................................................................................ 3 IEC 61000-4-4 Fast Transient and Burst Testing Example ..........7 Circuit Model for Analyzing System Test Performance .............. 3 ESD-Hardened Digital Isolators ......................................................8 Latch-Up in CMOS Devices ............................................................ 4 Inside the ESD-Hardened Series .....................................................8 IEC 61000-4-2 ESD Testing............................................................. 4 Conclusion..........................................................................................8 REVISION HISTORY 8/14—Rev. 0 to Rev. A Changes to Introduction Section.................................................... 1 Changes to Injected ESD Current Section .................................... 5 Changes to Table 3 ............................................................................ 8 7/06—Revision 0: Initial Version Rev. A | Page 2 of 8 Application Note AN-793 CIRCUIT MODEL FOR ANALYZING SYSTEM TEST PERFORMANCE Table 1 summarizes the ESD test results for the ADuM1400/ ADuM1401/ADuM1402 quad isolator. One might conclude from Table 1 that these digital isolators can only be used in systems with ESD ratings of < 4 kV. In reality, it is quite common for these products to be used in systems that pass 15 kV ESD levels per IEC 61000-4-2. The difference is in the test methods: The component-level tests call for direct application of ESD events to the pins or body of an unpowered device, while system-level tests call for application ESD events to various locations in the system accessible to external ESD occurrences. Furthermore, the specific waveforms used in component-level and system-level testing differ. Figure 2 shows a circuit model of a digital isolator, which is useful to understand the impact of system-level testing. The L1, L2, L3, and L4 inductors are due largely to package pins and bond wires, while Capacitor C1 is due to the stray capacitance across the isolation barrier. The inductance values are approximately 0.2 nH. The capacitance value is approximately 0.3 pF per isolation channel. Table 1. ADuM1400/ADuM1401/ADuM1402 ESD Test Results1 ESD Model Human Body Model Field Induced Charge Device Model Machine Model 1 First Pass Voltage (V) 3,500 1,500 First Fail Voltage (V) 4,000 2,000 200 400 To accurately predict the performance in a system, the designer needs to understand the nature of the system tests and weigh how they impact the product at the component level. Table 2 lists common system-level tests used in isolated applications. Several examples of these tests are discussed in the IEC 6100004-5 ESD Testing, IEC 610000-4-2 Surge Testing, and IEC 610000-4-4 Transient ad Burst Testing Examples sections. Table 2. Common System Tests Used in Isolated Applications 1 Purpose ESD Fast Transient/Burst Surge VDD2 L1 L2 VO VIN GND1 GND2 L3 C1 L4 Figure 2. Circuit Model Useful in Analyzing System Designs For complete information on Analog Devices ESD testing, refer to the Analog Devices Reliability Handbook. Test Standard IEC 61000-4-2 IEC 61000-4-4 IEC 61000-4-5 VDD1 05547-002 TEST RESULTS Test Voltage (V rms)1 2,000 to 15,000 500 to 4,000 500 to 4,000 IEC 61000-4 tests include compliance levels; the test voltages shown are the ranges for level 1 (lowest) through level 4 (highest) compliance. Rev. A | Page 3 of 8 AN-793 Application Note LATCH-UP IN CMOS DEVICES IEC 61000-4-2 ESD TESTING Inherent in a CMOS process are parasitic PNP and NPN transistors configured as silicon control rectifiers (SCR). Latchup is a condition that comes about when this parasitic SCR is triggered. This causes a low resistance to appear from VDD to ground, and a subsequent large current to be drawn through the device. This excessive current lays open the possibility of damage due to electrical overstress (EOS). A block diagram of the IEC 61000-4-2 ESD test is shown in Figure 3. In this test, ESD contact or air discharges are applied at various points on a system chassis. This gives rise to several mechanisms that can cause latch-up problems. These include injected current via one of the grounds as well as inductive coupling from ESD currents in the system chassis or in printed wiring board traces. SYSTEM CHASSIS Damage caused by latch-up can range from complete destruction of the device to parametric degradation. More insidious are latent failures that could affect operation later in a system’s lifetime. An excellent treatise on the subject of latch-up in general can be found in the Analog Dialogue 35-05 (2001) article, “Winning the Battle Against Latch-Up in CMOS Switches.” While this article specifically addresses problems with CMOS switches, it is generally applicable to all CMOS devices, including digital isolators. Usually the mechanism that causes latch-up is an overvoltage condition beyond the part’s absolute maximum rating (>7.0 V or <–0.5 V for most products). Once a device is integrated into a system the source of the overvoltage is not always clear. However, it is usually manageable once understood. Rev. A | Page 4 of 8 ESD ZAP TO 15kV AIR OR CONTACT DISCHARGE ESD SOURCE Figure 3. IEC 61000-4-2 ESD Test 05547-003 The use of ceramic bypass capacitors to minimize supply noise between VDD and ground is highly recommended in all applications. Choose capacitors with a value between 0.01 µF and 0.1 µF and place them as close as possible to the device. Even with adequate bypassing, latch-up problems may still occur in some applications. Placing a 200 Ω resistor in series with VDD is also helpful. This limits the supply current to 25 mA in 5 V applications, which is below the latch-up trigger current. However, depending on the supply current being drawn, this series resistance can reduce the supply voltage at the device pin to an unacceptable level. This is most likely to be a concern when operating at high data rates that involve high supply currents. CHASSIS GROUND Application Note AN-793 INJECTED ESD CURRENT The following measures are recommended to avoid current injection difficulties: The first possible mechanism for latch-up is one in which excessive ESD current is injected into a ground. Figure 4 shows a situation where an isolator is used as a floating output (the same mechanism can be present in a floating input configuration). In this instance, the chassis impedance, ZCHASSIS, gives rise to an injected current during an ESD discharge. This current flows in the loop formed by L3, C2, L4, and CSTRAY. CSTRAY is the capacitance from the shield of an output cable to chassis ground. The larger the value of CSTRAY, the larger the injected current and the consequent internal noise voltage appearing across L4. If this voltage forces GND2 beyond its absolute maximum rating, then latch-up could occur. • • • Minimize the chassis impedance to ground. Minimize CSTRAY, the cross-isolation barrier capacitance. If possible place a resistor, RS, in series with VDD1 and VDD2 to limit latch-up trigger current. The recommended resistor value is 200 Ω. If it’s not possible to place RS as recommended, place a transient voltage suppressor (TVS) with an optional resistor, RS, in series with the TVS and each VDD pin. The recommended RS value is between 50 Ω and 200 Ω. The TVS should trigger at the absolute maximum voltage rating of the product and limit the current into the power supply nodes, VDD1 and VDD2. Do not use a series resistor on the VISO output pin for isoPower devices. Place a 50 Ω resistor between chassis ground and GND1. This reduces IINJECTED and ultimately VNOISE. Place a transient absorbing Zener diode from the connection to chassis ground. This clamps the noise voltage to within the Zener voltage. • • • ESD ZAP 200Ω RESISTOR TO LIMIT LATCH-UP TRIGGER CURRENT USE 50Ω RESISTOR TO DECREASE I INJECTED VDD1 VDD2 50Ω GND1 200Ω DOUT DIN L3 L4 VLOGIC GND2 +VNOISE– ZCHASSIS IINJECTED C2 CHASSIS/EARTH GROUND ADDITION OF TRANSIENT ABSORBER TO CLAMP NOISE VOLTAGE AT GND1 PIN MINIMIZE SIZE OF CSTRAY , COUPLING FROM OUTPUT CABLE SHIELD TO CHASSIS GROUND Figure 4. Injected ESD Current Mechanism and Recommended Solutions Rev. A | Page 5 of 8 05547-004 CSTRAY AN-793 Application Note INDUCTIVE COUPLING FROM ESD CURRENT SYSTEM CHASSIS One consideration is the possibility of inductive coupling from the ESD current present in the printed wiring board or system chassis. Inductive pickup on iCoupler transformers from external magnetic fields is not a problem in the vast majority of applications; however, there have been rare instances in IEC 61000-4-2 ESD testing where this phenomenon has been noted. Solutions to this problem are straightforward. APPLICATION BOARD IESD GOOD GROUND TECHNIQUE: 1. USE OF WIDE GROUND PLANE LOWERS INDUCTANCE AND WILL LOWER NOISE 2. NO LOOP SO IESD FLOWS THROUGH THE CHASSIS ONLY Figure 5 and Figure 6 shows an ESD test setup and the paths of currents IESD and I1 caused by an ESD strike. These currents can be very large, and induce large magnetic fields on the application printed wiring board and chassis. The placement and geometry of ground traces, ground circuit connections, board location, and orientation within the chassis are all critical in minimizing inductive pickup from the radiated magnetic fields. ESD ZAP POINT 05547-010 GROUND PLANE I1 iCoupler Figure 6. Good Ground Layout Example of a Board Ground Circuit WORST ORIENTATION iCoupler PACKAGE CHIP SCALE TRANSFORMER Figure 5 shows a poor layout, which uses a thin ground trace near the device. It also shows a ground loop that allows some of IESD to flow through the board ground circuit as I1. Close proximity and narrow trace widths increase the magnitude of the induced magnetic field. If strong enough, this can cause latch-up as previously discussed. Figure 6 shows an optimal design using a wide ground plane further away from the device and a single point ground which prevents IESD from flowing in the board ground circuit. When designing ground circuits, it is always helpful to think in terms of current paths. VDD + VINDUCED – MAGNETIC FIELD ORIENTATION RIGHT ANGLE TO TRANSFORMER WINDINGS MAXIMIZES VINDUCED When designing the chassis for the system, it is important to minimize impedance of the chassis ground connection. It is also helpful to mount printed circuit boards as far away from the edge of the chassis as possible, and to have the board oriented so that devices are parallel to any radiated magnetic fields as depicted in Figure 7. BEST ORIENTATION PC BOARD CHIP SCALE TRANSFORMER MAGNETIC FIELD ORIENTATION PARALLEL TO TRANSFORMER WINDINGS MINIMIZES VINDUCED SYSTEM CHASSIS iCoupler PACKAGE iCoupler I1 I2 05547-006 APPLICATION BOARD Figure 7. External Magnetic Field Interaction with iCoupler Transformers If inductive coupling is a problem, recommended solutions include the following: IESD ESD ZAP POINT Figure 5. Poor Ground Layout Example of a Board Ground Circuit 05547-005 POOR GROUND TECHNIQUE: 1. GROUND LOOP ALLOWS PART OF THE IESD TO FLOW THROUGH BOARD GROUND 2. THIN GROUND CONDUCTOR WILL RADIATE MAGNETIC FIELD AND CAUSE PICKUP IN iCoupler TRANSFORMERS • • • • Rev. A | Page 6 of 8 Properly design the ground system to avoid ground loops. Use a ground plane instead of single narrow traces. Orient print wiring boards away from chassis boundaries. If possible, orient the device parallel to external magnetic fields as depicted in Figure 7. Application Note AN-793 IEC 61000-4-5 SURGE TESTING Surge testing per IEC 61000-4-5 is another common systemlevel test in industrial and instrumentation applications. Figure 8 depicts an isolator in a surge test configuration showing associated bypass and stray capacitances. VTEST is the surge test voltage appearing between earth ground and the board’s local ground GND1. This test typically has test voltages up to 4 kV. As shown in Figure 8, if excessive stray capacitance exists across the isolation barrier, the voltage at VDD1 can be driven above its absolute maximum rating and damage the device. Equation 2 shows that making CSTRAY small compared to CBP1 can minimize VX. For example, with a test voltage of 4 kV and a bypass capacitance of 0.01 µF, even the moderate amount of 10 pF of stray capacitance would create a coupled VDD1 voltage of 4 V. When imposed on top of the normal supply voltage, this would induce latch-up. In such a situation, increase the bypass capacitance, CBP1, to 0.1 µF to reduce the coupled voltage to 0.4 V—a much safer value. Do the following for best results: • • C5 • • VDD2 VDD1 L2 L1 VO VIN CBP1 CBP2 C4 • GND2 GND1 L3 C1 IEC 61000-4-4 FAST TRANSIENT AND BURST TESTING EXAMPLE L4 C3 Fast transient and burst testing per IEC 61000-4-4 is another common system-level test that can cause problems if good design practice is not followed. This test couples high voltage fast edge signals onto system ac mains. 05547-007 VTEST Figure 8. Isolator in IEC 61000-4-5 Surge Test Setup Figure 9 shows the model reduced for easier analysis of circuit. The simplified schematic ignores negligible effects of lead inductances and lumps CSTRAY as a computed element (Equation 1). POSSIBLE FIXES TRANSIENT ABSORBER AND 200Ω VL 200Ω iCoupler VDD1 CBP1 Figure 10 shows a simplified circuit diagram of a fast transient test setup. The main mechanism for problems here is interwinding capacitance of the system power supplies transformers. This stray capacitance can couple fast transient signals from the ac mains to the supply pins. If the voltage impressed on the supplies is high enough, then maximum rated supply voltages can be exceeded and latch-up is possible. The best preventive measures in this example are: VDD2 • • • VX CSTRAY GND2 GND1 VTEST Use low interwinding capacitance supplies. Minimize supply noise by using adequate bypassing. Use Zener diode clamps across the supplies to clamp noise voltages. 05547-008 VX IS COUPLED VOLTAGE ON VDD1 DUE TO CSTRAY Minimize capacitances between digital isolator floating grounds and system grounds. Provide adequate bypassing with good quality ceramic bypass capacitors with values large enough to minimize the induced voltage at the supply pins. Ensure VDD1 and VDD2 are free from noise spikes. If possible add a 200 Ω resistor in series with VDD1 to limit parasitic SCR trigger current. Use a transient-absorbing Zener diode across VDD1. COUPLED TRANSIENT NOISE THROUGH CSTRAY TO VDD1 OR VDD2 Figure 9. Simplified Equivalent Circuit of Figure 8 C STRAY = C4 + C BP2 × C5 C BP2 + C5 (1) The coupled voltage, VX, is calculated using a simple capacitor divider V x = VTEST C STRAY × C STRAY + C BP1 (2) TRANSFORMER WINDING CAPACITANCE CSTRAY VDD1 EFT/BURST GENERATOR COUPLING NETWORK AC LINES VDD2 SYSTEM POWER SUPPLIES COUPLED TRANSIENT NOISE ONTO AC LINE RECOMMENDED SOLUTION TRANSIENT ABSORBER Figure 10. IEC 61000-4-4 Fast Transient/Burst Test Setup Rev. A | Page 7 of 8 05547-009 BOARD WITH iCoupler Using Figure 9, and ignoring inductances, CSTRAY is given as AN-793 Application Note ESD-HARDENED DIGITAL ISOLATORS INSIDE THE ESD-HARDENED SERIES To better support the use of digital isolators in harsh applications, Analog Devices has introduced a line of ESDhardened products. The ESD-hardened series takes advantage of improved circuit designs and layouts to increase robustness to ESD events. These products are pin- and specificationcompatible with the standard isolator series counterparts. For many installed applications, the standard products perform well and meet robustness requirements. Therefore, both the standard isolators and the ESD-hardened series continue to be offered. Several design enhancements are incorporated into the ESDhardened series to create a more robust device. Specific improvements include: The part numbering for the ESD-hardened series is analogous to that of the standard product. Table 3 gives examples of the part numbering for the two product families. Table 3. Part Numbering Examples for Various Standard and ESD-Hardened iCoupler Products Standard Products ADuM1100 ADuM1200 ADuM1201 ADuM1300 ADuM1301 ADuM1400 ADuM1401 ADuM1402 ESD-Hardened Products ADuM3100 ADuM3200 ADuM3201 ADuM3300 ADuM3301 ADuM3400 ADuM3401 ADuM3402 • • • • • ESD protection cells added to all input/output interfaces. Key metal trace resistances reduced using wider geometry and paralleling of lines with vias. The SCR effect inherent in CMOS devices minimized by use of guarding and isolation techniques between PMOS and NMOS devices. Areas of high electric field concentration eliminated using 45° corners; on metal traces. Supply pin overvoltage prevented with larger ESD clamps between each supply pin and its respective ground. CONCLUSION By following the guidelines in this application note, designers can be assured of success in their application of digital isolators at the system level. Problems with system-level tests can be anticipated using the lumped-element circuit model presented. With this model and a good understanding of the various system tests, designers can avoid problems by employing the preventive techniques suggested in this application note. In situations where the recommendations cannot be implemented due to cost, system design, or other considerations, the ESDhardened family provides an alternative method of avoiding ESD/latch-up problems. ©2006–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. AN05547-0-8/14(A) Rev. A | Page 8 of 8