High Performance, Sub GHz Radio Transceiver IC ADF7030-1 Preliminary Technical Data FEATURES On-chip ARM Cortex-M0 processor for Radio control and calibration Packet management Clear channel assessment (CCA) IEEE802.15.4g support Frame format Data whitening Dual-sync word detection Forward error correction (FEC) and interleaving Suitable for systems targeting compliance with ETSI EN 300 220 EN 54-25, EN 13757-4 FCC Part 15, Part 22, Part 24, Part 90, and Part 101 ARIB STD-T30, T67, T108, T96 Packages 6 mm × 6 mm, 40-lead LFCSP 7 mm × 7 mm, 48-lead LQFP Radio frequency (RF) ranges 169.4 MHz to 169.6 MHz 426 MHz to 470 MHz 863 MHz to 960 MHz Data rates 2FSK/2GFSK: 0.1 kbps to 300 kbps 4FSK/4GFSK: 0.1 kbps to 360 kbps (transmit only) Dual power amplifiers (PAs) Programmable receiver channel bandwidth from 3 kHz to 738 kHz Receiver (Rx) performance Up to 102 dB blocking at ±20 MHz offset Up to 66 dB adjacent channel rejection −121.2 dBm sensitivity at 2.4 kbps Transmitter (Tx) performance −20 dBm to +17 dBm range with 0.1 dB step resolution Very low output power variation vs. temperature and supply Low active current 50 mA Tx current at 17 dBm 21.2 mA Rx current at12.5 kbps Ultralow sleep current 10 nA with memory retained Autonomous smart wake modes Host microprocessor interface Easy to use programming serial peripheral interface (SPI) Configurable 8-bit general-purpose input/output (GPIO) bus APPLICATIONS IEEE 802.15.4g (MR-FSK PHY) Wireless M-Bus (EN 13757-4) Smart metering Security and building automation Active tag asset tracking Industrial control Wireless sensor networks (WSNs) FUNCTIONAL BLOCK DIAGRAM CREGx HFXTALN HFXTALP GPIO6 GPIO7 ADF7030-1 LDOx LNAIN1 LNAIN2 TCXO BUFFER LNA 26MHz OSC 32kHz OSC 26kHz RCOSC INTERRUPT CONTROLLER ARM® CORTEX®-M0 RECEIVER DIGITAL BASEBAND PAOUT1 PA SPI SLAVE CONFIGURABLE GPIOs SYNTHESIZER SPI GPIOx ROM PA TRANSMITTER RAM TEMP SENSOR 14373-001 PAOUT2 NOTES 1. CREGx, GPIOx AND SPI CONTAIN MULTIPLE PINS. Figure 1. Rev. PrE Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADF7030-1 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 868 MHz—Receive ..................................................................... 36 Applications ....................................................................................... 1 868 MHz—Transmit .................................................................. 38 Functional Block Diagram .............................................................. 1 915 MHz—Receive ..................................................................... 40 General Description ......................................................................... 3 915 MHz—Transmit .................................................................. 42 Specifications..................................................................................... 4 Theory of Operation ...................................................................... 44 Temperature and Voltage............................................................. 4 State Machine .............................................................................. 44 General RF..................................................................................... 4 Radio Timing .............................................................................. 45 Receive ........................................................................................... 5 Host Interface.............................................................................. 46 Transmit ......................................................................................... 6 Receiver........................................................................................ 46 Current Consumption ................................................................. 8 Transmitter .................................................................................. 48 Band Specific Receive and Transmit .......................................... 9 Calibration................................................................................... 49 External 26 MHz Oscillator ...................................................... 19 Packet Handling ......................................................................... 50 Low Frequency Oscillator ......................................................... 19 Applications Information .............................................................. 51 Temperature Sensor ................................................................... 19 Typical Application Circuit ....................................................... 51 Digital Input/Output .................................................................. 20 Silicon Anomaly ............................................................................. 52 Digital Timing ............................................................................. 20 ADF7030-1 Functionality Issues .............................................. 52 Absolute Maximum Ratings .......................................................... 22 Functionality Issues.................................................................... 53 ESD Caution ................................................................................ 22 Section 1. ADF7030-1 Functionality Issues ............................ 53 Pin Configurations and Function Descriptions ......................... 23 Development Support .................................................................... 54 Typical Performance Characteristics ........................................... 27 Design Package ........................................................................... 54 169 MHz—Receive ..................................................................... 27 Reference Manuals ..................................................................... 54 169 MHz—Transmit .................................................................. 28 Evaluation Kits ............................................................................ 54 433 MHz—Receive ..................................................................... 30 Evaluation Software ................................................................... 54 433 MHz—Transmit .................................................................. 31 Outline Dimensions ....................................................................... 55 460 MHz—Receive ..................................................................... 33 460 MHz—Transmit .................................................................. 34 Rev. PrE | Page 2 of 55 Preliminary Technical Data ADF7030-1 GENERAL DESCRIPTION The ADF7030-1 is a fully integrated, radio transceiver achieving high performance at very low power. The ADF7030-1 is ideally suited for applications that require long range, network robustness, and long battery life. It is suitable for applications that operate in the ISM, SRD, and licensed frequency bands at 169.4 MHz to 169.6 MHz, 426 MHz to 470 MHz, and 863 MHz to 960 MHz. It provides extensive support for standards-based protocols like IEEE802.15.4g while also providing flexibility to support a wide range of proprietary protocols. The highly configurable low intermediate frequency (IF) receiver supports a large range of receiver channel bandwidths from 3 kHz to 738 kHz. This range of receiver channel bandwidths allows the ADF7030-1 to support ultranarrowband, narrow-band, and wideband channel spacing. The ADF7030-1 features two independent PAs supporting output power ranges of −20 dBm to +13 dBm and −20 dBm to +17 dBm. The PAs support ultrafine adjustment of the power with a step resolution of 0.1 dB. The PA output power is exceptionally robust over temperature and voltage. The PAs have an automatic power ramp control to limit spectral splatter to meet regulatory standards. The ADF7030-1 features an on-chip ARM® Cortex®-M0 processor that performs radio control, radio calibration, and packet management. Cortex-M0 eases the processing burden of the host processor because the ADF7030-1 integrates the lower layers of a typical communication protocol stack. This internal processor also permits the download and execution of Analog Devices, Inc., provided firmware modules that can extend the functionality of the ADF7030-1. The ADF7030-1 has two packet modes: generic packet mode and IEEE802.15.4g mode. In generic packet mode, the packet format is highly flexible and fully programmable, thereby ensuring its compatibility with proprietary packet formats. In IEEE802.15.4g packet mode, the packet format conforms to the IEEE802.15.4g standard. FEC, as per the IEEE802.15.4g standard, is also supported. The ADF7030-1 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems. An ultralow power deep sleep mode achieves a typical current of 10 nA with the configuration memory retained. The ADF7030-1 supports smart wake mode (SWM) where the ADF7030-1 can wake up autonomously from sleep using an internal real-time clock (RTC) without intervention from the host processor. After wake-up, the ADF7030-1 operates autonomously. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby reducing overall system current consumption. The ADF7030-1 autonomous operation can also be triggered by the host processor using the interrupt input of the ADF7030-1. A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller). The host processor can configure the ADF7030-1 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function. The ADF7030-1 is available in two package types: a 6 mm × 6 mm 40-lead LFCSP and a 7 mm × 7 mm 48-lead LQFP. Both package types use NiPdAu plating to mitigate against silver migration in high humidity applications. The ADF7030-1 operating temperature range is −40°C to +85°C. For Figure 13 to Figure 22 in the 169 MHz—Transmit section, PA_COARSE is a programmable value that provides a coarse adjustment of the PA output power. This value can be programmed in the range of 1 to 6 for PA1, and from 1 to 10 for PA2. PA_FINE is a programmable value that provides a fine adjustment of the PA output power. This value can be programmed in the range of 3 to 127 for both PA1 and PA2. PA_MICRO is a programmable value that provides a microadjustment (typically <0.1 dB) of the PA output power. This value can be programmed in the range of 1 to 31 for both PA1 and PA2. PAOLDO_VOUT_ CON is a programmable value that configures the internal LDO voltage that provides bias for the PA. For additional information on these bit settings, see the ADF7030-1 Software Reference Manual, which is the detailed programming guide for the device. Rev. PrE | Page 3 of 55 ADF7030-1 Preliminary Technical Data SPECIFICATIONS VDD = VBAT1 = VBAT2 = VBAT3 = VBAT4 = VBAT5 = VBAT6 = 2.2 V to 3.6 V, exposed pad (EPAD) = 0 V (ground), TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C, unless otherwise noted. All VBATx pins must be tied together. A one-time radio calibration required, unless otherwise noted. TEMPERATURE AND VOLTAGE Table 1. Parameter TEMPERATURE RANGE, TA VOLTAGE SUPPLY VBATx Pin Voltage Min −40 Typ 2.2 2.85 PA LDO voltage + 0.2 V Max +85 Unit °C Test Conditions/Comments 3.6 3.6 3.6 V V V Transmit power ≤ 13dBm Transmit power ≥ 17dBm, PA LDO voltage = 2.65 V Transmit power >13dBm and < 17dBm; the PA LDO voltage is configurable GENERAL RF Table 2. Parameter RF FREQUENCY Frequency Range Channel Frequency Resolution DATA RATE IEEE802.15.4g Packet Mode 2FSK, 2GFSK Modulation Generic Packet Mode 2FSK, 2GFSK Modulation 4FSK, 4GFSK Modulation On/Off Keying (OOK) Modulation Resolution FREQUENCY DEVIATION Range 2FSK, 2GFSK Modulation 4FSK, 4GFSK Modulation Resolution GAUSSIAN FILTER BANDWIDTH TIME (BT) PRODUCT Min Typ 169.4 426 863 Max Unit 169.6 470 960 MHz MHz MHz Hz 1.5 2.4 150 0.1 1 300 360 kbps kbps 16.384 kbps kbps kbps 1 bps 1 1 250 250 100 0.3, 0.35, 0.4, 0.5 Rev. PrE | Page 4 of 55 Test Conditions/Comments kHz kHz Hz Tx only, generic packet mode only Tx only, Manchester encoded, generic packet mode only Tx only, generic packet mode only Programmable Preliminary Technical Data ADF7030-1 RECEIVE Table 3. Parameter MAXIMUM DATA RATE ERROR TOLERANCE RECEIVER CHANNEL FILTER BANDWIDTH Narrow-Band Mode Maximum Minimum Wideband Mode Maximum Minimum MAXIMUM RF INPUT LEVEL RECEIVER LINEARITY Input Third-Order Intercept (IP3) Min Typ ±0.1 Max Unit % Programmable; see Table 27 and Table 28 for a list of all supported values 20 3 kHz kHz 738 77 10 kHz kHz dBm −8.5 dBm Input Second-Order Intercept (IP2) 53 dBm 1 dB Compression (P1dB) −18.7 dBm 0.25 ±2 dB dB 78 − j20 69 − j25 68 − j25 56 − j29 55 − j30 Ω Ω Ω Ω Ω 7 + j2 7 + j4 7 + j4 8 + j8 8 + j8 Ω Ω Ω Ω Ω 78 − j16 71 − j18 73 − j22 58 − j20 57 − j20 Ω Ω Ω Ω Ω 7 + j3 8 + j9 8 + j9 9 + j18 9 + j19 Ω Ω Ω Ω Ω RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) Resolution Calibrated Absolute Accuracy DIFFERENTIAL LOW NOISE AMPLIFIER (LNA) INPUT IMPEDANCE 40-LEAD LFCSP PACKAGE LNA in Rx Mode f = 169 MHz f = 433 MHz f = 460 MHz f = 868 MHz f = 915 MHz LNA in Tx Mode f = 169 MHz f = 433 MHz f = 460 MHz f = 868 MHz f = 915 MHz DIFFERENTIAL LNA INPUT IMPEDANCE 48-LEAD LQFP PACKAGE LNA in Rx Mode f = 169 MHz f = 433 MHz f = 460 MHz f = 868 MHz f = 915 MHz LNA in Tx Mode f = 169 MHz f = 433 MHz f = 460 MHz f = 868 MHz f = 915 MHz Test Conditions/Comments Measured at maximum receiver gain Receiver channel frequency = 169.43125 MHz, fSOURCE1 = 171.35 MHz, fSOURCE2 = 173.26875 MHz Receiver channel frequency = 169.53125 MHz, fSOURCE1 = 171.55 MHz, fSOURCE2 = 171.63125 MHz Receiver channel frequency = 169.43125 MHz, fSOURCE1 = 171.43125 MHz Refer to the Typical Performance Characteristics section for further detail; sensitivity defined as BER = 0.1% −40 dBm to sensitivity + 6 dB; one-point offset calibration Combined match enabled Combined match enabled Rev. PrE | Page 5 of 55 ADF7030-1 Preliminary Technical Data TRANSMIT Table 4. Parameter POWER AMPLIFIER (PA) Power Amplifier 1 (PA1) Transmit Power Maximum Transmit Power Minimum Transmit Power Step Resolution Transmit Power Variation vs. Temperature Transmit Power Variation vs. VDD Transmit Power Accuracy Power Amplifier 2 (PA2) Transmit Power Maximum Transmit Power Minimum Transmit Power Step Resolution Transmit Power Variation vs. Temperature Transmit Power Variation vs. VDD Transmit Power Accuracy PA IMPEDANCE 40-LEAD LFCSP PACKAGE Optimum PA Load in Transmit PA1 f = 169 MHz f = 433 MHz, f = 460 MHz f = 868 MHz, f = 915 MHz PA2 f = 169 MHz f = 433 MHz, f = 460 MHz f = 868 MHz, f = 915 MHz PA Input Impedance While in Rx PA1 f = 169 MHz f = 433 MHz f = 460 MHz f = 868 MHz f = 915 MHz PA2 f = 169 MHz f = 433 MHz f = 460 MHz f = 868 MHz f = 915 MHz Min Typ 13 −20 0.1 ±0.15 Max Unit Test Conditions/Comments dBm dBm dB From −40°C to +85°C, transmit power = 13 dBm, RF frequency = 169 MHz From VDD = 2.2 V to VDD = 3.6 V, transmit power = 13 dBm, RF frequency = 169 MHz transmit power = 13 dBm, RF frequency = 169 MHz ±0.1 ±0.3 17 13 −20 0.1 ±0.1 dBm dBm dBm dB dB ±0.1 dB ±0.25 dB 50 + j0 45 + j30 50 + j20 Ω Ω Ω 38 + j0 38 + j25 38 + j18.5 Ω Ω Ω 7 − j232 5 − j102 5 − j96 4 − j49 4 − j46 Ω Ω Ω Ω Ω 5 − j177 3 − j69 3 − j65 3 − j33 3 − j31 Ω Ω Ω Ω Ω Rev. PrE | Page 6 of 55 The maximum output power level achievable on PA2 depends on the programmable PA CREG3 LDO voltage setting; refer to the ADF7030-1 Software Reference Manual for further details 2.85 V ≤ VDD ≤ 3.6 V 2.2 V ≤ VDD ≤ 3.6 V From −40°C to +85°C, transmit power = 17 dBm, RF frequency = 169 MHz From VDD = 3.0 V to VDD = 3.6 V, transmit power = 17 dBm, RF frequency = 169 MHz Transmit power = 17 dBm, RF frequency = 169 MHz For guidance on impedance matching, refer to the ADF7030-1 Hardware Reference Manual Preliminary Technical Data Parameter PA IMPEDANCE 48-LEAD LQFP PACKAGE Optimum PA Load in Transmit PA1 f = 169 MHz f = 433 MHz, f = 460 MHz f = 868 MHz f = 915 MHz PA2 f = 169 MHz f = 433 MHz, f = 460 MHz f = 868 MHz, f = 915 MHz PA Input Impedance While in Rx PA1 f = 169 MHz f = 433 MHz, f = 460 MHz f = 868 MHz f = 915 MHz PA2 f = 169 MHz f = 433 MHz, f = 460 MHz f = 868 MHz f = 915 MHz Min ADF7030-1 Typ Max Unit 45 + j 8 40 + j20 40 + j20 40 + j20 Ω Ω Ω Ω 37 + j 9 30 + j25 30 + j15 Ω Ω Ω 6 − j236 6 − j87 5 − j37 5 − j34 Ω Ω Ω Ω 5 − j169 4 − j58 3 − j22 3 − j19 Ω Ω Ω Ω Rev. PrE | Page 7 of 55 Test Conditions/Comments For guidance on impedance matching, refer to the ADF7030-1 Hardware Reference Manual ADF7030-1 Preliminary Technical Data CURRENT CONSUMPTION Table 5. Parameter TRANSMIT CURRENT CONSUMPTION f = 169.4 MHz Tx Power = 0 dBm , PA1 Tx Power = 10 dBm, PA1 Tx Power = 13 dBm, PA1 Tx Power = 17 dBm, PA2 f = 433 MHz Tx Power = 0 dBm, PA1 Tx Power = 10 dBm, PA1 Tx Power = 13 dBm, PA1 f = 460 MHz Tx Power = 17 dBm, PA2 f = 868 MHz, f = 915 MHz Tx Power = 0 dBm, PA1 Tx Power = 10 dBm, PA1 Tx Power = 13 dBm, PA1 Tx Power = 17 dBm, PA2 RECEIVE CURRENT CONSUMPTION f = 169.4 MHz Data Rate = 4.8 kbps f = 433 MHz, f = 460 MHz Data Rate = 4.8 kbps Data Rate = 50 kbps f = 868 MHz, f = 915 MHz Data Rate = 5 kbps Data Rate = 12.5 kbps Data Rate = 50 kbps Data Rate = 100 kbps Data Rate = 150 kbps Data Rate = 300 kbps RADIO STATE CURRENT CONSUMPTION PHY_SLEEP State Min Typ Max Unit 18 31 39 65 mA mA mA mA 19 31 39 mA mA mA 50 mA 20 34 43 65 mA mA mA mA Test Conditions/Comments In the PHY_TX state transmitting a carrier In the PHY_RX state, waiting for preamble 24.8 mA Narrow-band receive path 24.5 24 mA mA Narrow-band receive path Wideband receive path 23.2 21.2 21.4 23.7 24 25.4 mA mA mA mA mA mA Narrow-band receive path Wideband receive path Wideband receive path Wideband receive path Wideband receive path Wideband receive path 2 nA 10 nA 1 µA 1 µA PHY_OFF State 1.9 mA PHY_OFF State 3.7 mA Memory not retained, no wakeup oscillator enabled, RTC disabled Memory retained, no wakeup oscillator enabled, RTC disabled Memory retained, internal 26 kHz RC oscillator enabled, RTC enabled Memory retained, external 32 kHz oscillator enabled, RTC enabled First entry to PHY_OFF after wake from PHY_SLEEP or after reset event Second and subsequent entries to PHY_OFF after wake from PHY_SLEEP or after reset event PHY_ON State 3.7 mA Rev. PrE | Page 8 of 55 Preliminary Technical Data ADF7030-1 BAND SPECIFIC RECEIVE AND TRANSMIT 169.4 MHz to 169.6 MHz Unless otherwise noted, the configurations detailed in Table 6 are used to specify the performance of the ADF7030-1 in Table 7. All measurements are performed on the EV-ADF70301-169BZ evaluation board, unless otherwise noted. The EV-ADF70301-169BZ uses a separate transmit/receive match design and a 26 MHz thermally compensated crystal oscillator (TCXO) reference. Table 6. Configurations in the 169.4 MHz to 169.6 MHz Frequency Band RF Frequency (MHz) 169.43125 Data Rate (kbps) 2.4 169.41875 MHz/ 4.8 kbps 169.41875 169.46875 MHz/ 6.4 kbps 169.46875 Configuration Name 169.43125 MHz/ 2.4 kbps Modulation 2GFSK Frequency Deviation (kHz) 2.4 Channel Spacing (kHz) 12.5 IF Frequency (kHz) 81.25 Receiver Bandwidth (BW) (kHz) 8.7 4.8 2GFSK 2.4 12.5 81.25 10.6 6.4 4GFSK 3.2 (outer deviation) 12.5 Not applicable (Tx only) Not applicable (Tx only) Packet Setup for Packet-Based Testing Preamble = 0x5555, syncword = 0xF672, payload length = 23 bytes, CRC = 2 bytes Preamble = 0x5555, syncword = 0xF672, payload length = 23 bytes, CRC = 2 bytes Not applicable Table 7. Specifications in the 169.4 MHz to 169.6 MHz Frequency Band Parameter SENSITIVITY, PACKET ERROR RATE (PER) Configuration 169.43125 MHz/2.4 kbps Configuration 169.41875 MHz/4.8 kbps Min Typ Max Unit Test Conditions/Comments −121.2 dBm −119.4 dBm At PER = 5%, AFC enabled, RF frequency error range = ±11.5 ppm At PER = 5%, AFC enabled, RF frequency error range = ±11.5 ppm Desired signal 3 dB above the input sensitivity level (BER = 0.1%), carrier wave (CW) interferer power level increased until BER = 0.1%; AFC disabled, image calibrated 66 66 94 92 102 dB dB dB dB dB 55 63 92 90 dB dB dB dB CHANNEL SELECTIVITY AND BLOCKING— BER-BASED TEST METHOD Configuration 169.43125 MHz/2.4 kbps Adjacent Channel (±12.5 kHz) Alternate Channel (±25 kHz) ±2 MHz ±10 MHz ±20 MHz Configuration 169.41875 MHz/4.8 kbps Adjacent Channel (±12.5 kHz) Alternate Channel (±25 kHz) ±2 MHz ±10 MHz CHANNEL SELECTIVITY AND BLOCKING— PER-BASED TEST METHOD Configuration 169.43125 MHz/2.4 kbps Adjacent Channel (±12.5 kHz) Alternate Channel (±25 kHz) ±2 MHz ±10 MHz Configuration 169.41875 MHz/4.8 kbps Adjacent Channel (±12.5 kHz) Alternate Channel (±25 kHz) ±2 MHz ±10 MHz Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5%, AFC enabled, Image calibrated 62 70 94 96 dB dB dB dB 55 69 91 95 dB dB dB dB Rev. PrE | Page 9 of 55 ADF7030-1 Parameter CHANNEL SELECTIVITY AND BLOCKING— ETSI EN 300 220-1 TEST METHOD Configuration 169.43125 MHz/2.4 kbps ±2 MHz ±10 MHz Configuration 169.41875 MHz/4.8 kbps Preliminary Technical Data Min Typ −15 −12 Configuration 169.43125 MHz/2.4 kbps Configuration 169.41875 MHz/4.8 kbps CALIBRATED IMAGE REJECTION −10 −10 Configuration 169.43125 MHz/2.4 kbps ADJACENT CHANNEL POWER (ACP) 55 dBm dBm dBm dBm Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5%, AFC enabled dB dB dB 17 dBm Output Power Second Harmonic Third Harmonic All Other Harmonics Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5%, AFC enabled, image calibrated dB spectrum analyzer settings: resolution bandwidth (RBW) = 100 Hz, video bandwidth (VBW) = 300 Hz PA1, output power = 13 dBm −83 −82 dBc dBc −59 −81 dBc dBc −68 −81 dBc dBc PA2, output power = 17 dBm PA1, output power = 13 dBm 6.3 7.8 8.2 kHz kHz kHz −58 −49 dBm dBm Transmit < 1 GHz 1 GHz to 4 GHz HARMONIC EMISSIONS Test Conditions/Comments Measured as per EN 300 220-1 V2.4.1, AFC disabled Wanted signal level = −105.8 dBm (3 dB above the reference sensitivity level) −16 −13 Configuration 169.43125 MHz/2.4 kbps Configuration 169.41875 MHz/4.8 kbps Configuration 169.46875 MHz/6.4 kbps SPURIOUS EMISSIONS (EXCLUDING HARMONICS) Receive < 1 GHz 1 GHz to 4 GHz Unit Wanted signal level = −106.7 dBm (3 dB above the reference sensitivity level) ±2 MHz ±10 MHz COCHANNEL REJECTION Configuration 169.43125 MHz/2.4 kbps Adjacent Channel Alternate Channel Configuration 169.41875 MHz/4.8 kbps Adjacent Channel Alternate Channel Configuration 169.46875 MHz/6.4 kbps Adjacent Channel Alternate Channel OCCUPIED BANDWIDTH Max Occupied bandwidth is the bandwidth containing 99% of the total integrated power; spectrum analyzer settings: resolution bandwidth (RBW) = 100 Hz, video bandwidth (VBW) = 300 Hz PA1, output power = 13 dBm PA2, output power = 17 dBm PA1, output power = 13 dBm Measured conductively at antenna input; RF frequency = 169.43125 MHz PA2, output power = 17 dBm, transmitting continuous carrier wave − 75 − 78 dBc dBc Measured conductively at antenna input, transmitting continuous carrier wave; RF frequency = 169.43125 MHz PA2 −81 −90 <−90 dBc dBc dBc Rev. PrE | Page 10 of 55 Preliminary Technical Data ADF7030-1 433 MHz Unless otherwise noted, the configuration detailed in Table 8 is used to specify the performance of the ADF7030-1 in Table 9. All measurements performed on the EV-ADF70301-460BZ evaluation board, unless otherwise noted. The EV-ADF70301-460BZ uses a separate transmit/receive match design and a 26 MHz TCXO reference. Table 8. 433 MHz Configurations Configuration Name 433 MHz/50 kbps RF Frequency (MHz) 433 Data Rate (kbps) 50 Modulation 2GFSK Frequency Deviation (kHz) 25 Channel Spacing (kHz) 200 IF Frequency (kHz) 154 Receiver Bandwidth (BW) (kHz) 127 Packet Setup for Packet Based Testing Preamble = 0xAAAA, syncword = 0xF672, payload length = 16 bytes, CRC = 2 bytes Table 9. 433 MHz Specifications Parameter SENSITIVITY, PACKET ERROR RATE (PER) Configuration 433 MHz/50 kbps Min Typ Max Unit Test Conditions/Comments −108.2 dBm At PER = 5%, AFC enabled, RF frequency error range = ±25 ppm Desired signal 3 dB above the input sensitivity level (BER = 0.1%), CW interferer power level increased until BER = 0.1%, image calibrated, AFC disabled 48 58 74 83 91 dB dB dB dB dB CHANNEL SELECTIVITY AND BLOCKING— BER-BASED TEST METHOD Configuration 433 MHz/50 kbps Adjacent Channel (±200 kHz) Alternate Channel (±400 kHz) ±2 MHz ±10 MHz ±20 MHz CHANNEL SELECTIVITY AND BLOCKING— PER BASED TEST METHOD Configuration 433 MHz/50 kbps Adjacent Channel (±200 kHz) Alternate Channel (±400 kHz) ±2 MHz ±10 MHz COCHANNEL REJECTION Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5%, image calibrated, AFC enabled 46 55 71.5 77 dB dB dB dB Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5%, AFC enabled Configuration 433.92 MHz/50 kbps CALIBRATED IMAGE REJECTION −10 Configuration 433 MHz/50 kbps ADJACENT CHANNEL POWER (ACP) Configuration 433 MHz/50 kbps OCCUPIED BANDWIDTH (OBW) 54 dB −59 dBc Configuration 433 MHz/50 kbps dB Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5%, AFC enabled, image calibrated spectrum analyzer settings: RBW = 100 Hz, VBW = 300 Hz Occupied bandwidth is the bandwidth containing 99% of the total integrated power; spectrum analyzer settings: RBW = 100 Hz, VBW = 300 Hz 86 kHz Rev. PrE | Page 11 of 55 ADF7030-1 Parameter SPURIOUS EMISSIONS (EXCLUDING HARMONICS) Receive <1 GHz 1 GHz to 4 GHz Transmit <1 GHz 1 GHz to 4 GHz HARMONIC EMISSIONS Second Harmonic All Other Harmonics Preliminary Technical Data Min Typ −82 −47 Max Unit Test Conditions/Comments Measured conductively at antenna port; RF frequency = 433 MHz dBm dBm PA1, output power = 10 dBm, transmitting continuous carrier wave −53 −76 dBc dBc Measured conductively at antenna input, transmitting continuous carrier wave; RF frequency = 433 MHz, PA1, output power = 10 dBm −64 <−90 dBc dBc Rev. PrE | Page 12 of 55 Preliminary Technical Data ADF7030-1 450 MHz to 470 MHz Unless otherwise noted, the configuration detailed in Table 10 is used to specify the performance of the ADF7030-1 in Table 11. All measurements performed on the EV-ADF70301-460BZ evaluation board, unless otherwise noted. The EV-ADF70301-460BZ uses a separate transmit/receive match design and a 26 MHz TCXO reference. Table 10. Configurations in the 450 MHz to 470 MHz Frequency Band Configuration Name 460 MHz/7.2 kbps RF Frequency (MHz) 460 Data Rate (kbps) 7.2 Modulation 2GFSK Frequency Deviation (kHz) 2.0 Channel Spacing (kHz) 12.5 IF Frequency (kHz) 81.25 Receiver Bandwidth (BW) (kHz) 11.7 Packet Setup for Packet Based Testing Preamble = 0xAAAA, syncword = 0xF672, payload length = 23 bytes, CRC = 2 bytes Table 11. Specifications in the 450 MHz to 470 MHz Frequency Band Parameter SENSITIVITY, PACKET ERROR RATE (PER) Configuration 460 MHz/7.2 kbps Min Typ Max Unit Test Conditions/Comments −116 dBm At PER = 5%, AFC enabled, RF frequency error range = ±3.9 ppm Desired signal 3 dB above the input sensitivity level (BER = 0.1%), CW interferer power level increased until BER = 0.1%, image calibrated, AFC disabled 54 61 84 92 dB dB dB dB CHANNEL SELECTIVITY AND BLOCKING— BER-BASED TEST METHOD Configuration 460 MHz/7.2 kbps Adjacent Channel (±12.5 kHz) Alternate Channel (±25 kHz) ±2 MHz ±10 MHz CHANNEL SELECTIVITY AND BLOCKING— PER-BASED TEST METHOD Configuration 460 MHz/7.2 kbps Adjacent Channel (±12.5 kHz) Alternate Channel (±25 kHz) ±2 MHz ±10 MHz ±20 MHz CO-CHANNEL REJECTION Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5%, image calibrated, AFC enabled 38 57 80 85 98 dB dB dB dB dB Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5%, AFC enabled Configuration 460 MHz/7.2 kbps CALIBRATED IMAGE REJECTION 10 dB Configuration 460 MHz/7.2 kbps ADJACENT CHANNEL POWER (ACP) Configuration 460 MHz/7.2 kbps OCCUPIED BANDWIDTH (OBW) 51 dB −45 dBc Configuration 460 MHz/7.2 kbps SPURIOUS EMISSIONS (EXCLUDING HARMONICS) Rx <960 MHz 960 MHz to 12.7 GHz 7.7 Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5%, AFC enabled, image calibrated spectrum analyzer settings: RBW = 100 Hz, VBW = 300 Hz Occupied bandwidth is the bandwidth containing 99% of the total integrated power; spectrum analyzer settings: RBW = 100 Hz, VBW = 300 Hz kHz Measured conductively at antenna port; RF frequency = 460 MHz −57 −66 dBm dBm Rev. PrE | Page 13 of 55 ADF7030-1 Parameter Tx <960 MHz 960 MHz to 12.7 GHz HARMONIC EMISSIONS Second Harmonic All Other Harmonics Preliminary Technical Data Min Typ −59 −76 Max Unit Test Conditions/Comments PA2, output power = 17 dBm, transmitting continuous carrier wave dBc dBc Measured conductively at antenna port, transmitting continuous carrier wave; RF frequency = 460 MHz, output power = 17 dBm, PA2 −60 < −90 dBc dBc Rev. PrE | Page 14 of 55 Preliminary Technical Data ADF7030-1 863 MHz to 876 MHz Unless otherwise noted, the configurations detailed in Table 12 are used to specify the performance of the ADF7030-1 in Table 13. All measurements performed on the EV-ADF70301-868BZ evaluation board, unless otherwise noted. The EV-ADF70301-868BZ uses a separate transmit/receive match design and a 26 MHz TCXO reference. Table 12. Configurations in the 863 MHz to 876 MHz Frequency Band Configuration Name 868 MHz/4.8 kbps RF Frequency (MHz) 868 Data Rate (kbps) 4.8 868 MHz/100 kbps 868 100 Modulation 2GFSK Frequency Deviation (kHz) 2.4 Channel Spacing (kHz) 12.5 IF Frequency (kHz) 81.25 Receiver Bandwidth (BW) (kHz) 10.6 2FSK 50 500 241 231 Packet Setup for Packet Based Testing Preamble = 0xAAAA, sync word = 0xF672, payload length = 23 bytes, CRC = 2 bytes Preamble = 0xAAAAAAAA, sync word = 0x543D54CD, payload length = 20 bytes, CRC = 2 bytes Table 13. Specifications in the 863 MHz to 876 MHz Frequency Band Parameter SENSITIVITY, PACKET ERROR RATE (PER) Configuration 868 MHz/4.8 kbps Configuration 868 MHz/100 kbps Min Typ Max Unit Test Conditions/Comments −118.5 −106 dBm dBm At PER = 5%, AFC enabled, RF frequency error range = ±3 ppm At PER = 5%, AFC enabled, RF frequency error range = ±25 ppm, data rate error range = ±100 ppm, frequency deviation error range = ±25% Desired signal 3 dB above the input sensitivity level (BER = 0.1%), CW interferer power level increased until BER = 0.1%, image calibrated, AFC disabled 56 56 78 87 98 dB dB dB dB dB CHANNEL SELECTIVITY AND BLOCKING— BER-BASED TEST METHOD Configuration 868 MHz/4.8 kbps Adjacent Channel (±12.5 kHz) Alternate Channel (±25 kHz) ±2 MHz ±10 MHz ±20 MHz CHANNEL SELECTIVITY AND BLOCKING— PER-BASED TEST METHOD Configuration 868 MHz/4.8 kbps Adjacent Channel (±12.5 kHz) Alternate Channel (±25 kHz) ±2 MHz ±10 MHz Configuration 868 MHz/100 kbps Adjacent Channel (±500 kHz) Alternate Channel (±1000 kHz) ±2 MHz ±10 MHz CO CHANNEL REJECTION Configuration 868 MHz/4.8 kbps Configuration 868 MHz/100 kbps Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5%, image calibrated, AFC enabled 47 55 79 90 dB dB dB dB 44 59 65 76 dB dB dB dB Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5%, AFC enabled −10 −10 dB dB Rev. PrE | Page 15 of 55 ADF7030-1 Parameter UNCALIBRATED IMAGE REJECTION Preliminary Technical Data Min Typ Max Unit Configuration 868 MHz/4.8 kbps Configuration 868 MHz/100 kbps ADJACENT CHANNEL POWER (ACP) Configuration 868 MHz/4.8 kbps Configuration 868 MHz/100 kbps OCCUPIED BANDWIDTH (OBW) 40 40 dB dB −65 −41 dBc dBc Configuration 868 MHz/4.8 kbps Configuration 868 MHz/100 kbps SPURIOUS EMISSIONS (EXCLUDING HARMONICS) Rx < 1 GHz 1 GHz to 4 GHz Tx 7.8 226 < 1 GHz 1 GHz to 4 GHz HARMONIC EMISSIONS 13 dBm Output Power Second Harmonic Third Harmonic Seventh Harmonic All Other Harmonics 17 dBm Output Power Second Harmonic Third Harmonic All Other Harmonics Test Conditions/Comments Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5%, AFC enabled spectrum analyzer settings: RBW = 100 Hz, VBW = 300 Hz Occupied bandwidth is the bandwidth containing 99% of the total integrated power; spectrum analyzer settings: RBW = 100 Hz, VBW = 300 Hz kHz kHz Measured conductively at antenna input; RF Frequency = 868 MHz −58 −46 dBm dBm PA2, 17dBm output power, transmitting continuous carrier wave −74 −77 dBc dBc Measured conductively at antenna input, transmitting continuous carrier wave; RF frequency = 868 MHz PA1 −50 −78 −88 <−90 dBc dBc dBc dBc −55 −73 <−90 dBc dBc dBc PA2 Rev. PrE | Page 16 of 55 Preliminary Technical Data ADF7030-1 902 MHz to 928 MHz Unless otherwise noted, the configurations detailed in Table 14 are used to specify the performance of the ADF7030-1 in Table 15. All measurements performed on the EV-ADF70301-868BZ evaluation board, unless otherwise noted. The EV-ADF70301-868BZ uses a separate transmit/receive match design and a 26 MHz TCXO reference. Table 14. Configurations in the 902 MHz to 928 MHz Frequency Band Modulation 2GFSK Frequency Deviation (kHz) 25 Channel Spacing (kHz) 200 IF Frequency (kHz) Receiver Bandwidth (BW) (kHz) 154 127 150 2GFSK 37.5 400 336 250 300 2GFSK 120 600 540 530 RF Frequency (MHz) 915 Data Rate (kbps) 50 915 MHz/ 150 kbps 915 915 MHz/ 300 kbps 915 Configuration Name 915 MHz/ 50 kbps Packet Setup for Packet Based Testing Preamble = AAAAAAAA, syncword = 0x904E, payload length = 100 bytes, CRC = 2 bytes Preamble = AA (x 12), syncword = 0xFF7D7F5D, payload length = 100 bytes, CRC = 2 bytes Preamble = AAAAAAAA, syncword = 0xF672, payload length = 23 bytes, CRC = 2 bytes Table 15. 902 MHz to 928 MHz Specifications Parameter 2GFSK SENSITIVITY, PACKET ERROR RATE (PER) Configuration 915 MHz/50 kbps Min Typ Max Unit Test Conditions/Comments −108.2 dBm Configuration 915 MHz/150 kbps −100.5 dBm Configuration 915 MHz/300 kbps −102 dBm At PER = 5%, FEC disabled, AFC enabled, RF frequency error range = ±40 ppm At PER = 5%, FEC disabled, AFC enabled, RF frequency error range = ±40 ppm At PER = 5%, AFC disabled, RF frequency error range = ±11.5 ppm Desired signal 3 dB above the input sensitivity level (BER = 0.1%), CW interferer power level increased until BER = 0.1%, AFC disabled 46 56 66 77 83 dB dB dB dB dB CHANNEL SELECTIVITY AND BLOCKING— BER-BASED TEST METHOD Configuration 915 MHz/150 kbps Adjacent Channel (±400 kHz) Alternate Channel (±800 kHz) ±2 MHz ±10 MHz ±20 MHz CHANNEL SELECTIVITY AND BLOCKING— PER-BASED TEST METHOD Configuration 915 MHz/50 kbps Adjacent Channel (±200 kHz) Alternate Channel (±400 kHz) ±2 MHz ±10 MHz Configuration 915 MHz/150 kbps Adjacent Channel (±400 kHz) Alternate Channel (±800 kHz) ±2 MHz ±10 MHz Configuration 915 MHz/300 kbps Adjacent Channel (±600 kHz) Alternate Channel (±1200 kHz) ±2 MHz ±10 MHz Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5%, image calibrated FEC disabled, AFC enabled 44.5 52 67 77 dB dB dB dB 43.5 44 60.5 70 dB dB dB dB 28 33 62 72 dB dB dB dB FEC disabled, AFC enabled AFC disabled Rev. PrE | Page 17 of 55 ADF7030-1 Parameter CO CHANNEL REJECTION Preliminary Technical Data Min Typ Max Unit Configuration 915 MHz/50 kbps Configuration 915 MHz/150 kbps Configuration 915 MHz/300 kbps UNCALIBRATED IMAGE REJECTION −10 −10 −10 Configuration 915 MHz/50 kbps Configuration 915 MHz/150 kbps Configuration 915 MHz/300 kbps ADJACENT CHANNEL POWER (ACP) Configuration 915 MHz/50 kbps Adjacent Channel (±200 kHz) Alternate Channel (±400 kHz) Configuration 915 MHz/150 kbps Adjacent Channel (±400 kHz) Alternate Channel (±800 kHz) Configuration 915 MHz/300 kbps Adjacent Channel (±600 kHz) Alternate Channel (±1200 kHz) OCCUPIED BANDWIDTH 37 44 36 dB dB dB −55 −62 dBc dBc −53 −66 dBc dBc −30.5 −66 dBc dBc Configuration 915 MHz/50 kbps Configuration 915 MHz/150 kbps Configuration 915 MHz/300 kbps SPURIOUS EMISSIONS (EXCLUDING HARMONICS) Rx <960 MHz 960 MHz to 12.7 GHz Tx 85 167 475 kHz kHz kHz −82 −47 dBm dBm <960 MHz 960 MHz to 12.7 GHz HARMONIC EMISSIONS −71 −73 13 dBm Output Power Second Harmonic Third Harmonic Seventh Harmonic All Other Harmonics 17 dBm Output Power Second Harmonic Third Harmonic All Other Harmonics Test Conditions/Comments Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5% dB dB dB Desired signal 3 dB above the input sensitivity level (PER = 5%), CW interferer power level increased until PER = 5% Spectrum analyzer settings: RBW = 300 Hz, VBW = 1 kHz Spectrum analyzer settings: RBW = 300 Hz, VBW = 1 kHz Spectrum analyzer settings:, RBW = 300 Hz, VBW = 1 kHz Occupied bandwidth is the bandwidth containing 99% of the total integrated power Spectrum analyzer settings: RBW = 300 Hz, VBW = 1 kHz Spectrum analyzer settings: RBW = 300 Hz, VBW = 1 kHz Spectrum analyzer settings: RBW = 300 Hz, VBW = 1 kHz Measured conductively at antenna input; RF Frequency = 915 MHz PA2, output power = 17 dBm, transmitting continuous carrier wave dBc dBc Measured conductively at antenna input, transmitting continuous carrier wave; RF frequency = 915 MHz PA1 −53 −83 −88 <−90 dBc dBc dBc dBc −54 −66 <−90 dBc dBc dBc PA2 Rev. PrE | Page 18 of 55 Preliminary Technical Data ADF7030-1 EXTERNAL 26 MHz OSCILLATOR The ADF7030-1 requires a 26 MHz reference clock. This reference can be a 26 MHz crystal oscillator operating in parallel mode and connected between the HFXTALP and HFXTALN pins. Alternatively, a 26 MHz TCXO can be dc-coupled to the HFXTALN input. A TCXO is typically used in narrow-band applications where the transmit and receive RF frequency must meet accuracies not supported by a crystal oscillator. Table 16. Parameter DC-COUPLED TCXO TCXO Frequency Peak-to-Peak Voltage Level Voltage Level with Respect to Ground Duty Cycle CRYSTAL OSCILLATOR Crystal Frequency Maximum Crystal ESR Crystal Oscillator Load Capacitance HFXTALN, HFXTALP Pin Capacitance in Parallel with Crystal Oscillator Min Typ Max Unit 1.8 +1.9 60 MHz V V % 26 0.8 −0.1 40 Test Conditions/Comments HFXTALN pin, clipped sine wave Parallel resonant crystal 26 50 12 5 MHz Ω pF pF LOW FREQUENCY OSCILLATOR Table 17. Parameter 26 kHz INTERNAL RC OSCIALLATOR Frequency Frequency Accuracy Frequency Drift Temperature Coefficient Voltage Coefficient Calibration time 32 kHz EXTERNAL OSCILLATOR Frequency Start-Up Time Min Typ Max Unit Test Conditions/Comments 26 0.2 kHz % After calibration After calibration at 25°C 0.3 0.5 30 %/°C %/V ms 32.768 1.45 kHz s TEMPERATURE SENSOR Table 18. Parameter TEMPERATURE SENSOR Range Accuracy Min Typ −40 ±5 Max Unit Test Conditions/Comments +85 °C °C TA = −40°C to +85°C; Calibrated at 25°C Rev. PrE | Page 19 of 55 ADF7030-1 Preliminary Technical Data DIGITAL INPUT/OUTPUT Table 19. Parameter LOGIC INPUTS Input Voltage High Low Input Capacitance LOGIC OUTPUTS Output Voltage High Low Maximum GPIO Drive Strength for VOH Maximum GPIO Drive Strength for VOL Symbol Min Typ VINH VINL CIN 0.7 × VDD VOH VOL VDD − 0.4 Max Unit 0.2 × VDD V V pF 0.4 2 V V mA 2 mA 3.6 Test Conditions/Comments IOH = 500 µA IOL = 500 µA DIGITAL TIMING Table 20. SPI Interface Timing Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t121 t13 1 Description Falling edge to MISO setup time CS low to SCLK setup time SCLK high time SCLK low time SCLK period SCLK falling edge to MISO delay MOSI to SCLK rising edge setup time MOSI to SCLK rising edge hold time SCLK falling edge to CS hold time CS high time CS low to MISO high wake-up time MISO high to SCLK setup time RST low time Min Typ Max 15 40 40 40 80 10 5 5 40 80 92 SCLK low time 2 The minimum for t12 changes with the SCLK frequency. Rev. PrE | Page 20 of 55 Unit ns ns ns ns ns ns ns ns ns ns µs µs µs Preliminary Technical Data ADF7030-1 Timing Diagrams CS 10 2 3 4 5 9 SCLK 1 6 MISO BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1 0 BIT 7 BIT 0 X BIT 7 8 MOSI 7 6 5 4 3 2 7 Figure 2. SPI Interface Timing CS 9 12 SCLK 7 11 6 5 4 3 2 1 0 6 MISO 14373-003 X SPI STATE SLEEP WAKE UP SPI READY Figure 3. PHY_SLEEP to SPI Ready State Timing 14373-004 t13 RST Figure 4. Reset Pin (RST) Timing Rev. PrE | Page 21 of 55 14373-002 7 ADF7030-1 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All VBATx pins must be tied together. The LNAIN1 and LNAIN2 inputs must be ac-coupled. Table 21. Parameter Supply Pins VBAT1, VBAT2, VBAT3, VBAT4, VBAT5, VBAT6 to Ground LNAIN1, LNAIN2 PAOUT1, PAOUT2 HFXTALP, HFXTALN CLF CREG1, CREG2, CREG4, CREG5, CREG6, CREG7 CREG3 Digital Inputs/Outputs, GPIOx MOSI, MISO, SCLK, CS, RST Industrial Operating Temperature Range Storage Temperature Range Maximum Junction Temperature θJA Thermal Impedance ESD Rating, Human Body Model (HBM) 40-Lead LFCSP Package LNAIN1, LNAIN2, PAOUT1, PAOUT2 All Other Pins 48-Lead LQFP Package LNAIN1, LNAIN2, PAOUT1, PAOUT2 All Other Pins ESD Rating, Field Induced Charged Device Model (FIDSM) 40-Lead LFCSP Package LNAIN1, LNAIN2, PAOUT1, PAOUT2 All Other Pins 48-Lead LQFP Package LNAIN1, LNAIN2, PAOUT1, PAOUT2 All Other Pins Reflow Soldering Peak Temperature Time at Peak Temperature Rating −0.3 V to +3.9 V −0.3 V to +1.98 V −0.3 V to +3.9 V −0.3 V to +1.98 V −0.3 V to +1.98 V −0.3 V to +1.98 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −40°C to +85°C −65°C to +125°C 150°C 26°C/W Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Connect the exposed pad of the 40-lead LFCSP device to ground. This device is a high performance, RF integrated circuit with an ESD rating as indicated in Table 21; it is ESD sensitive. Take proper precautions for handling and assembly. ESD CAUTION ±250 V ±2 kV ±250 V ±2 kV ±1250 V ±1250 V ±1250 V ±1250 V 260°C 40 sec Rev. PrE | Page 22 of 55 Preliminary Technical Data ADF7030-1 40 39 38 37 36 35 34 33 32 31 VBAT6 CLF CREG7 CREG6 HFXTALN HFXTALP CREG5 DNC GPIO7 DNC PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 ADF7030-1 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 DNC GPIO6 CS SCLK MISO MOSI VBAT5 VBAT4 GPIO5 GPIO4 NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. CONNECT THE EXPOSED PAD TO GROUND. 14373-005 DNC PAOUT1 PAOUT2 VBAT3 CREG4 GPIO0 GPIO1 GPIO2 GPIO3 DNC 11 12 13 14 15 16 17 18 19 20 RST VBAT1 CREG1 VBAT2 CREG2 LNAIN1 LNAIN2 DNC CREG3 DNC Figure 5. 40-Lead LFCSP Pin Configuration Table 22. 40-Lead LFCSP Pin Function Descriptions Pin No. 1 2 3 Mnemonic RST VBAT1 CREG1 4 5 6 7 8 9 VBAT2 CREG2 LNAIN1 LNAIN2 DNC CREG3 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DNC DNC PAOUT1 PAOUT2 VBAT3 CREG4 GPIO0 GPIO1 GPIO2 GPIO3 DNC GPIO4 GPIO5 VBAT4 VBAT5 MOSI MISO SCLK CS Description External Reset, Active Low. Power Supply Pin 1 to the Internal Regulators. Regulator Output 1. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. Also, place a 1.2 nF capacitor between this pin and the CLF pin. Power Supply Pin 2 to the Internal Regulators. Regulator Output 2. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. LNA Input 1. LNA Input 2. Do Not Connect. Do not connect to this pin. Regulator Output 3. Connect to the PA choke inductor to provide bias to the PA. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. Do Not Connect. Do not connect to this pin. Do Not Connect. Do not connect to this pin. Single-Ended PA1 Output. Single-Ended PA2 Output. Power Supply Pin 3 to the Internal Regulators. Regulator Output 4. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. Digital GPIO Pin 0. Digital GPIO Pin 1. Digital GPIO Pin 2. Digital GPIO Pin 3. Do Not Connect. Do not connect to this pin. Digital GPIO Pin 4. Digital GPIO Pin 5. Power Supply Pin 4 to the Internal Regulators. Power Supply Pin 5 to the Internal Regulators. Serial Port Master Output/Slave Input. Serial Port Master Input/Slave Output. Serial Port Clock. Chip Select (Active Low). A pull-up resistor of 100 kΩ to VDD is recommended to prevent the host processor from inadvertently waking the ADF7030-1 from sleep. Rev. PrE | Page 23 of 55 ADF7030-1 Pin No. 29 30 31 32 33 34 35 Mnemonic GPIO6 DNC DNC GPIO7 DNC CREG5 HFXTALP 36 HFXTALN 37 38 39 40 CREG6 CREG7 CLF VBAT6 EPAD Preliminary Technical Data Description Digital GPIO Pin 6. Do Not Connect. Do not connect to this pin. Do Not Connect. Do not connect to this pin. Digital GPIO Pin 7. Do Not Connect. Do not connect to this pin. Regulator Output 5. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. Positive Reference Input. If a 26 MHz TCXO is used as the external reference, do not connect this pin. If a 26 MHz XTAL is used as the reference, connect this pin to the XTAL. Negative Reference Input. If a 26 MHz TCXO is used as the external reference, connect this pin to the TCXO output. If a 26 MHz XTAL is used as the reference, connect this pin to the XTAL. Regulator Output 6. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. Regulator Output 7. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. External Loop Filter Capacitor. Place a 1.2 nF capacitor between this pin and the CREG1 pin. Power Supply Pin 6 to the Internal Regulators. Exposed Pad. Connect the exposed pad to ground. Rev. PrE | Page 24 of 55 GPIO6 GPIO7 GND CREG5 GND HFXTALP HFXTALN CREG6 CREG7 GND CLF ADF7030-1 VBAT6 Preliminary Technical Data 48 47 46 45 44 43 42 41 40 39 38 37 GND 1 36 GND RST 2 35 GND 3 34 CS CREG1 4 33 SCLK DNC 5 32 MISO ADF7030-1 31 TOP VIEW (Not to Scale) MOSI 30 VBAT5 GND 8 29 VBAT4 LNAIN1 9 28 GPIO5 LNAIN2 10 27 GPIO4 GND 11 26 GND CREG3 12 25 GPIO3 VBAT1 VBAT2 6 CREG2 7 NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 14373-006 GPIO2 GPIO1 GPIO0 GND CREG4 VBAT3 DNC GND PAOUT2 GND GND PAOUT1 13 14 15 16 17 18 19 20 21 22 23 24 Figure 6. 48-Lead LQFP Pin Configuration Table 23. 48-Lead LQFP Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic GND RST VBAT1 CREG1 5 6 7 8 9 10 11 12 DNC VBAT2 CREG2 GND LNAIN1 LNAIN2 GND CREG3 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 GND PAOUT1 GND PAOUT2 GND DNC VBAT3 CREG4 GND GPIO0 GPIO1 GPIO2 GPIO3 GND GPIO4 GPIO5 VBAT4 VBAT5 Description Connection to Ground. External Reset, Active Low. Power Supply Pin 1 to the Internal Regulators. Regulator Output 1. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. Also, place a 1.2 nF capacitor between this pin and the CLF pin. Do Not Connect. Do not connect to this pin. Power Supply Pin 2 to the Internal Regulators. Regulator Output 2. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. Connection to Ground. LNA Input 1. LNA Input 2. Connection to Ground. Regulator Output 3. Connect to the PA choke inductor to provide bias to the PA. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. Connection to Ground. Single-Ended PA1 Output. Connection to Ground. Single-Ended PA2 Output. Connection to Ground. Do Not Connect. Do not connect to this pin. Power Supply Pin 3 to the Internal Regulators. Regulator Output 4. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. Connection to Ground. Digital GPIO Pin 0. Digital GPIO Pin 1. Digital GPIO Pin 2. Digital GPIO Pin 3. Connection to Ground. Digital GPIO Pin 4. Digital GPIO Pin 5. Power Supply Pin 4 to the Internal Regulators. Power Supply Pin 5 to the Internal Regulators. Rev. PrE | Page 25 of 55 ADF7030-1 Pin No. 31 32 33 34 Mnemonic MOSI MISO SCLK CS 35 36 37 38 39 40 41 42 GND GND GPIO6 GPIO7 GND CREG5 GND HFXTALP 43 HFXTALN 44 45 46 47 48 CREG6 CREG7 GND CLF VBAT6 Preliminary Technical Data Description Serial Port Master Output/Slave Input. Serial Port Master Input/Slave Output. Serial Port Clock. Chip Select (Active Low). A pull-up resistor of 100 kΩ to VDD is recommended to prevent the host processor from inadvertently waking the ADF7030-1 from sleep. Connection to Ground. Connection to Ground. Digital GPIO Pin 6. Digital GPIO Pin 7. Connection to Ground. Regulator Output 5. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. Connection to Ground. Positive Reference Input. If a 26 MHz TCXO is used as the external reference, do not connect this pin. If a 26 MHz XTAL is used as the reference connect, this pin to the XTAL. Negative Reference Input. If a 26 MHz TCXO is used as the external reference, connect this pin to the TCXO output. If a 26 MHz XTAL is used as the reference, connect this pin to the XTAL. Regulator Output 6. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. Regulator Output 7. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection. Connection to Ground. External Loop Filter Capacitor. Place a 1.2 nF capacitor between this pin and the CREG1 pin. Power Supply Pin 6 to the Internal Regulators. Rev. PrE | Page 26 of 55 Preliminary Technical Data ADF7030-1 TYPICAL PERFORMANCE CHARACTERISTICS 169 MHZ—RECEIVE 100 80 –120.6dBm –117.6dBm –110.6dBm –50dBm 0dBm 70 60 70 50 BLOCKING (dB) 60 50 40 20 30 10 0 10 –2 –1 0 1 2 3 RF FREQUENCY ERROR (kHz) –10 –200 –175 –150 –125 –100 –75 –50 –25 14373-007 0 –3 Figure 7. Packet Error Rate vs. RF Frequency Error and RF Input Power, Configuration 169.43125 MHz/2.4 kbps; AFC Enabled; VDD = 3.0 V; TA = 25°C 0 25 50 75 100 INTERFERER FREQUENCY OFFSET (kHz) Figure 10. Receiver Close-In Blocking vs. Interferer Frequency Offset, Temperature, and VDD; Configuration 169.43125 MHz/2.4 kbps; Unmodulated Interferer; Wanted Signal 3 dB Above the Sensitivity Level of BER = 0.1%; BER-Based Test 110 100 –119dBm –116dBm –109dBm –50dBm 0dBm 90 80 100 90 80 70 BLOCKING (dB) 60 50 40 30 70 +85°C, 3.6V +85°C, 3.0V +85°C, 2.2V +25°C, 3.6V +25°C, 3.0V +25°C, 2.2V –40°C, 3.6V –40°C, 3.0V –40°C, 2.2V 60 50 40 30 20 20 10 10 Figure 8. Packet Error Rate vs. RF Frequency Error and RF Input Power, Configuration 169.43125 MHz/4.8 kbps; AFC Enabled; VDD = 3.0 V; TA = 25°C 27 INTERFERER FREQUENCY OFFSET (kHz) 14373-011 24 21 18 15 12 6 9 0 3 –3 –9 3 –6 2 –15 1 –12 0 –21 –1 RF FREQUENCY ERROR (kHz) 14373-008 –2 –10 –18 0 0 –3 –24 PACKET ERROR RATE (%) +85°C, 3.6V +85°C, 3.0V +85°C, 2.2V +25°C, 3.6V +25°C, 3.0V +25°C, 2.2V –40°C, 3.6V –40°C, 3.0V –40°C, 2.2V 30 20 Figure 11. Receiver Wideband Blocking vs. Interfer Frequency Offset, Temperature, and VDD; Configuration 169.43125 MHz/2.4 kbps; Unmodulated Interferer; Wanted Signal 3 dB Above the Sensitivity Level of BER = 0.1%; BER-Based Test 2.0 100 +85°C, 3.6V +85°C, 2.2V +25°C, 3.6V +25°C, 2.2V –40°C, 3.6V –40°C, 2.2V 90 80 70 ERROR STANDARD DEVIATION 1.5 1.0 RSSI ERROR (dB) PACKET ERROR RATE (%) IMAGE FREQUENCY 40 –27 PACKET ERROR RATE (%) 80 14373-010 90 60 50 40 0.5 0 –0.5 30 –1.0 20 Figure 9. Packet Error Rate vs. RF Input Power, Temperature and VDD Configuration 169.43125 MHz/2.4 kbps RECEIVE INPUT POWER (dBm) –4 –14 –24 –34 –2.0 –44 –116 –54 –117 14373-012 RECEIVE POWER (dBm) –118 –64 –119 –74 –120 –84 –121 –94 –122 –104 –123 –124 –124 14373-009 0 –125 –114 –1.5 10 Figure 12. Packet RSSI Error vs. Rx Input Power with One-Point Calibration at −50 dBm, VDD = 3.0 V, TA = 25°C, Configuration 169.43125 MHz/2.4 kbps (Error is Based on the Mean RSSI of 100 Packets) Rev. PrE | Page 27 of 55 ADF7030-1 Preliminary Technical Data 169 MHZ—TRANSMIT –110 16 –115 13 10 7 –125 –130 –135 –140 –145 –150 –155 –160 10k 100k 10M 1M –5 –8 –11 –14 –17 –20 –23 100M FREQUENCY OFFSET (Hz) Figure 13. Phase Noise vs. Frequency Offset, RF Frequency = 169.43125 MHz, PA2 Output Power = 17 dBm, VDD = 3.0 V, TA = 25°C 0.5 PA COARSE = 1 PA COARSE = 2 PA COARSE = 3 PA COARSE = 4 PA COARSE = 5 PA COARSE = 6 0.2 0.1 –0.1 –0.2 –0.3 Figure 16. PA1 Output Power vs. PA_FINE Setting and PA_COARSE Setting with PA_FINE on a Log Scale, RF Frequency = 169.43125 MHz, VDD = 3.0 V, TA = 25°C –0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 1 3 5 7 9 11 13 15 17 19 PA2 OUTPUT POWER (dBm) AT T = 25°C, VBAT = 3.0V 14373-018 –0.5 –13 –11 –9 –7 –5 –3 –1 14373-015 13 15 9 11 7 3 5 1 –1 –3 –7 –5 –9 –11 –15 –13 Figure 17. Change in PA2 Output Power vs. Temperature, and VDD with PA_COARSE = 10, PAOLDO_VOUT_CON=15, RF Frequency = 169.43125 MHz 80 45 +85°C, 3.6V +85°C, 3.0V +85°C, 2.2V +25°C, 3.6V +25°C, 3.0V +25°C, 2.2V –40°C, 3.6V –40°C, 3.0V –40°C, 2.2V 35 30 25 70 VBATx SUPPLY CURRENT (mA) 40 20 15 10 60 50 40 +85°C, 3.6V +85°C, 3.0V +85°C, 2.85V +25°C, 3.6V +25°C, 3.0V +25°C, 2.85V –40°C, 3.6V –40°C, 3.0V –40°C, 2.85V 30 20 10 15 13 11 9 0 –13 –11 –9 –7 –5 –3 –1 14373-016 PA1 OUTPUT POWER (dBm) 7 5 3 1 –1 –3 –5 –7 –9 –11 –13 –15 5 Figure 15. VBATx Supply Current vs. PA1 Output Power, Temperature, and VDD with PA_COARSE = 6, RF Frequency = 169.43125 MHz 1 3 5 7 9 PA2 OUTPUT POWER (dBm) 11 13 15 17 19 14373-019 –17 Figure 14. Change in PA1 Output Power vs. Temperature, and VDD with PA_COARSE = 6, RF Frequency = 169.43125 MHz; Variation Above 11dBm Can Be Improved by Matching the PA for Higher Output Power –17 +85°C, 3.6V +85°C, 3.0V +85°C, 2.85V +25°C, 3.6V +25°C, 2.85V –40°C, 3.6V –40°C, 3.0V –40°C, 2.85V –0.4 PA1 OUTPUT POWER (dBm) AT T = 25°C, VBAT = 3.0V 0 200 0.4 0 –0.5 20 PA_FINE SETTING CHANGE IN OUTPUT POWER (dB) 0.3 2 0.5 +85°C, 3.6V +85°C, 3.0V +85°C, 2.85V +25°C, 3.6V +25°C, 2.85V –40°C, 3.6V –40°C, 3.0V –40°C, 2.85V 0.4 –32 14373-014 –170 1k CHANGE IN OUTPUT POWER (dB) –2 –26 –29 –165 VBATx SUPPLY CURRENT (mA) 4 1 14373-017 PA1 OUTPUT POWER (dBm) PHASE NOISE (dBc/Hz) –120 Figure 18. VBATx Supply Current vs. PA2 Output Power, Temperature, and VDD, PA_COARSE = 10, PAOLDO_VOUT_CON=15, RF Frequency = 169.43125 MHz Rev. PrE | Page 28 of 55 Preliminary Technical Data ADF7030-1 18 3.0 2.5 2.0 FREQUENCY DEVIATION (kHz) 10 6 2 –2 –6 PA COARSE = 5 PA COARSE = 6 PA COARSE = 7 PA COARSE = 8 PA COARSE = 9 PA COARSE = 10 –14 –18 –22 2 20 200 PA_FINE SETTING 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 0.50 0.75 1.00 1.25 1.50 1.75 2.00 TRANSMIT SYMBOL (Bits) Figure 19. PA2 Output Power vs. PA_FINE Setting and PA_COARSE Setting with PA_FINE on a Logarithmic Scale, VDD = 3.0 V, TA = 25°C, RF Frequency = 169 MHz Figure 21. Transmit Eye Diagram, PA2 Output Power = 17 dBm,, Configuration 169.43125 MHz/2.4 kbps, VDD = 3.0 V, TA = 25°C 0 20 –10 –20 0 –30 –40 POWER (dBm) POWER (dBm) 0.25 14373-022 –10 14373-020 PA2 OUTPUT POWER (dBm) 14 –50 –60 –70 –80 –20 +85°C, 3.6V +85°C, 3.0V +85°C, 2.85V +25°C, 3.6V +25°C, 3.0V +25°C, 2.85V –40°C, 3.6V –40°C, 3.0V –40°C, 2.85V –40 –60 –90 –100 –80 2ND 3RD 4TH 7TH 5TH 6TH HARMONIC 8TH 9TH 10TH –100 –20 14373-021 –120 Figure 20. Conductive Harmonic Emission Level, PA2 Output Power = 17 dBm, Carrier Unmodulated, RF Frequency = 169.43125 MHz, VDD = 3.0 V, TA = 25°C –15 –10 –5 0 5 FREQUENCY OFFSET (kHz) 10 15 20 14373-023 –110 Figure 22. Transmit Spectrum, PA2 Output Power = 17 dBm, Configuration 169.43125 MHz/2.4 kbps, VDD = 3.0 V, TA = 25°C Rev. PrE | Page 29 of 55 ADF7030-1 Preliminary Technical Data 433 MHZ—RECEIVE 100 100 –108.1dBm –105.1dBm –98.1dBm –50dBm 0dBm 90 90 80 70 70 BLOCKING (dB) 60 50 40 30 +85°C, 3.6V +85°C, 3.0V +85°C, 2.2V +25°C, 3.6V +25°C, 3.0V +25°C, 2.2V –40°C, 3.6V –40°C, 3.0V –40°C, 2.2V 40 30 10 10 0 –10 –5 0 5 10 15 20 –10 –27 14373-024 –15 RF FREQUENCY ERROR (kHz) Figure 23. Packet Error Rate vs. RF Frequency Error and RF Input Power; Configuration 433 MHz/50 kbps AFC Enabled; VDD = 3.0 V; TA = 25°C 80 –9 –3 3 9 15 21 27 3 AVERAGE ERROR STANDARD DEVIATION 2 RSSI ERROR (dB) 70 –15 Figure 25. Receiver Wideband Blocking vs. Interferer Frequency Offset, Temperature, and VDD; Configuration 433 MHz/50 kbps; Unmodulated Interferer; Wanted Signal 3 dB Above the Sensitivity Level of BER = 0.1%; BERBased Test +85°C, 3.6V +85°C, 2.2V +25°C, 3.6V +25°C, 2.2V –40°C, 3.6V –40°C, 2.2V 90 –21 INTERFERER FREQUENCY OFFSET (MHz) 100 PACKET ERROR RATE (%) 50 20 20 0 –20 60 14373-027 PACKET ERROR RATE (%) 80 60 50 40 30 1 0 –1 20 –2 RECEIVE POWER (dBm) –3 –113 14373-025 0 –115 –114 –113 –112 –111 –110 –109 –108 –107 –106 –105 Figure 24. Packet Error Rate vs. RF Input Power, Temperature, and VDD; Configuration 433 MHz/50 kbps –103 –93 –83 –73 –63 –53 –43 RECEIVE INPUT POWER (dBm) –33 –23 14373-028 10 Figure 26. Packet RSSI Error vs. RX Input Power with One-Point Calibration at −77 dBm; Configuration 433 MHz/50 kbps; VDD = 3.0 V; TA = 25°C (Error is Based on the Mean RSSI of 100 Packets) Rev. PrE | Page 30 of 55 Preliminary Technical Data ADF7030-1 433 MHZ—TRANSMIT –105 PA1 OUTPUT POWER (dBm) –115 –120 –125 –130 –135 –140 –145 –150 –155 10k 100k 10M 1M 100M FREQUENCY OFFSET (Hz) Figure 27. Phase Noise vs. Frequency Offset, RF Frequency = 433 MHz, PA1 Output Power = 10 dBm, VDD = 3.0 V, TA = 25°C 2 20 200 Figure 30. PA1 Output Power vs. PA_FINE Setting and PA_COARSE Setting with PA_FINE on a Logarithmic Scale, RF Frequency = 433 MHz, VDD = 3.0 V, TA = 25°C 0 +85°C, 3.6V +85°C, 3.0V +85°C, 2.85V +25°C, 3.6V +25°C, 2.85V –40°C, 3.6V –40°C, 3.0V –40°C, 2.85V 0.3 0.2 0.1 –10 –20 –30 POWER (dBm) 0.4 0 –0.1 –40 –50 –60 –70 –80 –0.2 –90 –0.3 15 PA1 OUTPUT POWER (dBm) AT T = 25°C, VBAT = 3.0V 14373-030 13 9 11 5 7 1 3 –1 –5 –3 –7 –9 –13 –11 –120 –15 –110 –0.5 Figure 28. Change in PA1 Output Power vs. Temperature, and VDD with PA_COARSE = 6, RF Frequency = 433 MHz 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH HARMONIC Figure 31. Conductive Harmonic Emission Level, PA1 Output Power = 10 dBm, RF Frequency = 433.92 MHz, VDD = 3.0 V, TA = 25°C 30 50 +85°C, 3.6V +85°C, 3.0V +85°C, 2.2V +25°C, 3.6V +25°C, 3.0V +25°C, 2.2V –40°C, 3.6V –40°C, 3.0V –40°C, 2.2V 40 35 30 25 20 FREQUENCY DEVIATION (kHz) 45 25 20 15 10 15 10 5 0 –5 –10 –15 –20 15 13 9 11 14373-031 PA1 OUTPUT POWER (dBm) 7 5 3 1 –1 –3 –5 –7 –9 –11 –30 –13 –25 0 –15 5 –17 2ND 14373-033 –100 –0.4 –17 CHANGE IN OUTPUT POWER (dB) PA COARSE = 1 PA COARSE = 2 PA COARSE = 3 PA COARSE = 4 PA COARSE = 5 PA COARSE = 6 PA_FINE SETTING 0.5 VBATx SUPPLY CURRENT (mA) –17 –20 –23 –26 –29 –32 14373-029 –160 1k –2 –5 –8 –11 –14 Figure 29. VBATx Supply Current vs. PA1 Output Power, Temperature, and VDD with PA_COARSE = 6, RF Frequency = 433 MHz Rev. PrE | Page 31 of 55 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 TRANSMIT SYMBOL (Bits) Figure 32. Transmit Eye Diagram, PA2 Output Power = 17 dBm, Configuration 433 MHz/50 kbps, VDD = 3.0 V, TA = 25°C 14373-034 PHASE NOISE (dBc/Hz) –110 16 13 10 7 4 1 14373-032 –100 ADF7030-1 Preliminary Technical Data 10 +85°C, 3.6V +85°C, 3.0V +85°C, 2.85V +25°C, 3.6V +25°C, 3.0V +25°C, 2.85V –40°C, 3.6V –40°C, 3.0V –40°C, 2.85V 0 –10 POWER (dBm) –20 –30 –40 –50 –60 –70 –80 –200 –100 0 100 FREQUENCY OFFSET (kHz) 200 300 14373-035 –90 –100 –300 Figure 33. Transmit Spectrum, PA1 Output Power = 10 dBm, Configuration 433 MHz/50 kbps, VDD = 3.0 V, TA = 25°C Rev. PrE | Page 32 of 55 Preliminary Technical Data ADF7030-1 460 MHZ—RECEIVE 110 100 –116.7dBm –113.7dBm –106.7dBm –50dBm 0dBm 90 90 80 70 BLOCKING (dB) 60 50 40 30 60 +85°C, 3.6V +85°C, 3.0V +85°C, 2.2V +25°C, 3.6V +25°C, 3.0V +25°C, 2.2V –40°C, 3.6V –40°C, 3.0V –40°C, 2.2V 50 40 30 20 20 10 10 Figure 34. Packet Error Rate vs. RF Frequency Error and RF Input Power; Configuration 460 MHz/7.2 kbps; AFC Enabled; VDD = 3.0 V; TA = 25°C +85°C, VDD +85°C, VDD +25°C, VDD +25°C, VDD –40°C, V DD –40°C, V DD 80 14373-039 27 24 21 18 15 9 12 6 3 0 –3 3 3.6V 2.2V 3.6V 2.2V 3.6V 2.2V AVERAGE ERROR STANDARD DEVIATION 2 RSSI ERROR (dB) 70 –6 INTERFERER FREQUENCY OFFSET (kHz) Figure 37. Receiver Wideband Blocking vs. Inteferer Frequency Offset, Temperature, and VDD; Configuration 460 MHz/7.2 kbps; Unmodulated Interferer; Wanted Signal 3 dB Above the Sensitivity Level of BER = 0.1%; BERBased Test 100 90 –9 3 –12 2 –15 1 –18 0 –21 –1 RF FREQUENCY ERROR (kHz) 14373-036 –2 –10 –24 0 0 –3 PACKET ERROR RATE (%) 70 –27 PACKET ERROR RATE (%) 80 100 60 50 40 30 1 0 –1 20 –2 RECEIVE POWER (dBm) –3 –122 –123 –102 –92 14373-037 0 –123 –122 –121 –120 –119 –118 –117 –116 –115 –114 –113 Figure 35. Packet Error Rate vs. RF Input Power, Temperature, and VDD; Configuration 460 MHz/7.2 kbps 65 45 35 +85°C, 3.6V +85°C, 3.0V +85°C, 2.2V +25°C, 3.6V +25°C, 3.0V +25°C, 2.2V –40°C, 3.6V –40°C, 3.0V –40°C, 2.2V 5 –5 –15 –100 –80 –60 –40 –20 0 20 40 60 INTERFERER FREQUENCY OFFSET (kHz) 80 100 14373-038 BLOCKING (dB) 55 15 –72 –62 –52 –42 –32 –22 –12 Figure 38. Packet RSSI Error vs. RF Input Power with One-Point Calibration at −77 dBm; Configuration 460 MHz/7.2 kbps, 7.2 kbps; VDD = 3.0 V; TA = 25°C (Error is Based on the Mean RSSI of 100 Packets) 75 25 –82 RECEIVE INPUT POWER (dBm) 14373-040 10 Figure 36. Receiver Close-In Blocking vs. Interferer Frequency Offset and Temperature and VDD; Configuration 460 MHz/7.2 kbps; Unmodulated Interferer; Wanted Signal 3 dB Above the Sensitivity Level of BER = 0.1%; BERBased Test Rev. PrE | Page 33 of 55 ADF7030-1 Preliminary Technical Data 460 MHZ—TRANSMIT –100 18 –105 14 –115 –120 –125 –130 –135 –140 –145 10 6 2 –2 –6 PA COARSE = 5 PA COARSE = 6 PA COARSE = 7 PA COARSE = 8 PA COARSE = 9 PA COARSE = 10 –10 –150 –14 –155 10k 100k 10M 1M 100M FREQUENCY OFFSET (Hz) –18 14373-041 –160 1k Figure 39. Phase Noise vs. Frequency Offset, RF Frequency = 460 MHz, PA2 Output Power = 17 dBm, VDD = 3.0 V, TA = 25°C 200 Figure 42. PA2 Output Power vs. PA_FINE Setting and PA_COARSE Setting with PA_FINE on a Logarithmic Scale, PAOLDO_VOUT_CON=15, RF Frequency = 460 MHz, VDD = 3.0 V, TA = 25°C 0 –10 0.4 FUNDAMENTAL = 450.0125 MHz FUNDAMENTAL = 460MHz FUNDAMENTAL = 469.9875 MHz –20 0.3 –30 POWER (dBm) 0.2 0.1 0 –0.2 –0.3 –0.4 +85°C, 3.6V +85°C, 3.0V +85°C, 2.85V +25°C, 3.6V +25°C, 2.85V –40°C, 3.6V –40°C, 3.0V –40°C, 2.85V –0.5 –11 –9 –7 –5 –3 –1 –70 –90 –110 1 3 5 7 9 11 13 15 17 19 –120 2ND 3RD 4TH 5TH 6TH 7TH HARMONIC 8TH 9TH 10TH Figure 43. Conductive Harmonic Emission Level, PA2 Output Power = 17 dBm, RF Frequency = 460 MHz, VDD = 3.0 V, TA = 25°C 30 60 25 +85°C, 3.6V +85°C, 3.0V +85°C, 2.85V +25°C, 3.6V +25°C, 3.0V +25°C, 2.2V –40°C, 3.6V –40°C, 3.0V –40°C, 2.85V FREQUENCY DEVIATION (kHz) 30 –60 –100 Figure 40. Change in PA2 Output Power vs. Temperature, and VDD with PA_COARSE = 10, PAOLDO_VOUT_CON=15, RF Frequency = 460 MHz; Variation above 15 dBm can be improved by matching the PA for higher output power 40 –50 –80 PA2 OUTPUT POWER (dBm) AT T = 25°C, VBAT = 3.0V 50 –40 14373-059 –0.1 14373-042 CHANGE IN OUTPUT POWER (dB) 20 PA_FINE SETTING 0.5 VBATx SUPPLY CURRENT (mA) 2 14373-044 PA2 OUTPUT POWER (dBm) PHASE NOISE (dBc/Hz) –110 20 20 15 10 0 –10 –15 –20 10 1 3 5 7 9 11 13 15 17 19 PA2 OUTPUT POWER (dBm) –30 14373-043 0 –11 –9 –7 –5 –3 –1 Figure 41. VBATx Supply Current vs. PA2 Output Power, Temperature, and VDD with PA_COARSE = 10, PAOLDO_VOUT_CON=15, RF Frequency = 460 MHz 0 0.25 0.50 0.75 1.00 1.25 TRANSMIT SYMBOL (Bits) 1.50 1.75 2.00 14373-045 –25 Figure 44. Transmit Eye Diagram; PA2 Output Power = 17 dBm; Configuration 460 MHz/7.2 kbps; BT = 0.5; VDD = 3.0 V; TA = 25°C Rev. PrE | Page 34 of 55 Preliminary Technical Data ADF7030-1 20 10 POWER (dBm) 0 –10 +85°C, 3.6V +85°C, 3.0V +85°C, 2.85V +25°C, 3.6V +25°C, 3.0V +25°C, 2.85V –40°C, 3.6V –40°C, 3.0V –40°C, 2.85V FCC 90 MASK D –20 –30 –40 –50 –70 –50 –40 –30 –20 –10 0 10 20 FREQUENCY OFFSET (kHz) 30 40 50 14373-046 –60 Figure 45. Transmit Spectrum, PA2 Output Power = 17 dBm, Configuration 460 MHz/7.2 kbps, BT = 0.5, VDD = 3.0 V, TA = 25°C; Margin to the mask can be improved by reducing the BT or by reducing the data rate Rev. PrE | Page 35 of 55 ADF7030-1 Preliminary Technical Data 868 MHZ—RECEIVE 100 –119.3dBm –116.3dBm –109.3dBm –50dBm 0dBm 80 70 60 50 40 30 60 50 40 30 20 10 10 0 –4 –3 –2 –1 0 1 2 3 4 RF FREQUENCY ERROR (kHz) Figure 46. Packet Error Rate vs. RF Frequency Error and RF Input Power, Configuration 868 MHz/4.8 kbps, AFC Enabled, VDD = 3.0 V, TA = 25°C 0 –113 –112 –111 –110 –109 –108 –107 –106 –105 –104 –103 RECEIVE POWER (dBm) Figure 49. Packet Error Rate vs. RX Input Power, Temperature, and VDD; Configuration 868 MHz/100 kbps 100 60 –108.1dBm –105.1dBm –98.1dBm –50dBm 0dBm 90 80 50 40 70 BLOCKING (dB) PACKET ERROR RATE (%) 70 20 14373-047 PACKET ERROR RATE (%) 80 +85°C, 3.6V +85°C, 2.2V +25°C, 3.6V +25°C, 2.2V –40°C, 3.6V –40°C, 2.2V 90 PACKET ERROR RATE (%) 90 14373-050 100 60 50 40 +85°C, 3.6V +85°C, 3.0V +85°C, 2.2V +25°C, 3.6V +25°C, 3.0V +25°C, 2.2V –40°C, 3.6V –40°C, 3.0V –40°C, 2.2V 30 20 10 30 0 20 Figure 47. Packet Error Rate vs. RF Frequency Error and RF Input Power, Configuration 868 MHz/100 kbps, AFC Enabled, VDD = 3.0 V, TA = 25°C 75 50 40 30 55 +85°C, 3.6V +85°C, 3.0V +85°C, 2.2V +25°C, 3.6V +25°C, 3.0V +25°C, 2.2V –40°C, 3.6V –40°C, 3.0V –40°C, 2.2V 45 35 25 15 20 5 10 RECEIVE POWER (dBm) Figure 48. Packet Error Rate vs. RF Input Power, Temperature, and VDD; Configuration 868 MHz/4.8 kbps 12 9 6 3 0 –3 –6 –9 –12 –15 –18 –21 –24 –15 14373-049 0 –125 –124 –123 –122 –121 –120 –119 –118 –117 –116 –115 –27 –5 INTERFERER FREQUENCY OFFSET (MHz) 27 60 65 14373-053 70 95 85 BLOCKING (dB) PACKET ERROR RATE (%) 105 +85°C, 3.6V +85°C, 2.2V +25°C, 3.6V +25°C, 2.2V –40°C, 3.6V –40°C, 2.2V 80 14373-051 Figure 50. Receiver Close-In Blocking vs. Interferer Frequency Offset, Temperature, and VDD, Configuration 868 MHz/4.8 kbps, Unmodulated Interferer, Wanted Signal 3 dB Above the Sensitivity Level of BER = 0.1%, BER-Based Test 100 90 80 90 100 INTERFERER FREQUENCY OFFSET (kHz) 24 RF FREQUENCY ERROR (kHz) –20 21 50 18 40 15 30 40 50 60 70 20 20 30 10 –10 0 10 0 –20 –10 –40 –30 –20 –60 –50 –30 –80 –70 –40 14373-048 0 –50 –100 –90 –10 10 Figure 51. Receiver Wideband Blocking vs. Interferer Frequency Offset, Temperature, and VDD; Configuration 868 MHz/4.8 kbps, Unmodulated Interferer; Wanted Signal 3 dB Above the Sensitivity Level of BER = 0.1%; BERBased Test Rev. PrE | Page 36 of 55 Preliminary Technical Data ADF7030-1 95 3 85 AVERAGE ERROR STANDARD DEVIATION 2 75 RSSI ERROR (dB) BLOCKING (dB) 65 55 +85°C, 3.6V +85°C, 3.0V +85°C, 2.2V +25°C, 3.6V +25°C, 3.0V +25°C, 2.2V –40°C, 3.6V –40°C, 3.0V –40°C, 2.2V 45 35 25 15 5 1 0 –1 –2 Figure 52. Receiver Wideband Blocking vs. Interferer Frequency Offset, Temperature, VDD; Configuration 868 MHz/100 kbps; Unmodulated Interferer; Wanted Signal 3 dB Above the Sensitivity Level of BER = 0.1%; BERBased Test RSSI ERROR (dB) 1 0 –1 –82 –72 –62 –52 –42 –32 –22 –12 14373-055 –2 RECEIVE INPUT POWER (dBm) –80 –70 –60 –50 –40 –30 –20 Figure 54. Packet RSSI Error vs. Rx Input Power with One-Point Calibration at −70 dBm; Configuration 868 MHz/100 kbps; VDD = 3.0 V; TA = 25°C (Error is Based on the Mean RSSI of 100 Packets) AVERAGE ERROR STANDARD DEVIATION –3 –122 –112 –102 –92 –90 RECEIVE INPUT POWER (dBm) 3 2 –100 14373-056 27 INTERFERER FREQUENCY OFFSET (MHz) –3 –110 14373-054 24 21 18 15 9 12 6 3 0 –3 –6 –9 –12 –15 –18 –21 –24 –15 –27 –5 Figure 53. Packet RSSI Error vs. Rx Input Power with One-Point Calibration at −77 dBm; Configuration 868 MHz/4.8 kbps; VDD = 3.0 V; TA = 25°C (Error is Based on the Mean RSSI of 100 Packets) Rev. PrE | Page 37 of 55 ADF7030-1 Preliminary Technical Data 868 MHZ—TRANSMIT –100 60 50 VBAT SUPPLY CURRENT (mA) –120 –130 –140 –150 20 10M 1M 100M 0 –17 –15 –13 –11 –9 –7 –5 –3 –1 Figure 55. Phase Noise vs. Frequency Offset, RF Frequency = 868 MHz, PA2 Output Power = 17 dBm, VDD = 3.0 V, TA = 25°C 0.1 0 –0.1 –0.2 –0.3 60 50 11 13 15 40 30 20 15 14373-058 9 11 7 5 3 1 –1 –3 –9 –5 0 –7 –0.5 –11 10 –13 –0.4 –15 9 PA1 OUTPUT POWER (dBm) AT T = 25°C, VBAT = 3.0V 13 11 7 5 3 1 1 3 5 7 9 11 13 15 17 19 PA2 OUTPUT POWER (dBm) Figure 59. VBATx Supply Current vs. PA2 Output Power, Temperature, and VDD with PA_COARSE = 10, RF Frequency = 868 MHz Figure 56. Change in PA1 Output Power vs. Temperature, and VDD with PA_COARSE = 10, RF Frequency = 868 MHz 17 0.5 –40°C, 2.85V –40°C, 3.0V –40°C, 3.6V +25°C, 2.85V +25°C, 3.6V +85°C, 2.85V +85°C, 3.0V +85°C, 3.6V 9 14373-259 0.2 T = 25°C VBAT = 3V PA COARSE = 1 PA COARSE = 2 PA COARSE = 3 PA COARSE = 4 PA COARSE = 5 PA COARSE = 6 13 PA1 OUTPUT POWER (dBm) 9 0.1 0 –0.1 –0.2 –0.3 5 1 –3 –7 –11 –15 –19 –23 –0.4 –27 13 11 9 7 5 3 1 1 3 5 7 9 PA2 OUTPUT POWER (dBm) 11 13 15 17 19 –31 14373-257 –0.5 7 –40°C, 2.85V –40°C, 3.0V –40°C, 3.6V +25°C, 2.85V +25°C, 3.0V +25°C, 3.6V +85°C, 2.85V +85°C, 3.0V +85°C, 3.6V 70 VBAT SUPPLY CURRENT (mA) 0.3 0.2 5 80 +85°C, 3.6V +85°C, 3.0V +85°C, 2.85V +25°C, 3.6V +25°C, 2.85V –40°C, 3.6V –40°C, 3.0V –40°C, 2.85V 0.4 0.3 3 Figure 58. VBATx Supply Current vs. PA1 Output Power, Temperature, and VDD with PA_COARSE = 6, RF Frequency = 868 MHz 0.5 0.4 1 PA1 OUTPUT POWER (dBm) 14373-258 100k 14373-057 10k FREQUENCY OFFSET (Hz) CHANGE IN OUTPUT POWER (dB) 30 10 –160 1k CHANGE IN OUTPUT POWER (dB) 40 Figure 57. Change in PA2 Output Power vs. Temperature, and VDD with PA_COARSE = 10, PAOLDO_VOUT_CON=15, RF Frequency = 868 MHz 2 20 PA_FINE SETTING 200 14373-260 PHASE NOISE (dBc/Hz) –110 –40°C, 2.2V –40°C, 3.0V –40°C, 3.6V +25°C, 2.2V +25°C, 3.0V +25°C, 3.6V +85°C, 2.2V +85°C, 3.0V +85°C, 3.6V Figure 60. PA1 Output Power vs. PA_FINE Setting and PA_COARSE Setting with PA_FINE on a Logarithmic Scale, RF Frequency = 868 MHz, VDD = 3.0 V, TA = 25°C Rev. PrE | Page 38 of 55 3.0 2.5 2.0 FREQUENCY DEVIATION (kHz) PA COARSE = 5 PA COARSE = 6 PA COARSE = 7 PA COARSE = 8 PA COARSE = 9 PA COARSE = 10 2 20 0.5 0 –0.5 –1.0 –1.5 –2.0 200 –3.0 0 0.25 0.50 0.75 1.00 1.25 1.50 2.00 Figure 63. Transmit Eye Diagram, PA2 Output Power = 17 dBm, Configuration 868 MHz/4.8 kbps; VDD = 3.0 V; TA = 25°C 20 FUNDAMENTAL = 863MHz FUNDAMENTAL = 868MHz FUNDAMENTAL = 876MHz +85°C, 3.6V +85°C, 3.0V +85°C, 2.85V +25°C, 3.6V +25°C, 3.0V +25°C, 2.85V –40°C, 3.6V –40°C, 3.0V –40°C, 2.85V 0 –20 –10 –30 –20 –40 POWER (dBm) POWER (dBm) 1.75 TRANSMIT SYMBOL (Bits) Figure 61. PA2 Output Power vs. PA_FINE Setting and PA_COARSE Setting with PA_FINE on a Logarithmic Scale, PAOLDO_VOUT_CON=15, RF Frequency = 868 MHz, VDD = 3.0 V, TA = 25°C 0 1.0 –2.5 PA_FINE SETTING –10 1.5 14373-062 19 17 15 13 11 9 7 5 3 1 –1 –3 –5 –7 –9 –11 –13 –15 –17 –19 ADF7030-1 14373-060 PA2 OUTPUT POWER (dBm) Preliminary Technical Data –50 –60 –70 –80 –30 –40 –50 –60 –90 –70 –100 2ND 3RD 4TH 7TH 6TH 5TH HARMONIC 8TH 9TH 10TH –90 –40 14373-061 –120 Figure 62. Conductive Harmonic Emission Level, PA2 Output Power = 17 dBm, RF Frequency = 868 MHz, VDD = 3.0 V, TA = 25°C –30 –20 –10 0 10 FREQUENCY OFFSET (kHz) 20 30 40 14373-063 –80 –110 Figure 64. Transmit Spectrum vs. Temperature, and VDD with PA2 Output Power = 17 dBm, Configuration 868 MHz/4.8 kbps, VDD = 3.0 V; TA = 25°C Rev. PrE | Page 39 of 55 ADF7030-1 Preliminary Technical Data 915 MHZ—RECEIVE 80 PACKET ERROR RATE (%) 80 90 70 60 50 40 30 50 40 30 20 10 10 –30 –20 –10 0 10 20 30 40 50 Figure 65. Packet Error Rate vs. RF Frequency Error and RF Input Power; Configuration 915 MHz/50 kbps; AFC Enabled; VDD = 3.0 V; TA = 25°C 100 PACKET ERROR RATE (%) 80 60 50 40 30 70 60 50 40 30 20 20 10 10 –40 –20 0 20 40 60 RF FREQUENCY ERROR (kHz) 0 –108 –107 –106 –105 –104 –103 –102 –101 –100 14373-165 Figure 66. Packet Error Rate vs. RF Frequency Error and RF Input Power; Configuration 915 MHz/150 kbps; AFC Enabled, VDD = 3.0 V; TA = 25°C –98 Figure 69. Packet Error Rate vs. Rx Power, Temperature, and VDD; Configuration 915 MHz/300 kbps; AFC Disabled 100 90 –101.9dBm –98.9dBm –91.9dBm –50dBm 0dBm 90 80 80 70 70 BLOCKING (dB) 60 60 50 40 50 40 30 30 20 20 10 10 0 –40 –20 0 20 RF FREQUENCY ERROR (kHz) 40 60 –10 –27 14373-166 0 –60 –99 RECEIVE POWER (dBm) Figure 67. Packet Error Rate vs. RF Frequency Error and RF Input Power, Configuration 915 MHz/300 kbps, AFC Disabled, VDD = 3.0 V, TA = 25°C +25°C, 2.2V +25°C, 3.0V +25°C, 3.6V –40°C, 2.2V –40°C, 3.0V –40°C, 3.6V +85°C, 2.2V +85°C, 3.0V +85°C, 3.6V –21 –15 –9 –3 3 9 15 INTERFERER FREQUENCY OFFSET (MHz) 21 27 14373-169 0 –60 –97 –40°C, 2.2V –40°C, 3.6V +25°C, 2.2V +25°C, 3.6V +85°C, 2.2V +85°C, 3.6V 90 70 –98 Figure 68. Packet Error Rate vs. Rx Input Power, Temperature, and VDD; Configuration 915 MHz/150 kbps; FEC Disabled; AFC Enabled –101.2dBm –98.2dBm –91.2dBm –50dBm 0dBm 80 –99 RECEIVE POWER (dBm) 100 90 –40°C, 2.2V –40°C, 3.6V +25°C, 2.2V +25°C, 3.6V +85°C, 2.2V +85°C, 3.6V 0 –107 –106 –105 –104 –103 –102 –101 –100 14373-164 –40 RF FREQUENCY ERROR (kHz) PACKET ERROR RATE (%) 60 20 0 –50 PACKET ERROR RATE (%) 70 14373-167 90 PACKET ERROR RATE (%) 100 –108.6dBm –105.6dBm –98.6dBm –50dBm 0dBm 14373-168 100 Figure 70. Receiver Wideband Blocking vs. Interferer Frequency Offset, Temperature, and VDD; Configuration 915 MHz/150 kbps; Unmodulated Interferer; Wanted Signal 3 dB Above the Sensitivity Level of BER = 0.1%; BERBased Test Rev. PrE | Page 40 of 55 Preliminary Technical Data ADF7030-1 3 CCA (RSSI) STANDARD DEVIATION (dB) AVERAGE ERROR STANDARD DEVIATION RSSI ERROR (dB) 2 1 0 –1 –3 –105 –95 –85 –75 –65 –55 –45 –35 –25 RECEIVE INPUT POWER (dBm) Figure 71. Packet RSSI Error vs. Rx Input Power with One-Point Calibration at −70 dBm; Configuration 915 MHz/150 kbps; VDD = 3.0 V; TA = 25°C (Error is Based on the Mean RSSI of 100 Packets) MEAN CCA (RSSI) ERROR (dB) 3 –40°C, 2.2V –40°C, 3.6V +25°C, 2.2V +25°C, 3.6V +85°C, 2.2V +85°C, 3.6V 2 –1 –75 –65 –55 –45 RECEIVE INPUT POWER (dBm) –35 –25 14373-171 –2 –85 0 –1 –2 –95 –85 –75 –65 –55 –45 –35 –25 Figure 73. CCA (RSSI) Standard Deviation vs. Rx Input Power, Temperature and VDD, with One-Point Calibration at −70 dBm (VDD = 2.2 V, TA = 25°C); Unmodulated RF signal; Configuration 915 MHz/150 kbps, (Standard Deviation is Based on 100 CCA Operations) 0 –95 1 RECEIVE INPUT POWER (dBm) 1 –3 –105 2 –3 –105 14373-170 –2 –40°C, 2.2V –40°C, 3.6V +25°C, 2.2V +25°C, 3.6V +85°C, 2.2V +85°C, 3.6V 14373-172 3 Figure 72. CCA (RSSI) Error vs. Rx Input Power, Temperature, and VDD with One-Point Calibration at −70 dBm (VDD = 2.2 V, TA = 25°C); Unmodulated RF signal; Configuration 915 MHz/150 kbps (Error is Based on the Mean of 100 CCA Operations) Rev. PrE | Page 41 of 55 ADF7030-1 Preliminary Technical Data 915 MHZ—TRANSMIT PA2 OUTPUT POWER (dBm) –120 –130 –140 –160 1k 10k 100k 1M 10M 14373-173 –150 100M FREQUENCY OFFSET (Hz) Figure 74. Phase Noise vs. Frequency Offset, RF Frequency = 915 MHz, PA2 Output Power = 17 dBm, VDD = 3.0 V, TA = 25°C 0.3 0.2 200 0 –40°C, 2.85V –40°C, 3.0V –40°C, 3.6V +25°C, 2.85V +25°C, 3.6V +85°C, 2.85V +85°C, 3.0V +85°C, 3.6V –10 FUNDAMENTAL = 902.2MHz FUNDAMENTAL = 915MHz FUNDAMENTAL = 927.8MHz –20 –30 0.1 0 –0.1 –40 –50 –60 –70 –80 –0.2 –90 –0.3 –0.4 –110 –0.5 –12 –120 –9 –6 –3 0 3 6 9 12 15 18 PA2 OUTPUT POWER (dBm) AT T = 25°C, VBAT = 3.0V 70 60 50 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH HARMONIC Figure 78. Conductive Harmonic Emission Level, PA2 Output Power = 17 dBm, RF Frequency = 915 MHz, VDD = 3.0 V, TA = 25°C 60 –40°C, 2.85V –40°C, 3.0V –40°C, 3.6V +25°C, 2.85V +25°C, 3.0V +25°C, 3.6V +85°C, 2.85V +85°C, 3.0V +85°C, 3.6V 50 40 FREQUENCY DEVIATION (kHz) 80 2ND 14373-177 –100 Figure 75. Change in PA2 Output Power vs. Temperature, and VDD with PA_COARSE = 10, PAOLDO_VOUT_CON=15, RF Frequency = 915 MHz VBATx SUPPLY CURRENT (mA) 20 Figure 77. PA2 Output Power vs. PA_FINE Setting and PA_COARSE Setting with PA_FINE on a Logarithmic Scale, PAOLDO_VOUT_CON=15, RF Frequency = 915 MHz, VDD = 3.0 V, TA = 25°C 14373-174 CHANGE IN OUTPUT POWER (dB) 0.4 2 PA_FINE SETTING POWER (dBm) 0.5 PA_COARSE = 5 PA_COARSE = 6 PA_COARSE = 7 PA_COARSE = 8 PA_COARSE = 9 PA_COARSE = 10 40 30 20 30 20 10 0 –10 –20 –30 –40 10 1 3 5 7 9 PA2 OUTPUT POWER (dBm) 11 13 15 17 19 14373-175 –50 0 –13 –11 –9 –7 –5 –3 –1 Figure 76. VBATx Supply Current vs. PA2 Output Power, Temperature, and VDD with PA_COARSE = 10, PAOLDO_VOUT_CON=15, RF Frequency = 915 MHz Rev. PrE | Page 42 of 55 –60 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 TRANSMIT SYMBOL (Bits) Figure 79. Transmit Eye Diagram, PA2 Output Power = 17 dBm, Configuration 915 MHz/150 kbps, VDD = 3.0 V, TA = 25°C 14373-178 PHASE NOISE (dBc/Hz) –110 19 17 15 13 11 9 7 5 3 1 –1 –3 –5 –7 –9 –11 –13 –15 –17 –19 14373-176 –100 Preliminary Technical Data ADF7030-1 0 200 –10 –20 100 –30 POWER (dBm) 50 0 –50 –50 –60 –70 –100 –80 –150 –90 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 TRANSMIT SYMBOL (Bits) 14373-179 –200 Figure 80. Transmit Eye Diagram, PA2 Output Power = 17 dBm, Configuration 915 MHz/300 kbps VDD = 3.0 V, TA = 25°C –100 –900 –20 –30 –40 –50 –60 –70 –400 –200 0 200 FREQEUNCY OFFSET (kHz) 400 600 14373-181 –80 –90 –600 –500 –300 –100 100 300 500 700 900 Figure 82. Transmit Spectrum vs. Temperature, and VDDPA2 Output Power = 17 dBm, Configuration: 915 MHz/300 kbps; VDD = 3.0 V; TA = 25°C +25°C, 2.2V +25°C, 3.0V +25°C, 3.6V –40°C, 2.2V –40°C, 3.0V –40°C, 3.6V +85°C, 2.2V +85°C, 3.0V +85°C, 3.6V –10 –700 FREQUENCY OFFSET (kHz) 0 POWER (dBm) –40 +25°C, 2.2V +25°C, 3.0V +25°C, 3.6V –40°C, 2.2V –40°C, 3.0V –40°C, 3.6V +85°C, 2.2V +85°C, 3.0V +85°C, 3.6V 14373-183 FREQUENCY DEVIATION (Hz) 150 Figure 81. Transmit Spectrum, PA2 Output Power = 17 dBm, Configuration: 915 MHz/150 kbps, VDD = 3.0 V, TA = 25°C Rev. PrE | Page 43 of 55 ADF7030-1 Preliminary Technical Data THEORY OF OPERATION STATE MACHINE The ADF7030-1 processor handles the sequencing of various radio circuits and critical timing functions, thereby simplifying radio operation and easing the burden on the host processor. TheADF7030-1 operates as a simple state machine as illustrated in Figure 83. The host processor can transition the ADF7030-1 between states by issuing single-byte commands over the SPI interface. The ADF7030-1 states are described in Table 24. RTC ALARM COLD START (BATTERY APPLIED) GPIO WAKEUP/CS LOW CMD_CONFIG_DEV (0x85) CMD_PHY_SLEEP (0x80) PHY_OFF (0x01) CONFIGURING (0x05) PHY_SLEEP CM 2) x8 1) (0 x8 N (0 O FF Y_ O PH Y_ D_ PH D_ CM NOTE THAT THE CALIBRATION FIRMWARE MODULE MUST BE DOWNLOADED BEFORE THE CMD_DO_CAL COMMAND IS SUPPORTED CALIBRATING (0x09) CMD_CCA (0x86) CMD _DO _CA L (0x8 9) CMD_CCA (0x86) PHY_ON (0x02) CMD_PHY_ON (0x82) CCA (0x06) MONITORING (0x0A) BUSY CHANNEL RX_EOF CM CM CM D_ D_ PH PH Y_ Y_ TX (0 O N x8 (0 x8 4) 2) 3) x8 2) (0 x8 RX (0 Y_ ON PH Y_ D_ PH D_ CM EL NN ) HA 84 (0x RC TX EA Y_ CL PH D_ CM TX_EOF CMD_PHY_TX (0x84) PHY_TX (0x04) PHY_RX (0x03) CMD_PHY_RX (0x83) CMD_PHY_TX (0x84) RX_TO_TX_AUTO_TURNAROUND CMD_PHY_RX (0x82) TX_TO_RX_AUTO_TURNAROUND KEY TRANSITION TRIGGERED BY A RADIO COMMAND TRANSITION TRIGGERED BY ADF7030-1 META STATE (FOR EXAMPLE, RETURN FROM THIS STATE TO THE PREVIOUS STATE WILL BE TRIGGERED BY THE ADF7030-1) 14373-087 STATES REQUIRING A FIRMWARE MODULE DOWNLOAD RADIO STATE Figure 83. Radio State Machine Diagram Table 24. Radio States State PHY_SLEEP PHY_OFF PHY_RX Description In this state, the ADF7030-1 is in sleep. Memory can be optionally retained. In this state, the ADF7030-1 executes using its own internal oscillator clock. The host configures the radio from this state. In this state, the external reference clock source is enabled. After entering this state, the ADF7030-1 is ready for the transmission and reception of packets. In this state, the ADF7030-1 can receive and process an incoming packet. PHY_TX In this state, the ADF7030-1 transmits the programmed packet data. CCA In this state, the ADF7030-1 performs clear channel assessment. PHY_ON Rev. PrE | Page 44 of 55 Typical Current 10 nA 3.7 mA 3.7 mA 21 mA to 25.4 mA (RF frequency and data rate dependent) 16 mA to 65 mA (RF frequency and Tx power dependent) 21 mA to 25.4 mA (frequency and data rate dependent) Preliminary Technical Data ADF7030-1 RADIO TIMING Table 25. Radio Timing Specifications Present State PHY_SLEEP Next State PHY_OFF PHY_SLEEP PHY_OFF PHY_OFF Command Initiated By Automatic Transition Time (μs), Typical at Data Rate = 2.4 kbps 101 Transition Time (μs), Typical at Data Rate = 300 kbps 101 Condition None Host 101 101 From CS low to PHY_OFF PHY_SLEEP Command/Bit Wake-up from PHY_SLEEP (RTC timeout event) Wake-up from PHY_SLEEP (CS low) CMD_PHY_SLEEP Host 95 95 PHY_OFF PHY_ON CMD_PHY_ON Host 206, 188 206, 188 PHY_OFF PHY_ON CMD_PHY_ON Host 490, 188 490, 188 PHY_OFF PHY_OFF PHY_ON PHY_ON PHY_ON PHY_ON PHY_ON CCA CCA CCA PHY_OFF PHY_OFF PHY_SLEEP PHY_OFF CCA PHY_TX PHY_RX PHY_ON PHY_ON PHY_TX CMD_CONFIG_DEV CMD_CONFIG_DEV CMD_PHY_SLEEP CMD_PHY_OFF CMD_CCA CMD_PHY_TX CMD_PHY_RX CMD_PHY_ON Channel busy Clear channel Host Host Host Host Host Host Host Host Automatic Automatic 36 10500 30 19 230 245 223 46 16 208 36 10500 30 19 230 245 225 46 16 203 CCA PHY_TX CMD_PHY_TX Host 239 239 PHY_TX PHY_ON CMD_PHY_ON Host 36 36 PHY_TX PHY_ON TX_EOF Automatic 26 26 PHY_TX PHY_TX CMD_PHY_TX Host 258 231 PHY_TX PHY_RX CMD_PHY_RX Host 204 208 PHY_TX PHY_RX Autoturnaround Automatic 204 208 PHY_RX PHY_RX PHY_ON PHY_ON CMD_PHY_ON RX_EOF Host Automatic 46 32 46 32 PHY_RX PHY_RX CMD_PHY_RX Host 216 220 PHY_RX PHY_TX Autoturnaround Automatic 220 220 PHY_RX PHY_TX CMD_PHY_TX Host 203 203 From CS low to PHY_SLEEP, memory retention enabled First transition after cold start or wake from PHY_SLEEP, subsequent transitions; 26 MHz TCXO reference First transition after cold start or wake from PHY_SLEEP, subsequent transitions; 26 MHz XTAL reference RTC not enabled RTC enabled None None To receiver enabled To start of PA ramp To receiver enabled None From receiver disabled From receiver disabled to start of PA ramp From receiver disabled to start of PA ramp From PA ramp finished to PHY_ON From PA ramp finished to PHY_ON From start of PA ramp down (at fastest PA ramp rate) to start of PA ramp up on new channel From PA ramp finished to receiver enabled From PA ramp finished to receiver enabled None From end of frame IRQ to PHY_ON From CS high to receiver enabled on new channel From end of frame IRQ to start of PA ramp From CS high to start of PA ramp Rev. PrE | Page 45 of 55 ADF7030-1 Preliminary Technical Data HOST INTERFACE Status Byte Physical Interface The ADF7030-1 reports the status via a status byte. The ADF7030-1 returns this byte on the SPI MISO in response to a no operation command (NOP) (0xFF) on the SPI MOSI. The ADF7030-1 provides a simple host interface (HIF) that consists of a 4-wire standard SPI, a hardware reset pin (RST) and GPIOs. The ADF7030-1 always acts as a slave to the host processor. The host uses the SPI to read and write ADF7030-1 memory and registers, to issue commands, and track status of the state machine, and to wake up the ADF7030-1 from PHY_SLEEP. Host Interface Protocol The ADF7030-1 implements a very simple protocol over the SPI interface. Using this protocol, the host processor can perform a number of operations, as described in the Memory Access section, the Radio Commands section, and the Status Byte section. RECEIVER The ADF7030-1 features a fully integrated, highly configurable receiver that enables exceptionally high performance reception of narrow-band and wideband 2FSK/2GFSK signals. The receiver is based on a low IF architecture. Figure 84 shows a simplified block diagram of the receiver. RF Front End The memory access commands allow the host processor to read from and write to the internal memory of the ADF7030-1. Typically, the host uses these commands to update the configuration of the ADF7030-1 and to write packets for transmission or read received packets. The receive signal is amplified by a differential LNA. The LNA is followed by a quadrature downconversion mixer that converts the RF signal to the IF frequency. The automatic gain control (AGC) circuit automatically controls the gain of the RF front end. The fully integrated, fractional N frequency synthesizer generates the LO for the mixer. When the ADF7030-1 enters the PHY_RX state, the bandwidth of the synthesizer is set automatically to ensure optimum interference rejection performance. Radio Commands IF Processing Memory Access A state machine command triggers a change of radio state as described in Table 26. Table 26. State Machine Radio Commands Command CMD_PHY_SLEEP CMD_PHY_OFF CMD_PHY_ON CMD_PHY_RX CMD_PHY_TX CMD_CONFIG_DEV CMD_CCA CMD_DO_CAL CMD_MON CMD_LFRC_CAL Description Performs a transition of the device into the PHY_SLEEP state Performs a transition of the device into the PHY_OFF state Performs a transition of the device into the PHY_ON state Performs a transition of the device into the PHY_RX state Performs a transition of the device into the PHY_TX state Configures the ADF7030-1 based on the radio profile Performs a transition of the device into the CCA state Executes selected calibration routines. Requires the OffLineCalibrations.cfg firmware module. Measures and reports the ADF7030-1 temperature Performs a frequency calibration of the internal 26kHz RC oscillator. Requires the OffLineCalibrations.cfg firmware module. The quadrature IF signal is band-pass filtered using a high performance, configurable analog filter. The filter is followed by a programmable gain array (PGA) that is controlled by the AGC circuit. The ADF7030-1 features a narrow-band and wideband IF processing path. In the narrow-band path, the IF signal is digitized by a high performance, high dynamic range ADC. RSSI, decimation, and offset correction are performed before the digitized IF is filtered using a configurable narrow-band digital channel filter. In the wideband path, a limiter converts the IF signal to digital levels for the demodulator. The limiter also provides offset correction and RSSI, which is digitized using the ADC. Rev. PrE | Page 46 of 55 ADF7030-1 14373-088 Preliminary Technical Data Figure 84. Receiver Block Diagram Table 27 and Table 28 list the supported channel bandwidths and IF frequencies. The ADF7030-1 graphic user interface (GUI) automatically chooses the correct receive path, channel bandwidth, and IF frequency based on the data rate and modulation settings. Table 27. Narrow-band Channel Bandwidths and IFs Narrow-Band Rx Path Channel BW (kHz) 3.0 3.2 3.4 3.7 3.9 4.2 4.4 4.7 5.1 5.4 5.8 6.2 6.6 7.0 7.5 8.1 8.5 8.7 9.1 9.7 10.4 10.6 11.1 11.7 11.9 12.7 13.5 14.4 15.4 16.4 17.6 18.7 20.0 IF (kHz) 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 81.25 Table 28. Wideband Channel Bandwidths and IFs Channel BW (kHz) 77 83 92 102 111 122 127 135 148 163 181 203 222 231 244 250 271 305 325 375 406 443 488 530 738 Wideband Rx Path IF (kHz) 155 110 184 135 222 162 154 271 196 325 240 406 295 241 487 336 360 609 432 750 540 886 648 540 588 AGC AGC is enabled by default and keeps the receiver gain at the correct level by selecting the LNA, mixer, and filter gain settings based on the measured RSSI level. AFC The ADF7030-1 features an internal real-time automatic frequency control loop. In receive mode, the control loop automatically monitors the frequency error during the packet preamble sequence and adjusts the receiver synthesizer local oscillator. AFC is supported without the need for any additional preamble bits in the received packet. Rev. PrE | Page 47 of 55 ADF7030-1 Preliminary Technical Data Baseband Processing The demodulator is based on a digital frequency correlator that performs filtering and frequency discrimination of the 2FSK/ 2GFSK spectrum. Following the demodulator is an oversampled digital clock and data recovery (CDR) PLL that resynchronizes the received bit stream to a local clock in all modulation modes. A serializer/deserializer (SERDES) block processes the received bit stream, carries out pattern matching, and produces the byte sized data for the ARM Cortex-M0 processor. The ARM Cortex-M0 processor performs all of the byte level packet processing and packet management. Received Signal Strength Indicator (RSSI) The ADF7030-1 support accurate measurement of the received signal strength. To achieve the calibrated absolute accuracy specification, a one-point factory calibration is required (see the Radio System Calibration section). The ADF7030-1 measures the RSSI during packet reception and the value is stored in a register for access by the host processor. The RSSI measurement is also used during CCA, where the RSSI measurement is evaluated against a user set threshold. The RSSI is reported in dBm. TRANSMITTER The ADF7030-1 transmitter supports 2FSK/2GFSK, 4FSK/4GFSK, and OOK modulation. It comprises a high performance PLL synthesizer and power efficient dual PAs. A block diagram of the ADF7030-1 transmitter architecture is shown in Figure 85. All blocks are fully integrated. Synthesizer and VCO An integrated low noise PLL synthesizer and VCO generate both the transmit signal and the receiver LO signal. The synthesizer loop filter has a programmable bandwidth. On entering the PHY_RX state, the ADF7030-1 sets a narrow bandwidth to ensure optimum receiver rejection. In the PHY_TX state, the bandwidth is chosen to ensure optimum modulation quality. A high speed, fully automatic calibration scheme ensures that the VCO performance is maintained over temperature, supply voltage, and process variations. The calibration is automatically performed when the CMD_PHY_RX or CMD_PHY_TX command is issued. Power Amplifiers The ADF7030-1 has two integrated power amplifiers. PA1 and PA2 are designed for optimum power consumption performance at 13 dBm and 17 dBm, respectively. The PAs cannot be operated simultaneously. The user selects the appropriate PA for their specific system. The power amplifiers are implemented as Class F type amplifiers. For systems where very fine power control is required, a PA microsetting can be used to achieve 0.1 dB of resolution across the power range. To reduce spectral splatter when the PA is turning on and off, a programmable PA ramp is provided. Transmit Modulation Schemes The ADF7030-1 supports 2FSK/2GFSK and 4FSK/4GFSK modulation in transmit mode. In 2FSK/2GFSK mode, a binary zero value generates a frequency deviation tone, –fDEV. A binary one generates a +fDEV tone. In 4FSK/4GFSK, the symbol mapping is configurable. OOK modulation is also supported in transmit mode at a data rate of 16.384 kbps. Transmit Filtering The ADF7030-1 supports Gaussian filtering in both 2FSK and 4FSK mode. Gaussian filtering reduces the occupied bandwidth of the signal by digitally prefiltering the transmit data. The BT factors is configurable with the following options: 0.5, 0.4, 0.35, or 0.3. Reducing BT increases the roll-off factor of the filter resulting in a narrower signal bandwidth. As BT is reduced, intersymbol interference is introduced, which affects the receiver sensitivity performance. 14373-089 Σ-Δ Figure 85. Transmitter Block Diagram Rev. PrE | Page 48 of 55 Preliminary Technical Data ADF7030-1 CALIBRATION is present on the RF input of the ADF7030-1 during calibration, this signal can degrade the calibration performance. The consequence of a degraded calibration is a reduction in the image rejection performance of the receiver. Table 28 provides an overview of the calibrations associated with the ADF7030-1 and when to run calibrations. Radio System Calibration To ensure that the ADF7030-1 radio performance meets the data sheet specifications, it is necessary to perform a one-time radio system calibration at 25°C ± 10°C. The radio system calibration routine is provided as a firmware module, OffLineCalibrations.cfg, that the host processor must download to the ADF7030-1 memory. The firmware module is available as part of the ADF7030-1 design package. The calibration is fully autonomous when initiated by the CMD_DO_CAL command. The radio system calibration firmware module can be downloaded to the ADF7030-1 and run as part of a factory calibration procedure and the calibration data stored on the host processor as part of the configuration settings for the ADF7030-1. Calibration data is maintained in PHY_SLEEP if memory retention is enabled. If the memory is not retained, the host processor must replay the calibration data to the ADF7030-1. Refer to the ADF7030-1 Software Reference Manual for further details on downloading and using firmware modules with the ADF7030-1. In the Field Radio System Calibration The only receiver performance metric, which benefits appreciably from a recalibration over temperature, is the image rejection. In applications where image rejection performance is critical over temperature, it may be necessary to perform a recalibration as the temperature changes. If the application requires the calibration to be performed in the field (in addition to the one-time factory calibration), it is important to consider interferer signals during calibration, because the calibration uses internally generated RF signals to perform certain aspects of the receiver calibration. If an interferer signal Table 29. ADF7030-1 Calibrations Calibration Radio System Description Calibration of the radio system When to Run this Calibration A one-time calibration is required to meet the datasheet specifications. This calibration can be performed as part of a factory calibration of the end product. 26 kHz RC Oscillator Frequency calibration of the internal 26 kHz RC oscillator RSSI Offset A single point, one-time, offset calibration of the RSSI A frequency calibration of the 26 kHz RC oscillator is required to meet the typical frequency accuracy specification. Depending on the frequency accuracy requirements of the application, it may also be necessary to calibrate as the temperature changes. Refer to Table 17 for specifications. A single-point, one-time, RSSI offset calibration is required to meet the RSSI accuracy specification of Table 3. This calibration can be performed as part of a factory calibration of the end product. If the application uses an external switch, the switch can be used to provide extra isolation between the antenna and the RF input of the ADF7030-1 during calibration. 26 kHz RC Oscillator Calibration To ensure that the 26 kHz RC oscillator meets the calibrated frequency accuracy specification, it is necessary to perform a calibration. During calibration, the OffLineCalibrations.cfg firmware module must be downloaded to the ADF7030-1. The calibration is fully autonomous when initiated by the CMD_LFRC_ CAL command. Refer to the ADF7030-1 Software Reference Manual for further details. RSSI Offset Calibration To ensure that the ADF7030-1 RSSI performance meets the calibrated RSSI data sheet specifications, it is necessary to perform a measurement of the ADF7030-1 RSSI measurement offset. The offset can be measured as part of a factory calibration procedure where an RF signal source applies a signal to the receiver input while the ADF7030-1 is in the continuous CCA state. The offset between the applied signal power and the ADF7030-1 RSSI result is stored on the host processor as part of the configuration settings for the ADF7030-1. The ADF7030-1 has allocated registers for the RSSI offset, and the ADF7030-1 automatically applies these offsets to the RSSI measurement result returned over the SPI. Refer to the ADF7030-1 Software Reference Manual for further details on the RSSI offset calibration procedure and the RSSI offset registers. Firmware Module Required Yes. The OffLineCalibrations.cfg firmware module must be downloaded to the ADF7030-1. Yes. The OffLineCalibrations.cfg firmware module must be downloaded to the ADF7030-1. None required. Rev. PrE | Page 49 of 55 Radio Command CMD_DO_CAL Typical Calibration Time (ms) 660 CMD_LFRC_CAL 30 N/A N/A ADF7030-1 Preliminary Technical Data PACKET HANDLING Transmitting and Receiving packets The ADF7030-1 includes comprehensive transmit and receive packet management capabilities and can be configured for use with a wide variety of packet-based radio protocols. The ADF7030-1 can be programmed to transmit and receive variable and fixed length payloads. The packet data to be transmitted must be written by the host into the ADF7030-1 internal memory. 511 bytes of dedicated RAM are available to store, transmit, and receive packets. For payload lengths greater than 511 bytes, the ADF7030-1 provides a rolling buffer mode. IEEE 802.15.4g Packet Mode The ADF7030-1 supports the multirate frequency shift keying (MR-FSK) PHY 802.15.4g specified packet format in the IEEE 802.15.4g-2012 standard with FEC, whitening and interleaving at data rates of up to 150 kbps. Generic Packet Mode The ADF7030-1 supports a wide variety of packet formats via its fully flexible generic packet format. In generic packet transmit mode, the ADF7030-1 can be configured to add the preamble, syncword, and CRC to the payload data stored in the packet memory. The number of preamble bits and sync bits is programmable, and an optional length field can be added to allow packet length decoding at the receiver. The CRC polynomial and length are fully programmable in generic packet mode. To transmit or receive a packet, the host processor must first configure the ADF7030-1. Then, the host processor issues the commands to place the ADF7030-1 into the PHY_RX state or the PHY_TX state. After either state is entered, the ADF7030-1 automatically starts transmitting or receiving a packet. In transmit mode, a preamble, sync word, and cyclic redundancy check (CRC) can be added by the ADF7030-1 to the payload data stored in the RAM. In receive mode, the ADF7030-1 can qualify received packets based on preamble detection, sync word detection, or CRC validation. On reception of a valid packet, the received payload data is loaded to packet memory. The host can track the progress of the transmission or reception of a packet by monitoring the interrupt signals coming from the ADF7030-1. There are two independent logical interrupts from the ADF7030-1, and events can be configured to trigger one or both of these logical interrupts. Rev. PrE | Page 50 of 55 Preliminary Technical Data ADF7030-1 APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT guide on application circuits, external hardware requirements, and RF matching for the ADF7030-1. A typical application circuit is shown in Figure 86. Refer to the ADF7030-1 Hardware Reference Manual for a comprehensive 26MHz TCXO 220nF 220nF 220nF OPTIONAL WAKEUP CRYSTAL 1.2nF 100nF 220nF 220nF RX MATCH OPTIONAL GPIO CONNECTION FROM ADF7030-1 100nF HARMONIC FILTER RST VBAT1 CREG1 VBAT2 CREG2 LNAIN1 LNAIN2 DNC CREG3 DNC ADF7030-1 TOP VIEW (Not to Scale) DNC GPIO6 CS SCLK MISO MOSI VBAT5 VBAT4 GPIO5 GPIO4 100kΩ GPIO CSN SCLK MISO MOSI 100nF INT1 INT2 220nF PA2 MATCH 100nF Figure 86. Typical Application Circuit with External Switch and TCXO Reference Rev. PrE | Page 51 of 55 14373-090 220nF HOST MICROPROCESSOR 100kΩ DNC PAOUT1 PAOUT2 VBAT3 CREG4 GPIO0 GPIO1 GPIO2 GPIO3 DNC 100nF VBAT6 CLF CREG7 CREG6 HFXTAL N HFXTAL P CREG5 DNC GPIO7 DNC 32.768kHz ADF7030-1 Preliminary Technical Data SILICON ANOMALY This anomaly list describes the known bugs, anomalies, and workarounds for the ADF7030-1. Analog Devices, Inc., is committed, through future silicon revisions and/or firmware module revisions, to continuously improve functionality. Analog Devices tries to ensure that these future revisions of the ADF7030-1 silicon or firmware modules remain compatible with your present software/systems by implementing the recommended workarounds outlined here. The silicon revision information can be electronically determined by reading the PART_ID and ROM_ID fields from the ADF7030-1 memory locations described in Table 30. Table 30. Silicon Revision ID IF Field PART_ID ROM_ID Length (Bytes) 2 1 Memory Address 0x00007FF6 0x00007FF9 ADF7030-1 FUNCTIONALITY ISSUES Silicon Revision ID PART_ID = 0x0602, ROM_ID = 0x02 Chip Marking ADF7030-1BCPZN or ADF7030-1BSTZN Rev. PrE | Page 52 of 55 Silicon Status Release No. of Reported Anomalies 2 Preliminary Technical Data ADF7030-1 FUNCTIONALITY ISSUES Table 31. Short Transmit Pulse Preceding Packet preamble on OOK Transmit [er001] Background Issue Workaround Related Issues In OOK transmit, a preamble sequence with the length controlled by PREAMBLE_LEN in the GENERIC_PKT_FRAME_CFG0 register is transmitted at the start of a packet. The first OOK transmit packet after a reset event or cold start has the correct preamble sequence. Subsequent OOK transmit packets prepend a short transmit pulse with a duration of less than one bit, before the preamble sequence. The output power of the pulse is at the configured output power. None. None. Table 32. CCA After Aborting PHY_TX During Packet Transmission for Data Rates < 3.064 kbps [er002] Background Issue The host processor can abort a transmission by issuing any radio command while the ADF7030-1 is in the PHY_TX state. For data rates < 3.064 kbps, the first CCA operation is inoperative after aborting a transmission. Workaround After aborting a transmission, enter the CCA state twice. On the first CCA entry, CCA is inoperative. On the second and subsequent entries to the CCA state, CCA is fully operational. None. Related Issues SECTION 1. ADF7030-1 FUNCTIONALITY ISSUES Reference Number er001 er002 Description Short transmit pulse preceding packet preamble on OOK transmit CCA after aborting PHY_TX during packet transmission for data rates < 3.064 kbps Rev. PrE | Page 53 of 55 Status Open Open ADF7030-1 Preliminary Technical Data DEVELOPMENT SUPPORT DESIGN PACKAGE The ADF7030-1 design resource package is a complete documentation and resource package for the ADF7030-1. It is recommended to download this package as a starting point for evaluation and development from the ADF7030-1 product page. It contains manuals, application notes, hardware information, and firmware modules. REFERENCE MANUALS ADF7030-1 Software Reference Manual (UG-1002) The ADF7030-1 Software Reference Manual is the detailed programming guide for the device. The ADF7030-1 hardware reference manual provides a description of the ADF7030-1 hardware features and application circuit requirements. ADF7030-1 Hardware Reference Manual (UG-957) The ADF7030-1 Hardware Reference Manual provides a description of the ADF7030-1 radio functionality, hardware features, and application circuit requirements. It is intended as a resource for a hardware engineer designing a printed circuit board (PCB) that includes the ADF7030-1. an evaluation and development system for the ADF7030-1 high performance, sub GHz, RF transceiver, and includes four models. These kits are listed in Table 33. Table 33. ADF7030-1 EZ-KIT Models Model ADF70301-915EZKIT ADF70301-868EZKIT ADF70301-433EZKIT ADF70301-169EZKIT Frequency (MHz) 902 to 928 863 to 876 433 to 434 169 A selection of individual daughter boards are also available covering various frequency bands and matching topologies. EVALUATION SOFTWARE The ADF7030-1 design center is a graphical user interface (GUI) that can be used for configuring the ADF7030-1, evaluating transmit and receive operation, and transmitting and receiving packets. This ADF7030-1 design center allows the user to rapidly prototype different configurations with the ADF7030-1 and simplifies the migration to host code development. EVALUATION KITS Evaluation and development kits are available that include the ADF7030-1 radio daughter boards. The ADF7030-1 EZ-KIT® is Rev. PrE | Page 54 of 55 Preliminary Technical Data ADF7030-1 OUTLINE DIMENSIONS 6.10 6.00 SQ 5.90 31 30 1 0.50 BSC 0.80 0.75 0.70 21 11 20 10 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 4.60 4.50 SQ 4.40 EXPOSED PAD 0.45 0.40 0.35 TOP VIEW PIN 1 INDICATOR 40 04-10-2014-A PIN 1 INDICATOR 0.30 0.25 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. Figure 87. 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm × 6 mm Body and 0.75 Package Height (CP-40-17) Dimensions shown in millimeters 0.75 0.60 0.45 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY (PINS DOWN) 25 12 13 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 88. 48-Lead Low Profile Quad Flat Package [LQFP] 7 mm × 7 mm Body, (ST-48) Dimensions shown in millimeters ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR14373-0-6/16(PrE) Rev. PrE | Page 55 of 55 24 0.27 0.22 0.17 051706-A 0.15 0.05 7.20 7.00 SQ 6.80 TOP VIEW 1.45 1.40 1.35