PDF Data Sheet Rev. PrA

Integrated, Dual RF Transceiver
with Observation Path
AD9371
Preliminary Technical Data
FEATURES
FUNCTIONAL BLOCK DIAGRAM
The AD9371 is a highly integrated, wideband RF transceiver
offering dual channel transmitters and receivers, integrated
synthesizers, and digital signal processing functions. The IC
delivers a versatile combination of high performance and low
power consumption required by 3G/4G micro and macro base
station equipment in both FDD and TDD applications. The
AD9371 operates from 300 MHz to 6000 MHz, covering most
of the licensed and unlicensed cellular bands. The IC supports
receiver bandwidths up to 100 MHz. It also supports observation
receiver and transmit synthesis bandwidths up to 250 MHz to
accommodate digital correction algorithms.
The transceiver consists of wideband direct conversion signal
paths with state-of-the-art noise figure and linearity. Each complete
receiver and transmitter subsystem includes dc offset correction,
quadrature error correction, and programmable digital filters,
eliminating the need for these functions in the digital baseband.
Several auxiliary functions such as an auxiliary analog-to-digital
converter (ADC), auxiliary digital-to-analog converters (DACs),
and general-purpose input/outputs (GPIOs) are integrated to
provide additional monitoring and control capability.
An observation receiver channel with two inputs is included to
monitor each transmitter output and implement interference
mitigation and calibration applications. This channel also connects
to three sniffer receiver inputs that can monitor radio activity in
different bands.
Rev. PrA
ADC
RX2–
LPF
ADC
MICROCONTROLLER
RX_EXTLO+
TX1–
RF
SYNTHESIZER
EXTERNAL
OPTION
SPI
PORT
TX1
LPF
TX2
DAC
TX2+
TX2–
pFIR,
DC OFFSET
QEC,
TUNING,
INTERPOLATION
LPF
DAC
TX_EXTLO+
TX_EXTLO–
LO
GENERATOR
RF
SYNTHESIZER
GPIO
ADXADC
AUXDAC
EXTERNAL
OPTION
LO
GENERATOR
RF
SYNTHESIZER
ORX1+
ORX1–
CLOCK
GENERATOR
OBSERVATION
Rx
SPI
TX1+
LO
GENERATOR
JESD204-B
RX_EXTLO–
JESD204-B
LPF
RX2
RX2+
ORX2+
ORX2–
SNRXA+
SNRXA–
SNRXB+
SNRXB–
SNRXC+
SNRXC–
SNIFFER
Rx
LPF
ADC
LPF
ADC
DECIMATION,
pFIR,
AGC,
DC OFFSET,
QEC,
TUNING,
RSSI,
OVERLOAD
14651-001
GENERAL DESCRIPTION
DECIMATION,
pFIR,
DC OFFSET
QEC,
TUNING,
RSSI,
OVERLOAD
CTRL I/F
3G/4G micro and macro base stations (BTS)
3G/4G multicarrier picocells
FDD and TDD active antenna systems
Microwave nonline-of-sight (NLOS) backhaul systems
RX1–
RX1
DEV_CLK_IN+/
DEV_CLK_IN–
APPLICATIONS
AD9371
RX1+
JESD204-B
Dual differential transmitters (Tx)
Dual differential receivers (Rx)
Observation receiver (ORx) with 2 inputs
Sniffer receiver (SnRx) with 3 inputs
Tunable range: 300 MHz to 6000 MHz
Tx synthesis bandwidth (BW) to 250 MHz
Rx BW: 8 MHz to 100 MHz
Supports frequency division duplex (FDD) and time division
duplex (TDD) operation
Fully integrated independent fractional-N radio frequency (RF)
synthesizers for Tx, Rx, ORx, and clock generation
JESD204B digital interface
Figure 1.
The high speed JESD204B interface supports lane rates up to
6144 Mbps. Four lanes are dedicated to the transmitters and four
lanes are dedicated to the receiver and observation receiver channels.
The fully integrated phase-locked loops (PLLs) provide high
performance, low power fractional-N frequency synthesis for
the transmitter, the receiver, the observation receiver, and the
clock sections. Careful design and layout techniques provide the
isolation demanded in high performance base station applications.
All voltage controlled oscillator (VCO) and loop filter components
are integrated to minimize the external component count.
A 1.3 V supply is required to power the core of the AD9371, and
a standard 4-wire serial port controls it. Other voltage supplies
provide proper digital interface levels and optimize transmitter
and auxiliary converter performance. The AD9371 is packaged in a
12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).
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Technical Support
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AD9371
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 45
Applications ....................................................................................... 1
Transmitter (Tx) ......................................................................... 45
General Description ......................................................................... 1
Receiver (Rx) ............................................................................... 45
Functional Block Diagram .............................................................. 1
Observation Receiver (ORx)..................................................... 45
Specifications..................................................................................... 3
Sniffer Receiver (SnRx) ............................................................. 45
Current and Power Consumption Specifications..................... 9
Clock Input.................................................................................. 45
Timing Specifications ................................................................ 11
Synthesizers ................................................................................. 46
Absolute Maximum Ratings .......................................................... 13
Serial Peripheral Interface (SPI) Interface .............................. 46
Reflow Profile .............................................................................. 13
GPIO_x AND GPIO_3P3_x Pins ............................................ 46
Thermal Resistance .................................................................... 13
Auxiliary Converters.................................................................. 46
ESD Caution ................................................................................ 13
JESD204B Data Interface .......................................................... 46
Pin Configuration and Function Descriptions ........................... 14
Power Supply Sequence ............................................................. 47
Typical Performance Characteristics ........................................... 17
JTAG Boundary Scan ................................................................. 47
2.6 GHz Band .............................................................................. 17
Outline Dimensions ....................................................................... 48
3.5 GHz Band .............................................................................. 27
5.5 GHz Band .............................................................................. 37
Rev. PrA | Page 2 of 48
Preliminary Technical Data
AD9371
SPECIFICATIONS
Electrical characteristics at ambient temperature range, VDDA_SER = 1.3 V, VDDA_DES = 1.3 V, JESD_VTT_DES = 1.3 V, VDDA_1P3 1 =
1.3 V, VDIG = 1.3 V, VDDA_1P8 = 1.8 V, VDD_IF = 2.5 V, and VDDA_3P3 = 3.3 V; all RF specifications based on measurements that
include printed circuit board (PCB) and matching circuit losses, unless otherwise noted.
Table 1.
Parameter
TRANSMITTERS (Tx)
Center Frequency
Tx Large Signal Bandwidth (BW)
Tx Synthesis BW 2
Symbol
Min
Typ
300
BW Flatness
Deviation from Linear Phase
Power Control Range
Max
Unit
6000
100
250
MHz
MHz
MHz
±0.5
dB
±0.15
dB
10
0
42
Power Control Resolution
ACLR 5 (Four Universal Mobile
Telecommunications System
[UMTS] Carriers)
700 MHz Local Oscillator (LO)
2600 MHz LO
3500 MHz LO
5500 MHz LO
In Band Noise
Tx to Tx Isolation
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Image Rejection
0.05
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Maximum Output Power
65
65
65
50
Degrees
dB
Wider bandwidth for use in
digital processing algorithms
250 MHz BW, compensated
by programmable finite
infinite response (FIR) filter
Any 20 MHz BW span,
compensated by
programmable FIR filter
250 MHz BW
Increased calibration time,
reduced QEC 3, LOL 4
performance beyond 20 dB
dB
−11.2 dBFS rms, 0 dB RF
attenuation
−64
−64
−63
−61
−155
dB
dB
dB
dB
dBFS 6/Hz
70
65
65
65
dB
dB
dB
dB
Up to 20 dB RF attenuation,
within large signal BW,
QEC3 active
dB
dB
dB
dB
0 dBFS, 1 MHz signal input,
50 Ω load, 0 dB RF attenuation
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
7
7
6
4
dBm
dBm
dBm
dBm
OIP3
Output Third-Order Intercept Point
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Test Conditions/Comments
−5 dBFS rms, 0 dB RF
attenuation
27
27
25
25
Rev. PrA | Page 3 of 48
dBm
dBm
dBm
dBm
AD9371
Parameter
Carrier Leakage
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Error Vector Magnitude (3GPP
Test Signals)
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Output Impedance
RECEIVERS (Rx)
Center Frequency
Gain Range
Analog Gain Step
BW Ripple
Preliminary Technical Data
Symbol
Min
dBFS6
dBFS6
dBFS6
dBFS6
−48
−39
−38.5
−37.5
50
300
0
75
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Test Conditions/Comments
After calibration, LOL
correction active, CW 7 input
signal, 3 dB RF and 3 dB digital
attenuation, 40 kHz
measurement BW
LTE 20 MHz downlink,
5 dB RF attenuation
Rx Alias Band Rejection
Maximum Recommended Input
Power 8
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Input Second-Order Intercept
Point
Unit
EVM
8
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Input Third-Order Intercept Point
Max
−81
−81
−81
−75
Rx Bandwidth
Noise Figure
Typ
dB
dB
dB
dB
Ω
6000
30
0.5
±0.5
MHz
dB
dB
dB
±0.2
dB
100
MHz
−14
dB
dBm
12
13.5
14
18
dB
dB
dB
dB
NF
IIP3
Differential
100 MHz BW, compensated
by programmable FIR filter
Any 20 MHz span,
compensated by
programmable FIR filter
Analog low-pass filter (LPF)
BW is 20 MHz minimum,
programmable FIR BW
configurable over the entire
range
Due to digital filters
Input is a CW7 signal at a 0 dB
attenuation setting; this level
increases dB for dB with
attenuation
Maximum Rx gain, at
Rx port, matching losses
de-embedded
Maximum Rx gain, thirdorder intermodulation (IM3)
1 MHz offset from LO
22
22
20
20
dBm
dBm
dBm
dBm
IIP2
Maximum Rx gain, secondorder intermodulation (IM2)
1 MHz offset from LO
65
65
65
57
Rev. PrA | Page 4 of 48
dBm
dBm
dBm
dBm
Preliminary Technical Data
Parameter
Image Rejection
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Input Impedance
Tx1 to Rx1 Signal Isolation and
Tx2 to Rx2 Signal Isolation
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Tx1 to Rx2 Signal Isolation and
Tx2 to Rx1 Signal Isolation
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Rx1 to Rx2 Signal Isolation
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Rx Band Spurs Referenced to
RF Input at Maximum Gain
Symbol
Rx LO Leakage at Rx Input at
Maximum Gain
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
OBSERVATION RECEIVER (ORx)
Center Frequency
Gain Range
Analog Gain Step
BW Ripple
Min
Typ
Max
Unit
75
75
75
75
200
dB
dB
dB
dB
Ω
68
68
62
60
dB
dB
dB
dB
70
70
62
60
dB
dB
dB
dB
60
60
60
60
−95
dB
dB
dB
dB
dBm
−65
−65
−62
−62
dBm
dBm
dBm
dBm
300
0
6000
18
1
±0.5
Deviation from Linear Phase
ORx Bandwidth
ORx Alias Band Rejection
Maximum Recommended Input
Power8
Signal-to-Noise Ratio 9
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
AD9371
10
MHz
dB
dB
dB
−13
Degrees
MHz
dB
dBm
60
60
60
59
dB
dB
dB
dB
250
60
SNR
Rev. PrA | Page 5 of 48
Test Conditions/Comments
QEC3 active, within Rx BW
Differential
No more than one spur at
this level per 10 MHz of Rx
BW; excludes harmonics of
the reference clock
Leakage decreases dB for dB
with attenuation for first 12 dB
250 MHz RF BW, compensated
by programmable FIR filter
250 MHz RF BW
Due to digital filters
Input is a CW7 signal at 0 dB
attenuation setting; this level
increases dB for dB with
attenuation
Maximum gain at ORx port
200 MHz BW, 245.76 MSPS
AD9371
Parameter
Input Third-Order Intercept Point
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Input Second-Order Intercept
Point
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Image Rejection
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Input Impedance
Tx1 to ORx1 Signal and Tx2 to
ORx2 Signal Isolation
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Tx1 to ORx2 Signal and Tx2 to
ORx1 Signal Isolation
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
SNIFFER RECEIVER (SnRx)
Center Frequency
Gain Range
Analog Gain Step
BW Ripple
Preliminary Technical Data
Symbol
IIP3
700 MHz LO
2600 MHz LO
3500 MHz LO
Input Third-Order Intercept Point
700 MHz LO
2600 MHz LO
3500 MHz LO
Typ
Max
22
22
18
18
Unit
Test Conditions/Comments
Maximum ORx gain,
IM3 1 MHz offset from LO
dBm
dBm
dBm
dBm
IIP2
Maximum ORx gain, IM2
1 MHz offset from LO
65
65
65
60
dBm
dBm
dBm
dBm
65
65
65
65
200
dB
dB
dB
dB
Ω
70
70
70
70
dB
dB
dB
dB
70
70
70
70
dB
dB
dB
dB
After online tone calibration
300
0
6000
52
1
±0.5
Rx Bandwidth
Rx Alias Band Rejection
Maximum Recommended Input
Power8
Noise Figure
Min
20
MHz
dB
dB
dB
−26
MHz
dB
dBm
5
5
7
dB
dB
dB
60
NF
IIP3
Differential
20 MHz RF BW, compensated
by programmable FIR filter
Due to digital filters
Input is a CW7 signal at 0 dB
attenuation setting; this level
increases dB for dB with
attenuation
Maximum gain at
SnRx port, matching losses
de-embedded
Maximum gain, IM3 1 MHz
offset from LO
1
1
1
Rev. PrA | Page 6 of 48
dBm
dBm
dBm
Preliminary Technical Data
Parameter
Input Second-Order Intercept
Point
700 MHz LO
2600 MHz LO
3500 MHz LO
Image Rejection
700 MHz LO
2600 MHz LO
3500 MHz LO
Input Impedance
Tx1 to SnRx Signal and Tx2 to
SNRx Signal Isolation
700 MHz LO
2600 MHz LO
3500 MHz LO
LO SYNTHESIZER
LO Frequency Step
Symbol
IIP2
AD9371
Min
Max
Unit
45
45
45
dBm
dBm
dBm
75
75
75
400
dB
dB
dB
Ω
60
60
60
dB
dB
dB
2.3
Hz
−80
dBc
−104
−107
−133
dBc
dBc
dBc
−93
−97
−123
dBc
dBc
dBc
−91
−97
−123
dBc
dBc
dBc
−98
−100
−110
dBc
dBc
dBc
Test Conditions/Comments
Maximum gain, IM2 1 MHz
offset from LO
After online tone calibration
LO Spur
Spot Phase Noise
700 MHz LO
10 kHz
100 kHz
1 MHz
2600 MHz LO
10 kHz
100 kHz
1 MHz
3500 MHz LO
10 kHz
100 kHz
1 MHz
5500 MHz LO
10 kHz
100 kHz
1 MHz
Integrated Phase Noise
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
REFERENCE CLOCK (DEV_CLK_IN
SIGNAL)
Frequency Range
Signal Level
Typ
Differential
Applies to each SnRx input
1.5 GHz to 3 GHz, 76.8 MHz
phase frequency detector
(PFD) frequency
Excludes integer boundary
spurs 1 kHz to 100 MHz
Integrated from 1 kHz to
100 MHz
0.20
0.49
0.55
0.75
10
0.3
°rms
°rms
°rms
°rms
320
2.0
Rev. PrA | Page 7 of 48
MHz
V p-p
AC-coupled, common-mode
voltage (VCM) = 618 mV; for
best spurious performance,
use a <1 V p-p input clock
AD9371
Parameter
AUXILIARY CONVERTERS
ADC
ADC Resolution
Input Voltage
Minimum
Maximum
Preliminary Technical Data
Symbol
Min
DAC
DAC Resolution
Output Voltage
Minimum
Maximum
Drive Capability
DIGITAL SPECIFICATIONS (CMOS)
Logic Inputs
Input Voltage
High Level
Low Level
Input Current
High Level
Low Level
Logic Outputs
Output Voltage
High Level
Typ
Input Differential Voltage
Threshold
Receiver Differential Input
Impedance
Logic Outputs
Output Voltage
High
Low
Differential
Offset
Unit
Test Conditions/Comments
12
Bits
0.05
VDDA_3P3 −
0.05
V
V
10
Bits
Includes four offset levels
0.5
VDDA_3P3 −
0.05
10
V
V
Reference voltage (VREF) = 1 V
VREF = 2.5 V
mA
VDD_IF ×
0.8
0
VDD_IF
V
VDD_IF ×
0.2
V
−10
−10
+10
+10
µA
µA
VDD_IF ×
0.8
V
Low Level
Drive Capability
DIGITAL SPECIFICATIONS (LVDS),
SYSREF_IN, SYNCINBx SIGNALS
Logic Inputs
Input Voltage Range
Max
VDD_IF ×
0.2
3
V
mA
825
1675
mV
−100
+100
mV
100
Ω
1375
1025
225
1200
Rev. PrA | Page 8 of 48
mV
mV
mV
mV
Each differential input in the
pair
Internal termination enabled
Preliminary Technical Data
Parameter
DIGITAL SPECIFICATIONS (CMOS),
GPIO_3P3_x SIGNAL
Logic Inputs
Input Voltage
High Level
Symbol
Low Level
Input Current
High Level
Low Level
Logic Outputs
Output Voltage
High Level
AD9371
Min
Typ
Max
Unit
VDDA_3P3
× 0.8
0
VDDA_3P3
V
VDDA_3P3
× 0.2
V
−10
−10
+10
+10
µA
µA
VDDA_3P3
× 0.8
V
Low Level
VDDA_3P3
× 0.2
Drive Capability
Test Conditions/Comments
4
V
mA
VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO,
VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.
Synthesis bandwidth (BW) is the extended bandwidth used by digital correction algorithms to measure conditions and generate compensation.
3
Quadrature error correction (QEC) is the system for minimizing quadrature images of a desired signal.
4
Local oscillator leakage (LOL) is a measure of the amount of the LO signal that is passed from a mixer with the desired signal.
5
Adjacent channel level reduction (ACLR) is a measure of the amount of power from the desired signal leaking into an adjacent channel.
6
dBFS represents the ratio of the actual output signal to the maximum possible output level for a continuous wave output signal at the given RF attenuation setting.
7
Continuous wave (CW) is a single frequency signal.
8
Note that the input signal power limit does not correspond to 0 dBFS at the digital output because of the nature of the continuous time Σ-Δ ADCs. Unlike the hard
clipping characteristic of pipeline ADCs, these converters exhibit a soft overload behavior when the input approaches the maximum level.
9
Signal-to-noise ratio is limited by the baseband quantization noise.
1
2
CURRENT AND POWER CONSUMPTION SPECIFICATIONS
Table 2.
Parameter
SUPPLY CHARACTERISTICS
VDDA_1P3 Analog Supplies 1
VDIG Supply
VDDA_1P8 Supply
VDD_IF Supply
VDDA_3P3 Supply
VDDA_SER, VDDA_DES,
JESD_VTT_DES Supplies
POSITIVE SUPPLY CURRENT (Rx MODE)
Min
Typ
Max
Unit
1.267
1.267
1.71
1.71
3.135
1.14
1.3
1.3
1.8
1.8
3.3
1.3
1.33
1.33
1.89
2.625
3.465
1.365
V
V
V
V
V
V
Test Conditions / Comments
CMOS and LVDS supply, 1.8 V to 2.5 V nominal range
Two Rx channels enabled, Tx upconverter disabled, 60 MHz
Rx BW, 122.88 MSPS data rate
VDDA_1P3 Analog Supplies1
VDIG Supply
VDD_IF Supply (CMOS and LVDS)
VDDA_3P3 Supply
1055
625
8
1
mA
mA
mA
mA
VDDA_SER, VDDA_DES,
JESD_VTT_DES Supplies
Total Power Dissipation
375
mA
2.70
W
Rx QEC 2 enabled, QEC2 engine active
No auxiliary DACs or auxiliary ADCs enabled; if enabled, the
auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA
Rev. PrA | Page 9 of 48
AD9371
Parameter
POSITIVE SUPPLY CURRENT (Tx MODE)
VDDA_1P3 Analog Supplies1
VDIG Supply
VDDA_1P8 Supply
VDD_IF Supply
VDDA_3P3 Supply
VDDA_SER, VDDA_DES,
JESD_VTT_DES Supplies
Total Power Dissipation
POSITIVE SUPPLY CURRENT (FDD
MODE), 2× Rx, 2× Tx, ORx ACTIVE
VDDA_1P3 Analog Supplies1
VDIG Supply
VDDA_1P8 Supply
VDD_IF Supply
VDDA_3P3 Supply
VDDA_SER, VDDA_DES,
JESD_VTT_DES Supplies
Total Power Dissipation
Preliminary Technical Data
Min
Typ
Max
1000
410
mA
mA
405
80
8
1
mA
mA
mA
mA
375
mA
3.70
3.11
W
W
1700
1080
mA
mA
405
80
8
2
mA
mA
mA
mA
375
mA
4.86
4.27
MAXIMUM OPERATING JUNCTION
TEMPERATURE
Unit
110
W
W
°C
Test Conditions / Comments
250 MHz Tx BW, 245.76 MSPS data rate
Tx QEC2 active
Full scale CW 3
Tx RF attenuation = 0 dB,
Tx RF attenuation = 15 dB
No auxiliary DACs or auxiliary ADCs enabled; if enabled, the
auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA
Typical supply voltages, Tx QEC2 active
Tx RF attenuation = 0 dB
Tx RF attenuation = 15 dB
250 MHz Tx BW, 245.76 MSPS data rate
Tx QEC2 active
Full scale CW3
Tx RF attenuation = 0 dB
Tx RF attenuation = 15 dB
No auxiliary DACs or auxiliary ADCs enabled; if enabled, the
auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA
Typical supply voltages, Tx QEC2 active
Tx RF attenuation = 0 dB
Tx RF attenuation = 15 dB
Device designed for 10-year lifetime when operating at
maximum junction temperature
VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO,
VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.
2
QEC is the system for minimizing quadrature images of a desired signal.
3
Continuous wave (CW) is a single frequency signal.
1
Rev. PrA | Page 10 of 48
Preliminary Technical Data
AD9371
TIMING SPECIFICATIONS
Table 3.
Parameter
SERIAL PERIPHERAL INTERFACE (SPI) TIMING
SCLK Period
SCLK Pulse Width
CSB Setup to First SCLK Rising Edge
Last SCLK Falling Edge to CSB Hold
SDIO Data Input Setup to SCLK
SDIO Data Input Hold to SCLK
SCLK Falling Edge to Output Data Delay (3- or 4-Wire Mode)
Bus Turnaround Time After Baseband Processor (BBP) Drives
Last Address Bit
Bus Turnaround Time After AD9371 Drives Last Address Bit
DIGITAL TIMING
TXx_ENABLE Pulse Width
RXx_ENABLE Pulse Width
JESD204B DATA OUTPUT TIMING
Unit Interval
Data Rate per Channel (NRZ)
Rise Time
Fall Time
Output Common-Mode Voltage
Termination Voltage (VTT) = 1.2 V
Differential Output Voltage
Short-Circuit Current
Differential Termination Impedance
Total Jitter
Uncorrelated Bounded High Probability Jitter
Duty-Cycle Distortion
SYSREF_IN Signal Setup Time to DEV_CLK_IN Signal
SYSREF_IN Signal Hold Time to DEV_CLK_IN Signal
JESD204B DATA INPUT TIMING
Unit Interval
Data Rate per Channel (NRZ)
Input Common-Mode Voltage
VTT = 1.2 V
Differential Input Voltage
VTT Source Impedance
Differential Termination Impedance
VTT
AC-Coupled
DC-Coupled
Symbol
Min
tCP
tMP
tSC
tHC
tS
tH
tCO
tHZM
tHZS
Typ
Max
Unit
20
10
3
0
2
0
3
tH
8
tCO
ns
ns
ns
ns
ns
ns
ns
ns
0
tCO
ns
10
10
UI
tR
tF
VCM
VDIFF
IDSHORT
ZRDIFF
UBHPJ
DCD
ts
th
UI
VCM
VDIFF
ZTT
ZRDIFF
162.76
614.4
24
24
0
735
360
−100
80
µs
µs
1627.6
6144
35
35
466
100
17
1.2
3
1.8
1135
770
+100
120
48.8
24.4
8.1
2.5
−1.5
162.76
614.4
0.05
720
125
80
1.27
1.14
Rev. PrA | Page 11 of 48
Test Conditions/Comments
1.2
106
ps
Mbps
ps
ps
V
mV
mV
mA
Ω
ps
ps
ps
ns
ns
1627.6
6144
1.85
1200
750
30
120
ps
Mbps
V
mV
mV
Ω
Ω
1.33
1.26
V
V
20% to 80% in 100 Ω load
20% to 80% in 100 Ω load
AC-coupled
DC-coupled
Bit error rate (BER) = 10−15
See Figure 2 and Figure 3
See Figure 2 and Figure 3
AC-coupled
DC-coupled
AD9371
Preliminary Technical Data
Timing Diagrams
DEV_CLK_IN DELAY
IN REFERENCE TO SYSREF
AT DEVICE PINS
tS
AT DIGITAL CORE
tS
tH
t'S
tH
t'H
t'H
tH = –1.5ns
tS = +2.5ns
14651-002
DEV_CLK_IN
t'H = +0.5ns
t'S = +0.5ns
CLK DELAY = 2ns
Figure 2. SYSREF_IN Signal Setup and Hold Timing
tS
tS
tH
tS
tH
tS
tH
tH
DEV_CLK_IN
VALID SYSREF_IN
INVALID SYSREF_IN
tH = –1.5ns
tS = +2.5ns
Figure 3. SYSREF_IN Signal Setup and Hold Timing Examples Relative to DEV_CLK_IN Signal
Rev. PrA | Page 12 of 48
14651-003
SYSREF_IN
Preliminary Technical Data
AD9371
ABSOLUTE MAXIMUM RATINGS
REFLOW PROFILE
Table 4.
Parameter
VDDA_1P31 to VSSA
VDDA_SER, VDDA_DES, and
JESD_VTT_DES to VSSA
VDIG to VSSD
VDDA_1P8 to VSSA
VDD_IF to VSSA
VDDA_3P3 to VSSA
Logic Inputs and Outputs to VSSD
JESD204B Logic Outputs to VSSA
JESD204B Logic Inputs to VSSA
Input Current to Any Pin Except
Supplies
Maximum Input Power into RF Ports
(Excluding Sniffer Receiver Inputs)
Maximum Input Power into SNRXA±,
SNRXB±, and SNRXC±
Maximum Junction Temperature (TJ MAX)
Operating Temperature Range
Storage Temperature Range
1
The AD9371 reflow profile is in accordance with the JEDEC
JESD20 criteria for Pb-free devices. The maximum reflow
temperature is 260°C.
Rating
−0.3 V to +1.4 V
−0.3 V to +1.4 V
THERMAL RESISTANCE
−0.3 V to +1.4 V
−0.3 V to +2.0 V
−0.3 V to +3.0 V
−0.3 V to +3.9 V
−0.3 V to VDD_IF + 0.3 V
−0.3 V to VDDA_SER
-0.3 V to VDDA_DES
±10 mA
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
Table 5. Thermal Resistance
Package
BC-196-12
JEDEC5
23 dBm (peak)
2 dBm (peak)
10-Layer PCB
110°C
−40°C to +85°C
−65°C to +150°C
1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
θJA2, 3 (°C/W)
θJC2, 4 (°C/W)
0.0
1.0
2.5
0.0
1.0
2.5
20.5
18.5
17.2
14.1
12.4
11.6
0.05
N/A6
N/A6
0.05
N/A6
N/A6
Power dissipation is 3.0 W for all test cases.
Per JEDEC JESD51-7 for JEDEC JESD51-5 2S2P test board.
3
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
4
Per MIL-STD 883, Method 1012.1.
5
JEDEC entries refer to the JEDEC JESD51-9 (high-K thermal test board).
6
N/A means not applicable.
2
VDDA_1P3 refers to all analog 1.3 V supplies: VDDA_BB, VDDA_CLKSYNTH,
VDDA_TXLO, VDDA_RXSYNTH, VDDA_RXVCO, VDDA_RXTX, VDDA_RXRF,
VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH,
VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.
Airflow
Velocity1 (m/s)
ESD CAUTION
Rev. PrA | Page 13 of 48
AD9371
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9371
TOP VIEW
(Not to Scale)
2
3
4
5
6
7
8
9
10
11
12
13
14
A
VSSA
ORX2+
ORX2–
VSSA
RX2+
RX2–
VSSA
VSSA
RX1+
RX1–
VSSA
ORX1+
ORX1–
VSSA
B
VDDA_RXRF
VSSA
VSSA
VSSA
VSSA
VSSA
RX_EXTLO–
RX_EXTLO+
VSSA
VSSA
VSSA
VSSA
VSSA
VDDA_3P3
C
GPIO_3P3_0
GPIO_3P3_1
VSNRX_
VCO_LDO
VDDA_
SNRXVCO
VSSA
VDDA_RXLO
VDDA_
RXVCO
VRX_
VCO_LDO
VSSA
VSSA
AUXADC_1
AUXADC_2
GPIO_3P3_9
RBIAS
D
GPIO_3P3_3
SNRXC–
SNRXB–
SNRXA–
GPIO_3P3_5
VSSA
VSSA
VSSA
VSSA
VDDA_1P8
AUXADC_3
GPIO_3P3_7
GPIO_3P3_8 GPIO_3P3_10
E
GPIO_3P3_4
SNRXC+
SNRXB+
SNRXA+
VDDA_BB
VSSA
DEV_
CLK_IN+
DEV_
CLK_IN–
VSSA
VSSA
TX_EXTLO–
TX_EXTLO+
AUXADC_0
GPIO_3P3_6
F
GPIO_3P3_2
VDDA_RXTX
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VDDA_
TXVCO
VDDA_TXLO
VTX_
VCO_LDO
GPIO_3P3_11
G
VSSA
VSSA
VSSA
VDDA_
CALPLL
VSSA
VDDA_
CLKSYNTH
VDDA_
SNRXSYNTH
VDDA_
TXSYNTH
VDDA_
RXSYNTH
VSSA
VSSA
VSSA
VSSA
VSSA
H
TX2–
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
GPIO_12
GPIO_11
VSSA
TX1+
J
TX2+
VSSA
GPIO_18
RESET
GP_
INTERRUPT
TEST
GPIO_2
GPIO_1
SDIO
SDO
GPIO_13
GPIO_10
VSSA
TX1–
K
VSSA
VSSA
SYSREF_IN+
SYSREF_IN–
GPIO_5
GPIO_4
GPIO_3
GPIO_0
SCLK
CSB
GPIO_14
GPIO_9
VSSA
VSSA
L
VSSA
VSSA
SYNCINB1–
SYNCINB1+
GPIO_6
GPIO_7
VSSD
VDIG
VDIG
VSSD
GPIO_15
GPIO_8
VSSA
VSSA
VCLK_
VCO_LDO
VSSA
SYNCINB0–
SYNCINB0+
RX1_
ENABLE
TX1_
ENABLE
RX2_
ENABLE
TX2_
ENABLE
VSSA
GPIO_17
GPIO_16
VDD_IF
N
VDDA_CLK
VSSA
SERDOUT3–
SERDOUT3+
SERDOUT2–
SERDOUT2+
VSSA
VDDA_SER
VDDA_DES
SERDIN2–
SERDIN2+
SERDIN3–
SERDIN3+
VSSA
P
VSSA
VSSA
VSSA
SERDOUT1–
SERDOUT1+
SERDOUT0-
SERDOUT0+
VDDA_SER
JESD_VTT_
DES
VSSA
SERDIN0–
SERDIN0+
SERDIN1–
SERDIN1+
M
ANALOG
INPUT/OUTPUT
DIGITAL
INPUT/OUTPUT
DC POWER
SYNCOUTB0+ SYNCOUTB0–
GROUND
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
A1, A4, A7, A8, A11, A14, B2 to B6,
B9 to B13, C5, C9, C10, D6 to D9,
E6, E9, E10, F3 to F10, G1 to G3, G5,
G10 to G14, H2 to H10, H13, J2, J13,
K1, K2, K13, K14, L1, L2, L13, L14,
M2, M9, N2, N7, N14, P1, P2, P3, P10
A2, A3
Type1
I
Mnemonic
VSSA
Description
Analog ground.
I
ORX2+, ORX2−
A5, A6
I
RX2+, RX2−
A9, A10
I
RX1+, RX1−
Differential Input for Observation Receiver 2. Do not
connect if these pins are unused.
Differential Input for Receiver 2. Do not connect if these pins
are unused.
Differential Input for Receiver 1. Do not connect if these pins
are unused.
Rev. PrA | Page 14 of 48
14651-004
1
Preliminary Technical Data
AD9371
Pin No.
A12, A13
Type 1
I
Mnemonic
ORX1+, ORX1−
B1
B7, B8
I
I/O
VDDA_RXRF
RX_EXTLO−, RX_EXTLO+
B14
C1, C2, C13, D1, D5, D12 to D14,
E1, E14, F1, F14
I
I/O
VDDA_3P3
GPIO_3P3_0 to GPIO_3P3_11
C3
O
VSNRX_VCO_LDO
C4
I
VDDA_SNRXVCO
C6
I
VDDA_RXLO
C7
C8
I
O
VDDA_RXVCO
VRX_VCO_LDO
C11
C12
C14
I
I
N/A
AUXADC_1
AUXADC_2
RBIAS
D2, E2
I
SNRXC−, SNRXC+
D3, E3
I
SNRXB−, SNRXB+
D4, E4
I
SNRXA−, SNRXA+
D10
D11
E5
E7, E8
E11, E12
I
I
I
I
I/O
VDDA_1P8
AUXADC_3
VDDA_BB
DEV_CLK_IN+, DEV_CLK_IN−
TX_EXTLO−, TX_EXTLO+
E13
F2
I
I
AUXADC_0
VDDA_RXTX
F11
F12
I
I
VDDA_TXVCO
VDDA_TXLO
F13
O
VTX_VCO_LDO
G4
I
VDDA_CALPLL
G6
I
VDDA_CLKSYNTH
G7
I
VDDA_SNRXSYNTH
G8
I
VDDA_TXSYNTH
G9
I
VDDA_RXSYNTH
Rev. PrA | Page 15 of 48
Description
Differential Input for Observation Receiver 1. Do not
connect if these pins are unused.
1.3 V Supply Input.
Differential Rx External LO Input/Output. If used for
external LO, the input frequency must be 2× the desired
carrier frequency. Do not connect if these pins are unused.
Supply Voltage for GPIO_3P3_x.
General-Purpose Inputs and Outputs Referenced to 3.3 V
Supply. See Figure 4 to match the ball location to the
GPIO_3P3_x signal name. Some GPIO_3P3_x pins can also
function as auxiliary DAC outputs.
Sniffer VCO LDO 1.1 V Output. Bypass this pin with a 1 µF
capacitor.
1.3 V Supply Input for Sniffer VCO Low Dropout (LDO)
Regulator.
1.3 V Supply for the Rx Synthesizer LO Generator. This pin
is sensitive to aggressors.
1.3 V Supply Input for Receiver VCO LDO Regulator.
Receiver VCO LDO 1.1 V Output. Bypass this pin with a 1 µF
capacitor.
Auxiliary ADC 1 Input Pin.
Auxiliary ADC 2 Input Pin.
Bias Resistor Connection. This pin generates an internal
current based on an external 1% resistor. Connect a
14.3 kΩ resistor between this pin and ground (VSSA).
Differential Input for Sniffer Receiver Input C. If these pins are
unused, connect to VSSA with a short or with a 1 kΩ resistor.
Differential Input for Sniffer Receiver Input B. If these pins are
unused, connect to VSSA with a short or with a 1 kΩ resistor.
Differential Input for Sniffer Receiver Input A. If these pins are
unused, connect to VSSA with a short or with a 1 kΩ resistor.
1.8 V Tx Supply.
Auxiliary ADC 3 Input Pin.
1.3 V Supply Input for ADCs, DACs, and Auxiliary ADCs.
Device Clock Differential Input.
Differential Tx External LO Input/Output. If these pins are
used for the external LO, the input frequency must be 2×
the desired carrier frequency. Do not connect if these pins
are unused.
AUXADC 0 Input Pin.
1.3 V Supply Input for Tx/Rx Baseband Circuits,
Transimpedance Amplifier (TIA), Tx Transconductance (Gm),
Baseband Filters, and Auxiliary DACs.
1.3 V Supply Input for Transmitter VCO LDO Regulator.
1.3 V Supply for the Tx Synthesizer LO Generator. This pin is
sensitive to aggressors.
Transmitter VCO LDO 1.1 V Output. Bypass this pin with a
1 µF capacitor.
1.3 V Supply Input for Calibration PLL Circuits. Use a
separate trace on the PCB back to a common supply point.
1.3 V Clock Synthesizer Supply Input. This pin is sensitive
to aggressors.
1.3 V Sniffer Synthesizer Supply Input. This pin is sensitive
to aggressors.
1.3 V Tx Synthesizer Supply Input. This pin is sensitive to
aggressors.
1.3 V Rx Synthesizer Supply Input. This pin is sensitive to
aggressors.
AD9371
Preliminary Technical Data
Pin No.
H1, J1
H11, H12, J3, J7, J8, J11, J12, K5 to K8,
K11, K12, L5, L6, L11, L12, M10, M11
Type 1
O
I/O
Mnemonic
TX2−, TX2+
GPIO_0 to GPIO_18
H14, J14
J4
J5
J6
O
I
O
I
TX1+, TX1−
RESET
GP_INTERRUPT
TEST
J9
I/O
SDIO
J10
K3, K4
K9
K10
L3, L4
O
I
I
I
I
SDO
SYSREF_IN+, SYSREF_IN−
SCLK
CSB
SYNCINB1−, SYNCINB1+
L7, L10
L8, L9
I
I
VSSD
VDIG
M1
O
VCLK_VCO_LDO
M3, M4
I
SYNCINB0−, SYNCINB0+
M5
M6
M7
M8
M12
M13, M14
I
I
I
I
I
O
RX1_ENABLE
TX1_ENABLE
RX2_ENABLE
TX2_ENABLE
VDD_IF
SYNCOUTB0+, SYNCOUTB0−
N1
N3, N4
I
O
VDDA_CLK
SERDOUT3−, SERDOUT3+
N5, N6
O
SERDOUT2−, SERDOUT2+
N8, P8
N9
N10, N11
N12, N13
P4, P5
I
I
I
I
O
VDDA_SER
VDDA_DES
SERDIN2−, SERDIN2+
SERDIN3−, SERDIN3+
SERDOUT1−, SERDOUT1+
P6, P7
O
SERDOUT0−, SERDOUT0+
P9
P11, P12
P13, P14
I
I
I
JESD_VTT_DES
SERDIN0−, SERDIN0+
SERDIN1−, SERDIN1+
1
I is input, O is output, I/O is input/output, and N/A is not applicable.
Rev. PrA | Page 16 of 48
Description
Differential Output for Transmitter 2.
General-Purpose Inputs and Outputs Referenced to
VDD_IF. See Figure 4 to match the ball location to the
GPIO_x signal name.
Differential Output for Transmitter 1.
Active Low Chip Reset.
General-Purpose Interrupt Signal.
Test Pin Used for JTAG Boundary Scan. Ground this pin if
unused.
Serial Data Input in 4-Wire Mode or Input/Output in 3-Wire
Mode.
Serial Data Output.
LVDS SYSREF Clock Inputs for the JESD Interface.
Serial Data Bus Clock.
Serial Data Bus Chip Select. Active low.
LVDS Sync Signal Associated with ORx/Sniffer Channel
Data on the JESD Interface.
Digital Ground.
1.3 V Digital Core Supply. Use a separate trace on the PCB
back to a common supply point.
Clock VCO LDO 1.1 V Output. Bypass this pin with a 1 µF
capacitor.
LVDS Sync Signal Associated with Rx Channel Data on the
JESD Interface.
Enables Rx Channel 1 Signal Path.
Enables Tx Channel 1 Signal Path.
Enables Rx Channel 2 Signal Path.
Enables Tx Channel 2 Signal Path.
CMOS/LVDS Interface Supply.
LVDS Sync Signal Associated with Transmitter Channel
Data on the JESD Interface.
1.3 V Clock Supply Input.
RF Current Mode Logic (CML) Differential Output 3. This
JESD lane can be used by the receiver data or by the
sniffer/observation receiver data.
RF CML Differential Output 2. This lane can be used by the
receiver data or by the sniffer/observation receiver data.
JESD204B 1.3 V Serializer Supply Input.
JESD204B 1.3 V Deserializer Supply Input.
RF CML Differential Input 2.
RF CML Differential Input 3.
RF CML Differential Output 1. This lane can be used by
receiver data or by sniffer/observation receiver data.
RF CML Differential Output 0. This lane can be used by
receiver data or by sniffer/observation receiver data.
JESD204B Deserializer Termination Supply Input.
RF CML Differential Input 0.
RF CML Differential Input 1.
Preliminary Technical Data
AD9371
TYPICAL PERFORMANCE CHARACTERISTICS
2.6 GHz BAND
Temperature settings refer to the die temperature. The die temperature is 40°C for single trace plots.
100
–30
90
80
RECEIVER IIP2 (dBm)
–50
–60
–70
–80
+110°C
+40°C
–40°C
–90
50
40
30
5
10
15
20
25
30
F1 OFFSET FREQUENCY (MHz)
14651-008
+110°C
+40°C
–40°C
0
14651-005
2900
2800
2700
2600
2500
2400
2300
2200
2100
0
2000
–110
1900
10
RECEIVER LO FREQUENCY (MHz)
Figure 8. Receiver IIP2 vs. F1 Offset Frequency, 2600 MHz LO, 0 dB Attenuation,
40 MHz RF Bandwidth, F2 = F1 + 1 MHz, 122.88 MSPS Sample Rate
45
100
40
90
80
30
25
20
15
10
70
60
50
40
30
F2 – F1, +110°C
F2 – F1, +40°C
F2 – F1, –40°C
F2 + F1, +110°C
F2 + F1, +40°C
F2 + F1, –40°C
20
+110°C
+40°C
–40°C
5
10
0
0
3
6
9
12
15
RECEIVER ATTENUATION (dB)
0
Figure 6. Receiver Noise Figure vs. Receiver Attenuation, 2600 MHz LO,
40 MHz Bandwidth, 122.88 MSPS Sample Rate, 20 MHz Integration
Bandwidth (Includes 1.4 dB Matching Circuit Loss)
5
10
15
20
25
30
INTERMODULATION FREQUENCY (MHz)
14651-009
RECEIVER IIP2 (dBm)
35
14651-006
RECEIVER NOISE FIGURE (dB)
60
20
Figure 5. Receiver LO Leakage vs. Receiver LO Frequency, 0 dB Receiver
Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
Figure 9. Receiver IIP2 vs. Intermodulation Frequency, 2600 MHz LO, 0 dB
Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
30
40
35
25
30
RECEIVER IIP3 (dBm)
RECEIVER NOISE FIGURE (dB)
70
–100
1800
RECEIVER LO LEAKAGE (dBm)
–40
20
15
+110°C
+40°C
–40°C
10
25
20
15
10
5
2900
2800
0
14651-007
RECEIVER LO FREQUENCY (MHz)
2700
2600
2500
2400
2300
2200
2100
2000
1900
1800
0
Figure 7. Receiver Noise Figure vs. Receiver LO Frequency, 0 dB Receiver
Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate, 20 MHz
Integration Bandwidth (Includes Matching Circuit Loss)
Rev. PrA | Page 17 of 48
0
5
10
15
20
25
30
F1 OFFSET FREQUENCY (MHz)
Figure 10. Receiver IIP3 vs. F1 Offset Frequency, 2600 MHz LO,
0 dB Attenuation, 40 MHz RF Bandwidth, F2 = 2F1 + 2 MHz,
122.88 MSPS Sample Rate
14651-010
+110°C
+40°C
–40°C
5
AD9371
Preliminary Technical Data
–40
40
+110°C
+40°C
–40°C
35
RECEIVER DC OFFSET (dBFS)
–50
25
20
15
F2 – 2F1, +110°C
F2 – 2F1, +40°C
F2 – 2F1, –40°C
F2 + 2F1, +110°C
F2 + 2F1, +40°C
F2 + 2F1, –40°C
5
10
15
20
25
–70
–80
–90
0
5
–60
30
INTERMODULATION FREQUENCY (MHz)
–100
Figure 11. Receiver IIP3 vs. Intermodulation Frequency, 2600 MHz LO,
0 dB Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
0
15
20
25
30
Figure 14. Receiver DC Offset vs. Receiver Attenuation, 2600 MHz LO,
40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
–40
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–50
–50
–60
RECEIVER HD2 (dBc)
–60
–70
–80
–90
–70
–80
–90
0
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
–110
14651-012
–100
Figure 12. Receiver Image vs. Receiver Attenuation, 2600 MHz LO,
Continuous Wave Signal 5 MHz Offset, 40 MHz RF Bandwidth,
Background Tracking Calibration (BTC) Active, 122.88 MSPS Sample Rate
0
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
14651-015
–100
Figure 15. Receiver HD2 vs. Receiver Attenuation, 2600 MHz LO,
Continuous Wave Signal 5 MHz Offset, −20 dBm at 0 dB Attenuation,
Input Power Increasing dB for dB with Attenuation,
40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
25
–40
+110°C
+40°C
–40°C
20
+110°C
+40°C
–40°C
–50
15
–60
RECEIVER HD3 (dBc)
10
5
0
–70
–80
–90
–5
–100
–15
0
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
Figure 13. Receiver Gain vs. Receiver Attenuation, 2600 MHz LO,
Continuous Wave Signal 5 MHz Offset, 40 MHz RF Bandwidth,
122.88 MSPS Sample Rate
14651-013
–10
–110
0
5
10
15
20
RECEIVER ATTENUATION (dB)
25
30
14651-016
RECEIVER IMAGE (dBc)
10
RECEIVER ATTENUATION (dB)
–40
RECEIVER GAIN (dB)
5
14651-014
10
14651-011
RECEIVER IIP3 (dBm)
30
Figure 16. Receiver HD3 vs. Receiver Attenuation, 2600 MHz LO,
Continuous Wave Signal 5 MHz Offset, −20 dBm at 0 dB Attenuation,
Input Power Increasing dB for dB with Attenuation, 40 MHz RF Bandwidth,
122.88 MSPS Sample Rate
Rev. PrA | Page 18 of 48
Preliminary Technical Data
AD9371
0
30
25
RECEIVER NOISE FIGURE (dB)
–5
–10
RECEIVER EVM (dB)
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–15
–20
–25
–30
–35
20
15
10
5
0
RECEIVER INPUT POWER (dBm)
Figure 17. Receiver EVM vs. Receiver Input Power, 2600 MHz LO, 40 MHz
RF Bandwidth, LTE 20 MHz Uplink Centered at DC, BTC Active,
122.88 MSPS Sample Rate
–10
–20
–20
TRANSMITTER IMAGE (dBc)
–10
–40
–50
–60
–70
5
10
15
20
RF ATTENUATION (dB)
Figure 21. Transmitter Image vs. RF Attenuation, 40 MHz RF Bandwidth,
2600 MHz LO, Transmitter QEC Tracking Run with Two 20 MHz LTE
Downlink Carriers, Then Image Measured with Continuous Wave 10 MHz
Offset from LO, 3 dB Digital Backoff, 245.76 MSPS Sample Rate
30
0
+110°C
+40°C
–40°C
–10
25
–20
TRANSMITTER IMAGE (dBc)
20
15
10
–30
–40
–50
–60
–70
–80
+110°C
+40°C
–40°C
–45
–40
–35
–30
–25
–20
INTERFERER SIGNAL POWER (dBm)
Figure 19. Receiver Noise Figure vs. Close-In Interferer Signal Power,
2614 MHz LO, 2625 MHz Continuous Wave Interferer, Noise Figure
Integrated over 7 MHz to 10 MHz, 40 MHz RF Bandwidth
–90
–100
–20
–15
–10
–5
0
5
10
DESIRED OFFSET FREQUENCY (MHz)
15
20
14651-022
5
14651-019
RECEIVER NOISE FIGURE (dB)
0
+110°C
+40°C
–40°C
0
14651-018
2900
2800
2700
2600
2500
2400
2300
2200
–100
0
–50
–5
–70
–100
2100
–10
–60
–90
2000
–15
–50
–90
1900
–20
–40
–80
RECEIVER LO FREQUENCY (MHz)
–25
–30
–80
Figure 18. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency, 40 MHz
RF Bandwidth, Continuous Wave Tone 3 MHz Offset from LO
–30
Figure 20. Receiver Noise Figure vs. Out of Band Interferer Signal Power,
2614 MHz LO, 2435 MHz Continuous Wave Interferer, Noise Figure
Integrated over 7 MHz to 10 MHz
0
–30
–35
INTERFERER SIGNAL POWER (dBm)
0
1800
Rx2 TO Rx1 CROSSTALK (dB)
0
–40
14651-021
–5
14651-017
–45
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10
14651-020
–40
Figure 22. Transmitter Image vs. Desired Offset Frequency, 40 MHz RF
Bandwidth, 2300 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking
Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with
Continuous Wave Signal, 3 dB Digital Backoff, 245.76 MSPS Sample Rate
Rev. PrA | Page 19 of 48
Preliminary Technical Data
10
0
8
–10
6
–20
Tx1 TO Rx1 CROSSTALK (dB)
4
2
0
–2
–4
–6
–70
–80
2900
0
+110°C
+40°C
–40°C
Tx2 TO Rx2 CROSSTALK (dB)
–10
–70
–75
–80
–85
–90
–95
–20
–30
–40
–50
–60
–70
–80
2900
RECEIVER LO FREQUENCY (MHz)
Figure 27. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency,
40 MHz Receiver RF Bandwidth, 40 MHz Transmitter RF Bandwidth,
Continuous Wave Signal 3 MHz Offset from LO
Figure 24. Transmitter LO Leakage vs. RF Attenuation, 2300 MHz LO,
External Transmitter QEC and LO Leakage Tracking Active, Continuous Wave
Signal 10 MHz Offset from LO, 6 dB Digital Backoff, 1 MHz Measurement
Bandwidth (If Input Power to the ORx Channel Is Not Held Constant,
Device Performance Degrades as Shown in This Figure)
0
–60
–10
–80
–85
–90
–95
–30
–40
–50
–60
–70
–80
2900
TRANSMITTER LO FREQUENCY (MHz)
Figure 25. Transmitter LO Leakage vs. Offset Frequency, 2300 MHz LO,
External Transmitter QEC and LO Leakage Tracking Active, 6 dB Digital
Backoff, 1 MHz Measurement Bandwidth
Figure 28. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,
40 MHz RF Bandwidth, Continuous Wave Signal 3 MHz Offset from LO
Rev. PrA | Page 20 of 48
14651-028
2800
2700
2600
30
2500
20
2400
10
2300
0
2200
–10
OFFSET FREQUENCY (MHz)
2100
–20
–100
2000
–90
14651-025
–100
–30
–20
1900
–75
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
1800
–70
1.8GHz,
1.8GHz,
1.8GHz,
2.3GHz,
2.3GHz,
2.3GHz,
2.8GHz,
2.8GHz,
2.8GHz,
Tx2 TO Tx1 CROSSTALK (dB)
–65
14651-027
2800
2700
2600
2500
RF ATTENUATION (dB)
–100
2400
20
2300
15
2200
10
2100
5
2000
0
1900
–90
–100
TRANSMITTER LO LEAKAGE (dBFS)
14651-026
2800
2700
2600
2500
2400
2300
2200
2100
2000
1900
2900
1800
RECEIVER LO FREQUENCY (MHz)
Figure 26. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency,
40 MHz Receiver RF Bandwidth, 40 MHz Transmitter RF Bandwidth,
Continuous Wave Signal 3 MHz Offset from LO
14651-024
TRANSMITTER LO LEAKAGE (dBFS)
–60
–90
FREQUENCY (MHz)
–65
–50
–100
Figure 23. Tx Output Power, Transmitter QEC, and External LO Leakage Active,
5 MHz Continuous Wave Offset Signal, 1 MHz Resolution Bandwidth,
245.76 MSPS Sample Rate
–60
–40
14651-023
2700
2600
2500
2400
2300
2200
2100
2000
1900
1800
–8
–10
2800
+110°C
+40°C
–40°C
–30
1800
Tx OUTPUT (dBm)
AD9371
Preliminary Technical Data
AD9371
–60
–80
+110°C
+40°C
–40°C
–70
–80
–120
–130
–140
–150
–100
–110
–120
–160
–130
–170
–140
–180
20
RF ATTENUATION (dB)
Figure 29. Transmitter Noise vs. RF Attenuation, 2600 MHz LO,
10 MHz Offset Frequency
–150
100
Tx INTEGRATED PHASE NOISE (Degrees)
0.2
2900
0
TRANSMITTER LO FREQUENCY (MHz)
Figure 33. Tx Integrated Phase Noise vs. Transmitter LO Frequency,
40 MHz RF Bandwidth, Continuous Wave 20 MHz Offset from LO,
3 dB Digital Backoff
–40
35
+110°C UPPER
+40°C UPPER
–40°C UPPER
+110°C LOWER
+40°C LOWER
–40°C LOWER
–50
+110°C
+40°C
–40°C
30
TRANSMITTER OIP3 (dBm)
–45
–55
–60
–65
–70
25
20
15
10
–80
0
4
8
12
RF ATTENUATION (dB)
16
20
0
Figure 31. Tx Alternate Channel Leakage Ratio vs. RF Attenuation,
2600 MHz LO, 40 MHz RF Bandwidth, Four-Carrier W-CDMA Desired
Signal, 2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active
0
2
4
6
8
10
12
14
RF ATTENUATION (dB)
16
18
20
14651-034
5
–75
14651-031
Tx ALTERNATE CHANNEL LEAKAGE RATIO (dB)
Figure 30. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation,
2600 MHz LO, 40 MHz RF Bandwidth, Four-Carrier W-CDMA Desired
Signal, Transmitter QEC and LO Leakage Tracking Active
14651-033
+110°C
+40°C
–40°C
0.1
2800
20
0.3
2700
16
0.4
2600
12
RF ATTENUATION (dB)
0.5
2500
–80
0.6
14651-030
–75
0.7
2400
–70
0.8
2300
–65
8
10M
0.9
2200
–60
4
1M
1.0
–55
0
100k
Figure 32. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff,
2600 MHz
+110°C UPPER
+40°C UPPER
–40°C UPPER
+110°C LOWER
+40°C LOWER
–40°C LOWER
–50
10k
OFFSET FREQUENCY (Hz)
–40
–45
1k
2100
15
2000
10
1900
5
1800
0
Tx ADJACENT CHANNEL LEAKAGE RATIO (dB)
–90
14651-032
PHASE NOISE (dBc)
–110
14651-029
TRANSMITTER NOISE (dBm/Hz)
–90
–100
Figure 34. Transmitter OIP3 vs. RF Attenuation, 2600 MHz LO,
40 MHz RF Bandwidth, F1 = 20 MHz, F2 = 21 MHz, 3 dB Digital Backoff,
245.76 MSPS Sample Rate
Rev. PrA | Page 21 of 48
Preliminary Technical Data
0
0
–10
–10
–20
–20
TRANSMITTER HD2 (dBc)
–30
–40
–50
–60
–70
–30
–40
–50
–60
–70
–80
–80
–90
–90
2525
2550
2575
2600
2625
2650
2675
2700
FREQUENCY (MHz)
–100
14651-035
–100
2500
Figure 35. Transmitter Spectrum, 2 dB Digital and 3 dB RF Backoff,
40 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active,
LTE 10 MHz Signal, 2600 MHz LO, 1 MHz Resolution Bandwidth,
245.76 MSPS Sample Rate
+110°C
+40°C
–40°C
0
5
10
15
20
RF ATTENUATION (dB)
14651-038
Tx OUTPUT (dBm)
AD9371
Figure 38. Transmitter HD2 vs. RF Attenuation, 2600 MHz LO,
2605 MHz Continuous Wave Desired Signal, 40 MHz RF Bandwidth,
245.76 MSPS Sample Rate
0
0
–10
+110°C
+40°C
–40°C
–10
TRANSMITTER HD3 (dBc)
Tx OUTPUT (dBm)
–20
–30
–40
–50
–60
–70
–20
–30
–40
–50
–60
–80
–80
Figure 36. Transmitter Spectrum, 2 dB Digital and 3 dB RF Backoff,
40 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active,
LTE 10 MHz Signal, 2600 MHz LO, 1 MHz Resolution Bandwidth,
245.76 MSPS Sample Rate
–20
–30
–35
–40
8
12
RF ATTENUATION (dB)
16
20
20
Figure 37. Transmitter EVM vs. RF Attenuation, 2550 MHz LO, Transmitter
LO Leakage and Transmitter QEC Tracking Active, 200 MHz RF Bandwidth,
LTE 20 MHz Downlink Signal, 245.76 MSPS Sample Rate
+110°C
+40°C
–40°C
5
0
–5
–10
–15
–20
14651-037
–45
4
15
Figure 39. Transmitter HD3 vs. RF Attenuation, 2600 MHz LO,
2605 MHz Continuous Wave Desired Signal, 40 MHz RF Bandwidth,
245.76 MSPS Sample Rate
TRANSMITTER OUTPUT POWER (dBm)
TRANSMITTER EVM (dB)
–25
0
10
RF ATTENUATION (dB)
10
+110°C
+40°C
–40°C
–50
5
0
5
10
RF ATTENUATION (dB)
15
20
14651-040
3100
FREQUENCY (MHz)
0
14651-036
3000
2900
2800
2750
2600
2500
2400
2300
2200
2100
–100
14651-039
–70
–90
Figure 40. Transmitter Output Power vs. RF Attenuation, 2600 MHz LO,
2605 MHz Continuous Wave Desired Signal, 40 MHz RF Bandwidth,
245.76 MSPS Sample Rate
Rev. PrA | Page 22 of 48
Preliminary Technical Data
AD9371
30
8
10
12
14
16
18
20
RF ATTENUATION (dB)
0
2900
6
OBSERVATION RECEIVER LO FREQUENCY (MHz)
Figure 44. Observation Receiver Noise Figure vs. Observation Receiver
LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate, 100 MHz Integration Bandwidth
0.5
80
0.4
70
OBSERVATION RECEIVER IIP2 (dBm)
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–80
–60
–40
–20
0
20
40
60
80
100
FREQUENCY OFFSET FROM LO (MHz)
30
20
+110°C
+40°C
–40°C
10
10
20
30
40
50
60
70
80
90
100
110
F1 OFFSET FREQUENCY (MHz)
Figure 45. Observation Receiver IIP2 vs. F1 Offset Frequency, 2600 MHz LO,
0 dB Attenuation, 200 MHz RF Bandwidth, F2 = F1 + 1 MHz,
245.76 MSPS Sample Rate
80
OBSERVATION RECEIVER IIP2 (dBm)
+110°C
+40°C
–40°C
–45
–50
–55
–60
–65
–70
–75
70
60
50
40
30
20
+110°C
+40°C
–40°C
10
OBSERVATION RECEIVER LO FREQUENCY (MHz)
2900
5
14651-043
2800
2700
2600
2500
2400
2300
2200
2100
2000
0
1900
–80
40
0
–40
1800
OBSERVATION RECEIVER LO LEAKAGE (dBm)
Figure 42. Transmitter Frequency Response Deviation from Flatness vs.
Frequency Offset from LO, 2600 MHz LO, 100 MHz RF Bandwidth,
6 dB Digital Backoff, 245.76 MSPS Sample Rate
50
0
14651-042
–0.5
–100
60
Figure 43. Observation Receiver LO Leakage vs. Observation Receiver
LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
15
25
35
45
55
65
75
85
95
105
115
INTERMODULATION FREQUENCY (MHz)
Figure 46. Observation Receiver IIP2 vs. Intermodulation Frequency,
2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
Rev. PrA | Page 23 of 48
14651-046
DEVIATION FROM FLATNESS (dB)
Figure 41. Tx Attenuation Step Error vs. RF Attenuation, 2600 MHz LO,
2610 MHz Continuous Wave Desired Signal, 40 MHz RF Bandwidth,
245.76 MSPS Sample Rate
14651-044
4
14651-045
2
+110°C
+40°C
–40°C
2800
0
5
2700
–0.10
14651-041
–0.08
2600
–0.06
10
2500
–0.04
2400
–0.02
15
2300
0
20
2200
0.02
2100
0.04
25
2000
0.06
1900
Tx ATTENUATION STEP ERROR (dB)
0.08
OBSERVATION RECEIVER NOISE FIGURE (dB)
+110°C
+40°C
–40°C
1800
0.10
AD9371
Preliminary Technical Data
25
30
25
20
15
10
5
0
0
10
20
30
40
50
60
70
80
90
100
110
F1 OFFSET FREQUENCY (MHz)
10
5
0
–5
–10
–15
0
3
6
9
12
15
18
OBSERVATION RECEIVER ATTENUATION (dB)
OBSERVATION RECEIVER DC OFFSET (dBFS)
–40
+110°C
+40°C
–40°C
35
30
25
20
15
10
0
5
15
25
35
45
55
65
75
85
95
105
115
INTERMODULATION FREQUENCY (MHz)
–50
–60
–70
–80
–90
–100
14651-048
5
+110°C
+40°C
–40°C
0
3
6
9
12
15
18
OBSERVATION RECEIVER ATTENUATION (dB)
14651-051
40
Figure 51. Observation Receiver DC Offset vs. Observation Receiver
Attenuation, 2600 MHz LO, 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
Figure 48. Observation Receiver IIP3 vs. Intermodulation Frequency,
2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
0
0
OBSERVATION RECEIVER HD2 (dBc)
+110°C
+40°C
–40°C
–20
–40
–60
–80
–120
0
3
6
9
12
15
OBSERVATION RECEIVER ATTENUATION (dB)
18
14651-049
–100
Figure 49. Observation Receiver Image vs. Observation Receiver Attenuation,
2600 MHz LO, Continuous Wave Signal 25 MHz Offset,
200 MHz RF Bandwidth, Background Tracking Calibration (BTC) Active,
245.76 MSPS Sample Rate
+110°C
+40°C
–40°C
–20
–40
–60
–80
–100
–120
0
3
6
9
12
15
OBSERVATION RECEIVER ATTENUATION (dB)
18
14651-052
OBSERVATION RECEIVER IIP3 (dBm)
15
Figure 50. Observation Receiver Gain vs. Observation Receiver Attenuation,
2600 MHz LO, Continuous Wave Signal 25 MHz Offset,
200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
Figure 47. Observation Receiver IIP3 vs. F1 Offset Frequency,
2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,
F2 = 2F1 + 1 MHz, 245.76 MSPS Sample Rate
OBSERVATION RECEIVER IMAGE (dBc)
+110°C
+40°C
–40°C
20
14651-050
35
OBSERVATION RECEIVER GAIN (dB)
+110°C
+40°C
–40°C
14651-047
OBSERVATION RECEIVER IIP3 (dBm)
40
Figure 52. Observation Receiver HD2 vs. Observation Receiver Attenuation,
2600 MHz LO, Continuous Wave Signal 25 MHz Offset, −20 dBm at 0 dB
Attenuation, Input Power Increasing dB for dB with Attenuation,
200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
Rev. PrA | Page 24 of 48
Preliminary Technical Data
AD9371
90
+110°C
+40°C
–40°C
SNIFFER RECEIVER IIP2 (dBm)
–20
–40
–60
–80
60
50
40
30
20
3
6
9
12
15
18
OBSERVATION RECEIVER ATTENUATION (dB)
Figure 53. Observation Receiver HD3 vs. Observation Receiver Attenuation,
2600 MHz LO, Continuous Wave Signal 25 MHz Offset, −20 dBm at 0 dB
Attenuation, Input Power Increasing dB for dB with Attenuation,
200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
–40
0
3
9
12
Figure 56. Sniffer Receiver IIP2 vs. Intermodulation Frequency, 2600 MHz LO,
0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
20
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
15
SNIFFER RECEIVER IIP3 (dBm)
–50
6
INTERMODULATION FREQUENCY (MHz)
14651-056
10
0
–60
–70
–80
–90
–100
10
5
0
–5
–120
2300
2400
2500
2600
2700
2800
SNIFFER RECEIVER LO FREQUENCY (MHz)
–10
Figure 54. Sniffer Receiver LO Leakage vs. Sniffer Receiver LO Frequency,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
0
2
4
6
8
10
Figure 57. Sniffer Receiver IIP3 vs. Intermodulation Frequency, 2600 MHz
LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
30
0
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–10
SNIFFER RECEIVER IMAGE (dBc)
25
20
15
10
5
12
INTERMODULATION FREQUENCY (MHz)
14651-057
–110
14651-054
–20
–30
–40
–50
–60
–70
–80
0
2300
2400
2500
2600
2700
SNIFFER RECEIVER LO FREQUENCY (MHz)
2800
14651-055
–90
Figure 55. Sniffer Receiver Noise Figure vs. Sniffer Receiver LO Frequency,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate,
20 MHz Integration Bandwidth
–100
0
5
10
15
20
SNIFFER RECEIVER ATTENUATION (dB)
Figure 58. Sniffer Receiver Image vs. Sniffer Receiver Attenuation,
2600 MHz LO, Continuous Wave Signal 1 MHz Offset,
20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
Rev. PrA | Page 25 of 48
14651-058
SNIFFER RECEIVER LO LEAKAGE (dBm)
70
–100
–120
SNIFFER RECEIVER NOISE FIGURE (dB)
+110°C
+40°C
–40°C
80
14651-053
OBSERVATION RECEIVER HD3 (dBc)
0
AD9371
Preliminary Technical Data
0
+110°C
+40°C
–40°C
–60
–70
–80
–90
–100
–10
–15
–20
–25
–30
–35
0
5
10
15
20
SNIFFER RECEIVER ATTENUATION (dB)
–45
–70 –65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10
Figure 59. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation,
2600 MHz LO, CS Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation,
Input Power Increasing dB for dB with Attenuation,
20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
SNIFFER RECEIVER INPUT POWER (dBm)
Figure 62. Sniffer Receiver EVM vs. Sniffer Receiver Input Power,
2600 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,
BTC Active, 30.72 MSPS Sample Rate
0
40
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
30
–20
SNIFFER RECEIVER GAIN (dB)
–30
–40
–50
–60
–70
–80
20
10
0
–10
–20
–30
–90
0
5
10
15
20
SNIFFER RECEIVER ATTENUATION (dB)
–40
14651-060
–100
Figure 60. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation, 2600 MHz LO,
Continuous Wave Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation,
Input Power Increasing dB for dB with Attenuation, 20 MHz RF Bandwidth,
30.72 MSPS Sample Rate
0
–40
–60
–80
5
10
15
SNIFFER RECEIVER ATTENUATION (dB)
20
14651-061
–100
0
12
16
20
24
28
32
36
40
44
48
52
Figure 63. Sniffer Receiver Gain vs. Sniffer Receiver Attenuation,
2600 MHz LO, Continuous Wave Signal 1 MHz Offset,
20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
+110°C
+40°C
–40°C
–120
8
SNIFFER RECEIVER ATTENUATION (dB)
0
–20
4
Figure 61. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation, 2600 MHz LO,
Continuous Wave Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation,
Input Power Increasing dB for dB with Attenuation, 20 MHz RF Bandwidth,
30.72 MSPS Sample Rate
Rev. PrA | Page 26 of 48
14651-063
SNIFFER RECEIVER HD2 (dBc)
–10
14651-062
–40
–110
SNIFFER RECEIVER HD3 (dBc)
+110°C
+40°C
–40°C
–5
SNIFFER RECEIVER EVM (dB)
–50
14651-059
SNIFFER RECEIVER DC OFFSET (dBFS)
–40
Preliminary Technical Data
AD9371
3.5 GHz BAND
90
–30
+110°C
+40°C
–40°C
80
–40
70
–45
RECEIVER IIP2 (dBm)
–50
–55
–60
–65
30
+110°C
+40°C
–40°C
3600
3700
3800
0
Figure 64. Receiver LO Leakage vs. Receiver LO Frequency, 0 dB Receiver
Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate
5
10
15
20
25
30
35
40
45
50
55
60
F1 OFFSET FREQUENCY (MHz)
14651-067
3500
14651-064
3400
RECEIVER LO FREQUENCY (MHz)
Figure 67. Receiver IIP2 vs. F1 Offset Frequency, 3500 MHz LO, 0 dB
Attenuation, 40 MHz RF Bandwidth, F2 = F1 + 1 MHz, 153.6 MSPS Sample Rate
45
100
+110°C
+40°C
–40°C
40
F2 – F1, +110°C
F2 – F1, +40°C
F2 – F1, –40°C
F2 + F1, +110°C
F2 + F1, +40°C
F2 + F1, –40°C
90
80
RECEIVER IIP2 (dBm)
35
30
25
20
15
10
70
60
50
40
30
20
5
10
0
0
14651-065
RECEIVER NOISE FIGURE (dB)
40
10
–75
RECEIVER ATTENUATION (dB)
Figure 65. Receiver Noise Figure vs. Receiver Attenuation, 3500 MHz LO,
100 MHz Bandwidth, 153.6 MSPS Sample Rate, 50 MHz Integration
Bandwidth (Includes 1 dB Matching Circuit Loss)
5
10
15
20
25
30
35
40
45
50
55
60
INTERMODULATION FREQUENCY (MHz)
Figure 68. Receiver IIP2 vs. Intermodulation Frequency, 3500 MHz LO,
0 dB Attenuation, 40 MHz RF Bandwidth, 153.6 MSPS Sample Rate
40
30
+110°C
+40°C
–40°C
25
+110°C
+40°C
–40°C
35
30
RECEIVER IIP3 (dBm)
RECEIVER NOISE FIGURE (dB)
50
20
–70
–80
3300
60
14651-068
RECEIVER LO LEAKAGE (dBm)
–35
20
15
10
25
20
15
10
5
3400
3500
3600
3700
RECEIVER LO FREQUENCY (MHz)
3800
Figure 66. Receiver Noise Figure vs. Receiver LO Frequency,
0 dB Receiver Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate,
50 MHz Integration Bandwidth (Includes Matching Circuit Loss)
Rev. PrA | Page 27 of 48
0
5
10
15
20
25
30
35
40
45
50
55
60
F1 OFFSET FREQUENCY (MHz)
Figure 69. Receiver IIP3 vs. F1 Offset Frequency, 3500 MHz LO,
0 dB Attenuation, 100 MHz RF Bandwidth, F2 = 2F1 + 1 MHz,
153.6 MSPS Sample Rate
14651-069
0
3300
14651-066
5
AD9371
Preliminary Technical Data
40
RECEIVER IIP3 (dBm)
30
+110°C
+40°C
–40°C
RECEIVER DC OFFSET (dBFS)
F2 – F1, +110°C
F2 – F1, +40°C
F2 – F1, –40°C
F2 + F1, +110°C
F2 + F1, +40°C
F2 + F1, –40°C
35
25
20
15
10
15
20
25
30
35
40
45
50
55
60
INTERMODULATION FREQUENCY (MHz)
Figure 70. Receiver IIP3 vs. Intermodulation Frequency, 3500 MHz LO,
0 dB Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate
RECEIVER ATTENUATION (dB)
Figure 73. Receiver DC Offset vs. Receiver Attenuation, 3500 MHz LO,
100 MHz RF Bandwidth, 153.6 MSPS Sample Rate
–40
–40
+110°C
+40°C
–40°C
–60
–70
–80
–90
–100
–60
–70
–80
–90
–100
–110
14651-071
–110
RECEIVER ATTENUATION (dB)
RECEIVER ATTENUATION (dB)
Figure 71. Receiver Image vs. Receiver Attenuation, 3500 MHz LO,
Continuous Wave Signal 17 MHz Offset, 100 MHz RF Bandwidth,
Background Tracking Calibration (BTC) Active, 153.6 MSPS Sample Rate
Figure 74. Receiver HD2 vs. Receiver Attenuation, 3500 MHz LO,
Continuous Wave Signal 17 MHz Offset, −14dBm at 0 dB Attenuation,
Input Power Increasing dB for dB with Attenuation,
100 MHz RF Bandwidth, 153.6 MSPS Sample Rate
25
–40
+110°C
+40°C
–40°C
20
–60
RECEIVER HD3 (dBc)
10
5
0
–70
–80
–90
–5
–100
–15
–110
RECEIVER ATTENUATION (dB)
14651-072
–10
Figure 72. Receiver Gain vs. Receiver Attenuation, 3500 MHz LO,
Continuous Wave Signal 17 MHz Offset, 100 MHz RF Bandwidth,
De-Embedded to Receiver Port, 153.6 MSPS Sample Rate
+110°C
+40°C
–40°C
–50
15
RECEIVER GAIN (dB)
+110°C
+40°C
–40°C
–50
RECEIVER HD2 (dBc)
RECEIVER IMAGE (dBc)
–50
14651-074
10
RECEIVER ATTENUATION (dB)
14651-075
5
14651-073
0
14651-070
5
Figure 75. Receiver HD3 vs. Receiver Attenuation, 3500 MHz LO,
Continuous Wave Signal 17 MHz Offset, −14 dBm at 0 dB Attenuation,
Input Power Increasing dB for dB with Attenuation, 100 MHz RF Bandwidth,
153.6 MSPS Sample Rate
Rev. PrA | Page 28 of 48
Preliminary Technical Data
AD9371
30
0
+110°C
+40°C
–40°C
–5
+110°C
+40°C
–40°C
RECEIVER NOISE FIGURE (dB)
25
RECEIVER EVM (dB)
–10
–15
–20
–25
–30
–35
20
15
10
5
–5
0
RECEIVER INPUT POWER (dBm)
Figure 76. Receiver EVM vs. Receiver Input Power, 3600 MHz LO, 100 MHz
RF Bandwidth, LTE 20 MHz Uplink Centered at DC, BTC Active,
153.6 MSPS Sample Rate
0
–30
–25
–20
–15
–10
–5
0
INTERFERER SIGNAL POWER (dBm)
14651-079
–45
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10
14651-076
–40
Figure 79. Receiver Noise Figure vs. Out of Band Interferer Signal Power,
3614 MHz LO, 3665 MHz Continuous Wave Interferer,
Noise Figure Integrated over 7 MHz to 10 MHz
0
+110°C
+40°C
–40°C
–20
TRANSMITTER IMAGE (dBc)
Rx2 TO Rx1 CROSSTALK (dB)
–10
–30
–40
–50
–60
–70
–80
3400
3500
3600
3700
3800
RECEIVER LO FREQUENCY (MHz)
Figure 77. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency,
100 MHz RF Bandwidth, Continuous Wave Tone 3 MHz Offset from LO
14651-080
–100
3300
14651-077
–90
RF ATTENUATION (dB)
Figure 80. Transmitter Image vs. RF Attenuation, 100 MHz RF Bandwidth,
3550 MHz LO, Transmitter QEC Tracking Run with Two 20 MHz,
LTE Downlink Carriers, Then Image Measured with Continuous Wave
10 MHz Offset from LO, 6 dB Digital Backoff, 307.2 MSPS Sample Rate
30
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
26
TRANSMITTER IMAGE (dBc)
RECEIVER NOISE FIGURE (dB)
28
24
22
20
18
16
14
–45
–40
–35
–30
–25
–20
INTERFERER SIGNAL POWER (dBm)
Figure 78. Receiver Noise Figure vs. Close-In Interferer Signal Power,
3614 MHz LO, 3625 MHz Continuous Wave Interferer, Noise Figure
Integrated over 7 MHz to 10 MHz, 100 MHz RF Bandwidth
–50
–40
–30
–20
–10
0
10
20
30
DESIRED OFFSET FREQUENCY (MHz)
40
50
14651-081
10
–50
14651-078
12
Figure 81. Transmitter Image vs. Desired Signal Offset, 100 MHz RF
Bandwidth, 3550 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking
Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with
Continuous Wave Signal, 6 dB Digital Backoff, 307.2 MSPS Sample Rate
Rev. PrA | Page 29 of 48
AD9371
Preliminary Technical Data
0
8
–10
6
–20
Tx1 TO Rx1 CROSSTALK (dB)
10
2
0
–2
–4
–6
+110°C
+40°C
–40°C
3400
3500
3600
3700
–50
–60
–70
–80
3800
FREQUENCY (MHz)
–100
3300
Figure 82. Tx Output Power Spectrum, Transmitter QEC and
External LO Leakage Active, 5 MHz Continuous Wave Offset Signal,
1 MHz Resolution Bandwidth, 307.2 MSPS Sample Rate
3500
3600
3700
3800
RECEIVER LO FREQUENCY (MHz)
Figure 85. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency,
100 MHz Receiver RF Bandwidth, 40 MHz Transmitter RF Bandwidth,
Continuous Wave Signal 3 MHz Offset from LO
–60
0
+110°C
+40°C
–40°C
–10
Tx2 TO Rx2 CROSSTALK (dB)
–65
–70
–75
–80
–85
–90
–95
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15
20
RF ATTENUATION (dB)
–100
3300
14651-083
TRANSMITTER LO LEAKAGE (dBFS)
3400
14651-085
–10
3300
–40
–90
14651-082
–8
–30
Figure 83. Transmitter LO Leakage vs. RF Attenuation, 3550 MHz LO,
External Transmitter QEC and LO Leakage Tracking Active,
Continuous Wave Signal 10 MHz Offset from LO, 6 dB Digital Backoff,
1 MHz Measurement Bandwidth (Note that if Input power to ORx channel
is not held constant, performance will degrade as shown in this plot)
3400
3500
3600
3700
3800
RECEIVER LO FREQUENCY (MHz)
14651-086
Tx OUTPUT (dBm)
4
Figure 86. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency,
100 MHz Receiver RF Bandwidth, 40 MHz Transmitter RF Bandwidth,
Continuous Wave Signal 3 MHz Offset from LO
0
–10
Tx2 TO Tx1 CROSSTALK (dB)
TRANSMITTER LO LEAKAGE (dBFS)
3.3GHz, +110°C
3.3GHz, +40°C
3.3GHz, –40°C
3.55GHz, +110°C
3.55GHz, +40°C
3.55GHz, –40°C
3.8GHz, +110°C
3.8GHz, +40°C
3.8GHz, –40°C
–20
–30
–40
–50
–60
–70
–80
–20
–10
0
10
20
OFFSET FREQUENCY (MHz)
Figure 84. Transmitter LO Leakage vs. Offset Frequency,
External Transmitter QEC, and LO Leakage Tracking Active,
6 dB Digital Backoff, 1 MHz Measurement Bandwidth
30
3400
3500
3600
3700
TRANSMITTER LO FREQUENCY (MHz)
3800
14651-087
–30
14651-084
–90
–100
3300
Figure 87. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,
100 MHz RF Bandwidth, Continuous Wave Signal 3 MHz Offset from LO
Rev. PrA | Page 30 of 48
Preliminary Technical Data
–80
–60
+110°C
+40°C
–40°C
–90
–70
–100
–120
–130
–140
–150
–110
–120
–130
–170
–140
5
10
15
20
RF ATTENUATION (dB)
–150
100
1k
10k
100k
OFFSET FREQUENCY (Hz)
Figure 91. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff,
3500 MHz LO
Figure 88. Transmitter Noise vs. RF Attenuation, 3500 MHz LO,
100 MHz Offset Frequency, Zeros Input Data
1.0
–40
–50
Tx INTEGRATED PHASE NOISE (Degrees)
+110°C UPPER
+40°C UPPER
–40°C UPPER
+110°C LOWER
+40°C LOWER
–40°C LOWER
–45
–55
–60
–65
–70
0
5
10
15
20
RF ATTENUATION (dB)
+110°C
+40°C
–40°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3300
14651-089
–75
–80
10M
1M
3400
3500
3600
3800
3700
TRANSMITTER LO FREQUENCY (MHz)
14651-092
0
Figure 92. Tx Integrated Phase Noise vs. Transmitter LO Frequency,
100 MHz RF Bandwidth, Continuous Wave 20 MHz Offset from LO,
3 dB Digital Backoff
Figure 89. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation,
3500 MHz LO, 100 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,
2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active
35
–40
+110°C UPPER
+40°C UPPER
–40°C UPPER
+110°C LOWER
+40°C LOWER
–40°C LOWER
–50
+110°C
+40°C
–40°C
30
TRANSMITTER OIP3 (dBm)
–45
–55
–60
–65
–70
25
20
15
10
5
–75
0
5
10
RF ATTENUATION (dB)
15
20
0
14651-090
–80
Figure 90. Tx Alternate Channel Leakage Ratio vs. RF Attenuation,
3500 MHz LO, 100 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,
2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active
0
2
4
6
8
10
12
14
RF ATTENUATION (dB)
16
18
20
14651-093
Tx ADJACENT CHANNEL LEAKAGE RATIO (dB)
–100
–160
–180
Tx ALTERNATE CHANNEL LEAKAGE RATIO (dB)
–90
14651-091
LO PHASE NOISE (dBc)
–80
–110
14651-088
TRANSMITTER NOISE (dBm/Hz)
AD9371
Figure 93. Transmitter OIP3 vs. RF Attenuation, 3500 MHz LO,
100 MHz RF Bandwidth, F1 = 20 MHz, F2 = 21 MHz, 3 dB Digital Backoff,
307.2 MSPS Sample Rate
Rev. PrA | Page 31 of 48
Preliminary Technical Data
0
0
–10
–10
–20
–20
TRANSMITTER HD2 (dBc)
–30
–40
–50
–60
–70
–30
–40
–50
–60
–70
–80
–80
–90
–90
3425
3450
3475
3500
3525
3550
3575
3600
FREQUENCY (MHz)
–100
14651-094
–100
3400
Figure 94. Tx Spectrum, 2 dB Digital and 3 dB RF Backoff, 100 MHz RF
Bandwidth, Transmitter QEC and Internal LO Leakage Active, LTE 10 MHz
Signal, 3500 MHz LO, 1 MHz Resolution Bandwidth, 307.2 MSPS Sample Rate
+110°C
+40°C
–40°C
0
5
10
15
20
RF ATTENUATION (dB)
14651-097
Tx OUTPUT (dBm)
AD9371
Figure 97. Transmitter HD2 vs. RF Attenuation, 3500 MHz LO,
3505 MHz Continuous Wave Desired Signal, 100 MHz RF Bandwidth,
307.2 MSPS Sample Rate
0
0
–10
+110°C
+40°C
–40°C
–10
TRANSMITTER HD3 (dBc)
Tx OUTPUT (dBm)
–20
–30
–40
–50
–60
–70
–20
–30
–40
–50
–60
–80
FREQUENCY (MHz)
Figure 95. Transmitter Spectrum, 2 dB Digital and 3 dB RF Backoff,
100 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active,
LTE 10 MHz Signal, 3500 MHz LO, 1 MHz Resolution Bandwidth,
307.2 MSPS Sample Rate (Noise Floor Includes Test Equipment Response)
–30
–35
–40
–50
RF ATTENUATION (dB)
15
15
20
Figure 98. Transmitter HD3 vs. RF Attenuation, 3500 MHz LO,
3505 MHz Continuous Wave Desired Signal, 100 MHz RF Bandwidth,
307.2 MSPS Sample Rate
20
Figure 96. Transmitter EVM vs. RF Attenuation, 3500 MHz LO,
Transmitter LO Leakage, and Transmitter QEC Tracking Active, 200 MHz
RF Bandwidth, LTE 20 MHz Downlink Signal, 307.2 MSPS Sample Rate
+110°C
+40°C
–40°C
5
0
–5
–10
–15
–20
–25
14651-096
–45
10
10
RF ATTENUATION (dB)
TRANSMITTER OUTPUT POWER (dBm)
TRANSMITTER EVM (dB)
–25
5
5
10
+110°C
+40°C
–40°C
0
0
0
5
10
RF ATTENUATION (dB)
15
20
14651-099
–20
–80
14651-095
–100
3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000
14651-098
–70
–90
Figure 99. Transmitter Output Power vs. RF Attenuation, 3500 MHz LO,
3505 MHz Continuous Wave Desired Signal, 100 MHz RF Bandwidth,
2 dB Digital Backoff, 307.2 MSPS Sample Rate
Rev. PrA | Page 32 of 48
Preliminary Technical Data
AD9371
0.10
+110°C
+40°C
–40°C
30
0.04
0.02
0
–0.02
–0.04
–0.06
–0.10
0
2
4
6
8
10
12
14
16
18
20
RF ATTENUATION (dB)
14651-100
–0.08
25
20
15
10
5
+110°C
+40°C
–40°C
0
3300
3400
3500
3600
3800
3700
OBSERVATION RECEIVER LO FREQUENCY (MHz)
Figure 100. Tx Attenuation Step Error vs. RF Attenuation, 3500 MHz LO,
3510 MHz Continuous Wave Desired Signal, 100 MHz RF Bandwidth,
De-Embedded to Transmitter Port, 307.2 MSPS Sample Rate
14651-103
0.06
OBSERVATION RECEIVER NOISE FIGURE (dB)
Tx ATTENUATION STEP ERROR (dB)
0.08
Figure 103. Observation Receiver Noise Figure vs. Observation Receiver
LO Frequency, 0 dB Receiver Attenuation, 240 MHz RF Bandwidth,
307.2 MSPS Sample Rate, 120 MHz Integration Bandwidth
1.0
80
0.4
0.2
0
–0.2
–0.4
–0.6
–1.0
–100
–80
–60
–40
–20
0
20
40
60
100
80
FREQUENCY OFFSET FROM LO (MHz)
–40
–55
–60
–65
–70
–75
3400
3500
3600
3700
OBSERVATION RECEIVER LO FREQUENCY (MHz)
3800
30
20
+110°C
+40°C
–40°C
10
10
20
30
40
50
60
70
80
90
Figure 102. Observation Receiver LO Leakage vs. Observation Receiver
LO Frequency, 0 dB Receiver Attenuation, 240 MHz RF Bandwidth,
307.2 MSPS Sample Rate
100
110
F1 OFFSET FREQUENCY (MHz)
Figure 104. Observation Receiver IIP2 vs. F1 Offset Frequency, 3600 MHz LO,
0 dB Attenuation, 240 MHz RF Bandwidth, F2 = F1 + 1 MHz,
307.2 MSPS Sample Rate
OBSERVATION RECEIVER IIP2 (dBm)
–50
–80
3300
40
80
+110°C
+40°C
–40°C
–45
50
0
+110°C
+40°C
–40°C
70
60
50
40
30
20
10
0
14651-102
OBSERVATION RECEIVER LO LEAKAGE (dBm)
Figure 101. Transmitter Frequency Response Deviation from Flatness vs.
Frequency Offset from LO, 3500 MHz LO, 100 MHz RF Bandwidth,
6 dB Digital Backoff, 307.2 MSPS Sample Rate
60
0
14651-101
–0.8
70
5
15
25
35
45
55
65
75
85
95
INTERMODULATION FREQUENCY (MHz)
105
115
14651-105
0.6
14651-104
OBSERVATION RECEIVER IIP2 (dBm)
DEVIATION FROM FLATNESS (dB)
0.8
Figure 105. Observation Receiver IIP2 vs. Intermodulation Frequency,
3500 MHz LO, 0 dB Attenuation, 240 MHz RF Bandwidth,
307.2 MSPS Sample Rate
Rev. PrA | Page 33 of 48
AD9371
Preliminary Technical Data
25
25
20
15
10
5
0
0
10
20
30
40
50
60
70
80
90
100
110
F1 OFFSET FREQUENCY (MHz)
15
10
5
0
–5
–10
–15
Figure 106. Observation Receiver IIP3 vs. F1 Offset Frequency, 3600 MHz LO,
0 dB Attenuation, 240 MHz RF Bandwidth, F2 = 2F1 + 1 MHz,
307.2 MSPS Sample Rate
0
9
12
OBSERVATION RECEIVER DC OFFSET (dBFS)
35
30
25
20
15
10
5
0
5
15
25
35
45
55
65
75
85
95
105
115
INTERMODULATION FREQUENCY (MHz)
Figure 107. Observation Receiver IIP3 vs. Intermodulation Frequency,
3500 MHz LO, 0 dB Attenuation, 240 MHz RF Bandwidth,
307.2 MSPS Sample Rate
+110°C
+40°C
–40°C
–50
–60
–70
–80
–90
–100
–110
–120
0
3
6
9
12
15
18
OBSERVATION RECEIVER ATTENUATION (dB)
Figure 110. Observation Receiver DC Offset vs. Observation Receiver
Attenuation, 3500 MHz LO, 240 MHz RF Bandwidth, 307.2 MSPS Sample Rate
0
0
OBSERVATION RECEIVER HD2 (dBc)
+110°C
+40°C
–40°C
–10
18
15
–40
+110°C
+40°C
–40°C
14651-107
–20
–30
–40
–50
–60
–70
–80
+110°C
+40°C
–40°C
–20
–40
–60
–80
–100
–100
0
3
6
9
12
15
OBSERVATION RECEIVER ATTENUATION (dB)
18
14651-108
–90
Figure 108. Observation Receiver Image vs. Observation Receiver Attenuation,
3500 MHz LO, Continuous Wave Signal 25 MHz Offset,
240 MHz RF Bandwidth, Background Tracking Calibration (BTC) Active,
307.2 MSPS Sample Rate
–120
0
3
6
9
12
15
OBSERVATION RECEIVER ATTENUATION (dB)
18
14651-111
OBSERVATION RECEIVER IIP3 (dBm)
6
Figure 109. Observation Receiver Gain vs. Observation Receiver
Attenuation, 3500 MHz LO, Continuous Wave Signal 25 MHz Offset,
240 MHz RF Bandwidth, De-Embedded to Receiver Port,
307.2 MSPS Sample Rate
40
OBSERVATION RECEIVER IMAGE (dBc)
3
OBSERVATION RECEIVER ATTENUATION (dB)
14651-109
30
+110°C
+40°C
–40°C
20
14651-110
35
OBSERVATION RECEIVER GAIN (dB)
+110°C
+40°C
–40°C
14651-106
OBSERVATION RECEIVER IIP3 (dBm)
40
Figure 111. Observation Receiver HD2 vs. Observation Receiver
Attenuation, 3500 MHz LO, Continuous Wave Signal 25 MHz Offset,
−20 dBm at 0 dB Attenuation, Input Power Increasing dB for dB with
Attenuation, 240 MHz RF Bandwidth, 307.2 MSPS Sample Rate
Rev. PrA | Page 34 of 48
Preliminary Technical Data
AD9371
0
–10
–20
–30
–40
–50
–60
–70
–80
70
60
50
40
30
20
0
3
6
9
12
15
18
OBSERVATION RECEIVER ATTENUATION (dB)
Figure 112. Observation Receiver HD3 vs. Observation Receiver
Attenuation, 3500 MHz LO, Continuous Wave Signal 25 MHz Offset,
−20 dBm at 0 dB Attenuation, Input Power Increasing dB for dB with
Attenuation, 240 MHz RF Bandwidth, 307.2 MSPS Sample Rate
10
14
18
INTERMODULATION FREQUENCY (MHz)
Figure 115. Sniffer Receiver IIP2 vs. Intermodulation Frequency, 3500 MHz LO,
0 dB Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate
20
+110°C
+40°C
–40°C
–60
–70
–80
–90
–100
+110°C
+40°C
–40°C
15
SNIFFER RECEIVER IIP3 (dBm)
–50
6
2
10
5
0
–5
3400
3500
3600
3700
3800
SNIFFER RECEIVER LO FREQUENCY (MHz)
Figure 113. Sniffer Receiver LO Leakage vs. Sniffer Receiver LO Frequency,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate
20
–10
6
8
10
+110°C
+40°C
–40°C
SNIFFER RECEIVER IMAGE (dBc)
–10
14
12
10
8
6
4
12
Figure 116. Sniffer Receiver IIP3 vs. Intermodulation Frequency, 3500 MHz LO,
0 dB Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate
0
16
–20
–30
–40
–50
–60
–70
–80
2
–90
3400
3500
3600
3700
SNIFFER RECEIVER LO FREQUENCY (MHz)
3800
14651-114
0
3300
4
INTERMODULATION FREQUENCY (MHz)
+110°C
+40°C
–40°C
18
2
0
Figure 114. Sniffer Receiver Noise Figure vs. Sniffer Receiver LO Frequency,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate,
10 MHz Integration Bandwidth
–100
0
5
10
15
20
25
30
35
40
SNIFFER RECEIVER ATTENUATION (dB)
45
50
14651-117
–120
3300
14651-116
–110
14651-113
SNIFFER RECEIVER LO LEAKAGE (dBm)
–40
0
14651-112
–100
14651-115
10
–90
SNIFFER RECEIVER NOISE FIGURE (dB)
+110°C
+40°C
–40°C
80
SNIFFER RECEIVER IIP2 (dBm)
OBSERVATION RECEIVER HD3 (dBc)
90
+110°C
+40°C
–40°C
Figure 117. Sniffer Receiver Image vs. Sniffer Receiver Attenuation,
3500 MHz LO, Continuous Wave Signal 5 MHz Offset, 20 MHz RF Bandwidth,
38.4 MSPS Sample Rate
Rev. PrA | Page 35 of 48
AD9371
Preliminary Technical Data
0
+110°C
+40°C
–40°C
–60
–70
–80
–90
–100
–10
–15
–20
–25
–30
–35
0
5
10
20
15
SNIFFER RECEIVER ATTENUATION (dB)
Figure 118. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation,
3500 MHz LO, Continuous Wave Signal 1 MHz Offset, −35 dBm at 0 dB
Attenuation, Input Power Increasing dB for dB with Attenuation,
20 MHz RF Bandwidth, 38.4 MSPS Sample Rate
0
–45
–70
–60
–55
–50
–45
–40
–35
Figure 121. Sniffer Receiver EVM vs. Sniffer Receiver Input Power,
3600 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,
BTC Active, 38.4 MSPS Sample Rate
35
+110°C
+40°C
–40°C
25
SNIFFER RECEIVER GAIN (dB)
–20
–30
–40
–50
–60
–70
–80
–30
SNIFFER RECEIVER INPUT POWER (dBm)
+110°C
+40°C
–40°C
–10
–65
14651-121
–40
–110
SNIFFER RECEIVER HD2 (dBc)
+110°C
+40°C
–40°C
–5
SNIFFER RECEIVER EVM (dB)
–50
14651-118
SNIFFER RECEIVER DC OFFSET (dBFS)
–40
15
5
–5
–15
–25
0
5
10
15
20
SNIFFER RECEIVER ATTENUATION (dB)
Figure 119. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation,
3500 MHz LO, Continuous Wave Signal 1 MHz Offset, −35 dBm at
0 dB Attenuation, Input Power Increasing dB for dB with Attenuation,
20 MHz RF Bandwidth, 38.4 MSPS Sample Rate
0
0
–30
–40
–50
–60
–70
–80
5
10
15
SNIFFER RECEIVER ATTENUATION (dB)
20
14651-120
–90
0
10
15
20
25
30
35
40
45
50
55
Figure 122. Sniffer Receiver Gain vs. Sniffer Receiver Attenuation,
3600 MHz LO, Continuous Wave Signal 5 MHz Offset, 20 MHz RF
Bandwidth, De-Embedded to Receiver Port, 38.4 MSPS Sample Rate
–20
–100
5
SNIFFER RECEIVER ATTENUATION (dB)
+110°C
+40°C
–40°C
–10
SNIFFER RECEIVER HD3 (dBc)
–35
14651-119
–100
Figure 120. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation, 3500 MHz LO,
Continuous Wave Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation,
Input Power Increasing dB for dB with Attenuation,
20 MHz RF Bandwidth, 38.4 MSPS Sample Rate
Rev. PrA | Page 36 of 48
14651-122
–90
Preliminary Technical Data
AD9371
5.5 GHz BAND
100
–30
80
–50
RECEIVER IIP2 (dBm)
RECEIVER LO LEAKAGE (dBm)
90
+110°C
+40°C
–40°C
–40
–60
–70
–80
70
60
50
40
F2 + F1, +110°C
F2 + F1, +40°C
F2 + F1, –40°C
F2 – F1, +110°C
F2 – F1, +40°C
F2 – F1, –40°C
30
20
–90
5500
5600
5700
5800
5900
RECEIVER LO FREQUENCY (MHz)
0
15
14651-223
5400
Figure 123. Receiver LO Leakage vs. Receiver LO Frequency, 0 dB Receiver
Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
30
35
40
45
Figure 126. Receiver IIP2 vs. Intermodulation Frequency, 5600 MHz LO,
0 dB Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
40
40
+110°C
+40°C
–40°C
35
35
30
RECEIVER IIP3 (dBm)
30
25
20
15
25
20
15
+110°C
+40°C
–40°C
10
10
0
3
6
9
12
15
RECEIVER ATTENUATION (dB)
0
15
14651-224
0
Figure 124. Receiver Noise Figure vs. Receiver Attenuation, 5600 MHz LO,
100 MHz Bandwidth, 122.88 MSPS Sample Rate, 50 MHz Integration
Bandwidth (Includes 1.2 dB Matching Circuit Loss)
25
–50
RECEIVER IMAGE (dBc)
–40
15
10
+110°C
+40°C
–40°C
5
30
35
+110°C
+40°C
–40°C
–60
–70
–80
–90
5400
5500
5600
5700
RECEIVER LO FREQUENCY (MHz)
5800
5900
–100
14651-225
0
5300
25
Figure 127. Receiver IIP3 vs. Intermodulation Frequency, 5600 MHz LO,
0 dB Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
30
20
20
INTERMODULATION FREQUENCY (MHz)
14651-227
5
5
Figure 125. Receiver Noise Figure vs. Receiver LO Frequency, 0 dB Receiver
Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate, 50 MHz
Integration Bandwidth (Includes Matching Circuit Loss)
0
5
10
15
20
RECEIVER ATTENUATION (dB)
25
30
14651-228
RECEIVER NOISE FIGURE (dB)
25
INTERMODULATION FREQUENCY (MHz)
45
RECEIVER NOISE FIGURE (dB)
20
14651-226
10
–100
5300
Figure 128. Receiver Image vs. Receiver Attenuation, 5600 MHz LO,
Continuous Wave Signal 10 MHz Offset, 100 MHz RF Bandwidth,
Background Tracking Calibration (BTC) Active, 122.88 MSPS Sample Rate
Rev. PrA | Page 37 of 48
AD9371
Preliminary Technical Data
20
–40
15
–50
RECEIVER HD3 (dBc)
5
0
–5
+110°C
+40°C
–40°C
–10
–70
–80
+110°C
+40°C
–40°C
–90
0
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
–110
14651-229
–20
Figure 129. Receiver Gain vs. Receiver Attenuation, 5600 MHz LO, Continuous
Wave Signal 10 MHz Offset, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
5
0
10
15
20
25
30
RECEIVER ATTENUATION (dB)
14651-232
–100
–15
Figure 132. Receiver HD3 vs. Receiver Attenuation, 5600 MHz LO,
Continuous Wave Signal 10 MHz Offset, −20 dBm at 0 dB Attenuation,
Input Power Increasing dB for dB with Attenuation,100 MHz RF Bandwidth,
122.88 MSPS Sample Rate
0
–40
–5
–50
+110°C
+40°C
–40°C
–60
+110°C
+40°C
–40°C
–10
RECEIVER EVM (dB)
RECEIVER DC OFFSET (dBFS)
–60
–70
–80
–90
–15
–20
–25
–30
–35
–100
–40
0
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
–45
–55
14651-230
–110
Figure 130. Receiver DC Offset vs. Receiver Attenuation, 5600 MHz LO,
100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
RECEIVER INPUT POWER (dBm)
14651-233
RECEIVER GAIN (dB)
10
Figure 133. Receiver EVM vs. Receiver Input Power, 5600 MHz LO, 100 MHz RF
Bandwidth LTE, 20 MHz Uplink Centered at DC, BTC Active, 122.88 MSPS
Sample Rate
0
–40
–10
Rx2 TO Rx1 CROSSTALK (dB)
RECEIVER HD2 (dBc)
–50
+110°C
+40°C
–40°C
–60
–70
–80
–90
–20
–30
–40
–50
–60
–70
–80
–100
0
5
10
15
20
RECEIVER ATTENUATION (dB)
25
30
–100
5300
14651-231
–110
Figure 131. Receiver HD2 vs. Receiver Attenuation, 5600 MHz LO,
Continuous Wave Signal 10 MHz Offset, −20 dBm at 0 dB Attenuation,
Input Power Increasing dB for dB with Attenuation, 100 MHz RF Bandwidth,
122.88 MSPS Sample Rate
5400
5500
5600
5700
RECEIVER LO FREQUENCY (MHz)
5800
5900
14651-234
–90
Figure 134. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency,
100 MHz RF Bandwidth, Continuous Wave Tone 3 MHz Offset from LO
Rev. PrA | Page 38 of 48
Preliminary Technical Data
AD9371
10
30
6
Tx OUTPUT (dBm)
RECEIVER NOISE FIGURE (dB)
8
25
20
15
+110°C
+40°C
–40°C
10
4
2
0
–2
+110°C
+40°C
–40°C
–4
–6
5
–30
–25
–20
–15
–10
–5
0
INTERFERER SIGNAL POWER (dBm)
14651-235
–35
–10
5300
Figure 135. Receiver Noise Figure vs. Out-of-Band Interferer Signal Power,
5400 MHz LO, 5600 MHz Continuous Wave Interferer, NF Integrated over
7 MHz to 10 MHz
5500
5600
5700
5800
5900
RECEIVER LO FREQUENCY (MHz)
Figure 138. Tx Output Power, Transmitter QEC, and External LO Leakage
Active, 5 MHz Continuous Wave Offset Signal, 1 MHz Resolution Bandwidth,
245.76 MSPS Sample Rate
0
–40
–10
+110°C
+40°C
–40°C
–20
TRANSMITTER LO LEAKAGE (dBFS)
TRANSMITTER IMAGE (dBc)
5400
14651-238
–8
0
–40
–30
–40
–50
–60
–70
–80
–50
–60
–70
+110°C
+40°C
–40°C
–80
–90
5
0
10
15
20
RF ATTENUATION (dB)
–100
14651-236
–100
Figure 136. Transmitter Image vs. RF Attenuation, 75 MHz RF Bandwidth,
5600 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking Run with
Two 20 MHz LTE Downlink Carriers, Then Image Measured with
Continuous Wave 10 MHz Offset from LO, 3 dB Digital Backoff,
245.76 MSPS Sample Rate
0
20
15
Figure 139. Transmitter LO Leakage vs. RF Attenuation, 5600 MHz LO,
External Transmitter QEC, and LO Leakage Tracking Active, Continuous
Wave Signal 10 MHz Offset from LO, 6 dB Digital Backoff, 1MHz
Measurement Bandwidth
–60
TRANSMITTER LO LEAKAGE (dBFS)
+110°C
+40°C
–40°C
–20
–30
–40
–50
–60
–70
–80
–30
–20
–10
0
10
20
DESIRED OFFSET FREQUENCY (MHz)
30
40
14651-237
–90
Figure 137. Transmitter Image vs. Desired Offset Frequency, 75 MHz RF
Bandwidth, 5600 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking
Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with
Continuous Wave Signal, 3 dB Digital Backoff, 245.76 MSPS Sample Rate
Rev. PrA | Page 39 of 48
–65
–70
–75
–80
–85
–90
–95
–100
–40
5.9GHz,
5.9GHz,
5.9GHz,
5.6GHz,
5.6GHz,
5.6GHz,
–30
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–20
–10
5.3GHz, +110°C
5.3GHz, +40°C
5.3GHz, –40°C
0
10
20
30
OFFSET FREQUENCY (MHz)
Figure 140. Transmitter LO Leakage vs. Offset Frequency,
External Transmitter QEC and LO Leakage Tracking Active,
6 dB Digital Backoff, 1 MHz Measurement Bandwidth
40
14651-240
–10
TRANSMITTER IMAGE (dBc)
10
RF ATTENUATION (dB)
0
–100
–40
5
14651-239
–90
Preliminary Technical Data
0
–80
–10
–90
TRANSMITTER NOISE (dBm/Hz)
–20
–30
–40
–50
–60
–70
–80
–90
5500
5600
5700
5800
5900
–140
–150
–160
5
10
15
20
RF ATTENUATION (dB)
Figure 144. Transmitter Noise vs. RF Attenuation, 5600 MHz LO,
1 MHz Offset Frequency
–40
–20
–30
–40
–50
–60
–70
–80
5400
5500
5600
5700
5800
5900
RECEIVER LO FREQUENCY (MHz)
Figure 142. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency, 100 MHz Receiver
RF Bandwidth, 75 MHz Transmitter RF Bandwidth,
Continuous Wave Signal 3 MHz Offset from LO
–50
–55
–60
–65
+110°C LOWER
+40°C LOWER
–40°C LOWER
+110°C UPPER
+40°C UPPER
–40°C UPPER
–70
–75
–80
14651-242
–90
–45
0
5
10
15
20
RF ATTENUATION (dB)
14651-245
Tx ADJACENT CH LEAKAGE RATIO (dB)
Tx2 TO Rx2 CROSSTALK (dB)
–130
0
0
–10
Figure 145. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation,
5600 MHz LO, 75 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,
Transmitter QEC and LO Leakage Tracking Active
–40
Tx ALTERNATE CH LEAKAGE RATIO (dB)
–10
–20
Tx2 TO Tx1 CROSSTALK (dB)
–120
–180
Figure 141. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency, 100 MHz Receiver
RF Bandwidth, 75 MHz Transmitter RF Bandwidth,
Continuous Wave Signal 3 MHz Offset from LO
–30
–40
–50
–60
–70
–80
–90
5400
5500
5600
5700
5800
TRANSMITTER LO FREQUENCY (MHz)
5900
Figure 143. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,
75 MHz RF Bandwidth, Continuous Wave Signal 3 MHz Offset from LO
–45
–50
–55
–60
–65
+110°C LOWER
+40°C LOWER
–40°C LOWER
+110°C UPPER
+40°C UPPER
–40°C UPPER
–70
–75
–80
14651-243
–100
–110
5300
–110
14651-244
5400
RECEIVER LO FREQUENCY (MHz)
–100
5300
–100
–170
14651-241
–100
5300
+110°C
+40°C
–40°C
0
5
10
RF ATTENUATION (dB)
15
20
14651-246
Tx1 TO Rx1 CROSSTALK (dB)
AD9371
Figure 146. Tx Alternate Channel Leakage Ratio vs. RF Attenuation,
5600 MHz LO, 75 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,
2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active
Rev. PrA | Page 40 of 48
Preliminary Technical Data
AD9371
–60
0
–70
–10
–20
Tx OUTPUT (dBm)
–90
–100
–110
–120
–50
–60
–80
–140
10k
100k
1M
14651-247
1k
–100
5750
10M
OFFSET FREQUENCY (Hz)
Figure 147. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff,
5850 MHz LO
–10
0.8
–20
0.7
–30
Tx OUTPUT (dBm)
0.9
0.4
+110°C
+40°C
–40°C
0.3
0.2
5825
5850
5875
5900
5925
5950
Figure 150. Transmitter Spectrum, 3 dB Digital and 1 dB RF Backoff,
40 MHz RF Bandwidth, Transmitter QEC, and Internal LO Leakage Active,
LTE 10 MHz Signal, 5850 MHz LO, 1 MHz Resolution Bandwidth, 122.88 MSPS
Sample Rate, Test Equipment Noise Floor De-Embedded
0
0.5
5800
FREQUENCY (MHz)
1.0
0.6
5775
14651-250
–90
–150
100
–40
–50
–60
–70
–80
0.1
–90
5400
5500
5600
5700
5800
–100
5350 5450 5550 5650 5750 5850 5950 6050 6150 6250 6350
14651-248
0
5300
5900
TRANSMITTER LO FREQUENCY (MHz)
Figure 148. Tx Integrated Phase Noise vs. Transmitter LO Frequency,
75 MHz RF Bandwidth, Continuous Wave 10 MHz Offset from LO,
3 dB Digital Backoff
FREQUENCY (MHz)
14651-251
Tx INTEGRATED PHASE NOISE (Degrees)
–40
–70
–130
Figure 151. Transmitter Spectrum, 3 dB Digital and 1 dB RF Backoff,
40 MHz RF Bandwidth, Transmitter QEC, and Internal LO Leakage Active,
LTE 10 MHz Signal, 5850 MHz LO, 1 MHz Resolution Bandwidth,
122.88 MSPS Sample Rate, Test Equipment Noise Floor De-Embedded
30
–20
+110°C
+40°C
–40°C
–25
TRANSMITTER EVM (dB)
25
TRANSMITTER OIP3 (dBm)
–30
20
15
10
+110°C
+40°C
–40°C
–30
–35
–40
–45
5
0
5
10
RF ATTENUATION (dB)
15
20
–50
14651-249
0
Figure 149. Transmitter OIP3 vs. RF Attenuation, 5600 MHz LO,
75 MHz RF Bandwidth, F1 = 20 MHz, F2 = 21 MHz, 3 dB Digital Backoff,
245.76 MSPS Sample Rate
0
5
10
RF ATTENUATION (dB)
15
20
14651-252
LO PHASE NOISE (dBc)
–80
Figure 152. Transmitter EVM vs. RF Attenuation, 5600 MHz LO, Transmitter
LO Leakage, and Transmitter QEC Tracking Active, 75 MHz RF Bandwidth,
LTE 20 MHz Downlink Signal, 245.76 MSPS Sample Rate
Rev. PrA | Page 41 of 48
AD9371
Preliminary Technical Data
0.10
0
–10
Tx ATTENUATION STEP ERROR (dB)
–20
–30
–40
–50
–60
–70
–80
0.04
0.02
0
–0.02
–0.04
–0.06
10
20
15
–0.10
RF ATTENUATION (dB)
Figure 153. Transmitter HD2 vs. RF Attenuation, 5850 MHz LO,
5855 MHz Continuous Wave Desired Signal, 75 MHz RF Bandwidth,
245.76 MSPS Sample Rate
0
5
10
20
15
RF ATTENUATION (dB)
14651-256
5
14651-253
0
Figure 156. Tx Attenuation Step Error vs. RF Attenuation, 5850 MHz LO,
5855 MHz Continuous Wave Desired Signal, 75 MHz RF Bandwidth,
245.76 MSPS Sample Rate
0
0.5
–10
0.4
+110°C
+40°C
–40°C
–20
DEVIATION FROM FLATNESS (dB)
–30
–40
–50
–60
–70
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
0
5
10
20
15
RF ATTENUATION (dB)
Figure 154. Transmitter HD3 vs. RF Attenuation, 5850 MHz LO,
5855 MHz Continuous Wave Desired Signal, 75 MHz RF Bandwidth,
245.76 MSPS Sample Rate
0
–5
–10
5
10
15
RF ATTENUATION (dB)
20
25
–40
–20
0
20
40
60
80
100
Figure 155. Transmitter Output Power vs. RF Attenuation, 5850 MHz LO,
5855 MHz Continuous Wave Desired Signal, 75 MHz RF Bandwidth,
245.76 MSPS Sample Rate
–40
–45
–50
+110°C
+40°C
–40°C
–55
–60
–65
–70
–75
–80
5300
14651-255
–15
0
–60
FREQUENCY OFFSET FROM LO (MHz)
OBSERVATION RECEIVER LO LEAKAGE (dBm)
+110°C
+40°C
–40°C
–20
–80
Figure 157. Transmitter Frequency Response Deviation from Flatness vs.
Frequency Offset from LO, 5850 MHz LO, 200 MHz Synthesis Bandwidth,
6 dB Digital Backoff, 245.76 MSPS Sample Rate
10
5
–0.5
–100
14651-254
–80
14651-257
TRANSMITTER HD3 (dBc)
0.06
–0.08
–90
–100
TRANSMITTER OUTPUT POWER (dBm)
+110°C
+40°C
–40°C
5400
5500
5600
5700
5800
OBSERVATION RECEIVER LO FREQUENCY (MHz)
5900
14651-258
TRANSMITTER HD2 (dBc)
0.08
+110°C
+40°C
–40°C
Figure 158. Observation Receiver LO Leakage vs. Observation Receiver
LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
Rev. PrA | Page 42 of 48
Preliminary Technical Data
AD9371
20
15
+110°C
+40°C
–40°C
10
5
0
5300
5400
5500
5600
5700
5900
5800
OBSERVATION RECEIVER LO FREQUENCY (MHz)
–30
–40
–50
–60
–70
–80
–90
0
OBSERVATION RECEIVER GAIN (dBc)
20
40
30
+110°C
+40°C
–40°C
20
10
20
30
40
50
60
70
80
90
100
110
INTERMODULATION FREQUENCY (MHz)
Figure 160. Observation Receiver IIP2 vs. Intermodulation Frequency,
5600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
6
9
12
15
18
Figure 162. Observation Receiver Image vs. Observation Receiver
Attenuation, 5600 MHz LO, Continuous Wave Signal 30 MHz Offset,
200 MHz RF Bandwidth, Background Tracking Calibration (BTC) Active,
245.76 MSPS Sample Rate
70
50
3
OBSERVATION RECEIVER ATTENUATION (dB)
25
0
10
+110°C
+40°C
–40°C
15
10
5
0
–5
–10
–15
0
3
6
9
12
15
18
OBSERVATION RECEIVER ATTENUATION (dB)
Figure 163. Observation Receiver Gain vs. Observation Receiver Attenuation,
5600 MHz LO, Continuous Wave Signal 30 MHz Offset,
200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
–40
35
30
25
20
15
+110°C
+40°C
–40°C
10
0
5
15
25
35
45
55
65
75
85
95
INTERMODULATION FREQUENCY (MHz)
105
115
Figure 161. Observation Receiver IIP3 vs. Intermodulation Frequency,
5600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth, 245.76 MSPS
Sample Rate
–60
–70
–80
–90
–100
–110
14651-261
5
+110°C
+40°C
–40°C
–50
0
3
6
9
12
15
OBSERVATION RECEIVER ATTENUATION (dB)
18
14651-264
OBSERVATION RECEIVER DC OFFSET (dBFS)
40
OBSERVATION RECEIVER IIP3 (dBm)
–20
80
60
+110°C
+40°C
–40°C
–100
14651-260
OBSERVATION RECEIVER IIP2 (dBm)
Figure 159. Observation Receiver Noise Figure vs. Observation Receiver
LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate, 100 MHz Integration Bandwidth
–10
14651-263
25
14651-262
OBSERVATION RECEIVER IMAGE (dBc)
0
14651-259
OBSERVATION RECEIVER NOISE FIGURE (dB)
30
Figure 164. Observation Receiver DC Offset vs. Observation Receiver
Attenuation, 5600 MHz LO, Continuous Wave Signal 30 MHz Offset,
−15 dBm Input, 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
Rev. PrA | Page 43 of 48
AD9371
Preliminary Technical Data
0
0
OBSERVATION RECEIVER HD3 (dBc)
OBSERVATION RECEIVER HD2 (dBc)
–10
+110°C
+40°C
–40°C
–20
–30
–40
–50
–60
–70
–80
+110°C
+40°C
–40°C
–20
–40
–60
–80
–100
0
3
6
9
12
15
OBSERVATION RECEIVER ATTENUATION (dB)
18
–120
14651-265
–100
Figure 165. Observation Receiver HD2 vs. Observation Receiver Attenuation,
5600 MHz LO, Continuous Wave Signal 30 MHz Offset, −15 dBm Input,
Input Power Increasing dB for dB with Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
0
3
6
9
12
15
OBSERVATION RECEIVER ATTENUATION (dB)
18
14651-266
–90
Figure 166. Observation Receiver HD3 vs. Observation Receiver Attenuation,
5600 MHz LO, Continuous Wave Signal 30 MHz Offset, −15 dBm Input,
Input Power Increasing dB for dB with Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
Rev. PrA | Page 44 of 48
Preliminary Technical Data
AD9371
THEORY OF OPERATION
The AD9371 is a highly integrated RF transceiver capable of
being configured for a wide range of applications. The device
integrates all the RF, mixed signal, and digital blocks necessary
to provide transmit and receive functions in a single device.
Programmability allows the two receiver channels and two
transmitter channels to be used in TDD and FDD systems for
3G and 4G cellular standards.
The observation receiver channel has two inputs for use in
monitoring the transmitter outputs. This channel has a wide
channel bandwidth that receives the entire transmit band and
feeds it back to the digital section for error correction purposes.
In addition, three sniffer receiver inputs can monitor different
radio frequency bands (one at a time). These channels share the
baseband ADC and digital processing with the two ORx inputs.
The AD9371 contains four high speed serial interface links for
the transmit chain and four high speed serial interface links
shared by the Rx, ORx, and SnRx channels (JESD204B,
Subclass 1 compliant), providing a low pin count and reliable
data interface to a field-programmable gate array (FPGA) or
other custom integrated baseband solutions.
The AD9371 also provides self calibration for dc offset and
quadrature error correction to maintain a high performance
level under varying temperatures and input signal conditions.
The device includes test modes that allow system designers to
debug designs during prototyping and optimize radio
configurations.
TRANSMITTER (Tx)
The AD9371 employs a direct conversion transmitter
architecture consisting of two identical and independently
controlled channels that provide all the digital processing,
mixed signal, and RF blocks necessary to implement a direct
conversion system. Both channels share a common frequency
synthesizer.
The digital data from the JESD204B lanes pass through a fully
programmable 96-tap FIR filter with optional interpolation.
The FIR output is sent to a series of conversion filters that
provide additional filtering and data rate interpolation prior to
reaching the DAC. Each DAC has an adjustable sample rate and
is linear up to full scale.
Once converted to baseband analog signals, the in-phase (I) and
quadrature (Q) signals are filtered to remove sampling artifacts,
and then the signals are fed to the upconversion mixers. At the
mixer stage, the I and Q signals are recombined and modulated
onto the carrier frequency for transmission to the output stage.
Each transmit chain provides a wide attenuation adjustment
range with fine granularity to help designers optimize SNR.
RECEIVER (Rx)
The AD9371 contains dual receiver channels. Each Rx channel
is a direct conversion system that contains a programmable
attenuator stage, followed by matched I and Q mixers that down
convert received signals to baseband for digitization.
To achieve gain control, a programmed gain index map is
implemented. This gain map distributes attenuation among the
various Rx blocks for optimal performance at each power level.
In addition, support is available for both automatic and manual
gain control modes.
The receiver includes Σ-Δ ADCs and adjustable sample rates
that produce data streams from the received signals. The signals
can be conditioned further by a series of decimation filters and
a fully programmable 72-tap FIR filter with additional decimation
settings. The sample rate of each digital filter block is adjustable
by changing the decimation factors to produce the desired
output data rate.
OBSERVATION RECEIVER (ORx)
The ORx operates in a similar manner to the main receivers.
Each input is differential and uses a dedicated mixer. The ORx
inputs share a baseband ADC and baseband section; therefore,
only one can be active at any time. The mixed signal and digital
section is identical in design and operation to the main receiver
channels. This channel can monitor the Tx channels and
implement error correction functions. It can also be used as a
general-purpose receiver.
SNIFFER RECEIVER (SnRx)
The sniffer receiver provides three differential inputs that can
monitor different frequency bands. Each input has a low noise
amplifier (LNA) that is multiplexed to feed a single mixer. The
output of this mixer stage is multiplexed with the ORx receiver
mixers to feed the same baseband section. The SnRx bandwidth
is limited to 20 MHz. This receiver can also be used as a generalpurpose receiver if the bandwidth and RF performance are
acceptable for a given application.
CLOCK INPUT
The AD9371 requires a differential clock connected to the
DEV_CLK_IN+/DEV_CLK_IN− pins. The frequency of the
clock input must be between 10 MHz and 320 MHz, and it must
have very low phase noise because this signal generates the RF
local oscillator and internal sampling clocks.
Rev. PrA | Page 45 of 48
AD9371
Preliminary Technical Data
SYNTHESIZERS
AUXILIARY CONVERTERS
RF PLL
Auxiliary ADCs (AUXADC_x)
The AD9371 contains three fractional-N PLLs to generate the
RF LOs used by the transmitter, receiver, and observation
receiver. The PLL incorporates an internal VCO and loop filter
that require no external components. The internal VCO LDO
regulators eliminate the need for additional external power
supplies for the PLLs. These regulators only require an external
bypass capacitor for each supply.
The AD9371 contains an auxiliary ADC that is multiplexed to four
input pins (AUXADC_0 through AUXADC_3). This block can
monitor system voltages without adding additional components.
The auxiliary ADC is 12 bits with an input voltage range of 0.05 V
to VDDA_3P3 − 0.05 V. When enabled, the auxiliary ADC is
free running. Software reads of the output value provide the last
value latched at the ADC output.
Clock PLL
Auxiliary DACs (AUXDAC_x)
The AD9371 contains a PLL synthesizer that generates all of the
baseband related clock signals and SERDES clocks. This PLL is
programmed based on the data rate and sample rate requirements
of the system.
The AD9371 contains ten identical auxiliary DACs (AUXDAC_0
to AUXDAC_9) that can supply bias voltages, analog control
voltages, or other system functionality. The inputs of these
AUXDAC_xs are multiplexed with GPIO_3P3_x pins according
to Table 7. The auxiliary DACs are 10 bits and have an output
voltage range of approximately 0.5 V to VDDA_3P3 − 0.05 V
and have a current drive of 10 mA.
SERIAL PERIPHERAL INTERFACE (SPI) INTERFACE
The AD9371 uses a SPI to communicate with the baseband
processor (BBP). This interface can be configured as a 4-wire
interface with dedicated receive and transmit ports, or it can be
configured as a 3-wire interface with a bidirectional data
communications port. This bus allows the BBP to set all device
control parameters using a simple address data serial bus protocol.
Write commands follow a 24-bit format. The first bit sets the
bus direction of the bus transfer. The next 15 bits set the address
where data is written. The final eight bits are the data being
transferred to the specific register address.
Read commands follow a similar format with the exception that
the first 16 bits are transferred on the SDIO, and the final 8 bits
are read from the AD9371, either on the SDO pin in 4-wire
mode or on the SDIO pin in 3-wire mode.
Table 7. AUXDAC Input Pin Assignments
GPIO_3P3 Pin
GPIO_3P3_9
GPIO_3P3_7
GPIO_3P3_6
GPIO_3P3_10
GPIO_3P3_0
GPIO_3P3_1
GPIO_3P3_3
GPIO_3P3_4
GPIO_3P3_5
GPIO_3P3_8
AUXDAC Output
AUXDAC_0
AUXDAC_1
AUXDAC_2
AUXDAC_3
AUXDAC_4
AUXDAC_5
AUXDAC_6
AUXDAC_7
AUXDAC_8
AUXDAC_9
GPIO_x AND GPIO_3P3_x PINS
JESD204B DATA INTERFACE
The AD9371 general-purpose input/output signals referenced
to the VDD_IF supply can be configured for numerous functions.
Some of these pins, when configured as outputs, are used by the
BBP as real-time signals to provide a number of internal settings
and measurements. This configuration allows the BBP to
monitor receiver performance in different situations. A pointer
register selects what information is output to these pins. Signals
used for manual gain mode, calibration flags, state machine
states, and various receiver parameters are among the outputs
that can be monitored on these pins. In addition, certain pins
can be configured as inputs and used in various functions such
as setting the receiver gain in real time.
The digital data interface for the AD9371 uses JEDEC Standard
JESD204B Subclass 1. The serial interface operates at speeds up
to 6144 Mbps. The benefits of the JESD204B interface include a
reduction in required board area for data interface routing and
smaller package options due to the need for fewer pins. Digital
filtering is included in all receiver and transmitter paths to
provide proper signal conditioning and sampling rates to meet
the JESD data requirements. Examples of the digital filtering
configurations for the Tx and Rx paths are shown in Figure 167
and Figure 168, respectively.
The GPIO_3P3_x pins referenced to the VDDA_3P3 supply are
also included in the device and can provide control signals to
the external components such as VGAs or attenuators in the RF
section that typically use a higher reference voltage.
Rev. PrA | Page 46 of 48
Preliminary Technical Data
AD9371
Table 8. Example Rx/Tx Interface Rates (2 Rx/2 Tx Channels, Maximum JESD Lane Rates)
Tx Input
Rate (MSPS)
307.2
245.76
122.88
122.88
Rx Output
Rate (MSPS)
153.6
122.88
61.44
30.72
TRANSMITTER
HALF-BAND
FILTER 2
TRANSMITTER
HALF-BAND
FILTER 1
JESD Lane Rate
(Mbps), 2 Tx/2 Rx
6144
4915.2
2457.6
2457.6
JESD204B (No.
of Lanes) Tx/Rx
4/2
4/2
4/2
4/1
TRANSMITTER FIR
(INTERPOLATION
1, 2, 4)
Reference Clock Options (MHz)
122.88, 153.6, 245.76, 307.2
122.88, 245.76
122.88, 245.76
122.88, 245.76
QUADRATURE
ERROR
CORRECTION
DIGITAL
GAIN
14651-125
Tx/Tx Synthesis/
Rx Bandwidth (MHz)
100/250/100
75/200/100
20/100/40
20/100/20
Figure 167. Example Tx Data Path Filter Implementation
DEC5
RECEIVER
HALF-BAND
FILTER 3
RECEIVER
HALF-BAND
FILTER 2
RECEIVER
HALF-BAND
FILTER 1
RFIR
(DECIMATION
1, 2, 4)
QEC
CORRECTION
FILTER
DIGITAL
GAIN
DC
CORRECTION
REAL
IF
JESD204B
14651-126
ADC
Figure 168. Data Rx Data Path Filter Implementation
POWER SUPPLY SEQUENCE
Table 9. Dual Function Boundary Scan Test Pins
The AD9371 requires a specific power-up sequence to avoid
undesired power-up currents. The optimal power-on sequence
starts the process by powering up the VDIG and the
VDDA_1P3 (analog) supplies simultaneously. If they cannot
power up simultaneously, the VDIG supply must power up first.
The VDDA_3P3, VDDA_1P8, and JESD_VTT_DES supplies
must then power up after the VDIG and VDDA_1P3 supplies.
Note that the VDD_IF supply can power up at any time. It is
also recommended to toggle the RESET signal after power has
stabilized prior to configuration. Follow the reverse order of
the power-up sequence to power-down.
Mnemonic
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_18
JTAG BOUNDARY SCAN
The AD9371 provides support for a JTAG boundary scan.
There are five dual function pins associated with the JTAG
interface. These pins, listed in Table 9, are used to access the onchip test access port. To enable the JTAG functionality, set the
GPIO_0 through GPIO_3 pins according to Table 10 depending
on how the desired JESD sync pin (that is, SYNCINB0+,
SYNCINB0−, SYNCINB1+, SYNCINB1−, SYNCBOUTB0+,
or SYNCBOUTB0−) is configured in the software (LVDS or
CMOS mode). Pull the TEST pin high to enable the JTAG mode.
JTAG Mnemonic
TRST
TDO
TDI
TMS
TCK
Description
Test access port reset
Test data output
Test data input
Test access port mode select
Test clock
Table 10. JTAG Modes
Test Pin Level
0
1
GPIO_0 to GPIO_3
XXXX1
1001
1
1011
1
X stands for don’t care.
Rev. PrA | Page 47 of 48
Description
Normal operation
JTAG mode with LVDS
JESD SYNC signals
JTAG mode with CMOS
JESD SYNC signals
AD9371
Preliminary Technical Data
OUTLINE DIMENSIONS
A1 BALL
CORNER
12.10
12.00 SQ
11.90
A1 BALL
PAD CORNER
14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN A1
INDICATOR
7.755 REF
A
B
C
D
E
F
G
H
J
K
L
M
N
P
10.40 SQ
0.80
TOP VIEW
BOTTOM VIEW
0.80 REF
8.165 REF
DETAIL A
DETAIL A
0.91
0.84
0.77
0.39
0.34
0.29
0.44 REF
PKG-004569
SEATING
PLANE
0.50
0.45
0.40
BALL DIAMETER
COPLANARITY
0.12
COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.
Figure 169. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-196-12)
Dimensions shown in millimeters
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14651-0-5/16(PrA)
Rev. PrA | Page 48 of 48
03-02-2015-A
1.27
1.18
1.09