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RHFLVDS217
Rad-hard LVDS serializer
Datasheet - preliminary data
Description
The RHFLVDS217 serializer converts 21 bits of
CMOS/TTL data into three LVDS (low voltage
differential signaling) data streams. A phaselocked transmitter clock is transmitted in parallel
with the data streams over a fourth LVDS link.
With every cycle of the transmitter clock, 21 bits
of input data are sampled and transmitted.
At a transmitter clock frequency of 75 MHz,
21 bits of TTL data are transmitted at a rate of
525 Mbps per LVDS data channel. Using a 75
MHz clock, the data throughput is 1.575 Gbit/s
(197 Mbytes/s).
The RHFLVDS217 serializer allows the use of
wide, high speed TTL interfaces while reducing
overall EMI and cable size.
All pins have cold spare buffers. These buffers
are high impedance when VCC is tied to 0 V.
Features
15 to 75 MHz shift clock support
Fail-safe function
8 kV HBM on LVDS pins
Power-down mode < 216 µW (max)
Cold sparing all pins
Narrow bus reduces cable size and cost
Up to 1.575 Gbps throughput
Up to 197 Mbytes/s bandwidth
325 mV (typ) LVDS swing
PLL requires no external components
Rising edge strobe
Operational environment: total dose
irradiation testing to MIL-STD-883 method
1019
Total dose: 300 krad (Si)
Latchup immune
(LET > 120 MeV-cm2/mg)
Compatible with ANSI/TIA/EIA-644 standard
April 2016
Table 1: Device summary
Parameter
SMD
RHFLVDS217K1
(1)
—
Quality level
Engineering model
Package
Flat-48
Mass
1.22 g
EPPL
(2)
Temp. range
—
-55 °C to 125 °C
Notes:
(1)
(2)
SMD = standard microcircuit drawing
EPPL = ESA preferred part list
DocID029114 Rev 1
This is preliminary information on a new product now in development
or undergoing evaluation. Details are subject to change without notice.
1/20
www.st.com
Contents
RHFLVDS217
Contents
1
Functional description .................................................................... 3
2
Pin configuration ............................................................................. 4
3
4
Typical application .......................................................................... 5
Absolute maximum ratings and operating conditions ................. 6
5
Electrical characteristics ................................................................ 7
6
Radiations ...................................................................................... 10
7
Test circuit and AC timing diagrams ........................................... 11
8
Package information ..................................................................... 15
8.1
Ceramic Flat-48 package information ............................................. 16
9
Ordering information..................................................................... 17
10
Other information .......................................................................... 18
10.1
11
2/20
Date code ........................................................................................ 18
Revision history ............................................................................ 19
DocID029114 Rev 1
RHFLVDS217
1
Functional description
Functional description
Figure 1: RHFLVDS217 serializer functional block diagram
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3/20
Pin configuration
2
RHFLVDS217
Pin configuration
Table 2: PIn description
Pin name
I/O
No.
Description
TxIN
I
21
TTL level input
TxOUT+
O
3
Positive LVDS differential data output
TxOUT-
O
3
Negative LVDS differential data output
TxCLK IN
I
1
TTL level clock input. The rising edge acts as data strobe.
Pin name TxCLK IN
TxCLK OUT+
O
1
Positive LVDS differential clock output
TxCLK OUT-
O
1
Negative LVDS differential clock output
PWR DWN
I
1
TTL level input. Assertion (low input) TRISTATEs the clock and data
outputs, ensuring low current at power down.
VCC
I
4
Power supply pins for TTL inputs and logic
GND
I
5
Ground pins for TTL inputs and logic
PLL VCC
I
1
Power supply pins for PLL
PLL GND
I
2
Ground pins for PPL
LVDS VCC
I
1
Power supply pin for LVDS output
LVDS GND
I
3
Ground pins for LVDS outputs
Figure 2: RHFLVDS217 pinout
4/20
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RHFLVDS217
3
Typical application
Typical application
Figure 3: RHFLVDS217 typical application
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5/20
Absolute maximum ratings and operating
conditions
4
RHFLVDS217
Absolute maximum ratings and operating conditions
Stresses outside the listed absolute maximum ratings may cause permanent damage to
the device. This is a stress rating only, and functional operation of the device at these or
any other conditions beyond the limits indicated in the operational sections of this
specification are not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability and performance.
Table 3: Absolute maximum ratings (references to GND)
Symbol
VCC
Vi
Tstg
Tj
Rthjc
ESD
Parameter
Supply voltage
Value
(1)
4.8
TTL inputs (operating or cold-spare)
-0.3 to 4.8
Storage temperature range
-65 to 150
Maximun junction temperature
150
Thermal resistance junction to case
HBM: human body model
(2)
22
All pins except LVDS outputs
2
LVDS outputs vs. GND
8
CDM: charge device model
500
Unit
V
°C
°C/W
kV
V
Notes:
(1)
All voltages, except the differential I/O bus voltage, are with respect to the network ground terminal.
(2)
Short-circuits can cause excessive heating. Destructive dissipation can result from short-circuits on the
amplifiers.
Table 4: Recommended operating conditions (referenced to GND)
Symbol
6/20
Parameter
Min.
Typ.
Max.
3.3
3.6
VCC
Supply voltage
3
VIN
Driver DC input voltage (TTL inputs)
0
VCC
TA
Ambient temperature range
-55
125
DocID029114 Rev 1
UNit
V
°C
RHFLVDS217
5
Electrical characteristics
Electrical characteristics
In Table 5: "DC electrical characteristics", VCC = 3 V to 3.6 V, - 55 °C < TA < 125 °C, unless
otherwise specified, TA is per the temperature noted. Current into device pins is defined as
positive. Current out of device pins is defined as negative. All voltages are referenced to
ground.
Table 5: DC electrical characteristics
Symbol
Parameter
Condition
Min.
Max.
Unit
CMOS/TTL DC specifications
VIH
High-level input voltage
2.0
VCC
VIL
Low-level input voltage
GND
0.8
IIH
High-level input current
VIN = 3.6 V, VCC = 3.6 V
-10
10
IIL
Low-level input current
VIN = 0 V, VCC = 3.6 V
-10
10
VCL
Input clamp voltage
ICL = -18 mA
ICS
Cold spare leakage current
VIN = 3.6V, VCC = 0 V
V
µA
-1.5
V
-20
20
µA
250
400
LVDS output DC specifications (OUT+, OUT-)
VOD
(1)
DVOD
VOS
(1)
(1)
DVOS
(2)
IOZ
IOS
(1) (3)
ICSOUT
Differential output voltage
RL = 100 ohm (see Figure 14)
Change in VOD between
complimentary output states
RL = 100 ohm (see Figure 14)
Offset voltage
RL = 100 ohm,
VOS = (VOH + VOL)/2
Change in VOS between
complimentary output states
RL = 100ohm
Output three-state current
PWR DWN = 0 V
VOUT = 0 V or VCC
Output short circuit current
VOUT+ or VOUT = 0 V
Cold spare leakage current
VIN = 3.6 V, VCC = 0 V
35
1.125
mV
1.450
V
35
mV
10
µA
3.5
9
mA
-20
20
µA
-10
Supply current
ICCL
(4)
ICCZ
Transmitter supply current
with loads
RL = 100 ohm all channels
(see Figure 5), CL = 5 pF,
f = 50 MHz
65
mA
Power down current
DIN = VSS/ PWR DWN = 0 V,
f = 0 Hz
200
µA
Notes:
(1)
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one
output should be shorted at a time, for a maximum duration of one second.
(2)
(3)
(4)
Clock outputs guaranteed by design.
Guaranteed by characterization.
Devices are tested at 3.6 V only.
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Electrical characteristics
RHFLVDS217
In Table 6: "AC switching characteristics", VCC = 3 V to 3.6 V, - 55 °C < TA < 125 °C, unless
otherwise specified, TA is per the temperature noted. For devices procured with a total
ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25 °C
per MIL-STD-883 Method 1019, condition A up to the maximum TID level procured. The
recommend transition time for TXCLK In is 1.0 to 6.0 ns (see Figure 6)
Table 6: AC switching characteristics
Symbol
Parameter
Max.
LLHT
LVDS low-to-high transition time (see Figure 5)
1.5
LHLT
(1)
LVDS high-to-low transition time (see Figure 5)
1.5
TPPos0
(1)
TPPos1
(1)
TPPos2
(1)
TPPos3
(1)
TPPos4
(1)
TPPos5
(1)
TPPos6
(1)
TCCS
(1)
Transmitter output pulse position for bit 0 (see Figure 13)
-0.18
0.270
Transmitter output pulse position for bit 1 (see Figure 13),
f = 75 MHz
1.72
2.17
Transmitter output pulse position for bit 2 (see Figure 13),
f = 75 MHz
3.63
4.08
Transmitter output pulse position for bit 3 (see Figure 13),
f = 75 MHz
5.53
5.98
Transmitter output pulse position for bit 4 (see Figure 13),
f = 75 MHz
7.44
7.89
Transmitter output pulse position for bit 5 (see Figure 13),
f = 75 MHz
9.34
9.79
Transmitter output pulse position for bit 6 (see Figure 13),
f = 75 MHz
11.25
11.70
Unit
ns
Channel to channel skew (see Figure 7), f = 75 MHz
0.45
TCIP
(1)
TxCLK IN period (see Figure 8)
13.3
66.7
TCIH
(2)
TxCLK IN high time (see Figure 8)
0.35
Tcip
0.65
Tcip
TxCLK IN low time (see Figure 8)
0.35
Tcip
0.65
Tcip
TxIN setup to TxCLK IN (see Figure 8), 15 MHz
1.0
TxIN setup to TxCLK IN (see Figure 8), 75 MHz
0.5
TxIN hold to TxCLK IN (see Figure 8), 15MHz
0.7
TxIN hold to TxCLK IN (see Figure 8), 75 MHz
0.5
TCCD
TxCLK IN to TxCLK OUT delay (see Figure 9)
0.5
TPLLS
Transmitter phase lock loop set (see Figure 10)
10
ms
TPDD
Transmitter power down delay (see Figure 12)
100
µs
TCIL
(2)
TSTC
(1)
THTC
(1)
Notes:
(1)
(2)
8/20
Min.
(1)
Guaranteed by characterization.
Guaranteed by design
DocID029114 Rev 1
3
RHFLVDS217
Electrical characteristics
Cold sparing
The RHFLVDS217 features a cold spare input and output buffer. In high reliability
applications, cold sparing enables a redundant device to be tied to the data bus with its
power supply at 0 V (VCC = GND) without affecting the bus signals or injecting current
from the I/Os to the power supplies. Cold sparing also allows redundant devices to be kept
powered off so that they can be switched on only when required. This has no impact on the
application. Cold sparing is achieved by implementing a high impedance between the I/Os
and VCC. ESD protection is ensured through a non-conventional dedicated structure.
Fail-safe
In many applications, inputs need a fail-safe function to avoid an uncertain output state
when the inputs are not connected properly. In case of TTL floating inputs, the LVDS
outputs remain in a stable logic-high state.
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Radiations
6
RHFLVDS217
Radiations
Total dose (MIL-STD-883 TM 1019)
The products guaranteed in radiation within the RHA QML-V system fully comply with the
MIL-STD-883 TM 1019 specification.
The RHFLVDS217 is RHA QML-V, tested and characterized in full compliance with the
MIL-STD-883 specification, between 50 and 300 rad/s only (full CMOS technology).
All parameters provided in Table 5: "DC electrical characteristics" apply to both pre- and
post-irradiation, as follows:
All test are performed in accordance with MIL-PRF-38535 and test method 1019 of
MIL-STD-883 for total ionizing dose (TID).
The initial characterization is performed in qualification only on both biased and
unbiased parts.
Each wafer lot is tested at high dose rate only, in the worst bias case condition, based
on the results obtained during the initial qualification.
Heavy ions
The behavior of the product when submitted to heavy ions is not tested in production.
Heavy-ion trials are performed on qualification lots only.
Table 7: Radiation
Type
TID
Characteristics
Value
Unit
High-dose rate (50 - 300 rad/sec) up to:
300
krad
SEL immune up to:
(with a particle angle of 60 ° at 125 °C)
120
Heavy ions
MeV.cm²/mg
SEL immune up to:
(with a particle angle of 0 ° at 125 °C)
10/20
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60
RHFLVDS217
7
Test circuit and AC timing diagrams
Test circuit and AC timing diagrams
Figure 4: Test pattern
Figure 5: RHFLVDS217 output load and transition times
Figure 6: RHFLVDS217 input clock transition time
Figure 7: RHFLVDS217 channel-to-channel skew
1.
2.
3.
Measurements at VDIFF = 0 V
TCCS measured between earliest and latest LVDS edges
TxCLK differential low-high edge
DocID029114 Rev 1
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Test circuit and AC timing diagrams
RHFLVDS217
Figure 8: RHFLVDS217 setup/hold and high/low times
Figure 9: RHFLVDS217 clock-to-clock out delay
Figure 10: RHFLVDS217 phase-lock-loop set time
12/20
DocID029114 Rev 1
RHFLVDS217
Test circuit and AC timing diagrams
Figure 11: RHFLVDS217 parallel TTL data inputs mapped to LVDS outputs
Figure 12: Transmitter powerdown delay
DocID029114 Rev 1
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Test circuit and AC timing diagrams
RHFLVDS217
Figure 13: RHFLVDS output pulse position measurement
Figure 14: Driver VOD and VOS test circuit or equivalent circuit
14/20
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RHFLVDS217
8
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
DocID029114 Rev 1
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Package information
8.1
RHFLVDS217
Ceramic Flat-48 package information
Figure 15: Ceramic Flat-48 package outline
Pin 1 identifier
48
e
(N-2 places)
D
b
(N places)
24
25
S1
(4 places)
L
E
L
c
A
E3
Q
1.
E2
f
E3
The upper metallic lid is connected to pin 17.
Table 8: Ceramic Flat-48 mechanical data
mm
inches
Dim
16/20
Typ
Min
Max
Typ
Min
Max
A
2.47
2.18
2.72
0.097
0.086
0.107
b
0.254
0.20
0.30
0.010
0.008
0.012
c
0.15
0.12
0.18
0.006
0.005
0.007
D
15.75
15.57
15.92
0.620
0.613
0.627
E
9.65
9.52
9.78
0.380
0.375
0.385
E2
6.35
6.22
6.48
0.250
0.245
0.255
E3
1.65
1.52
1.78
0.065
0.060
0.070
e
0.635
0.025
f
0.20
0.008
L
8.38
6.85
9.40
0.330
0.270
0.370
Q
0.79
0.66
0.92
0.031
0.026
0.036
S1
0.43
0.25
0.61
0.017
0.010
0.024
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RHFLVDS217
9
Ordering information
Ordering information
Table 9: Order codes
Order code
RHFLVDS217K1
Description
Temp. range
Package
Engineering model
-55 °C to 125 °C
Flat-48
Marking
(1)
RHFLVDS217K1
Packing
Strip pack
Notes:
(1)
Specific marking only. Complete marking includes the following:
- ST logo
- Date code (date the package was sealed) in YYWWA (year, week, and lot index of week)
- Country of origin (FR = France)
Contact your ST sales office for information regarding the specific conditions for products in die
form and QML-Q versions.
DocID029114 Rev 1
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Other information
RHFLVDS217
10
Other information
10.1
Date code
The date code is structured as follows: EM (engineering model) = xyywwz
Where:
x (EM only): 3, assembly location Rennes (France)
yy: last two digits year
ww: week digits
z: lot index in the week
18/20
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RHFLVDS217
11
Revision history
Revision history
Table 10: Document revision history
Date
Revision
08-Apr-2016
1
DocID029114 Rev 1
Changes
Initial release
19/20
RHFLVDS217
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