RHFLVDS218 Rad-hard LVDS deserializer Datasheet - preliminary data Description The RHFLVDS218 deserializer converts the three LVDS data streams back into 21 bits of CMOS/TTL data. At a transmitter clock frequency of 75 MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel. Using a 75 MHz clock, the data throughput is 1.575 Gbit/s (197 Mbytes/s). The RHFLVDS218 deserializer allows the use of wide, high speed TTL interfaces while reducing overall EMI and cable size. All pins have cold spare buffers. These buffers are high impedance when VCC is tied to 0 V. Table 1: Device summary Parameter SMD Features 15 to 75 MHz shift clock support 50 % duty cycle on receiver output clock -4 V to 5 V common-mode range Cold sparing all pins Fail-safe function Narrow bus reduces cable size and cost Up to 1.575 Gbps throughput Up to 197 Mbytes/s bandwidth 325 mV (typ) LVDS swing PLL requires no external components Rising edge strobe Operational environment: total dose irradiation testing to MIL-STD-883 method 1019 Total-dose: 300 krad (Si) Latchup immune (LET > 120 MeV-cm2/mg) Compatible with TIA/EIA-644 LVDS standard April 2016 RHFLVDS218K1 (1) — Quality level Engineering model Package Flat-48 Mass 1.22 g EPPL (2) Temp. range — -55 °C to 125 °C Notes: (1) (2) SMD = standard microcircuit drawing EPPL = ESA preferred part list DocID029115 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/20 www.st.com Contents RHFLVDS218 Contents 1 Functional description .................................................................... 3 2 Pin configuration ............................................................................. 4 3 4 Typical application .......................................................................... 5 Absolute maximum ratings and operating conditions ................. 6 5 Electrical characteristics ................................................................ 7 6 Radiations ...................................................................................... 10 7 Test circuit and AC timing diagrams ........................................... 11 8 Package information ..................................................................... 15 8.1 Ceramic Flat-48 package information ............................................. 16 9 Ordering information..................................................................... 17 10 Other information .......................................................................... 18 10.1 11 2/20 Date code ........................................................................................ 18 Revision history ............................................................................ 19 DocID029115 Rev 1 RHFLVDS218 1 Functional description Functional description Figure 1: RHFLVDS218 deserializer functional block diagram DocID029115 Rev 1 3/20 Pin configuration 2 RHFLVDS218 Pin configuration Table 2: PIn description Pin name I/O No. Description RxIN+ I 3 Positive LVDS differential data inputs RxIN- I 3 Negative LVDS differential data output RxOUT O 21 TTL level data outputs RxCLK IN+ I 1 Positive LVDS differential clock input RxCLK IN- I 1 Negative LVDS differential clock input RxCLK OUT O 1 TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT. PWR DWN I 1 TTL level input. When asserted (low input) the receiver outputs are low VCC I 4 Power supply pins for TTL outputs and logic GND I 5 Ground pins for TTL outputs and logic PLL VCC I 1 Power supply pins for PLL PLL GND I 2 Ground pins for PPL LVDS VCC I 1 Power supply pin for LVDS pins LVDS GND I 3 Ground pins for LVDS inputs (1) (1) Notes: (1) These receivers have input fail-safe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions receiver inputs are in a HIGH state. If a clock signal is present, data outputs are all be HIGH. If the clock input is also floating/terminated outputs remain in the last valid state. A floating/terminated clock input results in a LOW clock output. Figure 2: RHFLVDS218 pinout 4/20 DocID029115 Rev 1 RHFLVDS218 3 Typical application Typical application Figure 3: RHFLVDS218 typical application DocID029115 Rev 1 5/20 Absolute maximum ratings and operating conditions 4 RHFLVDS218 Absolute maximum ratings and operating conditions Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond the limits indicated in the operational sections of this specification are not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. Table 3: Absolute maximum ratings (references to GND) Symbol VCC Vi Parameter Supply voltage TTL inputs (operating or cold-spare) -0.3 to 4.8 LVDS common-mode (operating or cold-spare) Tstg Storage temperature range Rthjc ESD Unit 4.8 VCM Tj Value (1) -5 to 6 -65 to 150 Maximun junction temperature 150 Thermal resistance junction to case HBM: human body model V (2) 22 All pins except LVDS outputs 2 LVDS inputs vs. GND 8 CDM: charge device model °C °C/W kV 500 V Notes: (1) All voltages, except the differential I/O bus voltage, are with respect to the network ground terminal. (2) Short-circuits can cause excessive heating. Destructive dissipation can result from short-circuits on the amplifiers. Table 4: Recommended operating conditions (referenced to GND) Symbol 6/20 Parameter Min. Typ. Max. 3.3 3.6 VCC Supply voltage 3 VCM Static common-mode on the receiver -4 5 TA Ambient temperature range -55 125 CL Output capacitive load DocID029115 Rev 1 3 UNit V °C pF RHFLVDS218 5 Electrical characteristics Electrical characteristics In Table 5: "DC electrical characteristics", VCC = 3 V to 3.6 V, - 55 °C < TA < 125 °C, unless otherwise specified, TA is per the temperature noted. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground. Table 5: DC electrical characteristics Symbol Parameter Condition Min. Typ. Max. Unit CMOS/TTL DC specifications ( PWR DWN , RXOUT) VIH High-level input voltage 2 VCC VIL Low-level input voltage GND 0.8 VOL Low-level output voltage IOL = 2 mA, VCC = 3 V VOH High-level output voltage IOL = -0.4 mA, VCC = 3 V 2.7 IIH High-level input current VIN = 3.6 V, VCC = 3.6 V -10 10 IIL Low-level input current VIN = 0 V, VCC = 3.6 V -10 10 VCL Input clamp voltage ICL = -18 mA ICS Cold spare leakage current VIN = 3.6 V, VCC = GND IOS Output short-circuit current VOUT = 0 V IOFF TTL/CMOS and clock output leakage current in powerdown ZOUT Output impedance 0.25 V µA -1.5 V -10 10 µA 30 90 mA -10 10 µA Ω 100 LVDS receiver DC specifications (IN+, IN-) VTL Differential input low threshold VCM = 1.2 V -100 -4 V < VCM < 5 V -130 VCM = 1.2 V 100 -4 V < VCM < 5 V 130 -4 mV VTH Differential input high threshold VCMR Common-mode voltage range VID = 200 mVp-p VCMREJ Common-mode rejection F = 10 MHz IID Differential Input current VID = 400 mVp-p -10 10 IICM Common mode Input current VIC = - 4 V to 5 V -70 70 ICSIN Clod spare leakage current VIN = 3.6 V, VCC = GND -60 60 CIN Input capacitance On each LVDS input vs. GND 3 pF CL = 8 pF (see Figure 5) 65 mA 2 mA 5 V 300 mVpp µA Supply current ICCL Active supply current ICCPD Powerdown supply current PWR DWN = low, LVDS inputs = logic low, VCC = 3.6 V DocID029115 Rev 1 7/20 Electrical characteristics RHFLVDS218 In Table 6: "Receiver switching characteristics", VCC = 3 V to 3.6 V, TA = - 55 °C to 125 °C, and unless otherwise specified, T A is per the temperature noted. The receiver skew margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window). This margin allows for an LVDS interconnect skew, an inter-symbol interference (both dependent on type/length of cable), and a source clock jitter less than 250 ps which is calculated from T POS - RPOS (see Figure 11). Table 6: Receiver switching characteristics Symbol Parameter Min. Max. CLHT (1) CMOS/TTL low-to-high transition time (Figure 5) 3.5 CHLT (2) CMOS/TTL high-to-low transition time (Figure 5) 3.5 RSPos0 (2) Receiver input strobe position for bit 0 (Figure 10) 0.50 1.24 RSPos1 (2) Receiver input strobe position for bit 1 (Figure 10), f = 75 MHz 2.41 3.15 RSPos2 (2) Receiver input strobe position for bit 2 (Figure 10), f = 75 MHz 4.31 5.05 RSPos3 (2) Receiver input strobe position for bit 3 (Figure 10), f = 75 MHz 6.22 6.96 RSPos4 (2) Receiver input strobe position for bit 4 (Figure 10), f = 75 MHz 8.12 8.86 RSPos5 (2) Receiver input strobe position for bit 5 (Figure 10), f = 75 MHz 10.03 10.77 RSPos6 (2) Unit ns Receiver input strobe position for bit 6 (Figure 10), f = 75 MHz 11.93 12.67 RCOP (2) RxCLK OUT period (Figure 6), f = 75 MHz 13.3 66.7 RCOH (2) RxCLK OUT high time (Figure 6), f = 75 MHz 3.6 RCOL (2) RxCLK OUT low time (Figure 6), f = 75 MHz 3.6 RSRC (2) RxOUT setup to RxCLK OUT (Figure 6), f = 75 MHz 3.5 RHRC (3) RxOUT hold to RxCLK OUT (Figure 6), f = 75 MHz 3.5 RCCD (3) RxCLK IN to RxCLK OUT delay (Figure 7), f = 75 MHz 8.3 RPLLS (4) Receiver phase lock loop set (Figure 8), f = 75 MHz 10 ms Receiver powerdown delay (Figure 9) 2 µs RPDD Notes: (1) (2) Guaranteed by characterization. Guaranteed by design (3) Total latency for the channel link chip-set is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for LVDS217 serializer and the LVDS218 deserializer is (T + TCCD) + 2*T + RCCD), where T = clock period. (4) Tested functionally In powerdown, all CMOS/TTL and clock outputs are in high impedance 8/20 DocID029115 Rev 1 RHFLVDS218 Electrical characteristics Cold sparing The RHFLVDS218 features a cold spare input and output buffer. In high reliability applications, cold sparing enables a redundant device to be tied to the data bus with its power supply at 0 V (VCC = GND) without affecting the bus signals or injecting current from the I/Os to the power supplies. Cold sparing also allows redundant devices to be kept powered off so that they can be switched on only when required. This has no impact on the application. Cold sparing is achieved by implementing a high impedance between the I/Os and VCC. ESD protection is ensured through a non-conventional dedicated structure. Fail-safe In many applications, inputs need a fail-safe function to avoid an uncertain output state when the inputs are not connected properly. In case of an LVDS input short-circuit or floating inputs, the TTL outputs remain in a stable logic-high state. DocID029115 Rev 1 9/20 Radiations 6 RHFLVDS218 Radiations Total dose (MIL-STD-883 TM 1019) The products guaranteed in radiation within the RHA QML-V system fully comply with the MIL-STD-883 TM 1019 specification. The RHFLVDS218 is RHA QML-V, tested and characterized in full compliance with the MIL-STD-883 specification, between 50 and 300 rad/s only (full CMOS technology). All parameters provided in Table 5: "DC electrical characteristics" apply to both pre- and post-irradiation, as follows: All test are performed in accordance with MIL-PRF-38535 and test method 1019 of MIL-STD-883 for total ionizing dose (TID). The initial characterization is performed in qualification only on both biased and unbiased parts. Each wafer lot is tested at high dose rate only, in the worst bias case condition, based on the results obtained during the initial qualification. Heavy ions The behavior of the product when submitted to heavy ions is not tested in production. Heavy-ion trials are performed on qualification lots only. Table 7: Radiation Type TID Characteristics Value Unit High-dose rate (50 - 300 rad/sec) up to: 300 krad SEL immune up to: (with a particle angle of 60 ° at 125 °C) 120 Heavy ions MeV.cm²/mg SEL immune up to: (with a particle angle of 0 ° at 125 °C) 10/20 DocID029115 Rev 1 60 RHFLVDS218 7 Test circuit and AC timing diagrams Test circuit and AC timing diagrams Figure 4: Test pattern Figure 5: RHFLVDS218 output load and transition times Figure 6: RHFLVDS218 setup/hold and high/low times Figure 7: RHFLVDS218 clock-to-clock out delay DocID029115 Rev 1 11/20 Test circuit and AC timing diagrams RHFLVDS218 Figure 8: RHFLVDS218 phase-lock-loop set time Figure 9: RHFLVDS218 receiver powerdown delay 12/20 DocID029115 Rev 1 RHFLVDS218 Test circuit and AC timing diagrams Figure 10: RHFLVDS218 receiver input strobe position DocID029115 Rev 1 13/20 Test circuit and AC timing diagrams RHFLVDS218 Figure 11: RHFLVDS218 receiver skew margin 1. 2. 3. 4. 14/20 C: setup and hold time (internal data sampling window) defined by RSPosN (receiver input strobe position min and max TPPosN (transmitter output pulse position min and max). Cable skew: based on type and length, typically 10 ps - 40 ps per foot, media dependent Source clock jitter: cycle-to-cycle jitter is less than 250 ps at 75 MHz ISI: inter-symbol interference, dependent on interconnect length, may be zero DocID029115 Rev 1 RHFLVDS218 8 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. DocID029115 Rev 1 15/20 Package information 8.1 RHFLVDS218 Ceramic Flat-48 package information Figure 12: Ceramic Flat-48 package outline Pin 1 identifier 48 e (N-2 places) D b (N places) 24 25 S1 (4 places) L E L c A E3 Q 1. E2 f E3 The upper metallic lid is connected to pin 32. Table 8: Ceramic Flat-48 mechanical data mm inches Dim 16/20 Typ Min Max Typ Min Max A 2.47 2.18 2.72 0.097 0.086 0.107 b 0.254 0.20 0.30 0.010 0.008 0.012 c 0.15 0.12 0.18 0.006 0.005 0.007 D 15.75 15.57 15.92 0.620 0.613 0.627 E 9.65 9.52 9.78 0.380 0.375 0.385 E2 6.35 6.22 6.48 0.250 0.245 0.255 E3 1.65 1.52 1.78 0.065 0.060 0.070 e 0.635 0.025 f 0.20 0.008 L 8.38 6.85 9.40 0.330 0.270 0.370 Q 0.79 0.66 0.92 0.031 0.026 0.036 S1 0.43 0.25 0.61 0.017 0.010 0.024 DocID029115 Rev 1 RHFLVDS218 9 Ordering information Ordering information Table 9: Order codes Order code RHFLVDS218K1 Description Temp. range Package Engineering model -55 °C to 125 °C Flat-48 Marking (1) RHFLVDS218K1 Packing Strip pack Notes: (1) Specific marking only. Complete marking includes the following: - ST logo - Date code (date the package was sealed) in YYWWA (year, week, and lot index of week) - Country of origin (FR = France) Contact your ST sales office for information regarding the specific conditions for products in die form and QML-Q versions. DocID029115 Rev 1 17/20 Other information RHFLVDS218 10 Other information 10.1 Date code The date code is structured as follows: EM (engineering model) = xyywwz Where: x (EM only): 3, assembly location Rennes (France) yy: last two digits year ww: week digits z: lot index in the week 18/20 DocID029115 Rev 1 RHFLVDS218 11 Revision history Revision history Table 10: Document revision history Date Revision 08-Apr-2016 1 DocID029115 Rev 1 Changes Initial release 19/20 RHFLVDS218 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 20/20 DocID029115 Rev 1