10-Bit, 4× Oversampled SDTV Video Decoder with Deinterlacer ADV7280 Data Sheet FEATURES APPLICATIONS Worldwide NTSC/PAL/SECAM color demodulation support One 10-bit analog-to-digital converter (ADC), 4× oversampling per channel for CVBS, Y/C, and YPrPb modes Analog video input channels with on-chip antialiasing filter ADV7280: up to 4 input channels ADV7280-M: up to 8 input channels Video input support for CVBS (composite), Y/C (S-Video), and YPrPb (component) NTSC/PAL/SECAM autodetection Up to 1.47 V common-mode input range solution Excellent common-mode noise rejection capabilities 5-line adaptive 2D comb filter and CTI video enhancement Adaptive Digital Line Length Tracking (ADLLT), signal processing, and enhanced FIFO management provide mini-time base correction (TBC) functionality Integrated automatic gain control (AGC) with adaptive peak white mode Fast switching capability Integrated interlaced-to-progressive (I2P) video output converter Adaptive contrast enhancement (ACE) Down dither (8-bit to 6-bit) Rovi (Macrovision) copy protection detection MIPI CSI-2 output interface (ADV7280-M) 8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, or field synchronization (ADV7280) Full featured vertical blanking interval (VBI) data slicer Power-down mode available 2-wire, I2C-compatible serial interface Qualified for automotive applications −40°C to +105°C temperature grade 32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP Smartphone/multimedia handsets Automotive infotainment DVRs for video security Media players Rev. A GENERAL DESCRIPTION The ADV7280/ADV7280-M are versatile one-chip, multiformat video decoders. The ADV7280/ADV7280-M automatically detect standard analog baseband video signals compatible with worldwide NTSC, PAL, and SECAM standards in the form of composite, S-Video, and component video. The ADV7280 converts the analog video signals into a YCrCb 4:2:2 video data stream that is compatible with the 8-bit ITU-R BT.656 interface standard. The ADV7280-M converts the analog video signals into an 8-bit YCrCb 4:2:2 video data stream that is output over a mobile industry processor interface (MIPI®) CSI-2 interface. The analog video inputs of the ADV7280/ADV7280-M accept single-ended signals. The ADV7280 provides four analog inputs; the ADV7280-M provides eight analog inputs. The ADV7280 and ADV7280-M support I2P conversion. The ADV7280/ADV7280-M are programmed via a 2-wire, serial bidirectional port (I2C compatible) and are fabricated in a 1.8 V CMOS process. The LFCSP package option makes these decoders ideal for space-constrained portable applications. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADV7280 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power-Down Sequence .............................................................. 15 Applications ....................................................................................... 1 Universal Power Supply (ADV7280 Only) ............................. 15 General Description ......................................................................... 1 Input Network ................................................................................. 16 Revision History ............................................................................... 2 Input Configuration ....................................................................... 17 Functional Block Diagrams ............................................................. 3 Adaptive Contrast Enhancement (ACE) ..................................... 18 Specifications..................................................................................... 4 I2P Function.................................................................................... 19 Electrical Specifications ............................................................... 4 MIPI CSI-2 Output (ADV7280-M Only) ................................... 20 Video Specifications ..................................................................... 5 ITU-R BT.656 Tx Configuration (ADV7280 Only) .................. 21 Analog Specifications ................................................................... 6 I2C Port Description ....................................................................... 22 MIPI Video Output Specifications (ADV7280-M Only) ........ 6 Register Maps .............................................................................. 23 Pixel Port Timing Specifications (ADV7280 Only) ................. 8 PCB Layout Recommendations.................................................... 25 Clock and I C Timing Specifications ......................................... 9 Analog Interface Inputs ............................................................. 25 Absolute Maximum Ratings.......................................................... 10 Power Supply Decoupling ......................................................... 25 Thermal Resistance .................................................................... 10 VREFN and VREFP Pins .......................................................... 25 Reflow Solder .............................................................................. 10 Digital Outputs (INTRQ, GPO0 to GPO2) ............................ 25 ESD Caution ................................................................................ 10 Exposed Metal Pad ..................................................................... 25 Pin Configurations and Function Descriptions ......................... 11 Digital Inputs .............................................................................. 25 Theory of Operation ...................................................................... 13 Analog Front End (AFE) ........................................................... 13 MIPI Outputs for the ADV7280-M (D0P, D0N, CLKP, CLKN) ............................................................................. 25 Standard Definition Processor (SDP) ...................................... 14 Typical Circuit Connections ......................................................... 26 Power Supply Sequencing .............................................................. 15 Outline Dimensions ....................................................................... 28 Optimal Power-Up Sequence.................................................... 15 Ordering Guide .......................................................................... 28 Simplified Power-Up Sequence ................................................ 15 Automotive Products ................................................................. 28 2 REVISION HISTORY 2/14—Rev. 0 to Rev. A Change to Single-Ended CVBS Input Parameter, Analog Supply Current, Table 1 ................................................................................ 4 8/13—Revision 0: Initial Version Rev. A | Page 2 of 28 Data Sheet ADV7280 FUNCTIONAL BLOCK DIAGRAMS ADV7280 CLOCK PROCESSING BLOCK XTALP PLL ADLLT PROCESSING 10-BIT ADC DIGITAL PROCESSING BLOCK LLC XTALN 2D COMB + SHA AA FILTER VBI SLICER ADC – COLOR DEMOD AA FILTER I2P FIFO HS ACE DOWN DITHER I2C/CONTROL REFERENCE 8-BIT PIXEL DATA P7 TO P0 INTRQ 11634-001 AIN3 AIN4 AA FILTER VS/FIELD/SFL OUTPUT BLOCK ANALOG VIDEO INPUTS AA FILTER MUX BLOCK AIN1 AIN2 SCLK SDATA ALSB RESET PWRDWN Figure 1. ADV7280 Functional Block Diagram ADV7280-M CLKP CLOCK PROCESSING BLOCK XTALP PLL MIPI Tx ADLLT PROCESSING XTALN CLKN D0P AA FILTER 2D COMB + SHA AA FILTER DIGITAL PROCESSING BLOCK ADC – VBI SLICER COLOR DEMOD AA FILTER I2P ACE DOWN DITHER I2C/CONTROL REFERENCE SCLK SDATA ALSB RESET PWRDWN Figure 2. ADV7280-M Functional Block Diagram Rev. A | Page 3 of 28 GPO0 GPO1 GPO2 INTRQ 11634-002 MUX BLOCK ANALOG VIDEO INPUTS AA FILTER OUTPUT BLOCK 10-BIT ADC AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 FIFO D0N ADV7280 Data Sheet SPECIFICATIONS ELECTRICAL SPECIFICATIONS AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. MVDD applies to the ADV7280-M only. Table 1. Parameter STATIC PERFORMANCE ADC Resolution Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage Symbol Test Conditions/Comments N INL DNL CVBS mode CVBS mode VIH Input Low Voltage VIL Input Leakage Current IIN DVDDIO = 3.3 V DVDDIO = 1.8 V, ADV7280 only DVDDIO = 3.3 V DVDDIO = 1.8 V, ADV7280 only RESET pin SDATA, SCLK pins PWRDWN, ALSB pins Min −10 −10 −10 VIH VIL XTALN pin XTALN pin 1.2 VOH 2.4 1.4 Output Low Voltage VOL DVDDIO = 3.3 V, ISOURCE = 0.4 mA DVDDIO = 1.8 V, ISOURCE = 0.4 mA, ADV7280 only DVDDIO = 3.3 V, ISINK = 3.2 mA DVDDIO = 1.8 V, ISINK = 1.6 mA, ADV7280 only PLL Power Supply Analog Power Supply Digital Power Supply MIPI Tx Power Supply Digital I/O Supply Current PVDD AVDD DVDD MVDD IDVDDIO PLL Supply Current MIPI Tx Supply Current Analog Supply Current Single-Ended CVBS Input Y/C Input YPrPb Input Digital Supply Current Single-Ended CVBS Input Y/C Input YPrPb Input IPVDD IMVDD IAVDD ADV7280-M only ADV7280-M ADV7280 ADV7280-M only 10 Bits LSB LSB 2.97 1.62 1.71 1.71 1.71 1.71 0.8 0.4 +10 +15 +50 10 V V V V µA µA µA pF 0.4 V V V V ILEAK COUT ADV7280-M ADV7280 Unit 2 1.2 CIN DVDDIO Max 2 ±0.6 Input Capacitance CRYSTAL INPUT Input High Voltage Input Low Voltage DIGITAL OUTPUTS Output High Voltage High Impedance Leakage Current Output Capacitance POWER REQUIREMENTS 1, 2, 3 Digital I/O Power Supply Typ 3.3 3.3 1.8 1.8 1.8 1.8 1.5 5 12 14 0.4 0.2 V V 10 20 µA pF 3.63 3.63 1.89 1.89 1.89 1.89 V V V V V V mA mA mA mA 47 60 75 mA mA mA 70 70 70 mA mA mA IDVDD Rev. A | Page 4 of 28 Data Sheet Parameter POWER-DOWN CURRENTS1 Digital I/O Supply Power-Down Current PLL Supply Power-Down Current Analog Supply Power-Down Current Digital Supply Power-Down Current MIPI Tx Supply Power-Down Current Total Power Dissipation in Power-Down Mode ADV7280 Symbol Test Conditions/Comments IDVDDIO_PD DVDDIO = 3.3 V, ADV7280-M DVDDIO = 3.3 V, ADV7280 IPVDD_PD IAVDD_PD IDVDD_PD IMVDD_PD Min Typ Max 73 84 46 0.2 420 4.5 1 ADV7280-M only Unit µA µA µA µA µA µA mW Guaranteed by characterization. Typical current consumption values are measured with nominal voltage supply levels and an SMPTE bar test pattern. 3 All specifications apply when the I2P core is activated, unless otherwise stated. 1 2 VIDEO SPECIFICATIONS AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Specifications guaranteed by characterization. MVDD applies to the ADV7280-M only. Table 2. Parameter NONLINEAR SPECIFICATIONS 1 Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS Signal-to-Noise Ratio, Unweighted Analog Front-End Crosstalk Common-Mode Rejection Ratio 2 LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range fSC Subcarrier Lock Range Color Lock-In Time Synchronization Depth Range Color Burst Range Vertical Lock Time Autodetection Switch Speed 3 Fast Switch Speed 4 LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy Symbol Test Conditions/Comments Min DP DG LNL CVBS input, modulated 5-step CVBS input, modulated 5-step CVBS input, 5-step 0.9 0.5 2.0 Degrees % % SNR Luma ramp Luma flat field 57.1 58 60 73 dB dB dB dB CMRR Typ −5 40 Max +5 70 Unit 2 100 100 % Hz kHz Lines % % Fields Lines ms 1 1 % % ±1.3 60 20 5 200 200 CVBS, 1 V input These specifications apply for all CVBS input types (NTSC, PAL, and SECAM). The CMRR of this circuit design is critically dependent on the external resistor matching on the circuit inputs (see the Input Network section). The CMRR measurement was performed with 0.1% tolerant resistors, a common-mode voltage of 1 V, and a common-mode frequency of 10 kHz. 3 Autodetection switch speed is the time required for the ADV7280/ADV7280-M to detect which video format is present at its input, for example, PAL I or NTSC M. 4 Fast switch speed is the time required for the ADV7280/ADV7280-M to switch from one analog input to another, for example, switching from AIN1 to AIN2. 1 2 Rev. A | Page 5 of 28 ADV7280 Data Sheet ANALOG SPECIFICATIONS AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Specifications guaranteed by characterization. MVDD applies to the ADV7280-M only. Table 3. Parameter CLAMP CIRCUITRY External Clamp Capacitor Input Impedance Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current Test Conditions/Comments Min Clamps switched off Typ Max 0.1 10 0.4 0.4 10 10 Unit µF MΩ mA mA µA µA MIPI VIDEO OUTPUT SPECIFICATIONS (ADV7280-M ONLY) AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. The CSI-2 clock lane of the ADV7280-M remains in high speed (HS) mode even when the data lane enters low power (LP) mode. For this reason, some measurements on the clock lane that pertain to low power mode are not applicable. Unless otherwise stated, all high speed measurements were performed with the ADV7280-M operating in progressive mode and with a nominal 432 Mbps output data rate. Specifications guaranteed by characterization. Table 4. Parameter UNIT INTERVAL Interlaced Output Progressive Output DATA LANE LP TX DC SPECIFICATIONS 1 Thevenin Output High Level Thevenin Output Low Level DATA LANE LP TX AC SPECIFICATIONS1 Rise Time, 15% to 85% Fall Time, 85% to 15% Rise Time, 30% to 85% Data Lane LP Slew Rate vs. CLOAD Maximum Slew Rate over Entire Vertical Edge Region Symbol UI Min Typ Max 4.63 2.31 VOH VOL Minimum Slew Rate 400 mV ≤ VOUT ≤ 930 mV 400 mV ≤ VOUT ≤ 700 mV 700 mV ≤ VOUT ≤ 930 mV Pulse Width of LP Exclusive-OR Clock Period of LP Exclusive-OR Clock CLOCK LANE LP TX DC SPECIFICATIONS1 Thevenin Output High Level Thevenin Output Low Level CLOCK LANE LP TX AC SPECIFICATIONS1 Rise Time, 15% to 85% Fall Time, 85% to 15% Test Conditions/Comments 1.1 −50 ns ns 1.3 +50 V mV 25 25 35 ns ns ns Rising edge 150 mV/ns Falling edge 150 mV/ns Falling edge Rising edge Rising edge First clock pulse after stop state or last pulse before stop state All other clock pulses VOH VOL 30 30 >0 40 mV/ns mV/ns mV/ns ns 20 90 ns ns 1.1 −50 Rev. A | Page 6 of 28 1.2 0 Unit 1.2 0 1.3 +50 V mV 25 25 ns ns Data Sheet Parameter Clock Lane LP Slew Rate Maximum Slew Rate over Entire Vertical Edge Region Minimum Slew Rate 400 mV ≤ VOUT ≤ 930 mV 400 mV ≤ VOUT ≤ 700 mV 700 mV ≤ VOUT ≤ 930 mV DATA LANE HS TX SIGNALING REQUIREMENTS Low Power to High Speed Transition Stage ADV7280 Symbol t9 t10 High Speed Differential Voltage Swing Differential Voltage Mismatch Single-Ended Output High Voltages Static Common-Mode Voltage Level Static Common-Mode Voltage Mismatch Dynamic Common Level Variations 50 MHz to 450 MHz Above 450 MHz Rise Time, 20% to 80% Fall Time, 80% to 20% High Speed to Low Power Transition Stage t11 |V1| t12 t14 t15 High Speed Differential Voltage Swing Differential Voltage Mismatch Single-Ended Output High Voltages Static Common-Mode Voltage Level Static Common-Mode Voltage Mismatch Dynamic Common Level Variations 50 MHz to 450 MHz Above 450 MHz Rise Time, 20% to 80% Fall Time, 80% to 20% Min Max Unit Rising edge 150 mV/ns Falling edge 150 mV/ns t9 Typ Falling edge Rising edge Rising edge See Figure 3 30 30 >0 mV/ns mV/ns mV/ns Time that the D0P pin is at VOL and the D0N pin is at VOH Time that the D0P and D0N pins are at VOL t10 plus the HS-zero period 50 ns 40 + (4 × UI) 145 + (10 × UI) 140 200 150 t13 CLOCK LANE HS TX SIGNALING REQUIREMENTS Low Power to High Speed Transition Stage 2 Test Conditions/Comments Time that the ADV7280-M drives the flipped last data bit after sending the last payload data bit of an HS transmission burst Post-end-of-transmission rise time (30% to 85%) Time from start of t12 to start of low power state following an HS transmission burst Time that a low power state is transmitted after an HS transmission burst See Figure 3 Time that the CLKP pin is at VOL and the CLKN pin is at VOH Time that the CLKP and CLKN pins are at VOL Clock HS-zero period |V2| 0.15 0.15 60 + (4 × UI) ns 270 10 360 250 5 ns mV p-p mV mV mV mV 25 15 0.3 × UI 0.3 × UI mV mV ns ns ns 35 ns 105 + (12 × UI) 100 50 ns ns ns 38 300 140 500 200 150 200 0.15 0.15 Rev. A | Page 7 of 28 200 85 + (6 × UI) 95 ns 270 10 360 250 5 ns mV p-p mV mV mV mV 25 15 0.3 × UI 0.3 × UI mV mV ns ns ADV7280 Data Sheet Parameter HS TX CLOCK TO DATA LANE TIMING REQUIREMENTS Data to Clock Skew 1 2 Symbol Test Conditions/Comments Min Typ 0.35 × UI Max Unit 0.65 × UI ns These measurements were performed with CLOAD = 50 pF. The clock lane remains in high speed mode throughout normal operation. These results apply only to the ADV7280-M during startup. |V2| CLKP/CLKN D0P/D0N t10 t9 t11 VOH |V1| VOL t13 TRANSMIT FIRST DATA BIT LOW POWER TO HIGH SPEED TRANSITION HS-ZERO START OF TRANSMISSION SEQUENCE HIGH SPEED DATA TRANSMISSION t15 HS-TRAIL HIGH SPEED TO LOW POWER TRANSITION 11634-005 t14 t12 Figure 3. ADV7280-M Output Timing Diagram (Conforms with MIPI CSI-2 Specification) PIXEL PORT TIMING SPECIFICATIONS (ADV7280 ONLY) AVDD, DVDD, and PVDD = 1.71 V to 1.89 V, DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Specifications guaranteed by characterization. Table 5. Parameter CLOCK OUTPUTS LLC Mark Space Ratio DATA AND CONTROL OUTPUTS Data Output Transitional Time Symbol Test Conditions/Comments Min t9:t10 Typ 45:55 t11 Negative clock edge to start of valid data (tSETUP = t10 − t11) End of valid data to negative clock edge (tHOLD = t9 − t12) t12 t9 t10 OUTPUT LLC t11 11634-004 t12 OUTPUTS P0 TO P7, HS, VS/FIELD/SFL Figure 4. ADV7280 Pixel Port and Control Output Timing Diagram Rev. A | Page 8 of 28 Max Unit 55:45 % duty cycle 3.8 ns 6.9 ns Data Sheet ADV7280 CLOCK AND I2C TIMING SPECIFICATIONS AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Specifications guaranteed by characterization. MVDD applies to the ADV7280-M only. Table 6. Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability I2C PORT SCLK Frequency SCLK Minimum Pulse Width High SCLK Minimum Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDATA Setup Time SCLK and SDATA Rise Times SCLK and SDATA Fall Times Setup Time (Stop Condition) RESET INPUT RESET Pulse Width Symbol Min Typ Max Unit ±50 MHz ppm 28.63636 400 t1 t2 t3 t4 t5 t6 t7 t8 kHz µs µs µs µs ns ns ns µs 0.6 1.3 0.6 0.6 100 300 300 0.6 5 ms t3 t5 t3 SDATA t2 t4 t7 2 Figure 5. I C Timing Diagram Rev. A | Page 9 of 28 t8 11634-003 t1 t6 SCLK ADV7280 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 7. Parameter AVDD to DGND DVDD to DGND PVDD to DGND MVDD to DGND1 DVDDIO to DGND PVDD to DVDD MVDD to DVDD1 AVDD to DVDD Digital Inputs Voltage Digital Outputs Voltage Analog Inputs to Ground Maximum Junction Temperature (TJ max) Storage Temperature Range Infrared Reflow Soldering (20 sec) 1 Rating 2.2 V 2.2 V 2.2 V 2.2 V 4V −0.9 V to +0.9 V −0.9 V to +0.9 V −0.9 V to +0.9 V DGND − 0.3 V to DVDDIO + 0.3 V DGND − 0.3 V to DVDDIO + 0.3 V Ground − 0.3 V to AVDD + 0.3 V 140°C −65°C to +150°C 260°C MVDD applies to the ADV7280-M only. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. These devices are high performance integrated circuits with an ESD rating of <2 kV, and they are ESD sensitive. Proper precautions must be taken for handling and assembly. The thermal resistance values in Table 8 are specified for the device soldered onto a 4-layer printed circuit board (PCB) with a common ground plane and with the exposed pad of the device connected to DGND. The values in Table 8 are maximum values. Table 8. Thermal Resistance for the 32-Lead LFCSP Thermal Characteristic Junction-to-Ambient Thermal Resistance (Still Air) Junction-to-Case Thermal Resistance Symbol θJA Value 32.5 Unit °C/W θJC 2.3 °C/W REFLOW SOLDER The ADV7280/ADV7280-M are Pb-free, environmentally friendly products. They are manufactured using the most up-todate materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The devices are suitable for Pb-free applications and can withstand surface-mount soldering at up to 255°C (±5°C). In addition, the ADV7280/ADV7280-M are backwardcompatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220°C to 235°C. ESD CAUTION Rev. A | Page 10 of 28 Data Sheet ADV7280 32 31 30 29 28 27 26 25 LLC PWRDWN HS VS/FIELD/SFL SCLK SDATA ALSB RESET PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADV7280 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 INTRQ AIN4 AIN3 AVDD VREFN VREFP AIN2 AIN1 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO DGND. 11634-006 1 2 3 4 5 6 7 8 P3 9 P2 10 P1 11 P0 12 DVDD 13 XTALP 14 XTALN 15 PVDD 16 DGND DVDDIO DVDD DGND P7 P6 P5 P4 Figure 6. Pin Configuration, ADV7280 Table 9. Pin Function Descriptions, ADV7280 Pin No. 1, 4 2 3, 13 5 to 12 14 Mnemonic DGND DVDDIO DVDD P7 to P0 XTALP Type Ground Power Power Output Output 15 XTALN Input 16 17, 18, 22, 23 19 20 21 24 PVDD AIN1 to AIN4 Power Input VREFP VREFN AVDD INTRQ Output Output Power Output 25 RESET Input 26 ALSB Input 27 28 29 SDATA SCLK VS/FIELD/SFL Input/output Input Output 30 31 32 HS PWRDWN LLC Output Input Output EPAD (EP) Description Ground for Digital Supply. Digital I/O Power Supply (1.8 V or 3.3 V). Digital Power Supply (1.8 V). Video Pixel Output Ports. Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external 1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7280. The crystal used with the ADV7280 must be a fundamental crystal. Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7280 must be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7280, the output of the oscillator is fed into the XTALN pin. PLL Power Supply (1.8 V). Analog Video Input Channels. Internal Voltage Reference Output. Internal Voltage Reference Output. Analog Power Supply (1.8 V). Interrupt Request Output. An interrupt occurs when certain signals are detected on the input video. System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to reset the ADV7280 circuitry. This pin selects the I2C write address for the ADV7280. When ALSB is set to Logic 0, the write address is 0x40; when ALSB is set to Logic 1, the write address is 0x42. I2C Port Serial Data Input/Output. I2C Port Serial Clock Input. The maximum clock rate is 400 kHz. Vertical Synchronization Output Signal/Field Synchronization Output Signal/Subcarrier Frequency Lock. When configured for the SFL function, this pin provides a serial output stream that can be used to lock the subcarrier frequency when the ADV7280 decoder is connected to any Analog Devices, Inc., digital video encoder. Horizontal Synchronization Output Signal. Power-Down Pin. A logic low on this pin places the ADV7280 in power-down mode. Line-Locked Output Clock for Output Pixel Data. The clock output is nominally 27 MHz, but it increases or decreases according to the video line length. Exposed Pad. The exposed pad must be connected to DGND. Rev. A | Page 11 of 28 Data Sheet 32 31 30 29 28 27 26 25 PWRDWN SCLK SDATA ALSB RESET AIN8 AIN7 AIN6 ADV7280 1 2 3 4 5 6 7 8 ADV7280-M TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 AIN5 AIN4 AIN3 AVDD VREFN VREFP AIN2 AIN1 NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO DGND. 11634-007 D0P D0N CLKP CLKN MVDD XTALP XTALN PVDD 9 10 11 12 13 14 15 16 DGND DVDDIO DVDD DGND INTRQ GPO2 GPO1 GPO0 Figure 7. Pin Configuration, ADV7280-M Table 10. Pin Function Descriptions, ADV7280-M Pin No. 1, 4 2 3 5 Mnemonic DGND DVDDIO DVDD INTRQ Type Ground Power Power Output 6 to 8 Output 9 10 11 12 13 14 GPO2 to GPO0 D0P D0N CLKP CLKN MVDD XTALP Output Output Output Output Power Output 15 XTALN Input 16 17, 18, 22, 23, 24, 25, 26, 27 19 20 21 28 PVDD AIN1 to AIN8 Power Input VREFP VREFN AVDD RESET Output Output Power Input 29 ALSB Input 30 31 32 SDATA SCLK PWRDWN EPAD (EP) Input/output Input Input Description Ground for Digital Supply. Digital I/O Power Supply (3.3 V). Digital Power Supply (1.8 V). Interrupt Request Output. An interrupt occurs when certain signals are detected on the input video. General-Purpose Outputs. These pins can be configured via I2C to allow control of external devices. Positive MIPI Differential Data Output. Negative MIPI Differential Data Output. Positive MIPI Differential Clock Output. Negative MIPI Differential Clock Output. MIPI Digital Power Supply (1.8 V). Connect this pin to the external 28.63636 MHz crystal, or leave it unconnected if an external 1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7280-M. The crystal used with the ADV7280-M must be a fundamental crystal. Input Pin for the External 28.63636 MHz Crystal. The crystal used with the ADV7280-M must be a fundamental crystal. If an external 1.8 V, 28.63636 MHz clock oscillator source is used to clock the ADV7280-M, the output of the oscillator is fed into the XTALN pin. PLL Power Supply (1.8 V). Analog Video Input Channels. Internal Voltage Reference Output. Internal Voltage Reference Output. Analog Power Supply (1.8 V). System Reset Input (Active Low). A minimum low reset pulse width of 5 ms is required to reset the ADV7280-M circuitry. This pin selects the I2C write address for the ADV7280-M. When ALSB is set to Logic 0, the write address is 0x40; when ALSB is set to Logic 1, the write address is 0x42. I2C Port Serial Data Input/Output. I2C Port Serial Clock Input. The maximum clock rate is 400 kHz. Power-Down Pin. A logic low on this pin places the ADV7280-M in power-down mode. Exposed Pad. The exposed pad must be connected to DGND. Rev. A | Page 12 of 28 Data Sheet ADV7280 THEORY OF OPERATION The ADV7280/ADV7280-M are versatile one-chip, multiformat video decoders. The ADV7280/ADV7280-M automatically detect standard analog baseband video signals compatible with worldwide NTSC, PAL, and SECAM standards in the form of composite, S-Video, and component video. The ADV7280 converts the analog video signals into an 8-bit YCrCb 4:2:2 component video data stream that is compatible with the ITU-R BT.656 interface standard. The ADV7280-M converts the analog video signals into an 8-bit YCrCb 4:2:2 video data stream that is output over a MIPI CSI-2 interface. The MIPI CSI-2 output interface connects to a wide range of video processors and FPGAs. The ADV7280/ADV7280-M accept composite video signals, as well as S-Video and YPbPr video signals, supporting a wide range of consumer and automotive video sources. The accurate 10-bit analog-to-digital conversion provides professional quality video performance for consumer applications with true 8-bit data resolution. The advanced interlaced-to-progressive (I2P) function allows the ADV7280/ADV7280-M to convert an interlaced video input into a progressive video output. This function is performed without the need for external memory. The ADV7280/ADV7280-M use edge adaptive technology to minimize video defects on low angle lines. The automatic gain control (AGC) and clamp restore circuitry allows an input video signal peak-to-peak range of 0 V to 1.0 V at the analog video input pins of the ADV7280/ADV7280-M. Alternatively, the AGC and clamp restore circuitry can be bypassed for manual settings. ANALOG FRONT END (AFE) The analog front end (AFE) of the ADV7280/ADV7280-M comprises a single high speed, 10-bit ADC that digitizes the analog video signal before applying it to the standard definition processor (SDP). The AFE also includes an input mux that enables multiple video signals to be applied to the ADV7280/ADV7280-M. The input mux allows up to four composite video signals to be applied to the ADV7280 and up to eight composite video signals to be applied to the ADV7280-M. Current clamps are positioned in front of the ADC to ensure that the video signal remains within the range of the converter. A resistor divider network is required before each analog input channel to ensure that the input signal is kept within the range of the ADC (see the Input Network section). Fine clamping of the video signal is performed downstream by digital fine clamping within the ADV7280/ADV7280-M. Table 11 lists the three ADC clock rates that are determined by the video input format to be processed. These clock rates ensure 4× oversampling per channel for CVBS, Y/C, and YPrPb modes. Table 11. ADC Clock Rates Input Format CVBS Y/C (S-Video) YPrPb 1 ADC Clock Rate (MHz)1 57.27 114 172 Oversampling Rate per Channel 4× 4× 4× Based on a 28.63636 MHz crystal between the XTALP and XTALN pins. The ADV7280/ADV7280-M support a number of other functions, including 8-bit to 6-bit down dither mode and adaptive contrast enhancement (ACE). The ADV7280/ADV7280-M are programmed via a 2-wire, serial bidirectional port (I2C compatible) and are fabricated in a 1.8 V CMOS process. The monolithic CMOS construction of the ADV7280/ADV7280-M ensures greater functionality with lower power dissipation. The LFCSP package option makes these decoders ideal for space-constrained portable applications. Rev. A | Page 13 of 28 ADV7280 Data Sheet STANDARD DEFINITION PROCESSOR (SDP) The ADV7280/ADV7280-M are capable of decoding a large selection of baseband video signals in composite, S-Video, and component formats. The video standards supported by the video processor include • • • PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N, PAL Nc, PAL 60 NTSC J, NTSC M, NTSC 4.43 SECAM B, SECAM D, SECAM G, SECAM K, SECAM L Using the standard definition processor (SDP), the ADV7280/ ADV7280-M can automatically detect the video standard and process it accordingly. The ADV7280/ADV7280-M have a five-line adaptive 2D comb filter that provides superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality without user intervention. Video user controls such as brightness, contrast, saturation, and hue are also available with the ADV7280/ADV7280-M. Adaptive contrast enhancement (ACE) offers improved visual detail using an algorithm that automatically varies contrast levels to enhance picture detail. ACE increases the contrast in dark areas of an image without saturating the bright areas of the image. This feature is particularly useful in automotive applications, where it can be important to discern objects in shaded areas. Down dithering converts the output of the ADV7280/ADV7280-M from an 8-bit to a 6-bit output, enabling ease of design for standard LCD panels. The I2P block converts the interlaced video input into a progressive video output without the need for external memory. The SDP can process a variety of VBI data services, such as closed captioning (CCAP), wide screen signaling (WSS), and copy generation management system (CGMS). VBI data is transmitted as ancillary data packets. The ADV7280/ADV7280-M are fully Rovi® (Macrovision®) compliant; detection circuitry enables Type I, Type II, and Type III protection levels to be identified and reported to the user. The decoders are also fully robust to all Macrovision signal inputs. The ADV7280/ADV7280-M implement the patented Adaptive Digital Line Length Tracking (ADLLT™) algorithm to track varying video line lengths from sources such as VCRs. ADLLT enables the ADV7280/ADV7280-M to track and decode poor quality video sources such as VCRs and noisy sources from tuner outputs and camcorders. The ADV7280/ADV7280-M contain a chroma transient improvement (CTI) processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions. Rev. A | Page 14 of 28 Data Sheet ADV7280 POWER SUPPLY SEQUENCING OPTIMAL POWER-UP SEQUENCE The optimal power-up sequence for the ADV7280/ADV7280-M is to first power up the 3.3 V DVDDIO supply, followed by the 1.8 V supplies: DVDD, PVDD, AVDD, and MVDD (for the ADV7280-M). When powering up the ADV7280/ADV7280-M, follow these steps. During power-up, all supplies must adhere to the specifications listed in the Absolute Maximum Ratings section. 5. 6. Assert the PWRDWN and RESET pins (pull the pins low). Power up the DVDDIO supply. After DVDDIO is fully asserted, power up the 1.8 V supplies. After the 1.8 V supplies are fully asserted, pull the PWRDWN pin high. Wait 5 ms and then pull the RESET pin high. After all power supplies and the PWRDWN and RESET pins are powered up and stable, wait an additional 5 ms before initiating I2C communication with the ADV7280/ ADV7280-M. SIMPLIFIED POWER-UP SEQUENCE Alternatively, the ADV7280/ADV7280-M can be powered up by asserting all supplies and the PWRDWN and RESET pins simultaneously. After this operation, perform a software reset, then wait 10 ms before initiating I2C communication with the ADV7280/ADV7280-M. VOLTAGE 3.3V 1.8V 3.3V SUPPLY POWER-DOWN SEQUENCE The ADV7280/ADV7280-M supplies can be deasserted simultaneously as long as DVDDIO does not go below a lower rated supply. UNIVERSAL POWER SUPPLY (ADV7280 ONLY) The ADV7280-M model requires a DVDDIO supply at a nominal value of 3.3 V. The ADV7280 model, however, can operate with a DVDDIO supply at a nominal value of 1.8 V. Therefore, it is possible to power up all the supplies for the ADV7280 (DVDD, PVDD, AVDD, and DVDDIO) to 1.8 V. When DVDDIO is at a nominal value of 1.8 V, power up the ADV7280 as follows: 1. 2. 3. Follow the power-up sequence described in the Optimal Power-Up Sequence section, but power up the DVDDIO supply to 1.8 V instead of 3.3 V. Also, power up the PWRDWN and RESET pins to 1.8 V instead of 3.3 V. Set the drive strengths of the digital outputs of the ADV7280 to their maximum setting. Connect any pull-up resistors connected to pins on the ADV7280 (such as the SCLK and SDATA pins) to 1.8 V instead of 3.3 V. PWRDWN PIN 1.8V SUPPLIES PWRDWN PIN POWER-UP 3.3V SUPPLY POWER-UP RESET PIN 1.8V SUPPLIES POWER-UP RESET PIN POWER-UP 5ms RESET OPERATION Figure 8. Optimal Power-Up Sequence Rev. A | Page 15 of 28 5ms WAIT TIME 11634-008 1. 2. 3. 4. While the supplies are being established, care must be taken to ensure that a lower rated supply does not go above a higher rated supply level. During power-up, all supplies must adhere to the specifications listed in the Absolute Maximum Ratings section. ADV7280 Data Sheet INPUT NETWORK An input network (external resistor and capacitor circuit) is required on the AINx input pins of the decoder. Figure 9 shows the input network to use on each AINx input pin of the ADV7280/ADV7280-M when any of the following video input formats is used: Single-ended CVBS YC (S-Video) YPrPb INPUT CONNECTOR VIDEO INPUT FROM SOURCE EXT ESD 24Ω 100nF AIN1 OF ADV7280 51Ω Figure 9. Input Network 11634-009 • • • The 24 Ω and 51 Ω resistors supply the 75 Ω end termination required for the analog video input. These resistors also create a resistor divider with a gain of 0.68. The resistor divider attenuates the amplitude of the input analog video and scales the input to the ADC range of the ADV7280/ADV7280-M. This allows an input range to the ADV7280/ADV7280-M of up to 1.47 V p-to-p. Note that amplifiers within the ADC restore the amplitude of the input signal so that signal-to-noise ratio (SNR) performance is maintained. The 100 nF ac coupling capacitor removes the dc bias of the analog input video before it is fed into the AINx pin of the ADV7280/ ADV7280-M. The clamping circuitry within the ADV7280/ ADV7280-M restores the dc bias of the input signal to the optimal level before it is fed into the ADC of the ADV7280/ADV7280-M. Rev. A | Page 16 of 28 Data Sheet ADV7280 INPUT CONFIGURATION The input format of the ADV7280/ADV7280-M is specified using the INSEL[4:0] bits (see Table 12). These bits also configure the SDP core to process CVBS, Y/C (S-Video), or component (YPrPb) format. The INSEL[4:0] bits are located in the user sub map of the register space at Address 0x00[4:0]. For more information about the registers, see the Register Maps section. The INSEL[4:0] bits specify predefined analog input routing schemes, eliminating the need for manual mux programming and allowing the user to route the various video signal types to the decoder. For example, if the CVBS input is selected, the remaining channels are powered down. Table 12. Input Format Specified by the INSEL[4:0] Bits INSEL[4:0] Bit Value 00000 00001 00010 00011 00100 00101 00110 00111 01000 Video Format CVBS CVBS CVBS CVBS CVBS CVBS CVBS CVBS Y/C (S-Video) 01001 Y/C (S-Video) 01010 Y/C (S-Video) ADV7280 CVBS input on AIN1 CVBS input on AIN2 CVBS input on AIN3 CVBS input on AIN4 Reserved Reserved Reserved Reserved Y input on AIN1; C input on AIN2 Y input on AIN3; C input on AIN4 Reserved 01011 Y/C (S-Video) Reserved 01100 YPrPb 01101 YPrPb Y input on AIN1; Pb input on AIN2; Pr input on AIN3 Reserved 01110 to 11111 Reserved Reserved Analog Inputs ADV7280-M CVBS input on AIN1 CVBS input on AIN2 CVBS input on AIN3 CVBS input on AIN4 CVBS input on AIN5 CVBS input on AIN6 CVBS input on AIN7 CVBS input on AIN8 Y input on AIN1; C input on AIN2 Y input on AIN3; C input on AIN4 Y input on AIN5; C input on AIN6 Y input on AIN7; C input on AIN8 Y input on AIN1; Pb input on AIN2; Pr input on AIN3 Y input on AIN4; Pb input on AIN5; Pr input on AIN6 Reserved Rev. A | Page 17 of 28 ADV7280 Data Sheet ADAPTIVE CONTRAST ENHANCEMENT (ACE) The ADV7280/ADV7280-M can increase the contrast of an image depending on the content of the picture, allowing bright areas to be made brighter and dark areas to be made darker. The optional ACE feature enables the contrast within dark areas to be increased without significantly affecting the bright areas. The ACE feature is particularly useful in automotive applications, where it can be important to discern objects in shaded areas. The ACE function is disabled by default. To enable the ACE function, execute the register writes shown in Table 13. To disable the ACE function, execute the register writes shown in Table 14. Table 13. Register Writes to Enable the ACE Function Register Map User Sub Map (0x40 or 0x42) User Sub Map 2 (0x40 or 0x42) User Sub Map 2 (0x40 or 0x42) Register Address 0x0E 0x80 0x0E Register Write 0x40 0x80 0x00 Description Enter User Sub Map 2 Enable ACE Reenter user sub map Register Write 0x40 0x00 0x00 Description Enter User Sub Map 2 Disable ACE Reenter user sub map Table 14. Register Writes to Disable the ACE Function Register Map User Sub Map (0x40 or 0x42) User Sub Map 2 (0x40 or 0x42) User Sub Map 2 (0x40 or 0x42) Register Address 0x0E 0x80 0x0E Rev. A | Page 18 of 28 Data Sheet ADV7280 I2P FUNCTION The advanced interlaced-to-progressive (I2P) function allows the ADV7280/ADV7280-M to convert an interlaced video input into a progressive video output. This function is performed without the need for external memory. The ADV7280/ADV7280-M use edge adaptive technology to minimize video defects on low angle lines. The I2P function is disabled by default. To enable the I2P function, use the recommended scripts from Analog Devices. Rev. A | Page 19 of 28 ADV7280 Data Sheet MIPI CSI-2 OUTPUT (ADV7280-M ONLY) The decoder in the ADV7280-M outputs an ITU-R BT.656 data stream. The ITU-R BT.656 data stream is connected into a CSI-2 Tx module. Data from the CSI-2 Tx module is fed into a D-PHY physical layer and output serially from the device. The clock lanes are used to clock the output video. After the ADV7280-M is programmed, the clock lanes exit low power mode and remain in high speed mode until the part is reset or powered down. The output of the ADV7280-M consists of a single data channel on the D0P and D0N lanes and a clock channel on the CLKP and CLKN lanes. The ADV7280-M outputs video data in an 8-bit YCrCb 4:2:2 format. When the I2P core is disabled, the video data is output in an interlaced format at a nominal data rate of 216 Mbps. When the I2P core is enabled, the video data is output in a progressive format at a nominal data rate of 432 Mbps (see the I2P Function section for more information). Video data is output over the data lanes in high speed mode. The data lanes enter low power mode during the horizontal and vertical blanking periods. D0P (1 BIT) CSI Tx DATA OUTPUT (8 BITS) VIDEO DECODER ITU-R BT.656 DATA STREAM CSI-2 Tx DATA LANE LP SIGNALS (2 BITS) D0N (1 BIT) D-PHY Tx CLOCK LANE LP SIGNALS (2 BITS) CLKP (1 BIT) CLKN (1 BIT) 11634-011 ANALOG VIDEO INPUT Figure 10. MIPI CSI-2 Output Stage of the ADV7280-M Rev. A | Page 20 of 28 Data Sheet ADV7280 ITU-R BT.656 Tx CONFIGURATION (ADV7280 ONLY) The ADV7280 receives analog video and outputs digital video according to the ITU-R BT.656 specification. The ADV7280 outputs the ITU-R BT.656 video data stream over the P0 to P7 data pins and has a line-locked clock (LLC) pin and two synchronization pins (HS and VS/FIELD/SFL). Video data is output over the P0 to P7 pins in YCrCb 4:2:2 format. Synchronization signals are automatically embedded in the video data signal in accordance with the ITU-R BT.656 specification. VIDEO DECODER The LLC output is used to clock the output data on the P0 to P7 pins at a nominal frequency of 27 MHz. The two synchronization pins (HS and VS/FIELD/SFL) output a variety of synchronization signals such as horizontal sync, vertical sync, field sync, and color subcarrier frequency lock (SFL) sync. The majority of these synchronization signals are already embedded in the video data. Therefore, the use of the synchronization pins is optional. ADV7280 P0 P1 P2 P3 ANALOG FRONT END STANDARD DEFINITION PROCESSOR P4 P5 P6 P7 LLC HS (OPTIONAL) VS/FIELD/SFL (OPTIONAL) Figure 11. ITU-R BT.656 Output Stage of the ADV7280 Rev. A | Page 21 of 28 11634-018 ANALOG VIDEO INPUT ITU-R BT.656 DATA STREAM ADV7280 Data Sheet I2C PORT DESCRIPTION 4. The ADV7280/ADV7280-M support a 2-wire, I2C-compatible serial interface. Two inputs, serial data (SDATA) and serial clock (SCLK), carry information between the ADV7280/ADV7280-M and the system I2C master controller. The I2C port of the ADV7280/ADV7280-M allows the user to set up and configure the decoder and to read back captured VBI data. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means that the master writes information to the peripheral. Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADV7280/ADV7280-M have a number of possible I2C slave addresses and subaddresses (see the Register Maps section). The main map of the ADV7280/ADV7280-M has four possible slave addresses for read and write operations, depending on the logic level of the ALSB pin (see Table 15). The ADV7280/ADV7280-M act as standard I2C slave devices on the bus. The data on the SDATA pin is eight bits long, supporting the 7-bit address plus the R/W bit. The device has subaddresses to enable access to the internal registers; therefore, it interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses auto-increment, allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register individually without updating all the registers. Table 15. Main Map I2C Address for the ADV7280/ADV7280-M R/W Bit 0 1 0 1 Slave Address 0x40 (write) 0x41 (read) 0x42 (write) 0x43 (read) The ALSB pin controls Bit 1 of the slave address. By changing the logic level of the ALSB pin, it is possible to control two ADV7280/ADV7280-M devices in an application without using the same I2C slave address. The LSB (Bit 0) specifies either a read or write operation: Logic 1 corresponds to a read operation, and Logic 0 corresponds to a write operation. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCLK high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7280/ADV7280-M do not issue an acknowledge and return to the idle condition. To control the device on the bus, a specific protocol is followed. 2. 3. The master initiates a data transfer by establishing a start condition, which is defined as a high to low transition on SDATA while SCLK remains high, and indicates that an address/data stream follows. All peripherals respond to the start condition and shift the next eight bits (the 7-bit address plus the R/W bit). The bits are transferred from MSB to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse; this is known as an acknowledge (ACK) bit. If the highest subaddress is exceeded in auto-increment mode, one of the following actions is taken: • • In read mode, the register contents of the highest subaddress continue to be output until the master device issues a no acknowledge, which indicates the end of a read. A no acknowledge condition occurs when the SDATA line is not pulled low on the ninth pulse. In write mode, the data for the invalid byte is not loaded into a subaddress register. A no acknowledge is issued by the ADV7280/ADV7280-M, and the part returns to the idle condition. SDATA SCLK S 1–7 8 9 START ADDR R/W ACK 1–7 8 9 1–7 SUBADDRESS ACK DATA 8 9 P ACK STOP Figure 12. Bus Data Transfer WRITE SEQUENCE S SLAVE ADDR A(S) SUBADDRESS A(S) LSB = 0 READ SEQUENCE A(S) DATA A(S) P LSB = 1 S SLAVE ADDR A(S) SUBADDRESS A(S) S S = START BIT P = STOP BIT DATA SLAVE ADDR A(S) A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER DATA A(M) A(S) = NO ACKNOWLEDGE BY SLAVE A(M) = NO ACKNOWLEDGE BY MASTER Figure 13. Read and Write Sequence Rev. A | Page 22 of 28 DATA A(M) P 11634-013 1. 11634-012 ALSB Pin 0 0 1 1 All other devices withdraw from the bus and maintain an idle condition. In the idle condition, the device monitors the SDATA and SCLK lines for the start condition and the correct transmitted address. Data Sheet ADV7280 REGISTER MAPS Interrupt/VDP Sub Map The ADV7280/ADV7280-M contain three register maps: the main register map, the VPP register map, and the CSI register map (ADV7280-M only). The interrupt/VDP sub map contains registers that can be used to program internal interrupts, control the INTRQ pin, and decode vertical blanking interval (VBI) data. Main Map The interrupt/VDP sub map has the same I2C slave address as the main map. To access the interrupt/VDP sub map, set the SUB_USR_EN bits in the main map (Address 0x0E[6:5]) to 01. The I2C slave address of the main map of the ADV7280/ ADV7280-M is set by the ALSB pin (see Table 15). The main map allows the user to program the I2C slave addresses of the VPP and CSI maps. The main map contains three sub maps: the user sub map, the interrupt/VDP sub map, and User Sub Map 2. These three sub maps are accessed by writing to the SUB_USR_EN bits (Address 0x0E[6:5]) within the main map (see Figure 14 and Table 16). User Sub Map The user sub map contains registers that program the analog front end and digital core of the ADV7280/ADV7280-M. The user sub map has the same I2C slave address as the main map. To access the user sub map, set the SUB_USR_EN bits in the main map (Address 0x0E[6:5]) to 00. User Sub Map 2 User Sub Map 2 contains registers that control the ACE, down dither, and fast lock functions. It also contains controls that set the acceptable input luma and chroma limits before the ADV7280/ ADV7280-M enter free run and color kill modes. User Sub Map 2 has the same I2C slave address as the main map. To access User Sub Map 2, set the SUB_USR_EN bits in the main map (Address 0x0E[6:5]) to 10. MAIN MAP VPP MAP CSI MAP DEVICE ADDRESS DEVICE ADDRESS DEVICE ADDRESS 0x0E[6:5] = 00 0x0E[6:5] = 01 0x0E[6:5] = 10 USER SUB MAP INTERRUPT/VDP SUB MAP USER SUB MAP 2 WRITE: 0x84 (RECOMMENDED READ: 0x85 SETTINGS) VPP MAP DEVICE ADDRESS IS PROGRAMMABLE AND SET BY REGISTER 0xFD IN THE USER SUB MAP WRITE: 0x88 (RECOMMENDED READ: 0x89 SETTINGS) CSI MAP ADDRESS IS PROGRAMMABLE AND SET BY REGISTER 0xFE IN THE USER SUB MAP 11634-014 ALSB PIN HIGH WRITE: 0x42 READ: 0x43 ALSB PIN LOW WRITE: 0x40 READ: 0x41 Figure 14. Register Map and Sub Map Access Table 16. I2C Register Map and Sub Map Addresses ALSB Pin 0 0 0 0 0 0 1 1 1 1 1 1 X1 X1 X1 X1 1 R/W Bit 0 (write) 1 (read) 0 (write) 1 (read) 0 (write) 1 (read) 0 (write) 1 (read) 0 (write) 1 (read) 0 (write) 1 (read) 0 (write) 1 (read) 0 (write) 1 (read) Slave Address 0x40 0x41 0x40 0x41 0x40 0x41 0x42 0x43 0x42 0x43 0x42 0x43 0x84 0x85 0x88 0x89 SUB_USR_EN Bits (Address 0x0E[6:5]) 00 00 01 01 10 10 00 00 01 01 10 10 XX1 XX1 XX1 XX1 Register Map or Sub Map User sub map User sub map Interrupt/VDP sub map Interrupt/VDP sub map User Sub Map 2 User Sub Map 2 User sub map User sub map Interrupt/VDP sub map Interrupt/VDP sub map User Sub Map 2 User Sub Map 2 VPP map VPP map CSI map (ADV7280-M only) CSI map (ADV7280-M only) X and XX mean don’t care. Rev. A | Page 23 of 28 ADV7280 Data Sheet VPP Map The video postprocessor (VPP) map contains registers that control the I2P core (interlaced-to-progressive converter). The VPP map has a programmable I2C slave address, which is programmed using Register 0xFD in the user sub map of the main map. The default value for the VPP map address is 0x00; however, the VPP map cannot be accessed until the I2C slave address is reset. The recommended I2C slave address for the VPP map is 0x84. To reset the I2C slave address of the VPP map, write to the VPP_SLAVE_ADDRESS[7:1] bits in the main register map (Address 0xFD[7:1]). Set these bits to a value of 0x84 (I2C write address; I2C read address is 0x85). To reset the I2C slave address of the CSI map, write to the CSI_TX_SLAVE_ADDRESS[7:1] bits in the main register map (Address 0xFE[7:1]). Set these bits to a value of 0x88 (I2C write address; I2C read address is 0x89). SUB_USR_EN Bits, Address 0x0E[6:5] The ADV7280/ADV7280-M main map contains three sub maps: the user sub map, the interrupt/VDP sub map, and User Sub Map 2 (see Figure 14). The user sub map is available by default. The other two sub maps are accessed using the SUB_USR_EN bits. When programming of the interrupt/VDP map or User Sub Map 2 is completed, it is necessary to write to the SUB_USR_EN bits to return to the user sub map. CSI Map (ADV7280-M Only) The CSI map contains registers that control the MIPI CSI-2 output stream from the ADV7280-M. The CSI map has a programmable I2C slave address, which is programmed using Register 0xFE in the user sub map of the main map. The default value for the CSI map address is 0x00; however, the CSI map cannot be accessed until the I2C slave address is reset. The recommended I2C slave address for the CSI map is 0x88. Rev. A | Page 24 of 28 Data Sheet ADV7280 PCB LAYOUT RECOMMENDATIONS The ADV7280/ADV7280-M are high precision, high speed, mixed-signal devices. To achieve maximum performance from the parts, it is important to use a well-designed PCB. This section provides guidelines for designing a PCB for use with the ADV7280/ADV7280-M. ANALOG INTERFACE INPUTS When routing the analog interface inputs on the PCB, keep track lengths to a minimum. Use 75 Ω trace impedances when possible; trace impedances other than 75 Ω increase the chance of reflections. POWER SUPPLY DECOUPLING It is recommended that each power supply pin be decoupled with 100 nF and 10 nF capacitors. The basic principle is to place a decoupling capacitor within approximately 0.5 cm of each power pin. Avoid placing the decoupling capacitors on the opposite side of the PCB from the ADV7280/ADV7280-M because doing so introduces inductive vias in the path. Place the decoupling capacitors between the power plane and the power pin. Current should flow from the power plane to the capacitor and then to the power pin. Do not apply the power connection between the capacitor and the power pin. The best approach is to place a via near, or beneath, the decoupling capacitor pads down to the power plane (see Figure 15). VIA TO SUPPLY SUPPLY 10nF 100nF VIA TO GND 11634-015 GROUND VREFN AND VREFP PINS Place the circuit associated with the VREFN and VREFP pins as close as possible to the ADV7280/ADV7280-M and on the same side of the PCB as the part. DIGITAL OUTPUTS (INTRQ, GPO0 TO GPO2) Minimize the trace length that the digital outputs must drive. Longer traces have higher capacitance, requiring more current and, in turn, causing more internal digital noise. Shorter traces reduce the possibility of reflections. Adding a 30 Ω to 50 Ω series resistor can suppress reflections, reduce EMI, and reduce current spikes inside the ADV7280/ ADV7280-M. If series resistors are used, place them as close as possible to the pins of the ADV7280/ADV7280-M. However, try not to add vias or extra length to the output trace in an attempt to place the resistors closer. If possible, limit the capacitance that each digital output must drive to less than 15 pF. This recommendation can be easily accommodated by keeping traces short and by connecting the outputs to only one device. Loading the outputs with excessive capacitance increases the current transients inside the ADV7280/ ADV7280-M, creating more digital noise on the power supplies. EXPOSED METAL PAD The ADV7280/ADV7280-M have an exposed metal pad on the bottom of the package. This pad must be soldered to ground. The exposed pad is used for proper heat dissipation, noise suppression, and mechanical strength. DIGITAL INPUTS Figure 15. Recommended Power Supply Decoupling The digital inputs of the ADV7280/ADV7280-M are designed to work with 1.8 V signals (3.3 V for DVDDIO) and are not tolerant of 5 V signals. Extra components are required if 5 V logic signals must be applied to the decoder. It is especially important to maintain low noise and good stability for the PVDD pin. Careful attention must be paid to regulation, filtering, and decoupling. It is highly desirable to provide separate regulated supplies for each circuit group (AVDD, DVDD, DVDDIO, PVDD, and, for the ADV7280-M, MVDD). Some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). This disparity can result in a measurable change in the voltage supplied to the analog supply regulator, which can, in turn, produce changes in the regulated analog supply voltage. This problem can be mitigated by regulating the analog supply, or at least the PVDD supply, from a different, cleaner power source, for example, from a 12 V supply. Using a single ground plane for the entire board is also recommended. Experience has shown that the noise performance is the same or better with a single ground plane. Using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. MIPI OUTPUTS FOR THE ADV7280-M (D0P, D0N, CLKP, CLKN) It is recommended that the MIPI output traces be kept as short as possible and on the same side of the PCB as the ADV7280-M device. It is also recommended that a solid plane (preferably a ground plane) be placed on the layer adjacent to the MIPI traces to provide a solid reference plane. MIPI transmission operates in both differential and singleended modes. During high speed transmission, the pair of outputs operates in differential mode; in low power mode, the pair operates as two independent single-ended traces. Therefore, it is recommended that each output pair be routed as two loosely coupled 50 Ω single-ended traces to reduce the risk of crosstalk between the two traces in low power mode. Rev. A | Page 25 of 28 ADV7280 Data Sheet TYPICAL CIRCUIT CONNECTIONS 0.1µF Y 24Ω AIN1 51Ω DVDD _1.8V DVDDIO _3.3V AVDD _1.8V 0.1µF Pb 24Ω AIN2 0.1µF 51Ω 10nF 0.1µF 0.1µF 0.1µF 10nF 10nF 10nF 0.1µF Pr 24Ω AIN3 51Ω PVDD _1.8V DVDDIO _3.3V DVDD _1.8V 0.1µF AVDD _1.8V CVBS INPUT EXAMPLE 10nF 18 AIN2 22 AIN3 23 AIN4 AIN2 16 21 3 P0 P1 P2 P3 P4 P5 P6 P7 12 11 10 9 8 7 6 5 LLC 32 INTRQ 24 VS/FIELD/SFL 29 HS 30 AIN3 AIN4 ADV7280 LOCATE VREFP AND VREFN CAPACITOR AS CLOSE AS POSSIBLE TO THE ADV7280 AND ON THE SAME SIDE OF THE PCB AS THE ADV7280 19 VREFP 20 VREFN P0 TO P7 PVDD AIN1 AVDD 17 AIN1 DVDD 51Ω DVDD AIN4 2 24Ω 13 0.1µF DVDDIO COMPONENT ANALOG VIDEO INPUT EXAMPLE Figure 16 provides an example of how to connect the ADV7280. For detailed schematics of the ADV7280 evaluation board, contact a local Analog Devices field applications engineer or an Analog Devices distributor. P0 P1 P2 P3 P4 P5 P6 P7 YCrCb 8-BIT ITU-R BT.656 DATA 0.1µF LOCATE CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS, THE ADV7280 14 47pF XTALP 28.63636MHz 15 XTALN 26 ALSB 31 PWRDWN 25 RESET 28 SCLK 27 SDATA 47pF LLC INTRQ VS/FIELD/SFL HS DVDDIO 4kΩ SCLK 11634-016 1 SDATA DGND RESET 4 PWRDWN DGND ALSB TIED HIGH: I2C ADDRESS = 0x42 ALSB TIED LOW: I2C ADDRESS = 0x40 Figure 16. Typical Connection Diagram, ADV7280 Rev. A | Page 26 of 28 Data Sheet ADV7280 Figure 17 provides an example of how to connect the ADV7280-M. For detailed schematics of the ADV7280-M evaluation board, contact a local Analog Devices field applications engineer or an Analog Devices distributor. 0.1µF Y 24Ω A IN1 51Ω COMPONENT VIDEO INPUT 0.1µF Pb 24Ω A IN2 51Ω 0.1µF Pr A IN3 24Ω 51Ω DVDDIO _3.3V D VDD _1.8V 24Ω 51Ω PVDD _1.8V A IN5 22 AIN3 0.1µF 23 AIN4 A IN7 24Ω 24 AIN5 51Ω AIN6 0.1µF A IN8 C 24Ω AIN7 AIN8 51Ω 21 13 AVDD MVDD D0P D0N CLKP 11 CLKP AIN5 CLKN 12 CLKN AIN7 27 AIN8 ADV7280-M LOCATE CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS, THE ADV7280-M GPO2 GPO1 GPO0 6 7 8 GPO2 GPO1 GPO0 XTALP 28.63636MHz INTRQ 47pF 10 AIN4 26 15 9 AIN3 AIN6 14 PVDD D0P D0N 25 47pF 16 3 AIN1 AIN2 5 INTRQ XTALN LOCATE VREFN AND VREFP CAPACITOR AS CLOSE AS POSSIBLE TO THE ADV7280-M AND ON THE SAME SIDE OF THE PCB AS THE ADV7280-M DVDDIO 4kΩ 29 ALSB 19 ALSB TIED HIGH: I2C ADDRESS = 0x42 ALSB TIED LOW: I2C ADDRESS = 0x40 VREFP 0.1µF SCLK SDATA 31 30 PWRDWN 20 RESET SCLK SDATA DGND 28 RESET VREFN 11634-017 4 PWRDWN DGND 32 1 S-VIDEO INPUT 18 AIN2 DVDD A IN6 51Ω Y 17 AIN1 0.1µF 10nF 2 51Ω 24Ω 0.1µF AVDD _1.8V DVDDIO 24Ω M VDD_1.8V DVDD _1.8V 0.1µF SINGLEENDED CVBS INPUT 10nF A IN4 D VDDIO _3.3V SINGLEENDED CVBS INPUT 10nF 10nF 10nF MVDD _1.8V 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF SINGLEENDED CVBS INPUT AVDD _1.8V Figure 17. Typical Connection Diagram, ADV7280-M Rev. A | Page 27 of 28 ADV7280 Data Sheet OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 1 24 0.50 BSC *3.75 3.60 SQ 3.55 EXPOSED PAD 17 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION. 08-16-2010-B PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 ADV7280WBCPZ ADV7280WBCPZ-RL ADV7280BCPZ ADV7280BCPZ-RL ADV7280KCPZ ADV7280KCPZ-RL ADV7280WBCPZ-M ADV7280WBCPZ-M-RL ADV7280BCPZ-M ADV7280BCPZ-M-RL ADV7280KCPZ-M ADV7280KCPZ-M-RL EVAL-ADV7280EBZ EVAL-ADV7280MEBZ 1 2 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +85°C −40°C to +85°C −10°C to +70°C −10°C to +70°C −40°C to +105°C −40°C to +105°C −40°C to +85°C −40°C to +85°C −10°C to +70°C −10°C to +70°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board for the ADV7280 Evaluation Board for the ADV7280-M Package Option CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 CP-32-12 Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The ADV7280W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11634-0-2/14(A) Rev. A | Page 28 of 28