Engineer-to-Engineer Note a EE-298 Technical notes on using Analog Devices DSPs, processors and development tools Visit our Web resources http://www.analog.com/ee-notes and http://www.analog.com/processors or e-mail [email protected] or [email protected] for technical support. Estimating Power for ADSP-BF538/BF539 Blackfin® Processors Contributed by Joe B. Rev 2 – July 12, 2007 Introduction This EE-Note discusses the methodology for estimating total average power consumption of ADSPBF538 and ADSP-BF539 Blackfin® embedded processors. It also applies to the processor models equipped with on-chip flash memory. The term Blackfin refers to all variations of processors addressed by this document. Power estimates are based on characterization data measured over power supply voltage, core frequency (CCLK), and junction temperature (TJ). The intent of this document is to assist board designers in estimating their power budget for power supply design and thermal relief designs using Blackfin processors. These processors feature dynamic power management control, allowing the regulation of applied core voltage (VDDINT) from an external I/O source (VDDEXT). The ranges for these supplies differ depending on the part being used. The total power consumption of the Blackfin processor is the sum of the power consumed for both of the power supply domains, VDDINT and VDDEXT. Please consult the following sections of the appropriate data-sheet[1][2] for details specific to discussions throughout this EE-Note: • See the Recommended Operating Conditions section for details regarding VDDINT and VDDEXT ranges. • See the Timing Specifications section for details regarding required VDDINT values to support the desired CCLK. • See the Ordering Guide section for a comprehensive list of the various speed and temperature grade models available for ADSP-BF538 and ADSP-BF539 Blackfin processors. Estimating Internal Power Consumption The total power consumption due to internal circuitry (on the VDDINT supply) is the sum of the static power component and dynamic power component of the processor’s core logic. The dynamic portion of the internal power depends on the instruction execution sequence, the data operands involved, and the instruction rate. The static portion of the internal power is a function of temperature and voltage; it is not related to processor activity. Copyright 2004 - 2007, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices’ Engineer-to-Engineer Notes. a Analog Devices provides current consumption figures and scaling factors for discrete dynamic activity levels. System application code can be mapped to these discrete numbers to estimate the dynamic portion of the internal power consumption for Blackfin processors in a given application. Internal Power Vector Definitions The following power vector definitions define the dynamic activity levels that apply to the internal power vectors shown in Table 1. These test vectors apply to all Blackfin processors. IDD-IDLE - VDDINT supply current for idle activity. Idle activity is the core executing the IDLE instruction only, with no core memory accesses, no DMA, and no interrupts. IDD-NOP - VDDINT supply current for no-op activity. No-op activity is the core executing the NOP instruction only, with no core memory accesses, no DMA, and no interrupts. This is a useful measurement for software-implemented delay loops. IDD-APP - VDDINT supply current for a specific application’s activity. This activity is the core executing an application comprised of 30% dual-MAC instructions and 70% load-store and no-op instructions. All instructions and data are located in L1 SRAM, and peripherals are not enabled. IDD-TYP - VDDINT supply current for typical activity. Typical activity is the core executing an application comprised of 75% dual-MAC instructions and 25% dual-ALU instructions. All instructions and data are located in L1 SRAM, and peripherals are not enabled. This is the test vector used for the dissipation numbers found in the data-sheet. IDD-HIGH - VDDINT supply current for high activity. High activity is the core executing an application comprised entirely of dual-MAC instructions. All instructions and data are located in L1 SRAM, and peripherals are disabled. IDD-PEAK - VDDINT supply current for peak activity for ADSP-BF538 processors. Peak activity is the core executing 100% dual-MAC instructions fetched from internal memory, with memory DMA moving a data pattern from L1 Data A memory to L1 Data B memory. The bit pattern toggles all bits in each access. This vector is also utilized for the ADSP-BF539 processor, however, it is not representative of a peak value as it does not utilize the dedicated MXVR DMA engine or the dedicated internal power rail for the MXVR. The test code used to measure IDD-PEAK represents worst-case processor operation for ADSP-BF538 processors. This activity level is not realistic under normal application conditions. For ADSP-BF539 processors, the MXVR peripheral contributes to the dynamic power profile when its DMA channels are powered and running in the background while these test vectors are run on the core. To represent this, the same test vectors as described above are suffixed with a trailing –MXVR in Table 1 to show the same test vector with the MXVR powered and running. The vectors are IDD-IDLE-MXVR, IDD-NOP-MXVR, IDD-APP-MXVR, IDD-TYP-MXVR, IDD-HIGH-MXVR, and IDD-PEAK-MXVR. The test code used to measure IDD-PEAK-MXVR represents worst-case processor operation for ADSP-BF539 processors. This activity level is not realistic under normal application conditions. Estimating Power for ADSP-BF538/BF539 Blackfin® Processors (EE-298) Page 2 of 14 a Estimating IDDINT Dynamic Current, IDD-DYN There are two steps required to estimate dynamic power consumption due to internal circuitry (i.e., on the VDDINT supply). The first step is to determine the dynamic baseline current, and the second step is to determine the percentage of activity for each discrete power vector with respect to the entire application. IDD Baseline Dynamic Current, IDD-BASELINE-DYN The Blackfin processors’ baseline dynamic current (IDD-BASELINE-DYN) graph is shown in Figure 1. The value of IDD-BASELINE-DYN is derived using the IDD-TYP dynamic activity level vs. core frequency. Each curve in the graph represents a baseline IDDINT dynamic current for a specified power supply setting. Using the curve specific to the application, IDD-BASELINE-DYN for the VDDINT power supply domain can be estimated at the CCLK of the processor in the application. For example, with VDDINT at 1.2 V and CCLK at 400 MHz, the corresponding IDD-BASELINE-DYN for the VDDINT power supply domain would be approximately 140 mA. ADSP-BF538/9 Idd Dynamic Typical (IDD-BASELINE-DYN) 250.00 200.00 0.80V 0.85V 0.90V Current (mA) 0.95V 150.00 1.00V 1.05V 1.10V 1.15V 1.20V 100.00 1.25V 1.30V 1.35V 1.40V 50.00 0.00 0 100 200 300 400 500 600 700 Core Clock Frequency (MHz) Figure 1. Baseline IDDINT Dynamic Current IDD Dynamic Current Running Your Application Table 1 lists the scaling factors for each activity level, which are used to estimate the dynamic current for each specific application. With knowledge of the program flow and an estimate of the percentage of time Estimating Power for ADSP-BF538/BF539 Blackfin® Processors (EE-298) Page 3 of 14 a spent at each activity level, system developers can use the IDD-BASELINE-DYN shown in Figure 1 and the corresponding activity scaling factors (ASF) from Table 1 to determine the dynamic portion of the internal current (IDD-DYN) for each Blackfin processor in a system. Power Vector Activity Scaling Factor (ASF) IDD-PEAK-MXVR* 1.36 IDD-HIGH-MXVR* 1.32 IDD-PEAK 1.30 IDD-HIGH 1.28 IDD-TYP-MXVR* 1.07 IDD-TYP 1.00 IDD-APP-MXVR* 0.92 IDD-APP 0.88 IDD-NOP-MXVR* 0.76 IDD-NOP 0.74 IDD-IDLE-MXVR* 0.50 IDD-IDLE 0.48 * Applies only to ADSP-BF539/ADSP-BF539F processors Table 1. Internal Power Vectors and Dynamic Scaling Factors IDD-DYN for a Blackfin processor in a specific application is calculated according to Equation 1a or Equation 1b, where “%” is the percentage of the overall time that the application spends in that state: ( % Peak activity level ( % High activity level ( % Typ. activity level ( % App. activity level ( % NOP activity level + ( % Idle activity level x IDD-PEAK ASF x IDD-BASELINE-DYN) x IDD-HIGH ASF x IDD-BASELINE-DYN) x IDD-TYP ASF x IDD-BASELINE-DYN) x IDD-APP ASF x IDD-BASELINE-DYN) x IDD-NOP ASF x IDD-BASELINE-DYN) x IDD-IDLE ASF x IDD-BASELINE-DYN) Total Dynamic Current for VDDINT (IDD-DYN) Equation 1a. Internal Dynamic Current (IDD-DYN) for ADSP-BF538 Processors Estimating Power for ADSP-BF538/BF539 Blackfin® Processors (EE-298) Page 4 of 14 a ( % Peak activity level w/MXVR x IDD-PEAK-MXVR ASF x IDD-BASELINE-DYN) ( % High activity level w/MXVR x IDD-HIGH-MXVR ASF x IDD-BASELINE-DYN) ( % Typ. activity level w/MXVR x IDD-TYP-MXVR ASF x IDD-BASELINE-DYN) ( % App. activity level w/MXVR x IDD-APP-MXVR ASF x IDD-BASELINE-DYN) ( % NOP activity level w/MXVR x IDD-NOP-MXVR ASF x IDD-BASELINE-DYN) ( % Idle activity level w/MXVR x IDD-IDLE-MXVR ASF x IDD-BASELINE-DYN) ( % Peak activity level x IDD-PEAK ASF x IDD-BASELINE-DYN) ( % High activity level x IDD-HIGH ASF x IDD-BASELINE-DYN) ( % Typ. activity level x IDD-TYP ASF x IDD-BASELINE-DYN) x IDD-BASELINE-DYN) ( % App. activity level x IDD-APP ASF x IDD-BASELINE-DYN) ( % NOP activity level x IDD-NOP ASF + ( % Idle activity level x IDD-IDLE ASF x IDD-BASELINE-DYN) Total Dynamic Current for VDDINT (IDD-DYN) Equation 1b. Internal Dynamic Current (IDD-DYN) for ADSP-BF539 Processors For example, after profiling the application code for a particular ADSP-BF538 processor system, activity is determined to be proportioned as shown in Figure 2. (10% Peak Activity Level) (20% High Activity Level) (50% Typ. Activity Level) (10% App. Activity Level) (10% NOP Activity Level) + (0% Idle Activity Level) 100% Activity Figure 2. Internal System Activity Levels for an ADSP-BF538 Blackfin Processor System Using the ASF provided for each activity level in Table 1 (and with VDDINT at 1.2 V and CCLK at 400 MHz), a value for IDD-DYN consumption of a single processor can be estimated as follows: (10% x 1.30 x 140) (20% x 1.28 x 140) (50% x 1.00 x 140) (10% x 0.88 x 140) (10% x 0.74 x 140) + (0% x 0.41 x 140) IDD-DYN = 146.72 mA = ~147 mA Figure 3. Internal Dynamic Current Estimation for ADSP-BF538 Blackfin Processor System The total estimated dynamic current on the VDDINT power supply in this ADSP-BF538 Blackfin processor example is ~147 mA. For ADSP-BF539 systems, the profiling of the application code must consider when the MXVR peripheral is running. Percentages spent in each possible application state would still add up to 100% activity, as defined in Figure 2 above, but there are six additional defined states for ADSP-BF539 Estimating Power for ADSP-BF538/BF539 Blackfin® Processors (EE-298) Page 5 of 14 a applications. Similarly, these additional six states would be added to Figure 3 as well when computing the total internal dynamic current estimation. Estimating IDDINT Static Current, IDD-DEEPSLEEP Deep Sleep mode for Blackfin processors is when power is applied to the core and L1 memories, but all clocks are turned off. In this mode, the IDD-DEEPSLEEP measurement can be taken, which is the baseline static component of overall average dissipation. The IDD-DEEPSLEEP current graph for the Blackfin processors is shown in Figure 4. The static current on the VDDINT power supply domain is a function of junction temperature (TJ) and voltage, but it is not a function of frequency or activity level. Therefore, unlike the dynamic portion of the internal current, the static current need not be calculated for each discrete activity level or power vector. Using the static current curve corresponding to the application (i.e., at specific VDDINT), IDD-DEEPSLEEP can be estimated vs. TJ of the Blackfin processor. Appendix A discusses the methodology for estimating TJ. This process involves knowing the total power profile for the processor; therefore, this process will be iterative to arrive at a final calculation for expected power dissipation. For example, in an application with VDDINT at 1.2 V and a Blackfin processor at a TJ of +100oC, the corresponding IDD-DEEPSLEEP for the VDDINT power domain would be approximately 360 mA. The static power of the Blackfin processor is constant for a given voltage and temperature. Therefore, it is simply added to the total estimated dynamic current when calculating the total power consumption due to the internal circuitry of the Blackfin processor. Note that the IDD-DEEPSLEEP currents shown in Figure 4 represent the worse-case static current as measured across the wafer fabrication process. Estimating Power for ADSP-BF538/BF539 Blackfin® Processors (EE-298) Page 6 of 14 a Figure 4. IDD_DEEPSLEEP Static Current Estimating Power for ADSP-BF538/BF539 Blackfin® Processors (EE-298) Page 7 of 14 a Estimating Total IDDINT Current The total current consumption due to the internal core circuitry (IDDINT) is the sum of the dynamic current component and the static current component, as shown in Equation 2. IDDINT = IDD-DYN + IDD-DEEPSLEEP Equation 2. Internal Core Current (IDDINT) Calculation Continuing with the example of the Blackfin processor operating at 1.2 V and 400 MHz (and with the code as profiled), assume that the resulting TJ is estimated to be +100oC. The total internal current consumed by the processor core under these conditions would be: IDDINT = 140 + 360 = 500 mA Equation 3. IDDINT Estimation Total Estimated Internal Power, PDDINT The resulting internal power consumption (PDDINT) is given by Equation 4. PDDINT = VDDINT x IDDINT Equation 4. Internal Power (PDDINT) Calculation Using Equation 4, the total estimated internal power consumed by the processor in the application described in this example would be: PDDINT = 1.20V x 500 mA = 600 mW Equation 5. PDDINT Estimation (High-Performance) Estimating External Power Consumption External power consumption (on the VDDEXT supply) is dependent on the enabled peripherals in a given system. Each unique group of peripheral pins contributes to a piece of the overall external power, based upon several parameters: • O - The number of output pins that switch during each cycle • f - The maximum frequency at which the output pins can switch • VDDEXT - The voltage swing of the output pins • CL - The load capacitance of the output pins • U - The utilization factor (the percentage of time that the peripheral is on and running) In addition to the input capacitance of each device connected to an output, the total capacitance (CL) should include the capacitance of the processor pin itself (COUT), which is driving the load. Estimating Power for ADSP-BF538/BF539 Blackfin® Processors (EE-298) Page 8 of 14 a Equation 6 shows how to calculate the average external current (IDDEXT) using the above parameters: IDDEXT = O x f/2 x VDDEXT x CL x U Equation 6. External Current (IDDEXT) Calculation The worst-case external pin power scenario occurs when the load capacitor charges and discharges continuously, requiring the pin to toggle each cycle. Since the state of the pin can change only once per cycle, the maximum toggling frequency is f/2. In terms of supply power, the worst-case VDDEXT value is 3.6 V. Table 2 contains data for a realistic example of a PPI application, which runs several peripherals simultaneously. Actual results may vary, but again, the intent of this document is to help designers size the power supplies. Estimated average external power consumption (PDDEXT) can be calculated as follows. PDDEXT = VDDEXT x IDDEXT Equation 7. External Power (PDDEXT) Calculation Using the sample Blackfin system configuration in Figure 5, the external current and, therefore, the external power consumption can be estimated. Figure 5. Blackfin System Sample Configuration Estimating Power for ADSP-BF538/BF539 Blackfin® Processors (EE-298) Page 9 of 14 a IDDEXT (Equation 6) can be calculated for each class of pins that can drive, as shown in Table 2. Peripheral Freq (Hz) # of pins C/pin (F) Toggle Ratio Util Vddext (V) Pout @ 3.6V (mW) PPI 27.00E+06 9 30.00E-12 1 1.00 3.6 47.24 SPORT0 4.00E+06 2 30.00E-12 1 1.00 3.6 1.56 SPORT1 4.00E+06 2 30.00E-12 1 1.00 3.6 1.56 UART 115.00E+03 2 30.00E-12 1 0.25 3.6 0.01 SDRAM 133.33E+06 36 30.00E-12 0.25 0.50 3.6 116.35 Total External Power Dissipation @ 3.6 V (est. mW) 166.71 Table 2. Sample Calculation For Total Average External Power In the above example, the total average external power consumption is estimated to be ~165 mW. This number was obtained with the parameters listed in Table 2 by applying Equation 8. The chosen operating frequencies are reasonable for each of the peripherals, including the maximum allowed SDRAM frequency of 133.33 MHz. This model assumes that each output pin changes state every clock cycle, which is a worst-case model, except in the case of the SDRAM (because the number of output pins transitioning each clock cycle will be less than the maximum number of output pins). Table 2 was taken from the External Power Spreadsheet[3], which is associated with this EE-Note. It contains calculations for four sample systems. The reader can tailor this spreadsheet to the application, adding or deleting rows as necessary. Since the equation provides results in Watts (W), an additional multiplier of 1000 in the spreadsheet converts results into mW. This equation is a more theoretically accurate version of the one used in the spreadsheet: P ext = VDDext ⋅ 2 ∑C ⋅f L All −Output − Pins Equation 8. Alternate External Power (PDDEXT) Calculation Rather than estimating average external power dissipated in each peripheral, the estimate applies to each individual output pin, based on the pin’s load capacitance and average toggling frequency. The voltage swing is uniform across all output pins within the VDDEXT supply domain, so it is multiplied by the summation of the dynamic charge changes on each output. Using the PPI data in Table 2, nine output pins change every cycle at an average frequency of 27 MHz. Since toggling between on-to-off and off-to-on requires two cycles, FAVG (13.5 MHz) is half the PPI clock. Since each pin changes at the same rate and the pin capacitance is presumed to be the same, the summation is simply nine times the value of any one PPI pin. Applying Equation 8: PEXT_AVG = VDDEXT2 * 9 pins * (FAVG * CL) = (3.6)2 * 9 * 13.5e6 * 30e-12 = 12.96 * 0.003645 = 0.0472392W = 47.239mW Estimating Power for ADSP-BF538/BF539 Blackfin® Processors (EE-298) Page 10 of 14 a As can be seen, the value derived using this equation is the same as the value estimated in Table 2. This model obtains the same estimate on a per-pin basis rather than a per-peripheral basis. In addition to the peripheral pins, there are two other output pins on Blackfin processors that will contribute to the VDDEXT supply domain power profile if the system uses a crystal to provide the CLKIN signal to the processor. In this case, the ADSP-BF538/BF539 processors drive the XTAL output pin when the PLL is active. The output drive frequency will be exactly the CLKIN rate, and the pin capacitance value can be obtained from the data-sheet. Note that the voltage swing will likely be less than VDDEXT for most crystals, and using VDDEXT in computations would be a worst-case model in terms of profiling power dissipation. Similarly, the same concepts apply for the MXI and MXO pins on the ADSP-BF539 Blackfin processor for the MXVR oscillator. For those processor models equipped with one, the on-chip flash memory will contribute to the VDDEXT supply domain power profile as well. Please see the appropriate Spansion Known Good Die data-sheet supplement[4][5] for details regarding power dissipation of the memory die. Finally, designers must be mindful of power supply efficiency when sizing the VDDEXT supply. Switching Regulator Design Considerations for ADSP-BF533 Blackfin Processors (EE-228)[6] describes the internal voltage regulator. Real-Time Clock (RTC) Power Consumption The final source of total power consumption comes from the optional third power domain, the Real-Time Clock (RTC) power domain (VDDRTC), which is a specified value. The RTC can be powered between 2.25 V and 3.6 V. For a worst-case analysis, a supply voltage of 3.6 V yields a current draw, IDDRTC, of 30 μA to 50 μA for a range of ambient temperature from 25 oC to 85 oC. For the sake of including this number in the final power consumption estimate, the power dissipated in the RTC domain, PDDRTC is: PDDRTC = VDDRTC x IDDRTC Equation 9. Total Power (PDDRTC) Calculation Knowing this value helps in selecting a battery as a potential power source for the RTC. The RTC can be used to take the Blackfin processor out of any low-power operating mode. Having a battery supply VDDRTC allows the removal of the VDDINT and VDDEXT supplies, thus significantly reducing total average power consumption. As a worst-case example, PDDEXT is 180 µW, which is the product of the maximized VDDRTC (3.6 V) and the high end of the IDDEXT range (50 μA) provided in the data sheet. Total Power Consumption For a given system, total power consumption is the sum of its individual components - power consumed by internal circuitry, power consumed due to switching I/O pins, and power consumed by the RTC circuitry, as follows: PTOTAL = PDDINT + PDDEXT + PDDRTC Equation 10. Total Power (PTOTAL) Calculation Estimating Power for ADSP-BF538/BF539 Blackfin® Processors (EE-298) Page 11 of 14 a Where : PDDINT = Internal power consumption as defined by Equation 4 PDDEXT = External power consumption as defined by Equation 7 PDDRTC = RTC power consumption as defined by Equation 9 For example, assuming that the processor in Figure 5 is operating under the conditions detailed in the example (the processor operating at 1.2 V, 400 MHz, and code as profiled in Figure 2), and also assuming that the resulting TJ has been estimated to be +100oC (see Appendix A for estimating TJ), the total estimated power consumed for the high-performance processor would be: PTOTAL = 600 mW + 166.71 mW + 0.18 mW = ~767 mW Figure 6. Total Power (PTOTAL) Calculation for Sample Shown in Figure While Running Code Described in Equation 5 Conclusion Several variables affect the power requirements of an embedded system. Measurements published in the Blackfin processor data sheets are indicative of typical parts running under typical conditions. However, these numbers do not reflect the actual numbers that may occur for a given processor under non-typical conditions. In addition to the type of silicon that the customer could have, the ambient temperature, core and system frequencies, supply voltages, pin capacitances, power modes, application code, and peripheral utilization contribute to the average total power that may be dissipated. The average power estimates obtained from methods described in this EE-Note indicate how much the Blackfin processor loads a power source over time. These estimates are useful in terms of expected power dissipation within a system, but designs must support worst-case conditions under which the application can be run. Do not use this average power estimation to size the power supply, as the power supply must support peak requirements. Estimating Power for ADSP-BF538/BF539 Blackfin® Processors (EE-298) Page 12 of 14 a Appendix A For Blackfin processors, the total power budget is limited by the maximum allowed junction temperature (TJ) of the device. Please see the processor data sheet for the maximum TJ specification. To guarantee correct operation, ensure that TJ does not exceed the maximum TJ specification. Use the following equation to determine TJ of the device while on the application’s printed circuit board (PCB): TJ = TT + (PTOTAL x ψJT) Equation 11. Junction Temperature (TJ ) Calculation Where: TT = Package temperature (°C) measured at the top center of the package PTOTAL = Total power consumption (W) as defined in Equation 10 ψJT Junction-to-top (of package) characterization parameter (°C/W) = Under natural convection, ψJT for a thin plastic package is relatively low. This means that under natural convection conditions, the typical TJ is just a little higher than the temperature at the top-center of the package (TT). The die is physically separated from the surface of the package by only a thin region of plastic mold compound. Unless the top of the package is forcibly cooled by significant airflow, there will be very little difference between TT and TJ. However, note that ψJT is affected by airflow and values for ψJT under various airflow conditions, and PCB design configurations are listed in the Thermal Characteristics section of the Blackfin processor data sheets for the 316-ball mini-BGA package. The Thermal Characteristics section of the respective data sheet also provides thermal resistance (θJA) values. Data sheet values for θJA are provided for PCB design considerations only and are not recommended for verifying TJ on an actual application PCB. Industrial applications of the mini-BGA package require thermal vias to an embedded ground plane on the PCB. Refer to JEDEC standard JESD51-9 for printed circuit board thermal ball land and thermal via design information. Estimating Power for ADSP-BF538/BF539 Blackfin® Processors (EE-298) Page 13 of 14 a References [1] ADSP-BF538/ADSP-BF538F Blackfin Embedded Processor Data Sheet. Rev. 0, May 2007. Analog Devices, Inc. [2] ADSP-BF539/ADSP-BF539F Blackfin Embedded Processor Data Sheet. Rev. 0, May 2007. Analog Devices, Inc. [3] External Power Spreadsheet. Associated file with Estimating Power for ADSP-BF531/ADSP-BF532/ADSP-BF533 Blackfin Processors (EE-229). September 2006. Analog Devices, Inc. [4] S29AL008D Known Good Die Datasheet Supplement. Rev. A, Amendment 3. June 22, 2005. Spansion, LLC. [5] S29AL004D Known Good Die Datasheet Supplement. Rev. A, Amendment 3. May 3, 2006. Spansion, LLC. [6] Switching Regulator Design Considerations for ADSP-BF533 Blackfin Processors (EE-228). Rev 1, February 2005. Analog Devices, Inc. Document History Revision Description Rev 2 – July 12, 2007 by Joe B. Updated to new format. Includes full power characterization data Rev 1 – October 9, 2006 by Joe B. Initial release Estimating Power for ADSP-BF538/BF539 Blackfin® Processors (EE-298) Page 14 of 14

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