2 Amp TO-220AB, N-Channel, VDSS 400

MTP2N40E
Designer’s™ Data Sheet
TMOS E−FET.™
Power Field Effect
Transistor
N−Channel Enhancement−Mode Silicon
Gate
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this advanced TMOS E−FET is
designed to withstand high energy in the avalanche and commutation
modes. The new energy efficient design also offers a drain−to−source
diode with a fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are critical
and offer additional safety margin against unexpected voltage
transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
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TMOS POWER FET
2.0 AMPERES, 400 VOLTS
RDS(on) = 3.5 W
TO−220AB
CASE 221A−06
Style 5
D
®
G
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−Source Voltage
VDSS
400
Vdc
Drain−Gate Voltage (RGS = 1.0 MΩ)
VDGR
400
Vdc
Gate−Source Voltage — Continuous
Gate−Source Voltage — Non−Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 40
Vdc
Vpk
ID
ID
2.0
1.5
6.0
Adc
PD
40
0.32
Watts
W/°C
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 μs)
IDM
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range
Apk
TJ, Tstg
−55 to 150
°C
Single Pulse Drain−to−Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 3.0 Apk, L = 10 mH, RG = 25 Ω)
EAS
45
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
RθJC
RθJA
3.13
62.5
°C/W
TL
260
°C
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred devices are Motorola recommended choices for future use and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 1
1
Publication Order Number:
MTP2N40E/D
MTP2N40E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
400
—
—
451
—
—
Vdc
mV/°C
—
—
—
—
10
100
—
—
100
nAdc
2.0
—
3.2
7.0
4.0
—
Vdc
mV/°C
—
3.1
3.5
Ohms
—
—
7.3
—
8.4
7.4
gFS
0.5
1.0
—
mhos
Ciss
—
229
320
pF
Coss
—
34
40
Crss
—
7.3
10
td(on)
—
8.0
16
tr
—
8.4
14
td(off)
—
12
26
tf
—
11
20
QT
—
8.6
12
Q1
—
2.6
—
Q2
—
3.2
—
Q3
—
5.0
—
—
—
0.88
0.76
1.2
—
trr
—
156
—
ta
—
99
—
tb
—
57
—
QRR
—
0.89
—
—
—
3.5
4.5
—
—
—
7.5
—
OFF CHARACTERISTICS
V(BR)DSS
Drain−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 μAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 400 Vdc, VGS = 0 Vdc)
(VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
μAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 μAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 1.0 Adc)
RDS(on)
Drain−Source On−Voltage (VGS = 10 Vdc)
(ID = 2.0 Adc)
(ID = 1.0 Adc, TJ = 125°C)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 200 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc,
RG = 9.1 Ω)
Fall Time
Gate Charge
(VDS = 320 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 2.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/μs)
Reverse Recovery Stored Charge
VSD
Vdc
ns
μC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
(1) Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
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2
nH
nH
MTP2N40E
TYPICAL ELECTRICAL CHARACTERISTICS
4
TJ = 25°C
VGS = 10 V
3.2
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
4
8V
7V
2.4
6V
1.6
0.8
VDS ≥ 10 V
3
2
1
0
4
16
20
2
3
4
5
6
7
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
VGS = 10 V
TJ = 100°C
6
25°C
4
−55 °C
2
0
12
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
8
8
TJ = −55°C
0
0
1
2
3
4
5
TJ = 25°C
4.5
4
VGS = 10 V
3.5
15 V
3
2.5
0
0.5
1
1.5
2
2.5
3
3.5
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1000
2.5
2
VGS = 0 V
VGS = 10 V
ID = 1 A
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0
25°C
100°C
5V
1.5
1
TJ = 125°C
100
0.5
0
−50
−25
0
25
50
75
100
125
10
150
0
100
200
300
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
4
MTP2N40E
POWER MOSFET SWITCHING
The capacitance (Ciss) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to
the on−state when calculating td(off).
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 8) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
speed. The circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components. Most power electronic loads are
inductive; the data in the figure is taken with a resistive load,
which approximates an optimally snubbed inductive load.
Power MOSFETs may be safely operated into an inductive
load; however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate
of average input current (I G(AV) ) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
C, CAPACITANCE (pF)
400
VDS = 0 V
VGS = 0 V
1000
TJ = 25°C
Ciss
C, CAPACITANCE (pF)
500
300
Ciss
200
Crss
Ciss
100
Coss
10
Crss
Coss
100
0
−10
VGS = 0 V
TJ = 25°C
Crss
−5
0
VGS
5
10
15
20
1
10
25
VDS
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 1b. High Voltage Capacitance
Variation
Figure 1a. Capacitance Variation
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4
10
400
QT
10
300
8
VGS
6
Q1
200
Q2
ID = 2 A
TJ = 25°C
4
100
2
0
0
Q3
2
VDS
4
6
QT, TOTAL CHARGE (nC)
8
0
100
VDD = 200 V
ID = 2 A
VGS = 10 V
TJ = 25°C
t, TIME (ns)
12
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
MTP2N40E
td(off)
10
tf
td(on)
tr
1
1
10
RG, GATE RESISTANCE (OHMS)
Figure 7. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
1
Figure 8. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
2
I S , SOURCE CURRENT (AMPS)
VGS = 0 V
TJ = 25°C
1.5
1
0.5
0
0.5
0.6
0.7
0.8
0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with
an increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as
shown in the accompanying graph (Figure 11). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the
procedures discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I DM ) nor rated voltage (V DSS ) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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MTP2N40E
SAFE OPERATING AREA
45
VGS = 20 V
SINGLE PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
10
10μs
1
100μs
1ms
10ms
dc
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1
10
40
ID = 2 A
35
30
25
20
15
10
5
0
100
25
1000
50
75
100
125
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 10. Maximum Rated Forward Biased
Safe Operating Area
Figure 11. Maximum Avalanche Energy versus
Starting Junction Temperature
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
D = 0.5
0.2
0.1
P(pk)
0.1
0.05
0.02
0.01
t1
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RθJC(t)
1.0E−01
t, TIME (s)
Figure 12. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 13. Diode Reverse Recovery Waveform
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1.0E+00
1.0E+0
MTP2N40E
PACKAGE DIMENSIONS
CASE 221A−06
(TO−220AB)
ISSUE Y
−T−
B
F
T
SEATING
PLANE
C
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
J
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−−
0.080
STYLE 5:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
GATE
DRAIN
SOURCE
DRAIN
E−FET and Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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MTP2N40E/D
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