3 Amp DPAK Surface Mount Products, N-Channel, VDSS 250

MTD3N25E
Designer’s™ Data Sheet
HTMOS E−FET.™
Power Field Effect
Transistor
DPAK for Surface Mount
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N−Channel Enhancement−Mode Silicon
Gate
This advanced TMOS E−FET is designed to withstand high energy
in the avalanche and commutation modes. The new energy efficient
design also offers a drain−to−source diode with a fast recovery time.
Designed for low voltage, high speed switching applications in power
supplies, converters and PWM motor controls, these devices are
particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Surface Mount Package Available in 16 mm, 13−inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
TMOS POWER FET
3 AMPERES, 250 VOLTS
RDS(on) = 1.4 W
DPAK
CASE 369A−13
Style 2
D
®
G
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−Source Voltage
VDSS
250
Vdc
Drain−Gate Voltage (RGS = 1.0 MΩ)
VDGR
250
Vdc
Gate−Source Voltage — Continuous
Gate−Source Voltage — Non−Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 40
Vdc
Vpk
ID
ID
3.0
2.0
9.0
Adc
PD
40
0.32
1.75
Watts
W/°C
Watts
Rating
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 μs)
IDM
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size
Operating and Storage Temperature Range
Apk
TJ, Tstg
−55 to 150
°C
Single Pulse Drain−to−Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25 Ω )
EAS
45
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted to minimum recommended pad size
RθJC
RθJA
RθJA
3.13
100
71.4
°C/W
TL
260
°C
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 3
1
Publication Order Number:
MTD3N25E/D
MTD3N25E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
250
—
—
367
—
—
Vdc
mV/°C
—
—
—
—
10
100
—
—
100
nAdc
2.0
—
—
6.0
4.0
—
Vdc
mV/°C
—
1.1
1.4
Ohm
—
—
—
—
5.04
4.41
gFS
1.0
1.8
—
mhos
Ciss
—
307
430
pF
Coss
—
57
75
Crss
—
14
25
td(on)
—
7.0
15
tr
—
5.0
15
td(off)
—
15
30
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 μAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 250 Vdc, VGS = 0 Vdc)
(VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
μAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 μAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 1.5 Adc)
RDS(on)
Drain−Source On−Voltage (VGS = 10 Vdc)
(ID = 3.0 Adc)
(ID = 1.5 Adc, TJ = 125°C)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 125 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc,
RG = 4.7 Ω)
Fall Time
ns
tf
—
6.0
15
QT
—
9.8
15
Q1
—
2.1
—
Q2
—
4.2
—
Q3
—
3.8
—
—
—
0.9
0.728
1.6
—
trr
—
153
—
ta
—
64
—
tb
—
89
—
QRR
—
0.51
—
μC
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
—
4.5
—
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
—
7.5
—
nH
Gate Charge
(See Figure 8)
(VDS = 200 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc)
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (1)
Reverse Recovery Time
(See Figure 14)
(IS = 3.0 Adc, VGS = 0 Vdc)
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C)
(IS = 3.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/μs)
Reverse Recovery Stored Charge
VSD
Vdc
ns
INTERNAL PACKAGE INDUCTANCE
(1) Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
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MTD3N25E
TYPICAL ELECTRICAL CHARACTERISTICS
6
6
VGS =10V
5
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
TJ = 25°C
7V
4
6V
3
2
5V
VDS ≥ 10 V
TJ = −55°C
5
25°C
4
100°C
3
2
1
1
4V
0
2
1
3
4
5
6
7
8
0
2.0
10
9
4.5
5.0
5.5
6.0
6.5
2.4
TJ = 100°C
2.0
1.6
25°C
1.2
0.8
−55°C
0.5 1.0
1.5
2.0 2.5 3.0 3.5 4.0 4.5
ID, DRAIN CURRENT (AMPS)
5.0
5.5
6.0
7.0
1.7
TJ = 25°C
1.6
1.5
1.4
1.3
VGS =10V
1.2
1.1
15 V
1.0
0
Figure 3. On−Resistance versus Drain Current
and Temperature
0.5
1.0 1.5
2.0 2.5 3.0 3.5 4.0 4.5
ID, DRAIN CURRENT (AMPS)
5.0
5.5 6
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.0
100
VGS =0V
VGS = 10 V
ID =1.5 A
1.6
TJ = 125°C
100°C
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
4.0
Figure 2. Transfer Characteristics
2.8
1.2
0.8
0.4
−50
3.5
Figure 1. On−Region Characteristics
VGS = 10 V
0
3.0
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
3.2
0.4
2.5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
10
25°C
1.0
150
Figure 5. On−Resistance Variation with
Temperature
0
50
100
150
200
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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MTD3N25E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (Ciss) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to
the on−state when calculating td(off).
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate
of average input current (I G(AV) ) can be made from a
rudimentary analysis of the drive circuit so that
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
speed. The circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components. Most power electronic loads are
inductive; the data in the figure is taken with a resistive load,
which approximates an optimally snubbed inductive load.
Power MOSFETs may be safely operated into an inductive
load; however, snubbing reduces switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
800
C, CAPACITANCE (pF)
700
VDS = 0
Ciss
VGS = 0
TJ = 25°C
600
500
Crss
400
Ciss
300
200
Coss
100
Crss
0
10
5
0
VGS
5
10
15
20
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
25
240
QT
200
10
VGS
8
Q1
160
Q2
6
120
4
TJ = 25°C
ID = 3 A
80
2
40
Q3
0
0
1
2
VDS
3
5
6
4
7
QG, TOTAL GATE CHARGE (nC)
8
9
0
10
100
t, TIME (ns)
12
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
MTD3N25E
VDD = 125 V
ID = 3 A
VGS = 10 V
TJ = 25°C
td(off)
10
tf
td(on)
tr
1
1
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Ttotal Charge
10
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
3.0
VGS = 0 V
TJ = 25°C
I S , SOURCE CURRENT (AMPS)
2.5
2.0
1.5
1.0
0.5
0
0.5
0.55
0.6
0.65
0.85
0.7
0.75
0.8
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
0.9
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with
an increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I DM ), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the
procedures discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I DM ) nor rated voltage (V DSS ) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the
total power averaged over a complete switching cycle must
not exceed (TJ(MAX) − TC)/(RθJC).
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MTD3N25E
shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
SAFE OPERATING AREA
VGS = 20 V
SINGLE PULSE
TC = 25°C
45
10μs
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
10
100μs
1.0
1ms
10ms
ds
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1.0
100
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
40
ID = 3 A
35
30
25
20
15
10
5
0
1000
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
25
1
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1.0
D = 0.5
0.2
0.1
P(pk)
0.1
0.05
0.02
t1
t2
DUTY CYCLE, D = t1/t2
0.01
SINGLE PULSE
0.01
1.0E−05
1.0E−04
1.0E−02
t, TIME (s)
1.0E−03
1.0E−01
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RθJC(t)
1.0E+00
1.0E+01
MTD3N25E
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.165
4.191
0.118
3.0
0.100
2.54
0.063
1.6
0.190
4.826
0.243
6.172
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
almost double the power dissipation with this method, one
will be giving up area on the printed circuit board which can
defeat the purpose of using surface mount technology. For
example, a graph of RθJA versus drain pad area is shown in
Figure 15.
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, RθJA, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data
sheet, PD can be calculated as follows:
R
JA , Thermal Resistance, Junction
to Ambient (C/W)
PD =
100
TJ(max) − TA
RθJA
1.75 Watts
Board Material = 0.0625″
G−10/FR−4, 2 oz Copper
80
TA = 25°C
°
θ
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For a DPAK
device, PD is calculated as follows.
60
3.0 Watts
40
20
0
PD = 150°C − 25°C = 1.75 Watts
71.4°C/W
5.0 Watts
2
4
6
A, Area (square inches)
8
10
Figure 15. Thermal Resistance versus Drain Pad
Area for the DPAK Package (Typical)
The 71.4°C/W for the DPAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 1.75 Watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of
the drain pad. By increasing the area of the drain pad, the
power dissipation can be increased. Although one can
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad™. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
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MTD3N25E
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC−59, SC−70/SOT−323, SOD−123, SOT−23, SOT−143,
SOT−223, SO−8, SO−14, SO−16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D2PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 16 shows a
typical stencil for the DPAK and D2PAK packages. The
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇÇ
ÇÇÇ
ÇÇ
ÇÇÇÇÇÇ ÇÇ
ÇÇÇ
ÇÇÇÇÇÇ
ÇÇÇ
SOLDER PASTE
OPENINGS
STENCIL
Figure 16. Typical Stencil for DPAK and
D2PAK Packages
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* Due to shadowing and the inability to set the wave height
to incorporate other surface mount components, the D2PAK
is not recommended for wave soldering.
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MTD3N25E
TYPICAL SOLDER HEATING PROFILE
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density board.
The Vitronics SMD310 convection/infrared reflow soldering
system was used to generate this profile. The type of solder
used was 62/36/2 Tin Lead Silver with a melting point
between 177 −189°C. When this type of furnace is used for
solder reflow work, the circuit boards and solder joints tend
to heat first. The components on the board are then heated
by conduction. The circuit board, because it has a large
surface area, absorbs the thermal energy more efficiently,
then distributes this energy to the components. Because of
this effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a
figure for belt speed. Taken together, these control settings
make up a heating “profile” for that particular circuit board.
On machines controlled by a computer, the computer
remembers these profiles from one operating session to the
next. Figure 17 shows a typical heating profile for use when
soldering a surface mount device to a printed circuit board.
This profile will vary among soldering systems but it is a good
starting point. Factors that can affect the profile include the
type of soldering system in use, density and types of
components on the board, type of solder used, and the type
of board or substrate material being used. This profile shows
temperature versus time. The line on the graph shows the
STEP 1
PREHEAT
ZONE 1
RAMP"
200°C
150°C
STEP 5
STEP 4
HEATING
HEATING
ZONES 3 & 6 ZONES 4 & 7
SPIKE"
SOAK"
170°C
STEP 2
STEP 3
VENT
HEATING
SOAK" ZONES 2 & 5
RAMP"
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
150°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TMAX
TIME (3 TO 7 MINUTES TOTAL)
Figure 17. Typical Solder Heating Profile
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STEP 7
COOLING
205° TO 219°C
PEAK AT
SOLDER JOINT
160°C
100°C
50°C
STEP 6
VENT
MTD3N25E
PACKAGE DIMENSIONS
CASE 369A−13
ISSUE W
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
Z
A
S
U
K
F
J
L
H
D
G
STYLE 2:
PIN 1.
2.
3.
4.
2 PL
0.13 (0.005)
M
T
GATE
DRAIN
SOURCE
DRAIN
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
INCHES
MIN
MAX
0.235
0.250
0.250
0.265
0.086
0.094
0.027
0.035
0.033
0.040
0.037
0.047
0.180 BSC
0.034
0.040
0.018
0.023
0.102
0.114
0.090 BSC
0.175
0.215
0.020
0.050
0.020
−−−
0.030
0.050
0.138
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.84
1.01
0.94
1.19
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.45
5.46
0.51
1.27
0.51
−−−
0.77
1.27
3.51
−−−
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