3 Amp TO-220AB, N-Channel, VDSS 500

MTP3N50E
Designer’s™ Data Sheet
TMOS E−FET.™
High Energy Power FET
N−Channel Enhancement−Mode Silicon
Gate
This advanced high voltage TMOS E−FET is designed to withstand
high energy in the avalanche mode and switch efficiently. This new
high energy device also offers a drain−to−source diode with fast
recovery time. Designed for high voltage, high speed switching
applications such as power supplies, PWM motor controls and other
inductive loads, the avalanche energy capability is specified to
eliminate the guesswork in designs where inductive loads are switched
and offer additional safety margin against unexpected voltage
transients.
• Avalanche Energy Capability Specified at Elevated
Temperature
• Low Stored Gate Charge for Efficient Switching
• Internal Source−to−Drain Diode Designed to Replace External Zener
Transient Suppressor — Absorbs High Energy in the Avalanche
Mode
• Source−to−Drain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode
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TMOS POWER FET
3.0 AMPERES, 500 VOLTS
RDS(on) = 3.0 W
TO−220AB
CASE 221A−06
Style 5
D
®
G
S
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 2
1
Publication Order Number:
MTP3N50E/D
MTP3N50E
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−Source Voltage
VDSS
500
Vdc
Drain−Gate Voltage (RGS = 1.0 MΩ)
VDGR
500
Vdc
Gate−Source Voltage — Continuous
Gate−Source Voltage — Non−repetitive (tp ≤ 50 μs)
VGS
VGSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous
Drain Current — Pulsed
ID
IDM
3.0
10
Adc
Total Power Dissipation @ TC = 25°C
Derate above 25°C
PD
50
0.4
Watts
W/°C
TJ, Tstg
−65 to 150
°C
WDSR (1)
mJ
WDSR (2)
210
33
5.0
RθJC
RθJA
2.5
62.5
°C/W
TL
260
°C
Operating and Storage Temperature Range
UNCLAMPED DRAIN−TO−SOURCE AVALANCHE CHARACTERISTICS (TJ < 150°C)
Single Pulse Drain−to−Source Avalanche Energy — TJ = 25°C
Single Pulse Drain−to−Source Avalanche Energy — TJ = 100°C
Repetitive Pulse Drain−to−Source Avalanche Energy
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case°
— Junction to Ambient°
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
(1) VDD = 50 V, ID = 3.0 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred devices are Motorola recommended choices for future use and best overall value.
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2
MTP3N50E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Drain−to−Source Breakdown Voltage
(VGS = 0, ID = 0.25 mA)
V(BR)DSS
500
—
—
Vdc
Zero Gate Voltage Drain Current
(VDS = 500 V, VGS = 0)
(VDS = 400 V, VGS = 0, TJ = 125°C)
IDSS
—
—
—
—
0.25
1.0
OFF CHARACTERISTICS
mAdc
Gate−Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0)
IGSSF
—
—
100
nAdc
Gate−Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0)
IGSSR
—
—
100
nAdc
2.0
1.5
—
—
4.0
3.5
—
2.4
3.0
—
—
—
—
10
8.0
gFS
1.0
—
—
mhos
Ciss
—
435
—
pF
Coss
—
56
—
Crss
—
9.2
—
td(on)
—
14
—
tr
—
14
—
td(off)
—
30
—
tf
—
20
—
Qg
—
15
21
Qgs
—
2.5
—
Qgd
—
10
—
VSD
—
—
1.5
Vdc
ton
—
**
—
ns
trr
—
200
—
—
—
3.5
4.5
—
—
—
7.5
—
ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mAdc)
(TJ = 125°C)
VGS(th)
Static Drain−Source On−Resistance (VGS = 10 Vdc, ID = 1.5 Adc)
RDS(on)
Drain−Source On−Voltage (VGS = 10 Vdc)
(ID = 3.0 A)
(ID = 1.5 A, TJ = 100°C)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc)
Vdc
Ohm
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 V, VGS = 0,
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS*
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 250 V, ID ≈ 3.0 A,
RG = 18 Ω, RL = 83 Ω,
VGS(on) = 10 V)
Fall Time
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
(VDS = 400 V, ID = 3.0 A,
VGS = 10 V)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS*
Forward On−Voltage
Forward Turn−On Time
Reverse Recovery Time
(IS = 3.0 A)
(IS = 3.0 A, di/dt = 100 A/μs)
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Ld
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
Ls
* Indicates Pulse Test: Pulse Width = 300 μs Max, Duty Cycle ≤ 2.0%.
** Limited by circuit inductance.
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3
nH
MTP3N50E
VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)
TYPICAL ELECTRICAL CHARACTERISTICS
6
I D, DRAIN CURRENT (AMPS)
TJ = 25°C
5
VGS = 10 V
7V
4
6V
3
2
1
0
5V
4V
0
2
4
8
12
16
6
10
14
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
18
20
1.2
1
0.9
0.8
−50
5
I D, DRAIN CURRENT (AMPS)
VDS ≥ 10 V
4
3
2
100°C
0
25°C
0
TJ = −55°C
2
4
6
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
8
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
6
TJ = 100°C
4
25°C
2
−55°C
2
3
1
VGS = 0
ID = 250 μA
1.1
1
0.9
0.8
−50
0
50
100
1
Figure 4. Breakdown Voltage Variation
With Temperature
VGS = 10 V
1
125
TJ, JUNCTION TEMPERATURE (°C)
8
0
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
1.2
Figure 3. Transfer Characteristics
0
−25
Figure 2. Gate−Threshold Voltage Variation
With Temperature
VBR(DSS), DRAIN−TO−SOURCE BREAKDOWN VOLTAGE
(NORMALIZED)
Figure 1. On−Region Characteristics
1
VDS = VGS
ID = 0.25 mA
1.1
4
2.5
VGS = 10 V
ID = 1.5 A
2
1.5
1
0.5
5
−50
−25
0
25
50
75
100
125
ID, DRAIN CURRENT (AMPS)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On−Resistance versus Drain Current
Figure 6. On−Resistance versus Temperature
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1
MTP3N50E
SAFE OPERATING AREA INFORMATION
16
1 μs
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 μs
I D, DRAIN CURRENT (AMPS)
I D, DRAIN CURRENT (AMPS)
10
100 μs
1
1 ms
0.1
0.01
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10 ms
dc
12
8
TJ ≤ 150°C
4
0
1
100
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
1000
Figure 7. Maximum Rated Forward Biased
Safe Operating Area
60
500
100
200
300
400
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Maximum Rated Switching
Safe Operating Area
applicable for both turn−on and turn−off of the devices for
switching times less than one microsecond.
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain−to−source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned
on. Because these curves include the limitations of
simultaneous high voltage and high current, up to the rating
of the device, they are especially useful to designers of
linear systems. The curves are based on a case
temperature of 25°C and a maximum junction temperature
of 150°C. Limitations for repetitive pulses at various case
temperatures can be determined by using the thermal
response curves. Motorola Application Note, AN569,
“Transient Thermal Resistance−General Data and Its Use”
provides detailed instructions.
t, TIME (ns)
1000
VDD = 250 V
ID = 3 A
VGS = 10 V
TJ = 25°C
100
1
td(on)
tf
10
SWITCHING SAFE OPERATING AREA
td(off)
tr
1
The switching safe operating area (SOA) of Figure 8 is
the boundary that the load line may traverse without
incurring damage to the MOSFET. The fundamental limits
are the peak current, IDM and the breakdown voltage,
V (BR)DSS . The switching SOA shown in Figure 8 is
10
100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
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100
RGS
DUT
I , DRAIN CURRENT (AMPS)
r(t),D EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
MTP3N50E
4
3
2
1
0
−
1
0.7
0.5
0.3
IFM
+
0.1
0.07
0.05
0.03
0.02
VDS
+
0.1
20 V
−
VGS P(pk)
0.05
RθJC(t) = r(t) RθJC
RθJC = 2.5°C/W MAX
VR = 80%APPLY
OF RATED
DS
D CURVES
FOR VPOWER
VdsL =TRAIN
Vf + LSHOWN
i ⋅ dls/dt
PULSE
READ TIME AT t1
TJ(pk) − TC = P(pk) RθJC(t)
0.02
di/dt ≤ 50 A/μs
0.01
SINGLE PULSE
0.02 0.03 0.05
t1
Li
IS
0.2
0.2
0.01
0.01
0
VR
D = 0.5
t2
DUTY13.
CYCLE,
D = t1/t2
Figure
Commutating
Safe Operating Area
Test Circuit
0.1
0.2 0.3
0.5
500
100
200
300
400
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
3
1
2
600
t, TIME (ms)
5
10
20
30
50
100
V(BR)DSSResponse
Figure 10. Thermal
Figure 12. Commutating Safe Operating Area (CSOA)
200 300
500
10
Vds(t)
COMMUTATING SAFE OPERATING AREA (CSOA)
IO
15 V
The Commutating Safe Operating Area (CSOA) of
L safe operation for
Figure 12 defines the limits of
commutated source-drain
current
versus re-applied
drain
VDS
C
voltage when the source-drain diode has4700
undergone
μF
ID
forward bias. The curve shows the limitations
of VIFM and
250
peak VR for a given commutation speed. It is applicable
VDD
when waveforms similar to those of Figure 11 are present.
Full or half-bridge PWM DC motor controllers are common
applications trequiring CSOA data.
The time interval tfrr is Rthe
GS speed of the commutation
50 Ω
cycle. Device stresses increase
with commutation speed,
so t frr is specified with a minimum value. Faster
commutation
speeds
require an appropriate
of IFM,
Figure
14. Unclamped
Inductive derating
Switching
peak VR or both. Ultimately,
t
is
limited
primarily
by
device,
frr Circuit
Test
package, and circuit impedances. Maximum device stress
occurs during trr as the diode goes from conduction to
reverse blocking.
VDS(pk) is the peak drain−to−source voltage that the
device must sustain during commutation; I FM is the
maximum forward source-drain diode current just prior to
the onset of commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has
only a second order effect on CSOA.
Stray inductances, L i in Motorola’s test circuit are
assumed to be practical minimums.
VGS
0
IFM
ID(t)
90%
dls/dt
IS
trr
10%
VDD
ton
IRM
tP
t, (TIME)
0.25 IRM
V(BR)DSS
WDSR + 1 LIO2 2
V(BR)DSS–VDD
VDS(pk)
ǒ
VDS
Ǔǒ
Ǔ
VR
Figure 15. Unclamped Inductive Switching
Waveforms
dV /dt
DS
Vf
VdsL
MAX. CSOA
STRESS AREA
Figure 11. Commutating Waveforms
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6
MTP3N50E
TJ = 25°C
VGS = 0
800
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
1000
600
Ciss
400
Crss
200
Coss
VDS = 0
0
5
10
5
0
VGS
15
10
20
16
250 V
TJ = 25°C
ID = 3 A
12
400 V
8
4
0
25
VDS = 100 V
0
5
10
15
QG, TOTAL GATE CHARGE (nC)
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 16. Capacitance Variation
Figure 17. Gate Charge versus
Gate−To−Source Voltage
+18 V
VDD
1 mA
47 k
Vin
20
10 V
15 V
SAME
DEVICE TYPE
AS DUT
100 k
2N3904
0.1 μF
2N3904
100 k
47 k
100
FERRITE
BEAD
Vin = 15 Vpk; PULSE WIDTH ≤ 100 μs, DUTY CYCLE ≤ 10%
Figure 18. Gate Charge Test Circuit
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DUT
2
MTP3N50E
PACKAGE DIMENSIONS
CASE 221A−06
ISSUE Y
−T−
B
F
T
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
SEATING
PLANE
C
S
4
A
Q
1 2 3
STYLE 5:
PIN 1.
2.
3.
4.
U
H
K
Z
L
GATE
DRAIN
SOURCE
DRAIN
R
V
J
G
D
N
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−−
0.080
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
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