30 V / 7 mOhm logic level N-channel MOSFET in a SO-8FL package

NVMFS4841N
Power MOSFET
30V, 7 mW, 89A, Single N−Channel SO8FL
Features
•
•
•
•
•
•
Small Footprint (5x6 mm) for Compact Design
Low RDS(on) to Minimize Conduction Losses
Low QG and Capacitance to Minimize Driver Losses
NVMFS4841NWF − Wettable Flanks Product
AEC−Q101 Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(ON) MAX
7.0 mW @ 10 V
30 V
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
"20
V
ID
89
A
Continuous Drain Current RYJ−mb (Notes 1,
2, 3, 4)
Power Dissipation
RYJ−mb (Notes 1, 2, 3)
Continuous Drain Current RqJA (Notes 1 &
3, 4)
Power Dissipation
RqJA (Notes 1, 3)
Pulsed Drain Current
Tmb = 25°C
Steady
State
Tmb = 100°C
Tmb = 25°C
63
PD
TA = 25°C
Steady
State
Current limited by package
(Note 4)
TA = 25°C
Operating Junction and Storage Temperature
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 24 V, VGS = 10 V,
IL(pk) = 19 A, L = 1.0 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
S (1,2,3)
A
16
N−CHANNEL MOSFET
11
PD
MARKING
DIAGRAM
W
3.7
TA = 100°C
TA = 25°C, tp = 10 ms
G (4)
56
ID
TA = 100°C
TA = 25°C
D (5,6)
W
112
Tmb = 100°C
89 A
11.4 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
ID MAX
1.8
IDM
336
A
IDmaxPkg
80
A
TJ, Tstg
−55 to
175
°C
IS
51
A
EAS
180
mJ
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
D
1
DFN5
(SO−8FL)
CASE 488AA
STYLE 1
A
Y
W
ZZ
S
S
S
G
D
XXXXXX
AYWZZ
D
D
= Assembly Location
= Year
= Work Week
= Lot Traceability
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)
Parameter
Junction−to−Mounting Board (top) − Steady
State (Note 2, 3)
Junction−to−Ambient − Steady State (Note 3)
Symbol
Value
Unit
RYJ−mb
1.3
°C/W
RqJA
41
1. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
2. Psi (Y) is used as required per JESD51−12 for packages in which
substantially less than 100% of the heat flows to single case surface.
3. Surface−mounted on FR4 board using a 650 mm2, 2 oz. Cu pad.
4. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 3
1
Publication Order Number:
NVMFS4841N/D
NVMFS4841N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
25
VGS = 0 V,
VDS = 30 V
mV/°C
TJ = 25 °C
1
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
±100
mA
nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
VGS(TH)/TJ
RDS(on)
1.5
2.5
5.6
VGS = 10 V
ID = 30 A
4.7
7.0
VGS = 4.5 V
ID = 30 A
9.2
11.4
gFS
VDS = 15 V, ID = 15 A
V
mV/°C
16
mW
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
177
Total Gate Charge
QG(TOT)
11.5
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
1436
VGS = 0 V, f = 1 MHz, VDS = 12 V
VGS = 4.5 V, VDS = 15 V; ID = 30 A
348
pF
17
2.0
nC
5.0
5.1
QG(TOT)
VGS = 10 V, VDS = 15 V,
ID = 30 A
25.4
nC
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
13.5
tr
td(OFF)
VGS = 4.5 V, VDS = 15 V, ID = 15 A,
RG = 3.0 W
tf
66.5
ns
15.5
7.5
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.9
TJ = 125°C
0.8
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 30 A
1.2
V
20.5
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
QRR
11.6
10.7
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
ns
8.9
nC
NVMFS4841N
ID, DRAIN CURRENT (AMPS)
TJ = 25°C
5.5 V to 10 V
VGS = 5 V
4.5 V
4V
3.8 V
3.6 V
3.4 V
0
2
3
4
5
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
−50
TJ = 125°C
TJ = 25°C
TJ = −55°C
2
1
3
4
5
6
7
8
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 30 A
TJ = 25°C
3
VDS = 10 V
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
4
5
6
7
8
9
10
11
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0.018
0.017
0.016
0.015
0.014
0.013
0.012
0.011
0.010
0.009
0.008
0.007
0.006
0.005
1
130
120
110
100
90
80
70
60
50
40
30
20
10
0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.017
TJ = 25°C
0.014
VGS = 4.5 V
0.011
0.008
VGS = 10 V
0.005
0.002
10
15
20
25
30
35
40
45
50
55
60
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10000
ID = 30 A
VGS = 10 V
VGS = 0 V
TJ = 150°C
1000
IDSS, LEAKAGE (nA)
130
120
110
100
90
80
70
60
50
40
30
20
10
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (AMPS)
TYPICAL PERFORMANCE CURVES
TJ = 125°C
100
10
TJ = 25°C
1
0.1
−25
0
25
50
75
100
125
150
175
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
30
NVMFS4841N
TYPICAL PERFORMANCE CURVES
C, CAPACITANCE (pF)
TJ = 25°C
Ciss
1800
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
2200
2000
1600
Ciss
1400
1200
1000
800
Crss
600
Coss
400
200
0
10
Crss
5
0
5
VGS
VDS
10
15
20
30
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
IS, SOURCE CURRENT (AMPS)
t, TIME (ns)
100
tr
td(off)
1
td(on)
tf
1
9
8
7
6
5
4
VDD = 15 V
VGS = 10 V
ID = 30 A
TJ = 25°C
3
2
1
0
0
10
RG, GATE RESISTANCE (W)
VGS = 20 V
SINGLE PULSE
TC = 25°C
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
TJ = 25°C
15
10
5
0.6
0.7
0.8
0.9
1.0
Figure 10. Diode Forward Voltage vs. Current
100 ms
1 ms
10 ms
dc
10
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D, DRAIN CURRENT (AMPS)
6 8 10 12 14 16 18 20 22 24 26
QG, TOTAL GATE CHARGE (nC)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
10 ms
100
0.1
4
20
0
0.5
100
1000
1
2
VGS = 0 V
25
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
10
QGD
QGS
30
VDD = 15 V
ID = 15 A
VGS = 10 V
10
QT
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
Figure 7. Capacitance Variation
1000
12
11
10
180
160
ID = 19 A
140
120
100
80
60
40
20
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
175
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
NVMFS4841N
TYPICAL PERFORMANCE CURVES
RqJ(t) (°C/W) EFFECTIVE TRANSIENT
THERMAL RESISTANCE
100
Duty Cycle = 0.5
10
0.2
0.1
0.05
1 0.02
0.01
0.1
SINGLE PULSE
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
t, PULSE TIME (s)
Figure 13. FET Thermal Response
DEVICE ORDERING INFORMATION
Device
NVMFS4841NT1G
NVMFS4841NWFT1G
NVMFS4841NT3G
NVMFS4841NWFT3G
Marking
Package
Shipping†
V4841
DFN5
(Pb−Free)
1500 / Tape & Reel
4841WF
DFN5
(Pb−Free)
1500 / Tape & Reel
V4841
DFN5
(Pb−Free)
5000 / Tape & Reel
4841WF
DFN5
(Pb−Free)
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NVMFS4841N
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE H
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
2
A
B
D1
2X
0.20 C
4X
E1
2
1
2
3
q
E
c
A1
4
TOP VIEW
C
3X
e
0.10 C
SIDE VIEW
8X
DETAIL A
3X
0.05
c
4X
1.270
0.750
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.15 BSC
4.70
4.90
5.10
3.80
4.00
4.20
6.15 BSC
5.70
5.90
6.10
3.45
3.65
3.85
1.27 BSC
0.51
0.61
0.71
1.20
1.35
1.50
0.51
0.61
0.71
0.05
0.17
0.20
3.00
3.40
3.80
0_
−−−
12 _
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
SOLDERING FOOTPRINT*
b
C A B
SEATING
PLANE
DETAIL A
A
0.10 C
0.10
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
4X
1.000
e/2
L
1
0.965
4
K
1.330
2X
0.905
2X
PIN 5
(EXPOSED PAD)
G
E2
L1
M
0.495
4.530
3.200
0.475
D2
2X
1.530
BOTTOM VIEW
4.560
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NVMFS4841N/D
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