30 V, 11.7 A, N-Channel, SO-8

NTMS4873NF
Power MOSFET
30 V, 11.5 A, N−Channel, SO−8
Features
•
•
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Includes SyncFET Schottky Diode
Optimized Gate Charge to Minimize Switching Losses
SOIC−8 Surface Mount Package Saves Board Space
This is a Pb−Free Device
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V(BR)DSS
RDS(ON) MAX
12 mW @ 10 V
30 V
Applications
N−Channel
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Drain−to−Source Voltage
Gate−to−Source Voltage
Symbol
Value
Unit
VDSS
30
V
VGS
±20
V
ID
8.9
A
Continuous Drain
Current RqJA (Note 1)
TA = 25°C
Power Dissipation RqJA
(Note 1)
TA = 25°C
PD
1.39
W
Continuous Drain
Current RqJA (Note 2)
TA = 25°C
ID
7.1
A
PD
0.87
Steady
State
ID
W
TA = 25°C
Power Dissipation
RqJA, t v 10 s(Note 1)
TA = 25°C
PD
TA = 25°C, tp = 10 ms
IDM
56
A
TJ,
Tstg
−55 to
150
°C
TA = 70°C
Operating Junction and Storage Temperature
11.5
A
9.2
Source Current (Body Diode)
Single Pulse Drain−to−Source Avalanche Energy
(TJ = 25°C, VDD = 30 V, VGS = 10 V,
IL = 11 Apk, L = 1 mH, RG = 25 W)
2.31
W
IS
3.3
A
EAS
60.5
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
260
°C
TL
Symbol
Value
Unit
Junction−to−Ambient – Steady State (Note 1)
RqJA
89.9
°C/W
Junction−to−Ambient – t v 10 s (Note 1)
RqJA
54.2
Junction−to−Foot (Drain)
RqJF
35.6
Junction−to−Ambient – Steady State (Note 2)
RqJA
143
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
S
MARKING DIAGRAM/
PIN ASSIGNMENT
5.7
Continuous Drain
Current RqJA, t v 10 s
(Note 1)
Pulsed Drain Current
G
7.2
TA = 70°C
TA = 25°C
D
1
SO−8
CASE 751
STYLE 12
Source
Source
Source
Gate
1
8
4873NF
AYWWG
G
Power Dissipation RqJA
(Note 2)
TA = 70°C
11.5 A
15 mW @ 4.5 V
• Synchronous FET for DC−DC Converters
• Low Side Notebook Non−VCORE Converters
Parameter
ID MAX
Drain
Drain
Drain
Drain
Top View
4873NF = Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
NTMS4873NFR2G
Package
Shipping†
SO−8
2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surfacemounted on FR4 board using 1 sq−in pad, 2 oz Cu.
2. Surfacemounted on FR4 board using the minimum recommended pad size.
© Semiconductor Components Industries, LLC, 2009
January, 2009 − Rev. 1
1
Publication Order Number:
NTMS4873NF/D
NTMS4873NF
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
V
10
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
IGSS
VGS = 0 V, VDS = 24 V
VDS = 0 V, VGS = ±20 V
TJ = 25°C
VGS(TH)
VGS = VDS, ID = 250 mA
mV/°C
250
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
Forward Transconductance
1.45
6
gFS
mV/°C
VGS = 10 V, ID = 10 A
9
12
VGS = 4.5 V, ID = 8.5 A
12
15
VDS = 1.5 V, ID = 10 A
22
mW
S
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
VGS = 0 V, f = 1.0 MHz, VDS = 15 V
1275
1900
345
525
Crss
145
225
Total Gate Charge
QG(TOT)
10.5
16
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 15 V, ID = 10 A
VGS = 10 V, VDS = 15 V, ID = 10 A
pF
nC
1.3
3.7
6.0
3.9
6.5
21.4
32
nC
9.8
16
ns
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(on)
tr
td(off)
3.8
7.0
22.3
45
14.3
25
TJ = 25°C
0.55
0.7
V
TJ = 125°C
0.5
20
35
ns
9.5
15
VGS = 10 V, VDS = 15 V,
ID = 1.0 A, RG = 6.0 W
tf
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
Discharge Time
VSD
VGS = 0 V, IS = 3.5 A
tRR
ta
10.6
20
QRR
9.0
14
Source Inductance
LS
0.66
nH
Drain Inductance
LD
0.20
nH
Gate Inductance
LG
1.5
nH
Gate Resistance
RG
Reverse Recovery Charge
tb
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 10 A
nC
PACKAGE PARASITIC VALUES
TA = 25°C
1.5
3. Pulse Test: pulse width = 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
3.0
W
NTMS4873NF
TYPICAL CHARACTERISTICS
ID, DRAIN CURRENT (A)
20
VDS ≥ 10 V
VGS = 3.2 V
3.5 V
15
3V
10
2.8 V
5
2.6 V
2.4 V
0
0.5
1.0
1.5
2.0
TJ = 125°C
1
1.5
2
2.5
3
3.5
4
Figure 2. Transfer Characteristics
0.025
0.015
4
5
6
7
8
9
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
4.5
0.015
TJ = 25°C
VGS = 4.5 V
0.013
0.011
0.009
VGS = 10 V
0.007
0.005
2.5
7.5
12.5
17.5
22.5
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100 M
1.5
ID = 11.5 V
VGS = 10 V
VGS = 0 V
1.3
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
TJ = −55°C
Figure 1. On−Region Characteristics
0.035
1.4
TJ = 25°C
10
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID = 10 A
3
20
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.045
0.005
30
0
2.5
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
40
5V
4.5 V
4.2 V
4V
10 V
ID, DRAIN CURRENT (A)
25
TJ = 125°C
10 M
1.2
1.1
1.0
0.9
TJ = 100°C
1M
0.8
0.7
−50
−25
0
25
50
75
100
125
150
0.1 M
2.5
TJ, JUNCTION TEMPERATURE (°C)
7.5
12.5
17.5
22.5
27.5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NTMS4873NF
TYPICAL CHARACTERISTICS
1750
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
VGS = 0 V
TJ = 25°C
1500
Ciss
1250
1000
750
500
Coss
250
Crss
0
0
5
10
15
20
25
30
4
2
0
ID = 10 A
TJ = 25°C
0
4
8
12
16
20
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
6
IS, SOURCE CURRENT (A)
t, TIME (ns)
Qgd
Figure 7. Capacitance Variation
td(off)
tf
tr
10
td(on)
1
10
VGS = 0 V
TJ = 25°C
5
4
3
2
1
0
100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
EAS, SINGLE PULSE DRAIN−TO−
SOURCE AVALANCHE ENERGY (mJ)
100
10 ms
−ID, DRAIN CURRENT (A)
Qgs
Qg, TOTAL GATE CHARGE (nC)
100
100 ms
10
1 ms
1
0.01
VGS
6
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VDD = 15 V
ID = 1 A
VGS = 10 V
0.1
QT
8
1000
1
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
10
2000
10 ms
VGS = 20 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
dc
10
100
60
ID = 11 A
50
40
30
20
10
0
25
50
75
100
125
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
150
NTMS4873NF
TYPICAL CHARACTERISTICS
R(t) (°C/W)
100
50% Duty Cycle
20%
10 10%
5%
2%
1
1%
0.1
0.01
Single Pulse
0.001
0.0000001 0.000001
0.00001
0.0001
0.01
0.001
0.1
1
PULSE TIME (sec)
Figure 13. Thermal Response − RqJA at Steady State (1 inch sq pad)
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5
10
100
1000
NTMS4873NF
PACKAGE DIMENSIONS
SOIC−8
CASE 751−07
ISSUE AJ
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
1.52
0.060
7.0
0.275
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTMS4873NF/D
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