30 V, 41 A, Single N Channel, SO 8 FL

NTMFS4943N
Power MOSFET
30 V, 41 A, Single N−Channel, SO−8 FL
Features
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• CPU Power Delivery
• DC−DC Converters
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V(BR)DSS
RDS(ON) MAX
7.2 mW @ 10 V
30 V
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
14
A
TA = 25°C
Continuous Drain
Current RqJA
(Note 1)
ID
TA = 100°C
TA = 25°C
PD
2.6
W
Continuous Drain
Current RqJA ≤
10 s (Note 1)
TA = 25°C
ID
23
A
Continuous Drain
Current RqJA
(Note 2)
TA = 100°C
TA = 25°C
Steady
State
TA = 25°C
PD
ID
TA = 100°C
6.83
8.3
5.2
0.91
W
Continuous Drain
Current RqJC
(Note 1)
TC = 25°C
ID
41
A
Power Dissipation
RqJC (Note 1)
TC = 25°C
PD
22.3
W
TA = 25°C, tp = 10 ms
IDM
125
A
IDmax
100
A
TJ,
TSTG
−55 to
+150
°C
IS
20
A
Drain to Source DV/DT
dV/dt
8.0
V/ns
Single Pulse Drain−to−Source Avalanche
Energy TJ = 25°C, VDD = 30 V, VGS = 10 V,
IL = 25 Apk, L = 0.1 mH, RG = 25 W
EAS
31
mJ
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
TC = 85°C
Operating Junction and Storage
Temperature
Source Current (Body Diode)
26
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
© Semiconductor Components Industries, LLC, 2012
June, 2012 − Rev. 3
N−CHANNEL MOSFET
MARKING
DIAGRAM
D
A
PD
TA = 25°C
S (1,2,3)
W
TA = 25°C
Current Limited by Package
G (4)
14.3
Power Dissipation
RqJA (Note 2)
Pulsed Drain
Current
D (5,6)
8.7
Power Dissipation
RqJA (Note 1)
Power Dissipation
RqJA ≤ 10 s
(Note 1)
41 A
11 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
ID MAX
1
1
SO−8 FLAT LEAD
CASE 488AA
STYLE 1
A
Y
W
ZZ
S
S
S
G
D
4943N
AYWZZ
D
D
= Assembly Location
= Year
= Work Week
= Lot Traceability
ORDERING INFORMATION
Device
Package
Shipping†
NTMFS4943NT1G
SO−8 FL
(Pb−Free)
1500 /
Tape & Reel
NTMFS4943NT3G
SO−8 FL
(Pb−Free)
5000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTMFS4943N/D
NTMFS4943N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Junction−to−Case (Drain)
Parameter
RqJC
5.6
Junction−to−Ambient – Steady State (Note 3)
RqJA
49.1
Junction−to−Ambient – Steady State (Note 4)
RqJA
137.2
Junction−to−Ambient – (t ≤ 10 s) (Note 3)
RqJA
18.3
Unit
°C/W
3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
V
Drain−to−Source Breakdown Voltage
(transient)
V(BR)DSSt
VGS = 0 V, ID(aval) = 10.5 A,
Tcase = 25°C, ttransient = 100 ns
34
V
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Parameter
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
15
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.2
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
VGS(TH)/TJ
RDS(on)
1.66
4.0
VGS = 10 V
VGS = 4.5 V
Forward Transconductance
1.2
gFS
ID = 30 A
5.8
ID = 15 A
5.8
ID = 30 A
8.2
ID = 15 A
8.2
VDS = 1.5 V, ID = 15 A
mV/°C
7.2
11
32
mW
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
1401
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Capacitance Ratio
CRSS /
CISS
Total Gate Charge
QG(TOT)
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
VGS = 0 V, f = 1 MHz, VDS = 15 V
446
pF
16
VGS = 0 V, VDS = 15 V, f = 1 MHz
0.011
0.023
9.2
VGS = 4.5 V, VDS = 15 V; ID = 30 A
2.7
4.4
nC
1.9
QG(TOT)
VGS = 10 V, VDS = 15 V; ID = 30 A
20.9
nC
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
11
tr
td(OFF)
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
31
18
3.0
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
ns
NTMFS4943N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
8.0
tr
td(OFF)
VGS = 10 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
21
ns
21
2.1
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.9
TJ = 125°C
0.8
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 30 A
1.1
V
23
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
12.5
ns
10.5
QRR
10
nC
Source Inductance
LS
0.93
nH
Drain Inductance
LD
0.005
nH
Gate Inductance
LG
1.84
nH
Gate Resistance
RG
PACKAGE PARASITIC VALUES
TA = 25°C
1.1
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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3
2.0
W
NTMFS4943N
TYPICAL CHARACTERISTICS
4.2 V
7V
80
TJ = 25°C
3.8 V
3.6 V
60 4.5 V
3.4 V
50
40
3.2 V
30
3.0 V
20
2.8 V
10
2.6 V
2.4 V
0
0
1
2
3
60
50
40
20
TJ = 125°C
10
0
1.0
4
TJ = −55°C
1.5
2.5
2.0
3.0
3.5
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 30 A
TJ = 25°C
0.013
0.012
0.011
0.010
0.009
0.008
0.007
0.006
4.0
5.0
6.0
7.0
8.0
9.0
VGS (V)
10
TJ = 25°C
0.011
0.010
0.009
VGS = 4.5 V
0.008
0.007
VGS = 10 V
0.006
0.005
0.004
20
30
40
50
60
70
80
ID, DRAIN CURRENT (A)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10,000
IDSS, LEAKAGE (nA)
1.9
1.8 ID = 30 A
1.7 VGS = 10 V
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
−50 −25
0
4.0
0.012
Figure 3. On−Resistance vs. VGS
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
TJ = 25°C
30
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.014
0.005
3.0
VDS = 10 V
70
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (A)
70
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
4.0 V
10 V
ID, DRAIN CURRENT (A)
80
VGS = 0 V
TJ = 150°C
1000
TJ = 125°C
100
TJ = 85°C
25
50
75
100
125
150
10
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
30
NTMFS4943N
TYPICAL CHARACTERISTICS
C, CAPACITANCE (pF)
1600
VGS = 0 V
TJ = 25°C
Ciss
1400
VGS, GATE−TO−SOURCE VOLTAGE (V)
1800
1200
1000
800
Coss
600
400
200
0
Crss
0
5
10
15
20
25
30
IS, SOURCE CURRENT (A)
t, TIME (ns)
Qgd
4
Qgs
3
VDD = 15 V
VGS = 10 V
ID = 30 A
2
1
0
0
2
4
8
6
10
12
14
16
18
20
VGS = 0 V
td(off)
td(on)
10
1
10
25
20
TJ = 125°C
15
10
5
TJ = 25°C
0
0.4
100
0.5
0.6
0.7
0.8
0.9
1.0
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
EAS, SINGLE PULSE DRAIN−TO−
SOURCE AVALANCHE ENERGY (mJ)
ID, DRAIN CURRENT (A)
6
5
30
tr
VGS = 20 V
Single Pulse
TC = 25°C
100 ms
10
1 ms
0.1
TJ = 25°C
7
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
tf
1
8
Figure 7. Capacitance Variation
100
100
9
Qg, TOTAL GATE CHARGE (nC)
VDD = 15 V
ID = 15 A
VGS = 10 V
1000
QT
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1000
1
11
10
10 ms
dc
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
10
100
35
ID = 25 A
30
25
20
15
10
5
0
25
50
75
100
125
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
150
NTMFS4943N
TYPICAL CHARACTERISTICS
100
1
Duty Cycle = 50%
20%
10%
5%
2%
1%
0.1
Single Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.1
0.01
1
10
PULSE TIME (sec)
Figure 13. Thermal Response
70
60
50
GFS (S)
R(t) (°C/W)
10
40
30
20
10
0
0
10
20
30
40
50
ID (A)
Figure 14. GFS vs. ID
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6
60
70
80
100
1000
NTMFS4943N
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA
ISSUE G
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
2
A
B
D1
2X
0.20 C
4X
E1
2
3
q
E
2
1
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
c
A1
4
TOP VIEW
C
3X
e
0.10 C
SEATING
PLANE
DETAIL A
A
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
0.10 C
SIDE VIEW
SOLDERING FOOTPRINT*
DETAIL A
3X
8X
0.10
C A B
0.05
c
4X
e/2
1
4
0.965
K
G
0.750
1.000
L
PIN 5
(EXPOSED PAD)
4X
1.270
b
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.15 BSC
4.50
4.90
5.10
3.50
−−−
4.22
6.15 BSC
5.50
5.80
6.10
3.45
−−−
4.30
1.27 BSC
0.51
0.61
0.71
1.20
1.35
1.50
0.51
0.61
0.71
0.05
0.17
0.20
3.00
3.40
3.80
0_
−−−
12 _
1.330
2X
0.905
2X
E2
L1
M
0.495
4.530
3.200
0.475
D2
2X
BOTTOM VIEW
1.530
4.560
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTMFS4943N/D
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