AND8345/D WDFN6 2x2 mCoolt 506AN Dual MOSFET Package Board Level Application Notes and Thermal Performance http://onsemi.com Prepared by: Anthony M. Volpe ON Semiconductor APPLICATION NOTE Introduction Figure 3 depicts a minimum recommended pad pattern that confines an improved thermal area of drain connections (pins 3, 6) to the basic footprint. Increased drain copper areas assist in directing the power dissipation path through the copper lead−frame and into the board. The addition of vias to other board layers further enhances device performance. An evaluation board containing the minimum recom− mended pad pattern and aforementioned vias is shown in Figure 4 of the subsequent section. New ON Semiconductor mCoolt MOSFETs in a WDFN6 2x2 506AN package are thermally enhanced and remarkably small to exclusively address power management challenges in portable devices such as synchronous buck and boost circuits, high and low side load switches, and lithium−ion battery charging circuits. This technical note discusses the dual site WDFN6 506AN device package overview, pad patterns, evaluation board layout and thermal performance. Package Overview The WDFN6 platform offers a versatility which allows either a single or dual semiconductor device to be implemented within a leadless package. Figure 1 illustrates a dual site WDFN6 semiconductor device package and pin−out description. A half etch lead−frame complements mold lock features allowing this leadless package to provide exposed drain pads for excellent thermal conduction and reduced electrical parasitics. This low profile (< 0.8 mm) compact design is similar to the popular DFN/QFN package allowing for an easy fit in thin environments. Suggested guidelines for mounting criteria on a printed circuit board are outlined in application note AND8211/D, “Board Level Application Notes for DFN and QFN Packages”. 6 1 Figure 2. Basic Pad Layout STYLE 1: PIN 1. SOURCE 1 2. GATE 1 3. DRAIN 2 4. SOURCE 2 5. GATE 2 6. DRAIN 1 Figure 1. The Underside of a Dual−Chip 6 Pin WDFN Package Basic Pad Patterns A recommended solder−mask defined mounting footprint is defined in Figure 2. mCoolt MOSFET 2 mm x 2 mm footprint dimensions are the same as a standard SC−88 and SC−70−6 package. However, the underside of this WDFN6 package offers an added feature of exposed flags acting as drain contacts and heat dissipation paths to promote operation at a lower junction temperature. This correlation is further explained in the thermal response section. © Semiconductor Components Industries, LLC, 2008 November, 2008 − Rev. 0 Figure 3. Minimum Recommended Pad Pattern 1 Publication Order Number: AND8345/D AND8345/D Evaluation Board The evaluation board, shown in Figure 4, measures 0.6 x 0.5 inch. The board contains 1 oz copper thickness on top−side and 1 oz copper thickness on the underside. Vias are added through to the underside of the board where contact is made with a copper pad area of approximately 0.198 square inch. On top−side, the copper pad areas surrounding the two drain leads are each increased to approximately 0.034 square inch. Front of Board Figure 5. Mounted Device Back of Board Figure 4. Evaluation Board This 6−pin DIP design allows the use of sockets to assist in testing. Figure 5 represents a WDFN6 506AN package mounted on the evaluation board with and without test sockets. A quick thermal analysis of this board is conducted by inducing a saturation current in Q1 while keeping Q2 off. The saturation current of 815 mA is induced by using a 5 W source−load, shorting gate to source and holding the drain potential at a constant 5.082 V. This delivers an approximate 4.1 W to Q1 which yields a junction temperature of 85.4°C and a board temperature of 52.8°C. Figure 6 shows a thermal image of this board under the aforementioned conditions. Figure 6. Thermal Image of Mounted Device Further results from the measured thermal performance of this package are described in the subsequent section. Testing included a thermal analysis of the package surface mounted on a FR4 board using one−inch square pad size and the minimum recommended pad size. http://onsemi.com 2 AND8345/D Thermal Performance Assumptions and Definitions The number designation associated with “foot” in the subscript of each Y (read psi) term corresponds to the pin identification number as shown in Figure 7. The subsequent sections outline the thermal performance of a WDFN6 506AN package. All values and equations are obtained from simulations and pertain to the Theta(DC) matrix with both MOSFETs operating at maximum power unless otherwise specified. A 10% duty cycle is arbitrarily chosen to evaluate various thermal responses. Refer to Figure 11 for thermal responses at varying duty cycles. The simulation models used to derive the results in this section are modeled around results obtained from physical testing and are considered reliable. Table 1 defines a set of parameters used throughout this section. Table 1. Thermal Analysis Parameters Symbol TJn TAMB PDn Definition Figure 7. Foot and Junction Identification Junction Temperature of MOSFET “n” Figures 8 and 9 represent Cauer and Foster Ladders respectively. This technical note assumes the reader has a general understanding of these networks. Please refer to the documentation cited under references for detailed descriptions of thermal RC networks. In this section, the Foster network is used to calculate various thermal characteristics. For example, as seen in Figure 9, a particular thermal resistance occurs between junction “n” and some location “L” (denoted here as YJn−L). Let the thermal resistance, at the C1/C2 node, be measured from Junction “n” to foot “n”. Then, that resistance is called a junction−to−foot thermal reference (YJn−Fn). Therefore, in the case of junction−to−C2/C3 node, the junction−to− ambient thermal resistance (Rq−JnA) is measured as the sum of thermal references such that, Ambient Temperature Power Dissipation of MOSFET “n” PTOTAL Total Power Dissipation Rq−JnL Thermal Resistance from Junction “n” to Location “L” R(u)EFF Effective (maximum) Thermal Resistance of Package YQXQY Thermal Resistance of FET “x” due to FET “y” YFn−L Thermal Reference between Foot “n” and location “L” YJn−L Thermal Reference between Junction “n” and location “L” R q−JnA + Y Jn−Fn ) Y Fn−A Figure 8. Grounded Capacitor Thermal Network (“Cauer” Ladder) Figure 9. Non−Grounded Capacitor Thermal Network (“Foster” Ladder) http://onsemi.com 3 (eq. 1) AND8345/D Junction−to−Foot / Foot−to−Ambient Junction−to−Ambient The Foster Network junction−to−foot thermal references and foot−to−ambient thermal references are outlined in Table 2. The thermal response of this package is parameterized by thermal interactions between adjacent MOSFETS. Switching one device OFF, such as Q1, alters the junction temperature and thermal resistance of each FET. Heat from Q2 will transfer to Q1 causing Q1 to exhibit an added thermal resistance equivalent to a factor of YQ1Q2. The following matrix equation illustrates the aforementioned relationships for a junction−to−ambient thermal response; Table 2. Thermal Reference Parameters Junction−to−Foot 10% Duty Cycle Min−pad Size 1 in sq. Pad Copper Area 30 mm2 [2 oz] 1.127 in2 [2 oz] YJ1−F2 30.2 °C/W 27.8 °C/W YJ1−F3 94.7 °C/W 69.3 °C/W NJ Nj ƪ T J1 T J2 Foot−to−Ambient 10% Duty Cycle Min−pad Size 1 in sq. Pad Copper Area 30 mm2 [2 oz] 1.127 in2 [2 oz] YF2−A 209.7 °C/W 80.4 °C/W YF3−A 145.2 °C/W 38.9 °C/W + ƫNJ Nj R q−J1A Y Q1Q2 Y Q2Q1 R q−J2A P D1 P D2 ) T AMB (eq. 4) Using data from Table 3, this matrix allows various junction temperatures and, in turn, the package R(u)EFF to be calculated at assumed ambient temperatures. R(u)EFF is defined as, R(u) EFF + ƪT MAX * T AMBƫ ń P TOTAL Where R(u)EFF is a function of either direct current or a transient response and TMAX is the maximum junction temperature between TJ1 and TJ2. Table 3 outlines the junction−to−ambient thermal analysis of the WDFN6 506AN package surface mounted on an FR4 board. Notice that Rq−J1A = Rq−J2A and YQ1Q2 = YQ2Q1 due to symmetrical die sizes. Furthermore, Quick reference steady state matrices are located in the Appendix. Note: * Refer to the Appendix for Theta(t) matrix equations. A relationship for the thermal resistance (Rq−JnA) of each device is established by using either of the following relationships, R q−J1A + Y J1−F2 ) Y F2−A (eq. 2) R q−J1A + Y J1−F3 ) Y F3−A (eq. 3) (eq. 5) Substituting appropriate values, from Table 2, into the above equations yields Rq−J1A = Rq−J2A = 108.2°C/W for the one−inch square pad size and Rq−J1A = Rq−J2A = 239.9°C/W for min pad size. In both cases the thermal resistances of each device are directly proportional to each other due to symmetrical die sizes. Table 3. Junction−to−Ambient Thermal Response Steady State 10% Duty Cycle 1 in sq. Pad Copper area in2 1.127 [2 oz] Pulsed Time = 5 seconds Min−pad Size 30 mm2 1 in sq. Pad 1.127 in2 [2 oz] [2 oz] PD1 = PD2 1.50 W 0.71 W 2.3 W TAMB 25.0°C 25.0°C 25.0°C Rq−J1A = Rq−J2A 108.21°C/W 239.94°C/W 108.21°C/W* YQ1Q2 = YQ2Q1 51.85°C/W 158.8°C/W 51.85°C/W* TJ1 TJ2 TJ (single pulse) 393.1°C* 265.1°C 308.1°C 228.4°C TJ (pulsed) 244.8°C R(DC)EFF 80.0°C/W R(t)EFF 80.0°C/W 199.4°C/W 44.2°C/W* Junction−to−Board A matrix equation defining junction temperatures for assumed board temperatures is defined by Equation 6. NJ Nj ƪ T J1 T J2 + Y J1−F2 (Y Q1Q2 * Y F3−A) (Y Q2Q1 * Y F3−A) Y J1−F2 http://onsemi.com 4 ƫNJ Nj P D1 P D2 ) T BOARD (eq. 6) AND8345/D Data from Table 2 and Table 3 can be used with Equation 6 to calculate various junction temperatures at assumed board temperatures. Table 4 outlines the junction-to-board thermal analysis of a WDFN6 506AN package surface mounted on an FR4 board. Furthermore, Quick reference steady state matrices are located in the Appendix. Table 4. Junction−to−Board Thermal Response Steady State Pulsed Time = 5 seconds 10% Duty Cycle 1 in sq. Pad Min−pad Size 1 in sq. Pad Cu area 1.127 in2 [2 oz] 30 mm2 [2 oz] 1.127 in2 [2 oz] PD1 = PD2 1.50 W 0.71 W 1.50 W TAMB 25.0°C 25.0°C 25.0°C TBOARD (DC) 204.0°C 277.0°C 204.0°C TBOARD (t)* 223.4°C 286.7°C 138.3°C 265.1°C 308.1°C R(DC)EFF(BOARD) 59.7°C/W 177.5°C/W 59.7°C/W R(t)EFF(BOARD)* 66.1°C/W 184.3°C/W 37.8°C/W TJ (single pulse) TJ (pulsed) 157.6°C 168.4°C Summary Figure 10 illustrates a steady state plot of the change in thermal resistance and max power dissipation that occurs with a change in the amount of copper spread across a given area. Evaluating the plots at the minimum recommended pad size and one−inch square pad size yields the following maximum values; Table 5. Maximum Ratings from Figure 10 10% Duty Cycle Cu area Min−pad Size 30 mm2 [1 oz] 1 in sq. Pad 30 mm2 [2 oz] 1.127 in2 [1 oz] 1.127 in2 [2 oz] Rq−J1A 279.1°C/W 239.9°C/W 132.7°C/W 108.2°C/W Max Power 0.448 W 0.521 W 0.942 W 1.16 W Figure 11 illustrates the packages change in effective thermal resistance with respect to pulse time. The plot reflects data sampled at a minimum recommended pad size (2 oz. Cu). Under steady state conditions the plot yields R(t)EFF = 199.38°C/W. Maintaining steady state conditions and increasing the copper area to 1.0 square inch, 2 oz Cu, will yield R(t)EFF = 79.99°C/W. These results show that this package exhibits more efficient thermal characteristics than the aforementioned SC−88 package. Although a SC−88 package carries the same footprint dimensions as a WDFN6 506AN, the minimum recommended pad size plot evaluated under steady state conditions yields R(t)EFF = 328.0°C/W. The decreased thermal resistance of a WDFN6 506AN package is attributed to the exposed flags acting as drain contacts and heat dissipation paths. http://onsemi.com 5 AND8345/D 330 1.3 Power curve with PCB cu thk 2.0 oz 280 1.1 1 230 0.9 0.8 T_ambient 25°C 180 Max Power (W) Power curve with PCB cu thk 1.0 oz RqJA (°C/W) 1.2 0.7 Theta JA curve with PCB cu thk 1.0 oz 0.6 130 0.5 Theta JA curve with PCB cu thk 2.0 oz 0.4 80 0 100 200 300 400 500 600 700 800 COPPER HEAT SPREADER AREA (mm2) Figure 10. Self Heating Thermal Characteristics as a Function of Copper Area on the PCB 1000 100 @50% Duty Cycle 20% 10% R(t)EFF (°C/W) 10 5% 2% 1% 1 0.1 Single Pulse 0.01 Psi LA(t) 0.001 0.000001 0.00001 0.0001 0.001 0.01 0.1 PULSE TIME (sec) 1 Figure 11. Thermal Response Minimum Pad Size http://onsemi.com 6 10 100 1000 AND8345/D REFERENCES 1. R.P. Stout, D.T. Billings, “How to Extend a Thermal−RC−Network Model (Derived From Experimental Data) to Respond to an Arbitrarily Fast Input,” On Semiconductor, 2006. 2. R.P. Stout, “Thermal RC Ladder Networks; Packaging Technology Development,” On Semiconductor, 2006. 3. R.P. Stout, “General Thermal Transient RC Networks,” On Semiconductor, 2006. APPENDIX Steady State Junction−to−Ambient Quick Reference Matrix (2 oz. Cu), 10% DC NJ Nj T J1 T J2 Steady State Junction−to−Board Quick Reference Matrix (2 oz. Cu), 10% DC. Min Pad Size ƫNJ0.71 0.71Nj ) T ƪ 239.94 158.82 + 158.82 239.94 NJ Nj T J1 T J2 NJ Nj 51.85 1.5 ƪ108.21 51.85 108.21ƫNJ1.5Nj ) T T J1 T J2 Junction−to−Ambient Theta(t) Matrix Equations ȍ Y(tn)J−A n+1 ȍ R(tn)q−J1A n+1 NJ Nj ƪ T J1 T J2 + One−inch square Pad ƫNJ1.5 1.5Nj ) T ƪ 80.4 38.91 + 38.91 80.4 BOARD m [1 * exp(−t pulseńt n)] YȀ QXQY + (eq. 7) m RȀ q−J1A + BOARD Junction−to−Board Theta(t) Matrix Equations m YȀ QXQY + 209.7 145.24 + 145.24 209.7 NJ Nj AMB ƫNJ0.71 0.71Nj ) T ƪ T J1 T J2 AMB One−inch Square Pad + Min Pad Size ȍ Y(tn)J−A n+1 [1 * exp(−t pulseńt n)] (eq. 10) m [1 * exp(−t pulseńt n)] ƫNJ Nj RȀ q−J1A YȀ Q1Q2 YȀ Q2Q1 RȀ q−J2A P D1 P D2 ) T AMB RȀ q−J1A + (eq. 8) ȍ Y(tn)F2−A n+1 NJ Nj ƪ T J1 T J2 (eq. 9) http://onsemi.com 7 + [1 * exp(−t pulseńt n)] ƫNJ Nj RȀ q−J1A YȀ Q1Q2 YȀ Q2Q1 RȀ q−J2A P D1 P D2 (eq. 11) ) T BOARD (eq. 12) AND8345/D PACKAGE DIMENSIONS WDFN6 2x2 CASE 506AN−01 ISSUE C D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A B ÍÍÍ ÍÍÍ ÍÍÍ E PIN ONE REFERENCE DIM A A1 A3 b D D2 E E2 e K L J 0.10 C 2X 2X 0.10 C A3 0.10 C MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.25 0.35 2.00 BSC 0.57 0.77 2.00 BSC 0.90 1.10 0.65 BSC 0.25 REF 0.30 0.20 0.15 REF A 6X 0.08 C A1 C D2 D2 6X e L 1 SEATING PLANE SOLDERMASK DEFINED MOUNTING FOOTPRINT 4X 3 2.30 6X 0.43 2X E2 6X 0.35 1 6X K 6 6X 4 J BOTTOM VIEW b 0.65 PITCH 6X 0.10 C A 0.05 C B NOTE 3 0.25 2X 0.72 1.05 DIMENSIONS: MILLIMETERS mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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