AND8380/D WDFN6 2x2 506AP Single MOSFET Package Board Level Application Notes and Thermal Performance www.onsemi.com APPLICATION NOTE Introduction promotes a decrease of inductance. A drain copper area of 2.39 sq. mm assists in directing the power dissipation path through the copper lead−frame and into the board. The addition of vias to other board layers further enhances device performance. An evaluation board containing the minimum recommended pad pattern and aforementioned vias is shown in Figure 4 of the subsequent section. New ON Semiconductor MOSFETs in a WDFN6 2x2 506AP package are thermally enhanced and remarkably small to exclusively address power management challenges in portable devices such as synchronous buck and boost circuits, high and low side load switches, and lithium−ion battery charging circuits. This technical note discusses the single−channel WDFN6 506AP package overview, pad patterns, evaluation board layout and thermal performance. Package Overview Figure 1 illustrates a single site WDFN6 semiconductor device package and pin−out description. A half etch lead−frame complements mold lock features allowing this leadless package to provide an exposed drain pad for excellent thermal conduction and reduced electrical parasitics. The low profile (< 0.8 mm) compact design is similar to the popular DFN/QFN package allowing for an easy fit in thin environments. Suggested guidelines for mounting criteria on a printed circuit board (PCB) are outlined in application note AND8211/D. STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN Figure 2. Basic Pad Layout Figure 1. The Underside of a Single−Chip 6 Pin WDFN Package Basic Pad Pattnes A recommended solder−mask defined mounting footprint is defined in Figure 2. The WDFN6 506AP footprint dimensions are the same as a standard SC−88 and SC−70−6 package. However, the underside of the 506AP package offers the added feature of an exposed flag acting as a drain contact and heat dissipation path to promote operation at a lower junction temperature. Figure 3 depicts a minimum recommended pad pattern that confines an improved thermal area of drain connections (Pins 1, 2, 5, 6) to the basic footprint. In addition, increasing the contact area of the exposed source to include Pin 4 © Semiconductor Components Industries, LLC, 2016 May, 2016 − Rev. 1 Figure 3. Minimum Recommended Pad Pattern 1 Publication Order Number: AND8380/D AND8380/D Evaluation Board The evaluation board, shown in Figure 4, measures 0.6 x 0.5 inch. The board contains 1 oz. copper thickness on top−side and 1 oz. copper thickness on the underside. Vias are added through to the underside of the board where contact is made with a copper pad area of approximately board size dimensions. On top−side, the copper pad area surrounding the four drain leads is increased to approximately 0.0544 square inch resulting in a total dissipation path area of 0.3544 square inch. Front of Board Figure 5. Mounted Device Back of Board Figure 4. Evaluation Board This 6−pin DIP design allows the use of sockets and facilitates wire interfacing. Figure 5 represents a WDFN6 506AP package mounted on the evaluation board with and without test pins. A quick thermal analysis of this board is conducted by inducing a saturation current of 820 mA. This yields a junction temperature of 79.4°C and a board temperature of 63.6°C. Figure 6 shows a thermal image of this board under the aforementioned conditions. Figure 6. Thermal Image of Mounted Device Further results from the measured thermal performance of this package are described in the subsequent section. Testing included a thermal analysis of the package surface mounted on a FR4 board using one−inch square pad size and the minimum recommended pad size. www.onsemi.com 2 AND8380/D THERMAL PERFORMANCE Assumptions and Definitions resistances between the C1/C2 node and the Cn−1/Cn node is called a junction−to−foot thermal reference (YJ−Fn). Therefore, in the case of Figure 9, the junction−to−ambient thermal resistance (RqJA) is measured as the sum of thermal references such that, The subsequent sections outline the thermal performance of a WDFN6 506AP package. All values and equations are obtained from simulations and pertain to the Theta(DC) matrix unless otherwise specified. A 10% duty cycle is arbitrarily chosen to evaluate various thermal responses. Refer to Figure 11 for thermal responses at varying duty cycles. The simulation models used to derive the results in this section are modeled around results obtained from physical testing and are considered reliable. Table 1 defines a set of parameters used throughout this section. R qJA + Y JFn ) Y FnA R1 YJ−Fn R2 YL−L’ Junction C1 C2 Junction Temperature TA Ambient Temperature PD Power Dissipation Rq−JL R(u)EFF Cn Ambient (Thermal Ground) Definition TJ YL’−Fn Rn YFn−A Cn−1 Table 1. THERMAL ANALYSIS PARAMETERS Symbol (eq. 1) Figure 8. Grounded Capacitor Thermal Network (“Cauer” Ladder) Junction Thermal Resistance from Junction to Location ”L” C1 Effective (maximum) Thermal Resistance of Package YFn−L Thermal Reference between Foot ”n” and location ”L” YJ−L Thermal Reference between Junction and location ”L” R1 YJ−Fn R2 YL−L’ C2 YL’−Fn Rn YFn−A Cn−1 Cn Ambient (Thermal Ground) Figure 9. Non−Grounded Capacitor Thermal Network (“Foster” Ladder) The number designation associated with “foot” in the subscript of each Y (read psi) term corresponds to the pin identification number as shown in Figure 7. Junction−to−Foot/Foot−to−Ambient The Foster Network junction−to−foot thermal references and foot−to−ambient thermal references under steady state conditions are outlined in Table 2. Table 2. THERMAL REFERENCE PARAMETERS Figure 7. Foot and Junction Identification Figures 8 and 9 represent Cauer and Foster Ladders respectively. This technical note assumes the reader has a general understanding of these networks. Please refer to the documentation cited under references for detailed descriptions of thermal RC networks. In this section, the Foster network is used to calculate various thermal characteristics. For example, as seen in Figure 9, a particular thermal resistance occurs between the junction and C1/C2 node (denoted here as YJ−L). Then, the sum of all thermal Junction−to−Foot 10% Duty Cycle Min−Pad Size 1 in sq. Pad PD 0.7 W 1.9 W Copper Area 30 mm2 (2 oz) 1.127 in2 (2 oz) YJF2 13.9°C/W 15.2°C/W YJF3 51.1°C/W 26.3°C/W Foot−to−Ambient 10% Duty Cycle Min−Pad Size 1 in sq. Pad PD 0.7 W 1.9 W Copper Area 30 mm2 (2 oz) 1.127 in2 (2 oz) YF2A 172.4°C/W 54.5°C/W YF3A 135.2°C/W 43.4°C/W A relationship for the thermal resistance (Rq−JnA) of each device is established by using either of the following relationships, R qJA + Y JF2 ) Y F2A www.onsemi.com 3 (eq. 2) AND8380/D R qJA + Y JF3 ) Y F3A T J + R qJA (eq. 3) Substituting appropriate values, from Table 2, into the above equations yields RqJA = 69.7°C/W for the one−inch square pad size and RqJA = 186.3°C/W for min pad size. PD ) TA The effective thermal resistance of the package, R(u)EFF, is defined as a function of DC or transient response. These two cases are modeled by Equations 5 and 6 respectively. Junction−to−Ambient R(DC) EFF + Table 3 outlines the junction−to−ambient thermal analysis of the WDFN6 506AP package surface mounted on an FR4 board. Substituting values from Table 3 into Equation 4 allows various junction temperatures to be calculated at assumed ambient temperatures. R(t) EFF + ǒT J * T AǓ PD ǒTJ(Pulse) * TAǓ PD Table 3. JUNCTION−TO−AMBIENT THERMAL CHARACTERISTICS Steady State 10% Duty Cycle 1 in sq. Pad Copper area in2 1.127 Pulsed Time = 5 seconds Min−Pad Size [2 oz] 30 mm2 [2 oz] 1 in sq. Pad 1.127 in2 (2 oz) TA 25.0°C 25.0°C 25.0°C PD 1.90 W 0.70 W 1.90 W RqJA R(DC)EFF R(singlepulse)EFF 69.7°C/W* 69.7°C/W 186.3°C/W 38.2°C/W* R(pulsed)EFF 41.3°C/W TJ 157.4°C TJ (single pulse) (eq. 4) 157.4°C 155.4°C TJ (pulsed) 97.5°C* 103.5°C* *Refer to Appendix−A for R(t) Derivation www.onsemi.com 4 (eq. 5) (eq. 6) AND8380/D Junction−to−Board Table 4 outlines the junction−to−board thermal analysis of the WDFN6 506AP package surface mounted on an FR4 board. Substituting values from Tables 2 and 4 into Equation 7 allows various junction temperatures to be calculated at assumed board temperatures. ǒR qJA * Y F2AǓ ) TBOARD TJ + PD (eq. 7) Table 4. JUNCTION−TO−BOARD THERMAL CHARACTERISTICS Steady State Pulsed time = 5 seconds 10% Duty Cycle 1 in sq. Pad Min−Pad Size 1 in sq. Pad Cu area 1.127 in2 [2 oz] 30 mm2 [2 oz] 1.127 in2 [2 oz] PD 1.90 W 0.70 W 1.90 W TA 25.0°C 25.0°C 25.0°C 128.5°C 145.7°C 128.5°C TBOARD (DC) TBOARD(single) TBOARD(pulsed) TJ (DC) 157.4°C TJ (single pulse) 157.4°C 97.5°C 155.4°C TJ (pulsed) 103.5°C Rq−A (DC) 69.7°C/W RqJA (single pulse) 69.7°C/W 186.3°C/W 38.2°C/W 41.3°C/W RqJA (pulsed) *Refer to Appendix−A for R(t) Derivation SUMMARY Figure 10 illustrates a steady state plot of the change in thermal resistance and max power dissipation that occurs with a change in the amount of copper spread across a given area. Evaluating the plots at the minimum recommended pad size and one−inch square pad size yields the following maximum values: Table 5. MAXIMUM RATINGS FROM FIGURE 10 10% Duty Cycle Min−Pad Size 1 in sq. Pad Cu area (Cu thk) 30 mm2 (1 oz) 30 mm2 (2 oz) 1.127 in2 (1 oz) 1.127 in2 (2 oz) RqJ1A 222.4°C/W 186.3°C/W 82.7°C/W 69.7°C/W Max Power 0.562 W 0.671 W 1.51 W 1.794 W the aforementioned SC−88 package. Although a SC−88 package carries the same footprint dimensions as a WDFN6 506AP, the minimum recommended pad size plot evaluated under steady state conditions yields R(t)EFF = 352.4°C/W. The decreased thermal resistance of a WDFN6 506AP package is attributed to the exposed flag acting as a drain contact and heat dissipation path. Figure 11 illustrates the packages change in effective thermal resistance with respect to pulse time. The plot reflects data sampled at a minimum recommended pad size (2 oz. Cu). Under steady state conditions the plot yields R(t)EFF = 186.34°C/W. Maintaining steady state conditions and increasing the copper area to 1.0 square inch, 2 oz Cu, will yield R(t)EFF = 69.68°C/W. These results show that this package exhibits more efficient thermal characteristics than www.onsemi.com 5 AND8380/D TA 25°C RqJA (°C/W) 225 2 Power Curve PCB cu thk 2.0 oz 1.6 1.4 175 Power Curve PCB cu thk 1.0 oz 125 1.2 1 qJA Curve with PCB cu thk 1.0 oz 75 25 1.8 MAXIMUM POWER (W) 275 0.8 qJA Curve with PCB cu thk 2.0 oz 0 0.6 100 200 300 400 500 600 700 COPPER HEAT SPREADER AREA (mm2) 0.4 800 Figure 10. Self−Heating Thermal Characteristics as a Function of Copper Area on the PCB 1000 @50% Duty Cycle 100 20% 10% 10 5% R(t)EFF (C/W) 2% 1 0.1 1% Single Pulse 0.01 0.001 0.000001 Psi LA(t) 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 Pulse Time (sec) Figure 11. Thermal Response Minimum Pad Size References 1. R.P. Stout, D.T. Billings, “How to Extend a Thermal−RC−Network Model (Derived From Experimental Data) to Respond to an Arbitrarily Fast Input,” ON Semiconductor, 2006. 2. R.P. Stout, “Thermal RC Ladder Networks; Packaging Technology Development ,” ON Semiconductor, 2006. 3. R.P. Stout, “General Thermal Transient RC Networks,” ON Semiconductor, 2006. www.onsemi.com 6 AND8380/D APPENDIX Junction−to−Ambient Theta(t) Derivation Where R(t)qJA is the total resistance of the network, Yn is the resistance node, t is the length of a single pulse in seconds and tn (tau) is the characteristic time of ladder. Assuming square wave impulses, the peak junction temperature is estimated by substituting R(t)qJA into Equation 4. Equation 8 describes the relationship used to derive a model describing temperature rise for a single pulse application (see Table 6). m R(t) qJA + S n+1 Yn ƪ1 * expǒ* tńt nǓƫ (eq. 8) Table 6. FOSTER NETWORK 1” Pad (2 oz. Cu) Min Pad (2 oz. Cu) n R (C/W) Tau (sec) R (C/W) Tau (sec) 1 0.068 1.0E−06 0.068 1.0E−06 2 0.148 1.0E−05 0.148 1.0E−05 3 0.466 1.0E−04 0.466 1.0E−04 4 0.347 2.3E−04 0.347 2.3E−04 5 8.42 0.0140 8.42 0.0140 6 9.92 0.071 9.92 0.071 7 6.4 0.340 6.4 0.340 8 4.0 4.41 15.4 0.42 9 7.9 1.67 64.3 10.98 10 32 72.4 80.9 31.3 www.onsemi.com 7 AND8380/D PACKAGE DIMENSIONS WDFN6 2x2 CASE 506AP ISSUE B D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. CENTER TERMINAL LEAD IS OPTIONAL. TERMINAL LEAD IS CONNECTED TO TERMINAL LEAD # 4. 6. PINS 1, 2, 5 AND 6 ARE TIED TO THE FLAG. A B PIN ONE REFERENCE 0.10 C 2X 2X ÍÍÍ ÍÍÍ ÍÍÍ E DIM A A1 A3 b b1 D D2 E E2 e K L L2 J J1 0.10 C A3 0.10 C A 7X 0.08 C A1 C D2 6X L SEATING PLANE SOLDERING FOOTPRINT* 4X 1 e L2 3 2.30 b1 B 1 b J J1 0.60 1.25 NOTE 5 4 6X 0.35 0.43 0.05 C 6 1.10 6X 6X 0.10 C A E2 K MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.25 0.35 0.51 0.61 2.00 BSC 1.00 1.20 2.00 BSC 1.10 1.30 0.65 BSC 0.15 REF 0.20 0.30 0.20 0.30 0.27 REF 0.65 REF 0.35 6X 0.10 C A 0.05 C B 0.34 NOTE 3 BOTTOM VIEW 0.65 PITCH 0.66 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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