Precision Analog Microcontroller with RF Transceiver, ARM Cortex-M3 ADuCRF101 Data Sheet FEATURES External watch crystal for wake-up timer 16 MHz internal oscillator with 8-way, programmable divider Memory 128 kB Flash/EE memory, 16 kB SRAM 10,000-cycle Flash/EE endurance 10-year Flash/EE retention In-circuit download via serial wire and UART On-chip peripherals UART, I2C, and SPI serial I/O 28-pin GPIO port 2 general-purpose, 16-bit timers 32-bit wake-up timer 16-bit watchdog timer 8-channel pulse-width modulation (PWM) Package 64-lead, 9 mm × 9 mm LFCSP Temperature range: −40°C to +85°C Tools Low cost development system Third-party compiler and emulator tool support Analog input/output (I/O) 6-channel, 12-bit SAR ADC Single-ended and differential inputs Programmable data rate of up to 167 kSPS On-chip voltage reference Supply range: 2.2 V to 3.6 V Power consumption 280 nA in shutdown mode, nonretained state 1.9 µA in hibernate mode, processor memory and transceiver memory retained, RF transceiver in sleep mode 210 µA/MHz Cortex-M3 dynamic current 12.8 mA transceiver in receive mode, Cortex-M3 in hibernate mode 9 mA to 32 mA transceiver in transmit mode, Cortex-M3 in hibernate mode RF transceiver Frequency bands 862 MHz to 928 MHz 431 MHz to 464 MHz Multiple configurations supported Receiver sensitivity, bit error rate (BER) −107.5 dBm at 38.4 kbps, 2FSK Single-ended and differential power amplifier (PA) Low external bill of materials (BOM) Microcontroller 32-bit ARM Cortex-M3 processor Serial wire download and debug APPLICATIONS Battery-powered wireless sensors Medical telemetry systems Industrial and home automation Asset tracking Security systems (access systems) Health and fitness applications FUNCTIONAL BLOCK DIAGRAM 6-INPUT MUX COMMUNICATIONS 12-BIT SAR ADC LOW POWER RF TRANSCEIVER WIRELESS TEMPERATURE SENSOR WIRED SERIAL WIRE I2C SPI UART PWM GPIOs BAND GAP REFERENCE PRECISION DATA ACQUISITION LOW POWER PROCESSING CORTEX-M3 PROCESSOR WATCHDOG TIMER 2× GENERALPURPOSE TIMERS INTERRUPT CONTROLLER OSC POR 16kB SRAM 128kB FLASH/EE ADuCRF101 ON-CHIP PERIPHERALS 09464-001 WAKE-UP TIMER Figure 1. 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Technical Support www.analog.com ADuCRF101 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ......................................................... 12 Applications ....................................................................................... 1 Thermal Resistance .................................................................... 12 Functional Block Diagram .............................................................. 1 ESD Caution................................................................................ 12 Revision History ............................................................................... 2 Pin Configuration and Function Descriptions........................... 13 General Description ......................................................................... 3 Typical Performance Characteristics ........................................... 17 Specifications..................................................................................... 4 Outline Dimensions ....................................................................... 19 Electrical Specifications ............................................................... 4 Ordering Guide .......................................................................... 19 RF Link Specifications ................................................................. 6 Timing Specifications .................................................................. 8 REVISION HISTORY 11/14—Revision A: Initial Version Rev. A | Page 2 of 19 Data Sheet ADuCRF101 GENERAL DESCRIPTION The ADuCRF101 is a fully integrated, data acquisition solution that is designed for low power, wireless applications. It features a 12-bit analog-to-digital converter (ADC), a low power ARM® Cortex®-M3 processor, a 862 MHz to 928 MHz and 431 MHz to 464 MHz RF transceiver, and Flash®/EE memory. The ADuCRF101 is packaged in a 9 mm × 9 mm LFCSP. A 16 MHz on-chip oscillator generates the system clock. This clock can be internally divided for the processor to operate at a lower frequency, thus saving power. A low power, internal 32 kHz oscillator is available and can be used to clock the four timers, as follows: two general-purpose timers, a wake-up timer, and a system watchdog timer. The data acquisition section consists of a 12-bit SAR ADC. The six inputs can be configured in single-ended or differential mode. When configured in single-ended mode, they can be used for ratiometric measurements on sensors that are powered, when required, from the internal low dropout regulator (LDO). An internal battery monitor channel and an on-chip temperature sensor are also available. A range of communication peripherals can be configured, as required, in a specific application. These peripherals include UART, I2C, SPI, GPIO ports, PWM, and RF transceivers. This wireless data acquisition system is designed to operate in battery-powered applications where low power is critical. The device can be configured in normal operating mode or different low power modes under direct program control. In flexi mode, any peripheral can wake up the device and operate it. In hibernate mode, the internal wake-up timer remains active. In shutdown mode, only an external interrupt can wake up the device. The ADuCRF101 integrates a low power ARM Cortex-M3 processor. It is a 32-bit RISC machine, offering up to 1.25 DMIPS peak performance. The ARM Cortex-M3 processor also has a flexible 14-channel direct memory access (DMA) controller that supports communication peripherals, serial peripheral interface (SPI), UART, and I2C. Also provided on chip are 128 kB of nonvolatile Flash/EE memory and 16 kB of SRAM. The RF transceiver communicates in the 862 MHz to 928 MHz and 431 MHz to 464 MHz frequency bands using multiple configurations. On-chip factory firmware supports in-circuit serial download via the UART, and nonintrusive emulation and program download are also supported via the serial wire interface. These features are incorporated into a low cost development system supporting this precision analog microcontroller family. The ADuCRF101 operates from 2.2 V to 3.6 V and is specified over an industrial temperature range of −40°C to +85°C. It is available in a 64-lead LFCSP package. Rev. A | Page 3 of 19 ADuCRF101 Data Sheet SPECIFICATIONS ELECTRICAL SPECIFICATIONS AVDD = IOVDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, VREF = 1.25 V internal reference, fCORE = 16 MHz, TA = −40°C to +85°C, unless otherwise noted. Default ADC sampling frequency of 167 kSPS (eight acquisition clocks and ADC clock frequency of 4 MHz). Table 1. Parameter DC ACCURACY Resolution Integral Nonlinearity Test Conditions/Comments Single-ended input mode; applies to all ADC input channels Min Offset Error Gain Error DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Signal-to-Noise + Distortion Ratio (SINAD) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) ANALOG INPUT Input Voltage Ranges 2 Single-Ended Input Differential Input Leakage Current Input Capacitance ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy Reference Temperature Coefficient Power Supply Rejection Ratio (PSRR) Output Impedance Internal VREF Power-On Time TEMPERATURE SENSOR2 Voltage Output at 25°C Voltage Temperature Coefficient Thermal Impedance CURRENT CONSUMPTION Cortex-M3 in Shutdown Mode Cortex-M3 in Hibernate Mode Max 12 −2.5 to +1 −2.5 to +0.5 ±1 VREF = 1.25 V from internal reference VREF = 1.8 V from LDO Differential Nonlinearity DC Code Distribution Differential Ratiometric Measurement CALIBRATED ENDPOINT ERRORS Typ Guaranteed no missing code at 167 kSPS ADC input shorted, VCM = 0.4 V Using two 10 kΩ resistors Measured using the factory-set default values of the ADCOF and ADCGN registers 1 Unit Bits LSB LSB LSB 1 5 LSB LSB ±1.6 ±1 LSB LSB 68 66 dB dB −69 70 dB dB fIN = 1 kHz sine wave 0 0 Excluding VREF pin During ADC acquisition Measured at TA = 25°C 0.47 µF external capacitor Indicates die temperature RF transceiver in sleep mode, memory not retained Wake-up timer running from external 32 kHz crystal, 8 kB of SRAM retained (8 kB not retained) RF Transceiver in Sleep Mode Memory Retained Memory Not Retained Rev. A | Page 4 of 19 VREF VCM ± VREF/2 100 20 V V nA pF 1.25 ±5 ±40 60 V mV ppm/°C dB 2 5 Ω ms 435 1.14 35 mV mV/°C °C/W 280 nA 1.9 1.75 µA µA Data Sheet Parameter RF Transceiver in Receive Mode RF Transceiver in Transmit Mode Cortex-M3 in Active Mode Static Current Dynamic Current START-UP TIME2 From Flexi Mode From Hibernate Mode From Power-On and Shutdown Mode RF Link, Waking Up from Sleep Mode POWER SUPPLY REQUIREMENTS Power Supply Voltage Range2 POWER SUPPLY MONITOR Trip Point Voltage WATCHDOG TIMER2 Timeout Period FLASH/EE MEMORY2 Endurance 3 Data Retention 4 DIGITAL INPUTS Input Current (Leakage Current) Input Capacitance LOGIC INPUTS Input Low Voltage, VINL Input High Voltage, VINH LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL 32.768 kHz CRYSTAL Input Current (Leakage Current) LFXTAL1 Input Capacitance LFXTAL2 Output Capacitance 26 MHz CRYSTAL XOSC26P Input Capacitance XOSC26N Output Capacitance INTERNAL HIGH FREQUENCY (HF) OSCILLATOR Tolerance INTERNAL LOW FREQUENCY (LF) OSCILLATOR Tolerance MCU CLOCK DIVIDER2 EXTERNAL CLOCK INPUT2 Range ADuCRF101 Test Conditions/Comments Min Typ 12.8 9 to 32 Max Unit mA mA RF transceiver idle (PHY_ON state or PHY_OFF state)1 FCLK is the Cortex-M3 clock or divided version of the 16 MHz oscillator From wake-up event to user code execution From applying power/asserting active external interrupt to user code execution Includes 310 µs for 26 MHz crystal startup (7 pF load capacitor at TA = 25°C) 2.0 210 mA µA/MHz 3 to 5 FCLK 13.4 55 µs ms 562.8 µs 2.2 3.6 2 Programmable 0 TJ = 85°C All digital inputs, excluding LFXTAL1 and XOSC26P VINH = IOVDD or VINH = 2.2 V, pull-up disabled; VINL = 0 V, pull-up disabled Excluding P2.4 All logic inputs, including LFXTAL1 but excluding XOSC26P V 512 10,000 10 10 nA 10 pF 0.2 × IOVDD IOVDD − 0.4 0.36 Processor clock by default Eight programmable core clock dividers External MCU clock range allowed sec Cycles Years 0.7 × IOVDD ISOURCE = 1 mA ISINK = 1 mA 32.768 kHz crystal, for use with timers VINH = IOVDD or VINH = 2.2 V, VINL = 0 V V V V V V 50 5 5 nA pF pF 10 10 16 pF pF MHz ±3 32.768 % kHz ±20 % 1 128 32.768 16,000 kHz For detailed information, see the UG-231 User Guide. These values are not production tested; they are guaranteed by design and/or characterization data at production release. 3 Endurance is qualified to 10,000 cycles as per JEDEC Standard No. 22-A117 and measured at −40°C, +25°C, and +85°C. Typical endurance at 25°C is 170,000 cycles. 4 Retention lifetime equivalent at a junction temperature (TJ) of 85°C as per JEDEC Standard No. 22-A117. Retention lifetime derates with junction temperature. 1 2 Rev. A | Page 5 of 19 ADuCRF101 Data Sheet RF LINK SPECIFICATIONS Table 2. Parameter FREQUENCY BANDS RANGE PHASE-LOCKED LOOP Channel Frequency Resolution Phase Noise (In Band) DATA RATE 2FSK/GFSK DIFFERENTIAL POWER AMPLIFIER (PA) Transmit Power1 Transmit Power Variation vs. Temperature Transmit Power Flatness SINGLE-ENDED PA Transmit Power1 Transmit Power Variation vs. Temperature Transmit Power Flatness HARMONICS Single-Ended PA Second Harmonic Third Harmonic Fourth Harmonic Differential PA Second Harmonic Third Harmonic Fourth Harmonic OPTIMUM PA LOAD IMPEDANCE Single-Ended PA, Transmit Mode fRF = 915 MHz fRF = 868 MHz fRF = 433 MHz Single-Ended PA, Receive Mode fRF = 915 MHz fRF = 868 MHz Differential PA, Transmit Mode fRF = 915 MHz fRF = 868 MHz fRF = 433 MHz 2FSK/GFSK INPUT SENSITIVITY, BER 1.0 kbps 38.4 kbps 300 kbps 2FSK/GFSK INPUT SENSITIVITY, PACKET ERROR RATE (PER) 1.0 kbps 38.4 kbps 300 kbps Test Conditions/Comments Min 862 431 Typ Max 928 464 396.7 −88 10 kHz offset, power amplifier (PA) output power = 10 dBm 1 Unit MHz MHz Hz dBc/Hz 300 kbps Programmable From −40°C to +85°C, RF frequency = 868 MHz −17 to +10 ±1 dBm dB From 902 MHz to 928 MHz and 863 MHz to 870 MHZ ±1 dB Programmable From −40°C to +85°C, RF frequency = 868 MHz −21 to 13 ±0.5 dBm dB From 431 MHz to 464 MHz and 862 MHz to 928 MHZ 868 MHz, unfiltered conductive, PA output power = 10 dBm ±1 dB −29.8 −15.9 −24 dBc dBc dBc −33.6 −15.6 −36.7 dBc dBc dBc 31.2 + j10.4 23.5 + j9.7 35.4 + j3.4 Ω Ω Ω 7.3 − j126.3 6.9 − j134.2 Ω Ω 38.7 + j20.6 42.2 + j20.1 55.6 + j54.9 Ω Ω Ω Frequency deviation = 10 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 20.0 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 75 kHz, IF filter bandwidth = 300 kHz At PER = 1%, packet length = 20 bytes, packet mode −116 −107.5 −100.0 dBm dBm dBm Frequency deviation = 10 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 20.0 kHz, IF filter bandwidth = 100 kHz Frequency deviation = 75 kHz, IF filter bandwidth = 300 kHz −114 −105.5 −96 dBm dBm dBm Load impedance between RFIO_1P and RFIO_1N to ensure maximum output power At BER = 10−3 Rev. A | Page 6 of 18 Data Sheet Parameter ADJACENT CHANNEL REJECTION Continuous Wave (CW) Interferer ±200 kHz Channel Spacing ±300 kHz Channel Spacing ±600 kHz Channel Spacing Modulated Interferer ±200 kHz Channel Spacing ±300 kHz Channel Spacing ±600 kHz Channel Spacing CO-CHANNEL REJECTION BLOCKING, ETSI EN 300 220 ±2 MHz ±10 MHz WIDEBAND INTERFERENCE REJECTION IMAGE CHANNEL ATTENUATION 868 MHz RSSI Range at Input Linearity Absolute Accuracy LNA INPUT IMPEDANCE Receive Mode fRF = 915 MHz fRF = 868 MHz fRF = 433 MHz Transmit Mode fRF = 915 MHz fRF = 868 MHz fRF = 433 MHz RX SPURIOUS EMISSIONS3 Maximum < 1 GHz Maximum > 1 GHz 1 2 3 ADuCRF101 Test Conditions/Comments Wanted signal 3 dB above the input sensitivity level (BER = 10−3), CW interferer power level increased until BER = 10−3, image calibrated IF bandwidth (BW) = 100 kHz, wanted signal: fDEV = 12.5 kHz, DR = 50 kbps +200 kHz channel spacing/−200 kHz channel spacing IF BW = 100 kHz, wanted signal: fDEV = 25 kHz, DR = 100 kbps +300 kHz channel spacing/−300 kHz channel spacing IF BW = 300 kHz, wanted signal: fDEV = 75 kHz, DR = 300 kbps +600 kHz channel spacing/−600 kHz channel spacing Wanted signal 3 dB above the input sensitivity level (BER = 10−3), modulated interferer with the same modulation as the wanted signal; interferer power level increased until BER = 10−3, image calibrated IF BW = 100 kHz, wanted signal: fDEV = 12.5 kHz, DR = 50 kbps +200 kHz channel spacing/−200 kHz channel spacing IF BW = 100 kHz, wanted signal: fDEV = 25 kHz, DR = 100 kbps +300 kHz channel spacing/−300 kHz channel spacing IF BW = 300 kHz, wanted signal: fDEV = 75 kHz, DR = 300 kbps +600 kHz channel spacing/−600 kHz channel spacing Wanted signal 10 dB above the input sensitivity level (BER = 10−3), data rate = 38.4 kbps, frequency deviation = 20 kHz Measurement procedure as per ETSI EN 300 220-1 V2.3.1; wanted signal 3 dB above the ETSI EN 300 220 reference sensitivity level of −99 dBm, IF bandwidth = 100 kHz, data rate = 38.4 kbps, unmodulated interferer Swept from 10 MHz to 100 MHz either side of the RF frequency Measured as image attenuation at the IF filter output, carrier wave interferer at 400 kHz below the channel frequency, 100 kHz IF filter bandwidth Uncalibrated2/calibrated At antenna input, unfiltered conductive At antenna input, unfiltered conductive Min Typ Max Unit 36/36 dB 39/39 dB 38/30 dB 34/34 dB 39/35 dB 35/16 −4 dB dB −29 −20.5 75 dBm dBm dB 36/42 dB −97 to −26 ±2 ±3 dBm dB dB 68.9 − j36.1 71.6 − j36.4 99.2 − j31.3 Ω Ω Ω 8.6 + j21.1 8.6 + j20.4 8.2 + j11.4 Ω Ω Ω −66 −51 dBm dBm Measured as the maximum unmodulated power. Measured with Bits IMAGE_REJECT_CAL_AMPLITUDE = 0x7 and Bits IMAGE_REJECT_CAL_PHASE = 0x16. For more detailed information, see the UG-231 User Guide. To achieve the relevant FCC/ETSI specifications, follow the matching and layout guideline information provided in the UG-231 User Guide. Rev. A | Page 7 of 18 ADuCRF101 Data Sheet TIMING SPECIFICATIONS I2C Timing Capacitive load for each of the I2C bus lines, Cb = 400 pF maximum as per the I2C bus specifications. I2C timing is guaranteed by design and not production tested. I2C Timing in Fast Mode (400 kHz) Table 3. Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF tSUP Description Clock (I2CSCL) low pulse width Clock (I2CSCL) high pulse width Start condition hold time Data (I2CSDA) setup time Data (I2CSDA) hold time Setup time for repeated start Stop condition setup time Bus free time between a stop condition and a start condition Rise time for both clock and data Fall time for both clock and data Pulse width of spike suppressed Min 1300 600 600 100 0 600 600 1.3 20 + 0.1 Cb 20 + 0.1 Cb 0 Max Min 4.7 4.0 4.7 250 0 4.0 4.0 4.7 Max Unit ns ns ns ns ns ns ns μs ns ns ns 300 300 50 I2C Timing in Standard Mode (100 kHz) Table 4. Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF Description Clock (I2CSCL) low pulse width Clock (I2CSCL) high pulse width Start condition hold time Data (I2CSDA) setup time Data (I2CSDA) hold time Setup time for repeated start Stop condition setup time Bus free time between a stop condition and a start condition Rise time for both clock and data Fall time for both clock and data tBUF Unit μs μs μs ns μs μs μs μs μs ns 1 300 tSUP tR MSB LSB tDSU tSHD P S tF tDHD 2 TO 7 tR tRSU tH 1 I2CSCL (I) MSB tDSU tDHD tPSU ACK 8 tL 9 tSUP STOP START CONDITION CONDITION 1 S(R) REPEATED START Figure 2. I2C Compatible Interface Timing Rev. A | Page 8 of 18 tF 09464-011 I2CSDA (I/O) Data Sheet ADuCRF101 tBUF tSUP tR MSB LSB tDSU tSHD P S tF tDHD 2 TO 7 tR tRSU tH 1 I2CSCL (I) MSB tDSU tDHD tPSU ACK 8 tL 9 tSUP STOP START CONDITION CONDITION 1 S(R) REPEATED START Figure 2. I2C Compatible Interface Timing Rev. A | Page 9 of 19 tF 09464-011 I2CSDA (I/O) ADuCRF101 Data Sheet SPI Timing SPI timing is guaranteed by design and not production tested. SPI Master Mode Timing Table 5. Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF Typ (SPIDIV 2 + 1) × tUCLK (SPIDIV2 + 1) × tUCLK 0 Max 32.0 10.6 10.6 10.6 10.6 32.0 32.0 32.0 32.0 Unit ns ns ns ns ns ns ns ns ns ns (SPIDIV2 + 1) × tUCLK 59.8 16.0 tUCLK = 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider. For more information about SPIDIV, see the UG-231 User Guide. 1/2 SCLK CYCLE 3/4 SCLK CYCLE CS SCLK (POLARITY = 0) tSH tSL tSR SCLK (POLARITY = 1) tDAV tDF MOSI MSB MISO tSF tDR BIT 6 TO BIT 1 MSB IN LSB BIT 6 TO BIT 1 LSB IN tDSU 09464-012 2 Min tDHD Figure 3. SPI Master Mode Timing (Phase Mode = 1) 1 SCLK CYCLE 3/4 SCLK CYCLE CS SCLK (POLARITY = 0) tSH tSL tSF tSR SCLK (POLARITY = 1) tDAV tDOSU MOSI MISO tDF MSB MSB IN tDR BIT 6 TO BIT 1 BIT 6 TO BIT 1 LSB LSB IN tDSU 09464-013 1 Description SCLK low pulse width 1 SCLK high pulse width1 Data output valid after SCLK edge Data output setup before SCLK edge1 Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time tDHD Figure 4. SPI Master Mode Timing (Phase Mode = 0) Rev. A | Page 10 of 19 Data Sheet ADuCRF101 SPI Slave Mode Timing Table 6. Parameter tCS Description CS to SCLK edge tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS SCLK low pulse width 1 SCLK high pulse width1 Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time Data output valid after CS edge CS high after SCLK edge Max (SPIDIV 2 + 1) × tUCLK (SPIDIV2 + 1) × tUCLK 62.5 47.4 25.8 12.9 10.6 10.6 10.6 10.6 32.0 32.0 32.0 32.0 59.8 12.9 tUCLK = 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider. For more information about SPIDIV, see the UG-231 User Guide. CS tSFS tCS SCLK (POLARITY = 0) tSH tSL tSR tSF SCLK (POLARITY = 1) tDAV tDF MISO MSB MOSI MSB IN tDR BIT 6 TO BIT 1 LSB BIT 6 TO BIT 1 LSB IN tDSU 09464-014 2 Typ tDHD Figure 5. SPI Slave Mode Timing (Phase Mode = 1) CS tCS tSFS SCLK (POLARITY = 0) tSL tSH tSF tSR SCLK (POLARITY = 1) tDAV tDOCS tDF MISO MOSI MSB MSB IN tDR BIT 6 TO BIT 1 BIT 6 TO BIT 1 LSB LSB IN 09464-015 1 Min 12.9 tDSU tDHD Figure 6. SPI Slave Mode Timing (Phase Mode = 0) Rev. A | Page 11 of 19 Unit ns ns ns ns ns ns ns ns ns ns ns ns ADuCRF101 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. The exposed package paddle must be soldered to a metal pad on the printed circuit board (PCB) and connected to ground. Table 7. Parameter AVDD, IOVDD, VDDBAT1, and VDDBAT2 to GND Digital Input Voltage to GND Digital Output Voltage to GND VREF to GND Analog Inputs to GND ESD (Human Body Model) Temperature Operating Temperature Range Storage Temperature Range Junction Temperature Peak Solder Reflow Temperature Pb-Free Assemblies (30 sec) Rating −0.3 V to +3.96 V −0.3 V to +3.96 V −0.3 V to +3.96 V −0.3 V to +3.96 V −0.3 V to +2.1 V ±2.5 kV −40°C to +85°C −65°C to +150°C 105°C THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 8. Thermal Resistance Package Type 64-Lead LFCSP_VQ ESD CAUTION 260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 12 of 19 θJA 35 Unit °C/W Data Sheet ADuCRF101 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P3.5 P3.4 P3.3/PWMTRIP P3.2/PWMSYNC ADCVREF P4.7/PWM7 P4.6/PWM6 VDDBAT1 VDD_DIG2 LFXTAL1 LFXTAL2 P4.5/PWM5 P4.4/PWM4 P4.3/PWM3 P4.2/PWM2 P4.1/PWM1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ADuCRF101 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P4.0/PWM0 RESET BM/P0.6/IRQ2/CS3/RTS/PWM0 P0.7/IRQ3/CS4/CTS IOVDD P0.0/MISO P0.1/SCLK P0.2/MOSI/PWM0 P2.4/IRQ8 P0.3/IRQ1/CS0/ADCCONVST/PWM1 P2.6 P0.4/CS1/ECLKOUT P0.5/CS2/ECLKIN P1.0/RXD/IRQ4/MOSI/PWM2 P1.1/POR/TXD/PWM3 P1.2/PWM4 NOTES 1. THE EXPOSED PACKAGE PADDLE MUST BE SOLDERED TO A METAL PAD ON THE PCB AND CONNECTED TO GROUND. 09464-010 VDDVCO LVDD2 SWDIO GND IOVDD SWCLK VCOGUARD VDDSYNTH CWAKE XOSC26P XOSC26N DGUARD VDD_DIG1 P1.5/IRQ6/I2CSDA/PWM7 P1.4/IRQ5/I2CSCL/PWM6 P1.3/PWM5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDDRF1 RBIAS VDDRF2 RFIO_1P RFIO_1N RFO2 VDDBAT2 AVDD VREF ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 LVDD1 Figure 7. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1 Mnemonic VDDRF1 2 3 RBIAS VDDRF2 4 5 6 7 8 RFIO_1P RFIO_1N RFO2 VDDBAT2 AVDD 9 10 11 12 13 14 15 16 VREF ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 LVDD1 Description Voltage Regulator Output for RF Block. For regulator stability and noise rejection, place a 220 nF capacitor between this pin and ground. External Bias Resistor. Use a 36 kΩ resistor with 2% tolerance. Voltage Regulator Output for RF Block. For regulator stability and noise rejection, place a 220 nF capacitor between this pin and ground. LNA Positive Input in Receive Mode; Differential PA Positive Output in Transmit Mode. LNA Negative Input in Receive Mode; Differential PA Negative Output in Transmit Mode. Single-Ended PA Output. Battery Terminal 1. Supply for the LDOs used in the RF section of the transceiver. Battery Terminal1. Supply for the analog circuits such as the ADC and ADC internal reference, POR, PSM, and LDOs. Internal 1.25 V ADC Reference. Place a 0.47 µF capacitor between this pin and ground. ADC Input Channel 0. Input of DIFF0 pair in differential mode. 2 ADC Input Channel 1. Input of DIFF0 pair in differential mode.2 ADC Input Channel 2. Input of DIFF1 pair in differential mode.2 ADC Input Channel 3. Input of DIFF1 pair in differential mode.2 ADC Input Channel 4. Input of DIFF2 pair in differential mode.2 ADC Input Channel 5. Input of DIFF2 pair in differential mode.2 On-Chip LDO Decoupling Output. Connect a 0.47 µF capacitor to the 1.8 V output to ensure that the core operating voltage is stable. For correct operation, connect a 1 µF capacitor between this pin and LVDD2 (Pin 18). Rev. A | Page 13 of 19 ADuCRF101 Pin No. 17 Mnemonic VDDVCO 18 LVDD2 19 20 21 22 23 24 SWDIO GND IOVDD SWCLK VCOGUARD VDDSYNTH 25 CWAKE 26 27 28 29 XOSC26P XOSC26N DGUARD VDD_DIG1 30 P1.5/IRQ6/I2CSDA/PWM7 31 P1.4/IRQ5/I2CSCL/PWM6 32 P1.3/PWM5 33 P1.2/PWM4 34 P1.1/POR/TXD/PWM3 35 P1.0/RXD/IRQ4/MOSI/PWM2 36 P0.5/CS2/ECLKIN 37 P0.4/CS1/ECLKOUT 38 P2.6 39 P0.3/IRQ1/CS0/ADCCONVST/PWM1 Data Sheet Description Voltage Regulator Output for Voltage Controlled Oscillator (VCO). For regulator stability and noise rejection, place a 220 nF capacitor between this pin and ground. On-Chip LDO Decoupling Output. Connect a 0.47 µF capacitor to the 1.32 V output to ensure that the core operating voltage is stable. For correct operation, connect a 1 µF capacitor between this pin and LVDD1( Pin 16). Serial Wire Bidirectional Data. Ground. Connect this pin to the exposed pad. General-Purpose I/O Supply1. Connect this pin to the battery terminal. Serial Wire Debug Clock. Guard, Screen for VCO. Connect this pin to VDDVCO. Voltage Regulator Output for Synthesizer. For regulator stability and noise rejection, place a 220 nF capacitor between this pin and ground. External Capacitor for Wake-Up Control. Place a 150 nF capacitor between this pin and ground. Connect the 26 MHz reference crystal between this pin and XOSC26N (HFXTAL). 3 Connect the 26 MHz reference crystal between this pin and XOSC26P (HFXTAL). Internal Guard, Screen for Digital Cells. Connect this pin to VDD_DIG1. Voltage Regulator Output for the Digital Section of the Transceiver. For regulator stability and noise rejection, place a 220 nF capacitor between this pin and ground. General-Purpose Input and Output Port 1.5 (P1.5). External Interrupt 6 (IRQ6). I2C Serial Data (I2CSDA). PWM Channel 7 (PWM7). General-Purpose Input and Output Port 1.4 (P1.4). External Interrupt 5 (IRQ5). I2C Serial Clock (I2CSCL). PWM Channel 6 (PWM6). General-Purpose Input and Output Port 1.3 (P1.3). PWM Channel 5 (PWM5). General-Purpose Input and Output Port 1.2 (P1.2). PWM Channel 4 (PWM4). General-Purpose Input and Output Port 1.1 (P1.1). Power-On Reset Output (POR). UART TXD (TXD). PWM Channel 3 (PWM3). General-Purpose Input and Output Port 1.0 (P1.0). UART RXD (RXD). External Interrupt 4 (IRQ4). SPI1 Master Out, Slave In (MOSI). PWM Channel 2 (PWM2). General-Purpose Input and Output Port 0.5 (P0.5). SPI1 Chip Select 2 (CS2). External Clock Input (ECLKIN). General-Purpose Input and Output Port 0.4 (P0.4). SPI1 Chip Select 1 (CS1). External Clock Output (ECLKOUT). General-Purpose Input and Output Port 2.6. Do not connect this pin. This pin is connected internally to the RF transceiver. It can be used for BER measurements. General-Purpose Input and Output Port 0.3 (P0.3). External Interrupt 1 (IRQ1). SPI1 Chip Select 0 (CS0). ADC Convert Start (ADCCONVST). PWM Channel 1 (PWM1). Rev. A | Page 14 of 19 Data Sheet Pin No. 40 Mnemonic P2.4/IRQ8 41 P0.2/MOSI/PWM0 42 P0.1/SCLK 43 P0.0/MISO 44 45 IOVDD P0.7/IRQ3/CS4/CTS 46 BM/P0.6/IRQ2/CS3/RTS/PWM0 47 48 RESET P4.0/PWM0 49 P4.1/PWM1 50 P4.2/PWM2 51 P4.3/PWM3 52 P4.4/PWM4 53 P4.5/PWM5 54 55 56 LFXTAL2 LFXTAL1 VDD_DIG2 57 58 VDDBAT1 P4.6/PWM6 59 P4.7/PWM7 60 ADCVREF 61 P3.2/PWMSYNC 62 P3.3/PWMTRIP ADuCRF101 Description General-Purpose Input and Output Port 2.4 (P2.4). Do not connect this pin. This pin is connected internally to the RF transceiver and can be used for debug purposes to monitor RF transceiver interrupts. External Interrupt 8 (IRQ8). General-Purpose Input and Output Port 0.2 (P0.2). SPI1 Master Out, Slave In (MOSI). PWM Channel 0 (PWM0). General-Purpose Input and Output Port 0.1 (P0.1). SPI1 Serial Clock (SCLK). General-Purpose Input and Output Port 0.0 (P0.0). SPI1 Master In, Slave Out (MISO). General-Purpose I/O Supply1. Connect this pin to the battery terminal. General-Purpose Input and Output Port 0.7 (P0.7). External Interrupt 3 (IRQ3). SPI1 Chip Select 4 (CS4). UART Handshake (CTS). Boot Mode (BM). The ADuCRF101 enters serial download mode if P0.6 is low during, and for a short time after, an external reset event. It executes user code after any reset event or if P0.6 is high during an external reset event. General-Purpose Input and Output Port 0.6 (P0.6). External Interrupt 2 (IRQ2). SPI1 Chip Select 3 (CS3). UART Handshake (RTS). PWM Channel 0 (PWM0). Reset, Active Low. A low signal on this pin for 24 system clocks causes the device to reset. General-Purpose Input and Output Port 4.0 (P4.0). PWM Channel 0 (PWM0). General-Purpose Input and Output Port 4.1 (P4.1). PWM Channel 1 (PWM1). General-Purpose Input and Output Port 4.2 (P4.2). PWM Channel 2 (PWM2). General-Purpose Input and Output Port 4.3 (P4.3). PWM Channel 3 (PWM3). General-Purpose Input and Output Port 4.4 (P4.4).l PWM Channel 4 (PWM4). General-Purpose Input and Output Port 4.5 (P4.5). PWM Channel 5 (PWM5). 32.768 kHz Watch Crystal Input for Wake-Up Timers. 32.768 kHz Watch Crystal Output for Wake-Up Timers. Voltage Regulator Output for the Digital Section of the Transceiver. For regulator stability and noise rejection, place a 220 nF capacitor between this pin and ground. Battery Terminal1. Supply for the digital section of the transceiver and GPIOs. General-Purpose Input and Output Port 4.6 (P4.6). PWM Channel 6 (PWM6). General-Purpose Input and Output Port 4.7 (P4.7). PWM Channel 7 (PWM7). Transceiver ADC Reference Output. For adequate noise rejection, place a 220 nF capacitor between this pin and ground General-Purpose Input and Output Port 3.2 (P3.2). PWM Synchronization (PWMSYNC). General-Purpose Input and Output Port 3.3 (P3.3). PWM Safety Cutoff (PWMTRIP). Rev. A | Page 15 of 19 ADuCRF101 Pin No. 63 64 65 1 2 3 Mnemonic P3.4 P3.5 EP Data Sheet Description General-Purpose Input and Output Port 3.4. General-Purpose Input and Output Port 3.5. Exposed Pad. The exposed package paddle must be soldered to a metal pad on the PCB and connected to ground. VDDBAT1, VDDBAT2, AVDD, and IOVDD must all be connected together. For detailed information about the DIFF0 to DIFF2 differential input pairs, see theUG-231 User Guide. For detailed information about HFXTAL, a 26 MHz external crystal used to set the RF transceiver communication frequency, see the UG-231 User Guide. Rev. A | Page 16 of 19 Data Sheet ADuCRF101 TYPICAL PERFORMANCE CHARACTERISTICS 15 5 0 –5 –10 2.2V 3.3V 3.6V –15 –20 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 PA LEVEL MCR Figure 8. Single-Ended PA at 868 MHz, Output Power vs. PA Level MCR Setting and VDD 30 25 20 15 10 5 –20 09464-002 OUTPUT POWER (dBm) 10 –15 –10 –5 0 10 5 15 TRANSCEIVER OUTPUT POWER (dBm) 09464-005 TRANSCEIVER SUPPLY CURRENT (mA) 35 Figure 11. Differential PA at 868 MHz, Transceiver Supply Current vs. Transceiver Output Power; VDD = 3.3 V 15 90 80 10 BLOCKING POWER (dBm) 0 –40°C, 2.2V –40°C, 3.3V –40°C, 3.6V +25°C, 2.2V +25°C, 3.3V +25°C, 3.6V +85°C, 2.2V +85°C, 3.3V +85°C, 3.6V –10 –15 –20 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 PA LEVEL MCR 40 30 20 10 0 Figure 9. Differential PA at 868 MHz; Output Power vs. PA Level MCR Setting, Temperature, and VDD –10 768 30 –10 INTERFERER POWER (dBm) 10 20 15 828 848 868 888 908 928 948 968 –30 –50 –70 –90 10 5 –20 808 Figure 12. Typical Receiver Wideband Blocking at 868 MHz, VDD = 3.3 V, Data Rate = 38.4 kbps, Frequency Deviation = 20 kHz, Measured as per ETSI EN 300 220 35 25 788 INTERFERER FREQUENCY (MHz) –15 –10 –5 0 5 TRANSCEIVER OUTPUT POWER (dBm) 10 15 09464-004 TRANSCEIVER SUPPLY CURRENT (mA) 50 Figure 10. Single-Ended PA at 868 MHz, Transceiver Supply Current vs. Transceiver Output Power, VDD = 3.3 V Rev. A | Page 17 of 19 –110 858 860 862 864 866 868 870 872 874 876 878 INTERFERER FREQUENCY (MHz) Figure 13. Typical Receiver Blocking at 868 MHz, VDD = 3.3 V, Data Rate = 38.4 kbps, Frequency Deviation = 20 kHz, Measured as per ETSI EN 300 220 09464-007 0 60 09464-006 –5 09464-003 OUTPUT POWER (dBm) 70 5 ADuCRF101 –20 Data Sheet MEAN RSSI IDEAL RSSI RSSI ERROR –30 10 1.0 8 0.8 6 0.6 4 0.4 SINGLE-ENDED PA DIFFERENTIAL 0 –60 –2 –70 POUT (dBm) 2 RSSI ERROR (dB) –50 0.2 0 –0.2 –4 –0.4 –6 –0.6 –8 –0.8 –90 –100 –100 –90 –80 –70 –60 –50 –40 –30 –10 –20 ACTUAL RECEIVED POWER (dBm) Figure 14. RSSI vs. Actual Received Power, 868 MHz, FSK, Data Rate = 38.4 kbps, Frequency Deviation = 20 kHz, IF Bandwidth = 100 kHz –1.0 –60 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 100 09464-009 –80 09464-008 RSSI (dBm) –40 Figure 15. Single-Ended and Differential PA Output Power (POUT) Deviation vs. Temperature; 868 MHz, VDD = 3.3 V Rev. A | Page 18 of 19 Data Sheet ADuCRF101 OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.30 0.23 0.18 0.60 MAX 0.60 MAX 64 1 49 48 PIN 1 INDICATOR PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 16 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 06-14-2012-A 12° MAX 17 BOTTOM VIEW TOP VIEW 1.00 0.85 0.80 5.25 5.10 SQ 4.95 EXPOSED PAD Figure 16. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-5) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADuCRF101BCPZ128 ADuCRF101BCPZ128R7 ADuCRF101BCPZ128RL EV-ADuCRF101MK3Z EV-ADuCRF101MK1Z EV-ADuCRF101QSP1Z EV-ADuCRF101QSP3Z EV-ADuCRF101QS1Z EV-ADuCRF101QS3Z 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Description 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board for 433 MHz Operation Evaluation Board for 868 MHz/915 MHz Operation QuickStart Plus for 868 MHz/915 MHz Operation QuickStart Plus for 433 MHz Operation QuickStart for 868 MHz/915 MHz Operation QuickStart for 433 MHz Operation Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11045-0-11/14(A) Rev. A | Page 19 of 19 Package Option CP-64-5 CP-64-5 CP-64-5