Easy to Use, Low Power, Sub GHz, ISM/SRD, FSK/GFSK, Transceiver IC ADF7024 Data Sheet FEATURES Receiver performance Highly linear: −11.5 dBm input IP3 Blocking: 76 dB at 10 MHz offset Receiver sensitivity, bit error rate (BER) −111 dBm at 9.6 kbps −105 dBm at 100 kbps Low power: 12.8 mA in Rx Transmitter performance High efficiency power amplifier (PA): 23.3 mA in Tx at 10 dBm Output power range: −20 dBm to +13.5 dBm Output power resolution: 0.5 dB Low power mode performance 0.33 μA in PHY_SLEEP mode (Deep Sleep Mode 1) 0.75 μA in PHY_SLEEP mode (32 kHz RC oscillator active) 11.75 μA autonomous Rx sniff using SWM, 300 kbps Supported regulations ETSI EN 300 220 FCC Part 15.231, Part 15.247, Part 15.249 Radio frequency (RF) bands: 431 MHz to 435 MHz and 862 MHz to 928 MHz Data rates supported: 9.6 kbps, 38.4 kbps, 50 kbps, 100 kbps, 200 kbps, and 300 kbps Modulation: two-level frequency (FSK) and Gaussian frequency (GFSK) shift keying 2.2 V to 3.6 V power supply Ultralow power sleep modes for long battery life Simple serial port interface (SPI) control interface Fast radio state transitions Automatic frequency control (AFC) and automatic gain control (AGC) Digital received signal strength indication (RSSI) Fully integrated low noise RF synthesizer and transmit (Tx)/receive (Rx) switch Image rejection calibration (U.S. Patent 8,238,865 and U.S. Patent 8,358,993) Integrated packet management support Insertion/detection of preamble/sync word/cyclic redundancy check (CRC) Manchester and 8-bit/10-bit data encoding and decoding Data whitening 240-byte packet buffer for Tx/Rx data Smart wake mode (SWM) Autonomous carrier sense, packet sniffing, and reception Integrated battery alarm and temperature sensor Integrated RC oscillator On-chip, 8-bit analog-to-digital converter (ADC) 5 mm × 5 mm, 32-lead LFCSP APPLICATIONS Wireless sensor networks (WSNs) Home and building automation sset tracking Process and building control Industrial control Internet of Things (IoT) FUNCTIONAL BLOCK DIAGRAM IRQ CTRL LNA RFI_P LOW IF RECEIVER RFI_N ADF7024 RFO LDO (1 TO 4) PA DIGITAL BASEBAND, PACKET HANDLER, AND MEMORY SYNTHESIZER IRQ_GP3 CS MISO SPI SCLK MOSI TRANSMITTER GPx GPx BIAS TEMPERATURE SENSOR BATTERY MONITOR 32kHz RC OSC SMART WAKE CONTROLLER 26MHz OSC CREGx RBIAS XOSC26P, XOSC26N 12027-001 2 Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADF7024 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions........................... 13 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 15 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 21 Revision History ............................................................................... 2 SPI Interface ................................................................................ 21 General Description ......................................................................... 3 Radio Control ............................................................................. 21 Specifications..................................................................................... 4 Memory Map .............................................................................. 21 RF and Synthesizer Specifications .............................................. 4 Radio Blocks ............................................................................... 21 Transmitter Specifications ........................................................... 5 Radio Profiles .............................................................................. 22 Receiver Specifications ................................................................ 6 Packet Management ................................................................... 22 Timing and Digital Specifications .............................................. 8 Smart Wake Modes .................................................................... 22 Auxilary Block Specifications ..................................................... 9 Typical Application Circuit ........................................................... 23 General Specifications ............................................................... 10 Outline Dimensions ....................................................................... 24 Timing Specifications ................................................................ 11 Ordering Guide .......................................................................... 24 Absolute Maximum Ratings .......................................................... 12 ESD Caution ................................................................................ 12 REVISION HISTORY 7/15—Rev. A to Rev. B Changes to Features Section............................................................ 1 Changes to General Description Section ...................................... 3 Changes to Theory of Operation Section .................................... 21 Changes to Radio Profiles Section ............................................... 22 Changes to Typical Application Circuit Section......................... 23 7/14—Rev. 0 to Rev. A Changes to Adjacent Channel Rejection Parameter .................... 6 Changes to Table 11 ........................................................................ 21 Updated Outline Dimensions ....................................................... 24 6/14—Revision 0: Initial Version Rev. B | Page 2 of 24 Data Sheet ADF7024 GENERAL DESCRIPTION The ADF7024 is an ultralow power, integrated transceiver for use in the license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. Its ease of use and high performance make it suitable for a wide variety of wireless applications. The ADF7024 is suitable for operation under the European ETSI EN 300-220 regulation, the North American FCC Part 15 regulation, and other similar regulatory standards. The ADF7024 can operate under a number of predefined radio profiles. For each radio profile, optimized register settings are provided for the ADF7024 radio. This ensures that the RF communication layer works seamlessly, allowing the user to concentrate on the protocol and system level design and prototyping. The radio profiles cover common data rate and modulation options. There are six radio profiles in total, as shown in Table 1. The ADF7024 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems while maintaining excellent RF performance. The low IF receiver minimizes power consumption and provides excellent sensitivity. The receiver is exceptionally linear and, therefore, is very resilient to the presence of interferers in spectrally noisy environments. The highly efficient transmitter has programmable output power up to 13.5 dBm and automatic power amplifier (PA) ramping to meet transient spurious specifications. The RF synthesizer comprises a voltage controlled oscillator (VCO), a low noise fractional-N phase-locked loop (PLL) and a loop filter, all of which are fully integrated and automatically calibrated. This agile frequency synthesizer facilitates the implementation of frequency-hopping spread spectrum (FHSS) systems. The smart wake mode (SWM) allows the ADF7024 to wake up autonomously from sleep using the internal wake-up timer without intervention from the host processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby reducing overall system current consumption. The ADF7024 eases the processing burden of the host processor by integrating the lower layers of a typical communication protocol stack. The host processor can configure the ADF7024 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function. A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller). For more information, see the ADF7024 Hardware Reference Manual, UG-698, which is only available as part of the ADF7024 design resource package. Table 1. Radio Profiles Radio Profile A B C D E F Data Rate (kbps) 9.6 38.4 50 100 200 300 Modulation FSK/GFSK FSK/GFSK FSK/GFSK FSK/GFSK FSK/GFSK FSK/GFSK Frequency Deviation (kHz) 9.6 20 25 25 50 75 IF Bandwidth (kHz) 100 100 100 100 200 300 Rev. B | Page 3 of 24 Typical Channel Spacing (kHz) 200 200 200 200 400 600 RF Range (MHz) 862 to 928 431 to 435, 862 to 928 862 to 928 862 to 928 862 to 928 862 to 928 ADF7024 Data Sheet SPECIFICATIONS VDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C. RF AND SYNTHESIZER SPECIFICATIONS Table 2. Parameter RF CHARACTERISTICS Frequency Ranges Min SPURIOUS EMISSIONS Integer Boundary Spurious 910.1 MHz 911.0 MHz Reference Spurious 868 MHz/915 MHz Clock Related Spur Level Max Unit Test Conditions/Comments 928 435 MHz MHz All radio profiles Radio Profile B only 396.7 −88 Hz dBc/Hz 10 kHz offset, PA output power = 10 dBm, RF = 868 MHz −126 −131 −142 142 56 dBc/Hz dBc/Hz dBc/Hz μs μs PA output power = 10 dBm, RF = 868 MHz PA output power = 10 dBm, RF = 868 MHz PA output power = 10 dBm, RF = 868 MHz Parallel load resonant crystal 1800 2.1 310 388 MHz pF Ω pF μs μs −39 dBc −79 dBc Radio Profile A, integer boundary spur at 910 MHz (26 MHz × 35), inside synthesizer loop bandwidth Radio Profile A, integer boundary spur at 910 MHz (26 MHz × 35), outside synthesizer loop bandwidth −80 −60 dBc dBc 862 431 PHASE-LOCKED LOOP (PLL) Channel Frequency Resolution Phase Noise (In-Band) Phase Noise at Offset 1 MHz 2 MHz 10 MHz VCO Calibration Time Synthesizer Settling Time CRYSTAL OSCILLATOR Crystal Frequency Recommended Load Capacitance Maximum Crystal ESR Pin Capacitance Start-Up Time Typ 26 7 18 Rev. B | Page 4 of 24 Frequency synthesizer settles to within ±5 ppm of the target frequency within this time following the VCO calibration in transmit and receive 26 MHz crystal with 18 pF load capacitance Capacitance for XOSC26P and XOSC26N 26 MHz crystal with 7 pF load capacitance 26 MHz crystal with 18 pF load capacitance Radio Profile A Measured in a span of ±350 MHz, RF = 868.95 MHz, PA output power = 10 dBm, VDD = 3.6 V Data Sheet ADF7024 TRANSMITTER SPECIFICATIONS Table 3. Parameter DATA RATE Radio Profile A Radio Profile B Radio Profile C Radio Profile D Radio Profile E Radio Profile F FSK/GFSK FREQUENCY DEVIATION Radio Profile A Radio Profile B Radio Profile C Radio Profile D Radio Profile E Radio Profile F GAUSSIAN FILTER BANDWITH TIME (BT) POWER AMPLIFIER Maximum Power1 Minimum Power Transmit Power Variation vs. Temperature Variation vs. VDD Flatness Programmable Step Size HARMONICS Second Harmonic Third Harmonic All Other Harmonics OPTIMUM PA LOAD IMPEDANCE PA Output in Transmit Mode fRF = 915 MHz fRF = 868 MHz fRF = 433 MHz PA Output in Receive Mode fRF = 915 MHz fRF = 868 MHz fRF = 433 MHz 1 2 Min Typ Max Unit Test Conditions/Comments 9.6 38.4 50 100 200 300 kbps kbps kbps kbps kbps kbps 9.6 20 25 25 50 75 0.5 kHz kHz kHz kHz kHz kHz 13.5 −20 dBm dBm Programmable, separate PA and LNA match2 ±0.5 ±1 ±1 0.5 dB dB dB dB −40°C to +85°C, RF = 868 MHz 2.2 V to 3.6 V, RF = 868 MHz 902 MHz to 928 MHz and 863 MHz to 870 MHz −20 dBm to +13.5 dBm, programmable in 60 steps 868 MHz, unfiltered conductive, PA output power = 10 dBm −15.1 −29.3 −47.6 dBc dBc dBc 50.8 + j10.2 45.5 + j12.1 46.8 + j19.9 Ω Ω Ω 9.4 − j124 9.5 − j130.6 11.9 − j260.1 Ω Ω Ω Not programmable Measured as the maximum unmodulated power. A combined single-ended PA and LNA match can reduce the maximum achievable output power by as much as 1 dB. Rev. B | Page 5 of 24 ADF7024 Data Sheet RECEIVER SPECIFICATIONS Table 4. Parameter INPUT SENSITIVITY, BIT ERROR RATE (BER)1 Radio Profile A Radio Profile B Radio Profile C Radio Profile D Radio Profile E Radio Profile F INPUT SENSITIVITY, PACKET ERROR RATE (PER)3 Radio Profile A Radio Profile B Radio Profile C Radio Profile D Radio Profile E Radio Profile F LNA AND MIXER, INPUT IP3 LNA Gain Minimum Maximum LNA AND MIXER, INPUT IP2 Gain Maximum LNA, Maximum Mixer Minimum LNA, Minimum Mixer LNA AND MIXER, 1 dB COMPRESSION POINT Gain Maximum LNA, Maximum Mixer Minimum LNA, Minimum Mixer ADJACENT CHANNEL REJECTION CW Interferer Min Typ Max Unit −111 −107.5 −107.4 −105 −103 −100.5 dBm dBm dBm dBm dBm dBm −110.6 −106 −104.1 −102.6 −99.1 −97.9 dBm dBm dBm dBm dBm dBm −11.5 −12.2 dBm dBm Test Conditions/Comments BER = 10−3, LNA and PA matched separately2 9.6 kbps 38.4 kbps 50 kbps 100 kbps 200 kbps 300 kbps At PER = 1%, LNA and PA matched separately,2 packet length = 128 bits 9.6 kbps 38.4 kbps 50 kbps 100 kbps 200 kbps 300 kbps Receiver local oscillator (LO) frequency (fLO) = 914.8 MHz, fSOURCE1 = fLO + 0.4 MHz, fSOURCE2 = fLO + 0.7 MHz fLO = 920.8 MHz, fSOURCE1 = fLO + 1.1 MHz, fSOURCE2 = fLO + 1.3 MHz 18.5 27 dBm dBm RF = 915 MHz −21.9 −21 dBm dBm 200 kHz Channel Spacing 400 kHz Channel Spacing 600 kHz Channel Spacing Modulated Interferer 41 40 41 dB dB dB 200 kHz Channel Spacing 400 kHz Channel Spacing 600 kHz Channel Spacing CO-CHANNEL REJECTION 37 34 35 −4 dB dB dB dB Rev. B | Page 6 of 24 Wanted signal 3 dB above the input sensitivity level (BER = 10−3), CW interferer power level increased until BER = 10−3, image calibrated Radio Profile B, RF = 433 MHz Radio Profile E Radio Profile F Wanted signal 3 dB above the input sensitivity level (BER = 10−3), modulated interferer with the same modulation as the wanted signal; interferer power level increased until BER = 10−3, image calibrated Radio Profile B, RF = 433 MHz Radio Profile E Radio Profile F Desired signal 10 dB above the input sensitivity level (BER = 10−3), Radio Profile B, RF = 868 MHz Data Sheet Parameter BLOCKING RF = 433 MHz ±2 MHz ±10 MHz RF = 868 MHz ±2 MHz ±10 MHz RF = 915 MHz ±2 MHz ±10 MHz BLOCKING, ETSI EN 300 220 ±2 MHz ±10 MHz WIDEBAND INTERFERENCE REJECTION ADF7024 Min Typ Max Unit 68 76 dB dB 66 74 dB dB 66 74 dB dB Measurement procedure as per ETSI EN 300-220-1 V2.3.1; desired signal 3 dB above the ETSI EN 300-220 reference sensitivity level of −99 dBm, Radio Profile B, unmodulated interferer −28 −20.5 75 dBm dBm dB 36/45 40/54 dB dB 1 kHz −97 to −26 ±2 ±3 12 dBm dB dB dBm 75.9 − j32.3 78.0 − j32.4 95.5 − j23.9 Ω Ω Ω 7.6 + j9.2 7.7 + j8.6 7.9 + j4.6 Ω Ω Ω −66 −62 dBm dBm IMAGE CHANNEL ATTENUATION 868 MHz, 915 MHz 433 MHz AFC Accuracy RSSI Range at Input Linearity Absolute Accuracy MAXIMUM RF INPUT LEVEL LNA INPUT IMPEDANCE, DIFFERENTIAL Receive Mode fRF = 915 MHz fRF = 868 MHz fRF = 433 MHz Transmit Mode fRF = 915 MHz fRF = 868 MHz fRF = 433 MHz RX SPURIOUS EMISSIONS4 Maximum < 1 GHz Maximum > 1 GHz Test Conditions/Comments Desired signal 3 dB above the input sensitivity level (BER = 10−3), carrier wave interferer, power level increased until BER = 10−3, Radio Profile B 1 RF = 868 MHz, swept from 10 MHz to 100 MHz either side of the RF Measured as image attenuation at the IF filter output, carrier wave interferer at 400 kHz below the channel frequency, 100 kHz IF filter bandwidth Uncalibrated/calibrated Uncalibrated/calibrated At antenna input, unfiltered conductive At antenna input, unfiltered conductive Sensitivity measured with FSK modulation. Sensitivity for combined Tx/Rx matching network case is typically 1 dB less than separate Tx/Rx matching networks. Sensitivity measured with FSK modulation and AFC disabled. 4 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications. 2 3 Rev. B | Page 7 of 24 ADF7024 Data Sheet TIMING AND DIGITAL SPECIFICATIONS Table 5. Parameter Rx AND Tx TIMING PARAMETERS PHY_ON to PHY_RX (on CMD_PHY_RX) PHY_ON to PHY_TX (on CMD_PHY_TX) LOGIC INPUTS Input Voltage High Low Input Current Input Capacitance LOGIC OUTPUTS Output Voltage High Low GPx Rise/Fall GPx Load Maximum Output Current ATB OUTPUTS ADCIN_ATB3 and ATB4 Output High Voltage, VOH Output Low Voltage, VOL Maximum Output Current GP5_ATB1 and ATB2 Output High Voltage, VOH Output Low Voltage, VOL Maximum Output Current Symbol Min VINH VINL IINH/IINL CIN 0.7 × VDD VOH VOL VDD − 0.4 Typ Max Unit Test Conditions/Comments 300 μs Includes VCO calibration and synthesizer settling 296 μs Includes VCO calibration and synthesizer settling, does not include PA ramp-up 0.2 × VDD ±1 10 0.4 5 10 5 V V µA pF V V ns pF mA IOH = 500 µA IOL = 500 µA Used for external PA and LNA control 1.8 0.1 0.5 V V mA VDD 0.1 5 V V mA Rev. B | Page 8 of 24 Data Sheet ADF7024 AUXILARY BLOCK SPECIFICATIONS Table 6. Parameter 32 kHz RC OSCILLATOR Frequency Frequency Accuracy Frequency Drift Temperature Coefficient Voltage Coefficient Calibration Time WAKE-UP CONTROLLER (WUC) Hardware Timer Wake-Up Period Firmware Timer Wake-Up Period ADC Resolution DNL INL Conversion Time Input Capacitance BATTERY MONITOR Absolute Accuracy Alarm Voltage Set Point Alarm Voltage Step Size Start-Up Time Current Consumption TEMPERATURE SENSOR Range Resolution Accuracy of Temperature Readback Min Typ Max Unit Test Conditions/Comments 32.768 1.5 kHz % After calibration After calibration at 25°C 0.14 4 1.25 %/°C %/V ms 61 × 10−6 1.31 × 105 sec 1 216 Hardware periods 8 ±1 ±1 1 12.4 Bits LSB LSB µs pF ±45 1.7 2.7 62 100 30 −40 +85 mV V mV µs µA 0.3 −4 to +7 °C °C °C ±4 °C ±3 °C Rev. B | Page 9 of 24 Firmware counter counts of the number of hardware wake-up cycles, resolution of 16 bits VDD from 2.2 V to 3.6 V, TA = 25°C VDD from 2.2 V to 3.6 V, TA = 25°C 5-bit resolution When enabled With averaging Temperature range = −40°C to +85°C (calibrated at 25°C) Temperature range = −36°C to +84°C (calibrated at 25°C) Temperature range = −12°C to +79°C (calibrated at 25°C) ADF7024 Data Sheet GENERAL SPECIFICATIONS Table 7. Parameter TEMPERATURE RANGE, TA VOLTAGE SUPPLY VDD TRANSMIT CURRENT CONSUMPTION 433 MHz −10 dBm 0 dBm 10 dBm 13.5 dBm 868 MHz/915 MHz −10 dBm 0 dBm 10 dBm 13.5 dBm POWER MODES PHY_SLEEP (Deep Sleep Mode 2) PHY_SLEEP (Deep Sleep Mode 1) PHY_SLEEP (RC Oscillator Active) PHY_OFF PHY_ON PHY_RX SMART WAKE MODE Min −40 Typ 2.2 Max +85 Unit °C Test Conditions/Comments 3.6 V Applied to VDDBAT1 and VDDBAT2 In the PHY_TX state, PA matched to 50 Ω, separate PA and LNA match 8.7 12.2 23.3 32.1 mA mA mA mA 10.3 13.3 24.1 32.1 mA mA mA mA 0.18 0.33 0.75 1 µA µA µA mA 1 mA 12.8 mA 21.78 µA 11.75 µA Rev. B | Page 10 of 24 Sleep mode, memory not retained Sleep mode, memory retained WUC active, RC oscillator running, memory retained Device in PHY_OFF state, 26 MHz oscillator running, digital and synthesizer regulators active, all register values retained Device in PHY_ON state, 26 MHz oscillator running, digital, synthesizer, VCO, and RF regulators active, baseband filter calibration performed, all register values retained Device in PHY_RX state Average current consumption Autonomous reception every 1 sec, with receive dwell time of 1.25 ms, using RC oscillator, Radio Profile B Autonomous reception every 1 sec, with receive dwell time of 0.5 ms, using RC oscillator, Radio Profile F Data Sheet ADF7024 TIMING SPECIFICATIONS VDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, VGND = GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Table 8. SPI Interface Timing Parameter t2 t3 t4 t5 t6 t7 t8 t9 t11 t12 t13 t14 t15 Limit 85 85 85 170 10 5 5 85 270 310 20 20 25 Unit ns min ns min ns min ns min ns max ns min ns min ns min ns min µs typ ns max ns max µs max Test Conditions/Comments CS low to SCLK setup time SCLK high time SCLK low time SCLK period SCLK falling edge to MISO delay MOSI to SCLK rising edge setup time MOSI to SCLK rising edge hold time SCLK falling edge to CS hold time CS high time CS low to MISO high wake-up time, 26 MHz crystal with 7 pF load capacitance, TA = 25°C SCLK rise time SCLK fall time Initialization time; do not issue a command during this time; alternatively, poll the status word and wait for the CMD_READY bit to go high Timing Diagrams CS t11 t3 t2 t4 t5 t14 t13 t9 SCLK t6 BIT 7 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 2 1 0 7 BIT 0 X BIT 7 t8 t7 MOSI BIT 6 7 6 5 4 3 7 Figure 2. SPI Interface Timing CS t9 t15 7 SCLK t12 6 5 4 3 2 1 0 t6 MISO SLEEP WAKE UP SPI READY Figure 3. PHY_SLEEP to SPI Ready State Timing (SPI Ready t12 After the Falling Edge of CS) Rev. B | Page 11 of 24 12027-003 X SPI STATE 12027-002 MISO ADF7024 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Connect the exposed pad of the LFCSP to ground. Table 9. This device is a high performance, RF integrated circuit with an ESD rating of <2 kV; it is ESD sensitive. Take proper precautions for handling and assembly. Parameter VDDBAT1, VDDBAT2 to GND Operating Temperature Range Industrial Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature Rating −0.3 V to +3.96 V ESD CAUTION −40°C to +85°C −65°C to +125°C 150°C 26°C/W 260°C 40 sec Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 12 of 24 Data Sheet ADF7024 32 31 30 29 28 27 26 25 ADCVREF ATB4 ADCIN_ATB3 VDDBAT1 ATB2 GP5_ATB1 CREGDIG2 GP4 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADF7024 TOP VIEW (Not to Scale) EPAD 24 23 22 21 20 19 18 17 CS MOSI SCLK MISO IRQ_GP3 GP2 GP1 GP0 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. CONNECT THE EXPOSED PAD TO GND. 12027-004 CREGVCO VCOGUARD CREGSYNTH CWAKEUP XOSC26P XOSC26N DGUARD CREGDIG1 9 10 11 12 13 14 15 16 CREGRF1 RBIAS CREGRF2 RFI_P RFI_N RFO VDDBAT2 NC Figure 4. Pin Configuration Table 10. Pin Function Descriptions Pin No. 1 Mnemonic CREGRF1 2 3 RBIAS CREGRF2 4 5 6 7 8 9 RFI_P RFI_N RFO VDDBAT2 NC CREGVCO 10 11 VCOGUARD CREGSYNTH 12 13 CWAKEUP XOSC26P 14 XOSC26N 15 16 DGUARD CREGDIG1 17 18 19 20 21 22 23 24 GP0 GP1 GP2 IRQ_GP3 MISO SCLK MOSI CS 25 GP4 Description Regulator Voltage for RF. For regulator stability and noise rejection, place a 220 nF capacitor between this pin and ground. External Bias Resistor. Place a 36 kΩ resistor with 2% tolerance between this pin and ground. Regulator Voltage for RF. For regulator stability and noise rejection, place a 220 nF capacitor between this pin and ground. LNA Positive Input in Receive Mode. LNA Negative Input in Receive Mode. PA Output. Power Supply Pin 2. Place decoupling capacitors to the ground plane as close as possible to this pin. No Connect. Do not connect to this pin. Regulator Voltage for the VCO. For regulator stability and noise rejection, place a 220 nF capacitor between this pin and ground. Guard/Screen for VCO. Connect this pin to Pin 9. Regulator Voltage for the Synthesizer. For regulator stability and noise rejection, place a 220 nF capacitor between this pin and ground. External Capacitor for Wake-Up Control. Place a 150 nF capacitor between this pin and ground. Crystal Oscillator, Positive. Connect the 26 MHz reference crystal between this pin and XOSC26N. If an external reference is connected to XOSC26N, leave this pin open circuited. Crystal Oscillator, Negative. Connect the 26 MHz reference crystal between this pin and XOSC26P. Alternatively, an external 26 MHz reference signal can be ac-coupled to this pin. Internal Guard/Screen for the Digital Circuitry. Connect this pin to Pin 16, CREGDIG1. Regulator Voltage for Digital Section of the Chip. For regulator stability and noise rejection, place a 220 nF capacitor between this pin and ground. Digital GPIO Pin 0. Digital GPIO Pin 1. Digital GPIO Pin 2. Interrupt Request/Digital GPIO Test Pin 3. Serial Port Master Input/Slave Output. Serial Port Clock. Serial Port Master Output/Slave Input. Chip Select (Active Low). A pull-up resistor of 100 kΩ to VDD is recommended to prevent the host processor from inadvertently waking the ADF7024 from sleep. Digital GPIO Test Pin 4. Rev. B | Page 13 of 24 ADF7024 Pin No. 26 Mnemonic CREGDIG2 27 28 29 30 31 32 GP5_ATB1 ATB2 VDDBAT1 ADCIN_ATB3 ATB4 ADCVREF EPAD Data Sheet Description Regulator Voltage for Digital Section of the Chip. For regulator stability and noise rejection, place a 220 nF capacitor between this pin and ground. Digital GPIO Test Pin 5/Analog Test Pin 1. Analog Test Pin 2. Digital Power Supply Pin One. Place decoupling capacitors to the ground plane as close as possible to this pin. Analog-to-Digital Converter Input/Analog Test Pin 3. Analog Test Pin 4. ADC Reference Output. Place a 220 nF capacitor between this pin and ground for adequate noise rejection. Exposed Package Pad. Connect the exposed pad to GND. Rev. B | Page 14 of 24 Data Sheet ADF7024 TYPICAL PERFORMANCE CHARACTERISTICS 16 8 4 35 SUPPLY CURRENT (mA) 12 0 –4 –8 –12 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 20 15 10 0 –20 12027-164 0 PA_LEVEL 35 –40°C, 3.6V –40°C, 3.0V –40°C, 2.4V +25°C, 3.6V +25°C, 3.0V +25°C, 2.4V +85°C, 3.6V +85°C, 3.0V +85°C, 2.4V 4 30 SUPPLY CURRENT (mA) 8 –12 –8 –4 0 4 8 12 16 PA OUTPUT POWER (dBm) 16 12 –16 Figure 8. Supply Current vs. PA Output Power, Temperature, and VDD at 433 MHz (Minimum Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness) Figure 5. Output Power vs. PA_LEVEL Setting, Temperature, and VDD at 433 MHz OUTPUT POWER (dBm) 25 5 –16 –20 30 –40°C, 3.6V –40°C, 1.8V +25°C, 3.6V +25°C, 1.8V +85°C, 3.6V +85°C, 1.8V 12027-165 OUTPUT POWER (dBm) 40 –40°C, 3.6V –40°C, 3.0V –40°C, 2.4V +25°C, 3.6V +25°C, 3.0V +25°C, 2.4V +85°C, 3.6V +85°C, 3.0V +85°C, 2.4V 0 –4 –8 –40°C, 3.6V –40°C, 1.8V +25°C, 3.6V +25°C, 1.8V +85°C, 3.6V +85°C, 1.8V 25 20 15 10 –12 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 PA_LEVEL 0 –20 12027-166 Figure 6. Output Power vs. PA_LEVEL Setting, Temperature, and VDD at 868 MHz SUPPLY CURRENT (mA) 4 35 0 –4 –8 –12 –20 –4 0 4 8 12 16 30 –40°C, 3.6V –40°C, 1.8V +25°C, 3.6V +25°C, 1.8V +85°C, 3.6V +85°C, 1.8V 25 20 15 10 5 –16 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 PA_LEVEL Figure 7. Output Power vs. PA_LEVEL Setting, Temperature, and VDD at 915 MHz 0 –20 12027-168 OUTPUT POWER (dBm) 8 –8 Figure 9. Supply Current vs. Output Power, Temperature, and VDD at 868 MHz (Minimum Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness) 40 12 –12 OUTPUT POWER (dBm) 16 –40°C, 3.6V –40°C, 3.0V –40°C, 2.4V +25°C, 3.6V +25°C, 3.0V +25°C, 2.4V +85°C, 3.6V +85°C, 3.0V +85°C, 2.4V –16 –16 –12 –8 –4 0 4 OUTPUT POWER (dBm) 8 12 16 12027-169 –20 12027-167 5 –16 Figure 10. Supply Current vs. Output Power, Temperature, and VDD at 915 MHz (Minimum Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness) Rev. B | Page 15 of 24 ADF7024 Data Sheet 3.6V, 1.8V, 3.6V, 1.8V, 0 5 –40°C –40°C +85°C +85°C 0 MIXER OUTPUT POWER (dBm) 10 –20 –30 –40 –50 50 100 150 200 250 Figure 11. Transmit Spectrum at 868 MHz, FSK, Radio Profile B, (Minimum Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness) –15 –20 –25 –30 P1dB = –21dBm –40 –40 –25 –20 –15 Figure 14. LNA/Mixer 1 dB Compression Point, VDD = 3.0 V, Temperature = 25°C, RF = 915 MHz, LNA Gain = Low, Mixer Gain = Low –20 –30 –40 –50 –50 0 50 100 150 200 250 FREQUENCY OFFSET (kHz) Figure 12. Transmit Spectrum at 868 MHz, GFSK, Radio Profile B, (Minimum Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness) OUTPUT POWER (FUNDAMENTAL) OUTPUT POWER IDEAL P1dB 10 5 0 –5 P1dB = –21.9dBm –10 –40 12027-041 –60 –250 –200 –150 –100 15 –35 –30 –25 LNA INPUT POWER (dBm) –20 –15 12027-226 MIXER OUTPUT POWER (dBm) –10 Figure 15. LNA/Mixer 1 dB Compression Point, VDD = 3.0 V, Temperature = 25°C, RF = 915 MHz, LNA Gain = High, Mixer Gain = High 15 10 0 5 –10 3.6V, 1.8V, 3.6V, 1.8V, 3.6V, 1.8V, MIXER OUTPUT POWER (dBm) 10 –10 –30 20 3.6V, –40°C 1.8V, –40°C 3.6V, +85°C 1.8V, +85°C 0 –5 –35 LNA INPUT POWER (dBm) 10 0 OUTPUT POWER (FUNDAMENTAL) OUTPUT POWER IDEAL P1dB 12027-225 0 12027-040 –50 FREQUENCY OFFSET (kHz) POWER (dBm) –10 –35 –60 –250 –200 –150 –100 POWER (dBm) –5 +25°C +25°C +85°C +85°C –40°C –40°C –15 –20 –25 –30 –35 –20 –30 –40 –50 –60 IIP3 = –11.5dBm –70 –80 –90 –100 FUNDAMENTAL TONE IM3 TONE FUNDAMENTAL 1/1 SLOPE FIT IM3 3/1 SLOPE FIT –110 1000 12027-217 FREQUENCY OFFSET (kHz) 500 600 700 800 900 –130 –50 –500 –400 –300 –200 –100 0 100 200 300 400 –120 –45 –1000 –900 –800 –700 –600 –40 Figure 13. Transmit Spectrum at 928 MHz, GFSK, Radio Profile F, (Minimum Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness) –45 –40 –35 –30 –25 –20 LNA INPUT POWER (dBm) –15 –10 12027-227 POWER (dBm) –10 Figure 16. LNA/Mixer IIP3, VDD = 3.0 V, Temperature = 25°C, RF = 915 MHz, LNA Gain = Low, Mixer Gain = Low, Source 1 Frequency = 915 MHz + 0.4 MHz, Source 2 Frequency = 915 MHz + 0.7 MHz Rev. B | Page 16 of 24 Data Sheet ADF7024 80 20 70 60 0 BLOCKING (dB) –10 –20 –30 IIP3 = –12.2dBm –40 –50 –60 40 30 20 –40 –35 –30 –25 –20 LNA INPUT POWER (dBm) –15 –10 –10 INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz) Figure 17. LNA/Mixer IIP3, VDD = 3.0 V, Temperature = 25°C, RF = 915 MHz, LNA Gain = High, Mixer Gain = High, Source 1 Frequency = 915 MHz + 0.4 MHz, Source 2 Frequency = 915 MHz + 0.7 MHz 10 Figure 20. Receiver Wideband Blocking at 433 MHz, Radio Profile B 80 100kHz 200kHz 300kHz 0 70 –10 60 BLOCKING (dB) –20 –40 –50 –60 50 40 30 20 –70 10 –80 0 0.2 0.3 0.4 0.5 0.6 FREQUENCY OFFSET (MHz) 0.7 0.8 –10 –11 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 0.1 12027-229 0 MODULATED INTERFERER CARRIER WAVE INTERFERER BLOCKER FREQUENCY OFFSET (MHz) Figure 18. IF Filter Profile vs. IF Bandwidth, VDD = 3.0 V, Temperature = 25°C Figure 21. Receiver Wideband Blocking at 868 MHz, Radio Profile D 10 70 –20 –30 –40 –50 60 50 –60 40 30 20 MODULATED INTERFERER CARRIER WAVE INTERFERER 10 0 –70 –10 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY OFFSET (MHz) 0.7 0.8 Figure 19. IF Filter Profile vs. VDD and Temperature, 100 kHz IF Filter Bandwidth (Minimum Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness) Rev. B | Page 17 of 24 –20 INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz) Figure 22. Receiver Wideband Blocking at 868 MHz, Radio Profile F 12027-236 0 12027-230 –80 –11 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 ATTENUATION (dB) –10 –40°C –40°C –40°C –40°C +25°C +25°C +25°C +25°C +85°C +85°C +85°C +85°C BLOCKING (dB) 1.8V, 2.4V, 3.0V, 3.6V, 1.8V, 2.4V, 3.0V, 3.6V, 1.8V, 2.4V, 3.0V, 3.6V, 0 –90 12027-235 –30 –90 12027-231 –45 2 4 6 8 10 12 14 16 18 20 –90 –50 0 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 –80 ATTENUATION (dB) MODULATED INTERFERER CARRIER WAVE INTERFERER 50 10 FUNDAMENTAL TONE IM3 TONE FUNDAMENTAL 1/1 SLOPE FIT IM3 3/1 SLOPE FIT –70 12027-228 MIXER OUTPUT POWER (dBm) 10 ADF7024 Data Sheet –10 70 –20 60 –30 INTERFERER POWER (dBm) 80 20 10 0 –60 –70 –80 –90 –110 –60 –50 –40 –30 –20 –10 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 12027-238 –100 –20 60 50 BLOCKING (dB) 40 MODULATED INTERFERER CARRIER WAVE INTERFERER 20 10 0 –10 12027-239 –11 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10 11 –20 INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz) 60 50 BLOCKING (dB) 40 30 20 +25°C 1.8V +25°C 3.0V +25°C 3.6V +85°C 1.8V +85°C 3.0V +85°C 3.6V –40°C 1.8V –40°C 3.0V –40°C 3.6V –20 –60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 INTERFERER FREQUENCY OFFSET (MHz) Figure 25. Receiver Wideband Blocking vs. VDD and Temperature, 915 MHz, Radio Profile F 12027-240 –10 30 40 50 60 60 55 50 45 40 35 30 25 20 15 10 5 0 –5 –10 CW INTERFERER –15 MODULATED INTERFERER –20 –2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 Figure 27. Receiver Close-In Blocking at 915 MHz, Radio Profile D, Image Calibrated 70 0 20 INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz) Figure 24. Receiver Wideband Blocking at 915 MHz, Radio Profile F 10 10 Figure 26. Receiver Wideband Blocking at 868 MHz, Radio Profile B, Measured as per ETSI EN 300 220 70 30 0 INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz) Figure 23. Receiver Wideband Blocking at 915 MHz, Radio Profile D BLOCKING (dB) –50 –10 BLOCKER FREQUENCY OFFSET (MHz) BLOCKING (dB) –40 12027-241 30 MODULATED INTERFERER CARRIER WAVE INTERFERER 12027-243 40 60 55 50 45 40 35 30 25 20 15 10 5 0 –5 –10 CW INTERFERER –15 MODULATED INTERFERER –20 –2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz) 12027-245 BLOCKING (dB) 50 Figure 28. Receiver Close-In Blocking at 915 MHz, Radio Profile E, Image Calibrated Rev. B | Page 18 of 24 ADF7024 0 –10 100kHz BW 200kHz BW 300kHz BW –20 ATTENUATION (dB) –30 –40 –50 –60 –70 –80 0.4 0.8 1.2 1.6 2.0 INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz) –90 –1.0 Figure 29. Receiver Close-In Blocking at 915 MHz, Radio Profile F, Image Calibrated –0.8 –0.6 –0.4 –0.2 0 0.4 0.6 0.8 1.0 Figure 32. IF Filter Profile with Calibrated Image vs. IF Filter Bandwidth, 921 MHz, VDD = 3.0 V, Temperature = 25°C –98 0 915MHz, 915MHz, 915MHz, 868MHz, 868MHz, 868MHz, CALIBRATED UNCALIBRATED –10 –99 SENSITIVITY (dBm) –20 ATTENUATION (dB) 0.2 OFFSET FROM LO FREQUENCY (MHz) 12027-249 60 55 50 45 40 35 30 25 20 15 10 5 0 –5 –10 CW INTERFERER –15 MODULATED INTERFERER –20 –2.0 –1.6 –1.2 –0.8 –0.4 0 12027-246 BLOCKING (dB) Data Sheet –30 –40 –50 –60 –40°C +25°C +85°C –40°C +25°C +85°C –100 –101 –102 –70 –103 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz) –104 Figure 30. Image Attenuation with Calibrated and Uncalibrated Images, 915 MHz, IF Filter Bandwidth = 100 kHz, VDD = 3.0 V, Temperature = 25°C 3.0 Figure 33. Receiver Sensitivity (Bit Error Rate at 10−3) vs. VDD, Temperature, and RF Frequency, Radio Profile F, FSK, (Minimum Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness) 100 CALIBRATED UNCALIBRATED –10 9.6kbps 38.4kbps 50kbps 100kbps 200kbps 300kbps 90 –20 PACKET ERROR RATE (%) 80 –30 –40 –50 –60 –70 70 60 50 40 30 –80 20 –90 10 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz) 0 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 12027-248 –100 –1.0 Figure 31. Image Attenuation with Calibrated and Uncalibrated Images, 433 MHz, IF Filter Bandwidth = 100 kHz, VDD = 3.0 V, Temperature = 25°C 3.6 VDD (V) 0 ATTENUATION (dB) 1.8 APPLIED RECEIVER POWER (dBm) 0 12027-252 –0.8 12027-247 –90 –1.0 12027-250 –80 Figure 34. Packet Error Rate vs. RF Input Power and Radio Profile (Data Rate), FSK, 928 MHz, Preamble Length = 64 Bits, VDD = 3.0 V, Temperature = 25°C Rev. B | Page 19 of 24 ADF7024 Data Sheet –96.0 6 –96.5 4 –97.0 +25°C +85°C –97.5 RSSI ERROR (dB) SENSITIVITY (dBm) 300kbps 200kbps 100kbps 50kbps 38.4kbps 9.6kbps –40°C –98.0 –98.5 2 0 –2 –99.0 –6 –120 –110 –100 VDD (V) –40 6 –50 4 –60 2 –70 0 –80 –2 –90 –4 IDEAL RSSI MEAN RSSI MEAN RSSI ERROR MAX POSITIVE RSSI ERROR MAX NEGATIVE RSSI ERROR –100 –110 –120 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 RSSI ERROR (dB) 8 –6 –8 –10 –20 INPUT POWER (dBm) Figure 36. RSSI (via CMD_GET_RSSI) vs. RF Input Power, 868 MHz, GFSK, Radio Profile B, IF Bandwidth = 100 kHz, 100 RSSI Measurements at Each Power Level –70 –60 –50 –40 –30 –20 Figure 37. Mean RSSI Error (via Automatic End of Packet RSSI Measurement) vs. RF Input Power and Data Rate, RF = 868 MHz, GFSK, 100 RSSI Measurements at Each Input Power Level 12027-262 RSSI (dBm) 10 –30 –80 INPUT POWER (dBm) Figure 35. Receiver Sensitivity (Packet Error Rate at 1%) vs. VDD, Temperature, and RF, Radio Profile F, FSK, (Minimum Recommended VDD = 2.2 V, 1.8 V Operation Shown for Robustness) –20 –90 80 70 60 MEAN ACCURACY 50 40 30 20 10 ERROR 0 –10 –20 –30 –40 –40 –30 –20 –10 0 10 20 30 40 50 APPLIED TEMPERATURE (°C) 60 70 80 12027-170 3.6 TEMPERATURE CALCULATED FROM SENSOR (°C) 1.8 12027-254 –100.0 12027-264 –4 –99.5 Figure 38. Typical Accuracy Range of Temperature Sensor vs. Applied Temperature, Calibration Performed at 25°C Rev. B | Page 20 of 24 Data Sheet ADF7024 THEORY OF OPERATION For detailed information on the operation of the ADF7024, see the ADF7024 Hardware Reference Manual, UG-698, which is only available as part of the ADF7024 design resource package. SPI INTERFACE The ADF7024 is equipped with a 4-wire SPI interface, using the SCLK, MISO, MOSI, and CS pins. The ADF7024 always acts as a slave to the host processor. The SPI interface allows the host processor to perform the following operations on the ADF7024: 0x300 CONFIGURATION REGISTERS 64 BYTES 0x100 0x0FF PACKET RAM 240 BYTES 0x010 NOT RETAINED IN PHY_SLEEP 0x00F AUXILIARY RAM 16 BYTES 0x000 RETAINED IN PHY_SLEEP Figure 40. Memory Map HOST PROCESSOR 12027-272 ADF7024 AUXILIARY REGISTERS 256 BYTES 0x13F Figure 39 shows a typical connection diagram between the processor and the ADF7024. The diagram also shows the direction of the signal flow for each pin. GPIO SCLK MOSI MISO IRQ 0x3FF NOT USED Read and write to the ADF7024 memory spaces. Issue commands to the ADF7024. Read back the status of the ADF7024. Wake the ADF7024 from the PHY_SLEEP state. CS SCLK MOSI MISO IRQ_GP3 The ADF7024 memory map is shown in Figure 40. Each memory space consists of 8-bit registers with an address length of 11 bits. Figure 39. Host Processor Interface The status word of the ADF7024 is returned over the MISO automatically each time a byte is transferred over the MOSI. The status word contains the current ADF7024 state, the interrupt status and flags to indicate that the ADF7024 is ready to accept a new SPI memory access command or a radio control command. RADIO CONTROL Configuration Registers The configuration registers consist of 64 bytes of memory space used to configure the operation of the ADF7024. The radio profile registers form part of this memory space. The configuration registers are retained in the PHY_SLEEP radio state. Auxiliary Registers The auxiliary registers consist of 256 bytes of memory space used for auxiliary radio functions or observation of the radio blocks of the ADF7024. The ADF7024 has five radio states designated as PHY_SLEEP, PHY_OFF, PHY_ON, PHY_RX, and PHY_TX, as described in Table 11. The host processor can transition the ADF7024 between states by issuing single-byte, radio control commands over the SPI interface. Packet RAM Table 11. Radio States The auxiliary RAM memory is reserved for use by the ADF7024. State PHY_SLEEP (Deep Sleep Mode 2) PHY_SLEEP (Deep Sleep Mode 1) PHY_SLEEP (WUC enabled) PHY_OFF PHY_ON PHY_TX PHY_RX Current (Typical) 0.18 μA 0.33 μA 0.75 μA 1.0 mA 1.0 mA 24.1 mA 12.8 mA 12027-273 MEMORY MAP Conditions Wake-up timer off, configuration registers not retained, entered by issuing CMD_HW_RESET Wake-up timer off, configuration registers retained Wake-up timer on using the 32 kHz RC oscillator, configuration registers retained The packet RAM memory consists of 240 bytes of memory for storage of data from valid received packets and packet data to be transmitted. Auxiliary RAM RADIO BLOCKS Frequency Synthesizer A fully integrated RF synthesizer is used to generate both the transmit signal and the local oscillator (LO) signal of the receiver. A high speed, fully automatic calibration scheme ensures that the frequency and amplitude characteristics of the VCO are maintained over temperature, supply voltage, and process variations. The receive and transmit synthesizer bandwidths are automatically and independently configured to achieve optimum phase noise and settling time. 10 dBm, 868 MHz Rev. B | Page 21 of 24 ADF7024 Data Sheet Crystal Oscillator PACKET MANAGEMENT A 26 MHz crystal oscillator operating in parallel mode must be connected between the XOSC26P and XOSC26N pins to provide a reference for the ADF7024. Two parallel loading capacitors are required for oscillation at the correct frequency. Their values are dependent upon the crystal specification. The ADF7024 includes comprehensive transmit and receive packet management capabilities and can be configured for use with a wide variety of packet-based radio protocols. There are 240 bytes of dedicated packet RAM available to store, transmit, and receive packets. In transmit mode, a preamble, sync word, and CRC can be added by the ADF7024 to the payload data stored in the packet RAM. In addition, all packet data after the sync word can be optionally whitened, Manchester encoded, or 8bit/10-bit encoded on transmission and decoded on reception. Transmitter The ADF7024 supports binary frequency shift keying (FSK) and binary level Gaussian filtered FSK (GFSK) modulation. For GFSK modulation, the Gaussian filter uses a fixed BT of 0.5. The ADF7024 PA has a single-ended output that can deliver up to 13.5 dBm of output power. The output power can be set with a typical resolution of 0.5 dB. The PA has built-in up and down ramping, which reduces spectral splatter. Receiver The ADF7024 is based on a fully integrated, low IF receiver architecture. The differential LNA is followed by a quadrature downconversion mixer that converts the RF signal to the IF frequency of 200 kHz (for IF filter bandwidths of 100 kHz and 200 kHz) or 300 kHz (for IF filter bandwidths of 300 kHz). The IF filter bandwidth is configured to 100 kHz, 200 kHz, or 300 kHz, depending on the radio profile selected. The bandwidth and center frequency of the IF filter are calibrated automatically. The IF filter gives excellent interference suppression of adjacent and neighboring channels while also suppressing the image channel. The ADF7024 is capable of providing improved receiver image rejection performance by the use of a fully integrated image rejection calibration system. A correlator demodulator is used for demodulation. An oversampled digital clock and data recovery (CDR) PLL is used to resynchronize the received bit stream to a local clock. In receive mode, the ADF7024 can qualify received packets based on preamble detection, sync word detection, or CRC validation and generate an interrupt on the IRQ_GP3 pin. On reception of a valid packet, the received payload data is loaded to packet RAM memory. SMART WAKE MODES The ADF7024 can be configured to operate in a broad range of energy sensitive applications where battery lifetime is critical. This includes support for applications where the ADF7024 is required to operate in a fully autonomous mode or applications where the host processor controls the transceiver during low power mode operation. These low power modes are implemented using a hardware WUC, a firmware timer, and the SWM functionality. The combination of the low power WUC, the firmware timer, and the SWM allows the ADF7024 to wake up autonomously from sleep without intervention from the host processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby dramatically reducing overall system current consumption. The SWM can then wake the host processor on an interrupt condition. RADIO PROFILES The ADF7024 radio profiles provide a set of optimized register settings for the ADF7024 radio. There are six radio profiles in total, as shown in Table 1. The profiles cover common data rates and modulation options. For further information on the ADF7024 radio profiles, see the ADF7024 Hardware Reference Manual, UG-698, which is only available as part of the ADF7024 design resource package. Rev. B | Page 22 of 24 Data Sheet ADF7024 TYPICAL APPLICATION CIRCUIT ground on the PCB. The component values for the matching and harmonic filtering are dependent on the RF band and the matching topology. For more information, see the ADF7024 Hardware Reference Manual, UG-698, which is only available as part of the ADF7024 design resource package. Figure 41 shows a typical application circuit for the ADF7024. All external components required for operation of the device, excluding supply decoupling capacitors, are shown. This example circuit uses a combined transmit and receive match. The bottom of the LFCSP has an exposed pad that must be soldered to VDD 220nF 25 GP4 GND PAD 220nF 220nF CREGDIG1 DGUARD GP0 23 22 21 20 19 GPIO MOSI SCLK MISO IRQ 18 17 16 XOSC26N GP1 15 VDDBAT2 NC GP2 24 HOST PROCESSOR 26 CREGDIG2 27 GP5_ATB1 29 28 ATB2 VDDBAT1 30 RFO XOSC26P 8 IRQ_GP3 ADF7024 RFI_N 14 7 MISO CWAKEUP VDD RFI_P 9 220nF 150nF 26MHz CRYSTAL 12027-271 ANTENNA CONNECTION CS SCLK 13 6 100kΩ CREGRF2 CREGSYNTH 5 HARMONIC FILTER VDD MOSI 12 4 RBIAS VCOGUARD 3 CREGRF1 11 1 36kΩ 2 CREGVCO COMBINED TX/RX MATCH 10 220nF ADCIN_ATB3 32 220nF ADCVREF 31 ATB4 220nF Figure 41. Typical ADF7024 Application Circuit Diagram Rev. B | Page 23 of 24 ADF7024 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 SQ 4.90 32 25 1 24 0.50 BSC 3.45 3.30 SQ 3.15 EXPOSED PAD 17 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 9 BOTTOM VIEW 0.25 MIN 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 05-24-2012-A PIN 1 INDICATOR 0.30 0.25 0.18 Figure 42. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-13) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADF7024BCPZ ADF7024BCPZ-RL EVAL-ADF7XXXMB4Z EVAL-ADF7024DB1Z EVAL-ADF7024DB2Z EVAL-ADF7024DB3Z EVAL-ADF7024DB4Z 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Evaluation Board (Motherboard) Evaluation Board (RF Daughter Board, 862 MHz to 928 MHz, Separate Match) Evaluation Board (RF Daughter Board, 862 MHz to 928 MHz, Combined Match) Evaluation Board (RF Daughter Board, 431 MHz to 435 MHz, Separate Match) Evaluation Board (RF Daughter Board, 431 MHz to 435 MHz, Combined Match) Z =RoHS Compliant Part. ©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12027-0-7/15(B) Rev. B | Page 24 of 24 Package Option CP-32-13 CP-32-13