LT3692 Monolithic Dual Tracking 3.5A Step-Down Switching Regulator Description Features Wide Input Range: – Operation from 3V to 36V – OVLO Protects Circuit Through 60V Transients n Independent Supply, Shutdown, Soft-Start, Programmable Current Limit and Programmable Power Good for Each 3.5A Regulator n Die Temperature Monitor n Adjustable/Synchronizable Fixed Frequency Operation from 250kHz to 2.25MHz with Synchronized Clock Output n Independent Synchronized Switching Frequencies Optimize Component Size n Antiphase Switching n Outputs Can Be Paralleled n Flexible Output Voltage Tracking n Enhanced Short-Circuit Protection n Low Dropout: 95% Maximum Duty Cycle n5mm × 5mm QFN Package The LT®3692 is a dual current mode PWM step-down DC/DC converter with two internal 3.8A switches. Independent input voltage, shutdown, feedback, soft-start, current limit and comparator pins for each channel simplify complex power supply tracking and sequencing requirements. n To optimize efficiency and component size, both converters have a programmable maximum current limit and are synchronized to either a common external clock input, or a resistor settable fixed 250kHz to 2.25MHz internal oscillator. A frequency divider is provided for channel 1 to further optimize component size. At all frequencies, a 180° phase relationship between channels is maintained, reducing voltage ripple and component size. A clock output is available for synchronizing multiple regulators. Minimum input to output voltage ratios are improved by allowing the switch to stay on through multiple clock cycles only switching off when the boost capacitor needs recharging. Independent channel operation can be programmed using the SHDN pin. Disabling both converters reduces the total quiescent to <10µA. Applications Automotive Supplies Distributed Supply Regulation n L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Typical Application Independent Synchronized Switching Frequencies Extend Full Frequency Input Range Dual 1.8V/3.5A and 5V/3.5A Step-Down Converter VIN 6V TO 32V 4.7µF ×2 VOUT1 1.8V 3.5A 500kHz/ 250kHz 143k 7.15k 6.8µH 0.47µF SW1 VIN2 VIN1 SHDN1 BST1 VOUT2 CLKOUT SHDN2 BST2 SW1 SW2 IND1 IND2 SW2 6.8µH 1µF LT3692 100µF ×2 8.06k 10k FB1 SS2 60.4k ILIM2 CMPI2 CMPO1 CMPO2 SS1 680pF 47pF 17.8k 13.0k 42.2k 100k 8.06k PG2 VIN = 12V 1µs/DIV 3692 TA01b VIN = 24V 1µs/DIV 3692 TA01c CLKOUT SS2 ILIM1 VC1 60.4k FB2 CMPI1 DIV VOUT2 5V 3.5A 47µF 500kHz VOUT2 VOUT1 ILIM2 CLKOUT VC2 RT/SYNC GND TJ 0.1µF CLOCKOUT 500kHz 330pF 36.5k SW1 60.4k 0.1µF 33pF 3692 TA01a For more information www.linear.com/3692 SW2 3692fa 1 LT3692 SS1 VIN1 SW1 DNC* IND1 DNC* TOP VIEW VOUT1 32 31 30 29 28 27 26 25 BST1 1 24 ILIM1 CMPO1 2 23 VC1 22 RT/SYNC CMPI1 3 FB1 4 21 CLKOUT 33 GND FB2 5 20 TJ CMPI2 6 19 DIV CMPO2 7 18 VC2 17 ILIM2 BST2 8 SS2 SHDN2 VIN2 SW2 DNC* 9 10 11 12 13 14 15 16 IND2 VIN1/2, SHDN1/2, CMPO1/2............................. 40V/–0.3V VIN1/2 Transient (Note 2)................................. 60V/–0.3V SW1/2.....................................................................VIN1/2 BST1/2............................................................ 60V/–0.3V BST1/2 Pin Above SW1/2...........................................25V IND1/2, VOUT1/2..........................................40V/–0.3V, 7A FB1/2, CMPI1/2, SS1/2.................................................5V RT/SYNC......................................................................5V DIV, ILIM1/2..............................................................2.5V VC1/2, TJ............................................................... ±100µA Operating Junction Temperature Range (Note 3) LT3692EUH......................................... –40°C to 125°C LT3692IUH.......................................... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C SHDN1 Pin Configuration DNC* (Note 1) VOUT2 Absolute Maximum Ratings UH PACKAGE 32-LEAD (5mm × 5mm) PLASTIC QFN θJA = 35°C/W EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB *DO NOT CONNECT Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3692EUH#PBF LT3692EUH#TRPBF 3692 –40°C to 125°C 32-Lead (5mm × 5mm) Plastic QFN LT3692IUH#PBF LT3692IUH#TRPBF 3692 –40°C to 125°C 32-Lead (5mm × 5mm) Plastic QFN Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ The l denotes the specifications which apply over the full operating Electrical Characteristics temperature range, otherwise specifications are at TA = 25°C. VVIN1/2 = 15V unless otherwise specified. (Note 3) PARAMETER CONDITIONS SHDN Voltage Threshold Ch 1/2 (Note 4) l SHDN Input Current Ch 1/2 VSHDN = 1.3V VIN1 Undervoltage Lockout (Note 5) VFB1/2 = 0V, VVOUT1/2 = 0V, VIND1/2 = 0V VIN Overvoltage Lockout Ch 1/2 (Note 6) MIN TYP MAX 1.24 1.32 1.4 UNITS V 1.5 5 µA 2.5 2.8 3.1 V 36 38 41 V VIN1 Shutdown Current VSHDN = 0V l 6 10 µA VIN2 Shutdown Current VSHDN = 0V l 0 2 µA VIN1 Quiescent Current VFB1/2 = 0.9V 3 4 5 mA VIN2 Quiescent Current VFB1/2 = 0.9V 400 630 1000 µA Feedback Voltage Ch 1/2 VVC1/2 = 1V 790 806 822 mV 2 l 3692fa For more information www.linear.com/3692 LT3692 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VVIN1/2 = 15V unless otherwise specified. (Note 3) PARAMETER CONDITIONS Feedback Voltage Regulation VVIN1/2 = 3 to 40V, VVC1/2 = 0.6 to 1.6V Feedback Voltage Offset Ch 1 to Ch 2 VVC1/2 = 1V Feedback Bias Current Ch 1/2 VFB1/2 = 0.8V, VVC1/2 = 1V TJ Output Voltage (Note 7) TJ = 25°C, ITJ = 25µA, Temperature = 25°C ITJ = 25µA, Temperature = 125°C ITJ = 25µA, Temperature = –40°C TJ Error MIN TYP MAX UNITS l 780 806 830 mV l –12 0 12 mV l 0 85 200 250 1.23 –380 nA mV V mV –60 0 60 mV Error Amp gm Ch 1/2 VVC1/2 = 1V, IVC1/2 = ±5µA 350 400 450 µMho Error Amp Source Current Ch 1/2 VFB1/2 = 0.6V, VVC1/2 = 1V 19 25 31 µA Error Amp Sink Current Ch 1/2 VFB1/2 =1V, VVC1/2 = 1V 22 28 34 µA Error Amp High Clamp Ch 1/2 VFB1/2 = 0.6V 1.7 1.9 2.1 V 0.75 0.9 1.05 V 9.5 12 14.5 µA l Error Amp Switching Threshold Ch 1/2 VFB1/2 = 0.6V Soft-Start Source Current Ch 1/2 VFB1/2 = 0.9V, VSS1/2 = 0.05V l Soft-Start VOH Ch 1/2 VFB1/2 = 0.9V 1.9 2.15 2.4 Soft-Start Sink Current Ch 1/2 VFB1/2 = 0.4V, VSS1/2 = 2V 0.9 1.4 2 mA Soft-Start VOL Ch 1/2 VFB1/2 = 0V 120 160 200 mV Soft-Start to Feedback Offset Ch 1/2 VVC1/2 = 1V, VSS1/2 = 0.4V –12 0 12 mV Soft-Start Sink Current Ch 1/2 POR VFB1/2 = 0V, VSS1/2 = 0.12V (Note 8) 150 400 600 µA Soft-Start POR Threshold Ch 1/2 VFB1/2 = 0V (Note 8) 70 90 120 mV Soft-Start SW Disable Ch 1/2 VFB1/2 = 0V (Note 8) 95 115 150 mV CMPI Bias Current Ch 1/2 VCMPI1/2 = 0.8V CMPO Leakage Ch 1/2 VCMP1/2 = 0.8V, VCMPO1/2 = 25V, CMPI Threshold Ch 1/2 VCMPI1/2 Rising CMPI Threshold Ch 1/2 of VFB1/2 VCMPI1/2 Rising (Note 9) 86 90 94 % CMPI Hysteresis Ch 1/2 VCMPI1/2 35 60 85 mV CMPO Sink Current Ch 1/2 VCMPI1/2 = 0.6V, VCMPO1/2 = 0.2V, RT/SYNC Reference Current VFB1/2 = 0.9V, VRT/SYNC = 0.5V l –100 l l 700 V 0 100 nA 70 200 nA 720 740 mV 200 300 400 µA 11.3 12 12.7 µA Minimum Switching Frequency RRT/SYNC =0Ω 50 110 150 kHz Switching Frequency RRT/SYNC = 28k 925 1 1075 MHz Maximum Switching Frequency RRT/SYNC =100k 2.25 2.5 2.75 MHz Switching Phase Angle Ch 1 ≥ Ch 2 DIV Reference Current 185 VFB1/2 = 0.9V, VDIV = 0.5V l Deg 10.5 12 13.5 µA CH1 DIV 2 Threshold RRT/SYNC = 0V 0.51 0.58 0.61 V CH1 DIV 4 Threshold RRT/SYNC = 0V 0.9 1.05 1.1 V 1.45 CH1 DIV 8 Threshold RRT/SYNC = 0V CLKOUT VOL ICLKOUT = –100µA 1.55 V 0.25 V CLKOUT VOH ICLKOUT = 100µA 2 V CLKOUT to SW1ON Delay ( tDCLKOSW1) CLKOUT Rising 60 ns CLKOUT to SW2ON Delay ( tDCLKOSW2) CLKOUT Falling 30 ns 3692fa For more information www.linear.com/3692 3 LT3692 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VVIN1/2 = 15V unless otherwise specified. (Note 3) PARAMETER CONDITIONS RT/SYNC to CLKOUT Delay ( tDRTSYNCH) VRT/SYNC = 0V to 2V Rising Edge MIN RT/SYNC to CLKOUT Delay ( tDRTSYNCL) VRT/SYNC = 2V to 0V Falling Edge MAX 300 250 SYNC Frequency = 250kHz UNITS ns 150 SYNC Frequency Range SYNC Phase Angle Ch 1 to Ch 2 TYP ns 2000 kHz 180 Deg Minimum Switch On-Time Ch 1/2 180 ns Minimum Switch Off-Time Ch 1/2 200 ns Minimum Boost for 100% DC Ch 1/2 (Note 10) 1.4 IND + VOUT Current Ch 1/2 VVOUT1/2 = 0V VVOUT1/2 = 5V ILIM1/2 Reference Current VFB1/2 = 0.9V, VILIM = 0.4V IND to VOUT Maximum Current Ch 1/2 2.2 V 1.5 0.5 5 5 µA µA l 10 12 14 µA VILIM1/2 = 0V, VVOUT = 1V (Note 11) VILIM1/2 = 0V, VVOUT = 5V (Note 11) VILIM1/2 = 0.5V, VVOUT = 1V (Note 11) VILIM1/2 = 0.5V, VVOUT = 5V (Note 11) VILIM1/2 = 1.5V, VVOUT = 1V (Note 11) VILIM1/2 = 1.5V, VVOUT = 5V (Note 11) l l 1 1.25 1.6 1.8 3.8 3.8 1.8 2 2.6 2.8 4.8 4.8 2.6 2.75 3.6 3.8 5.8 5.8 A A A A A A l 1 5.0 Switch Leakage Current Ch 1/2 VSW1/2 = 0V Switch Saturation Voltage Ch 1/2 ISW1/2 = 500mA, VBST1/2 = 18V ISW1/2 = 3A, VBST1/2 = 18V Boost Current Ch 1/2 ISW1/2 = 500mA, VBST1/2 = 18V ISW1/2 = 3A, VBST1/2 = 18V Minimum Boost Voltage Ch1/2 (Note 12) ISW1/2 = 3A, VBST1/2 = 18V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Absolute Maximum Voltage at VIN1/2 and SHDN1/2 pins is 60V for nonrepetitive 1 second transients and 40V for continuous operation. Note 3: The LT3692EUH is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3692IUH is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 4: The SHDN pins can be connected to VIN or driven by a logic-level source with a series current limiting resistor. Note 5: VIN undervoltage lockout is defined as the voltage which the VIN pin must exceed for operation. The threshold guarantees that internal bias lines are regulated and switching frequency is constant. Actual minimum input voltage to maintain a regulated output will depend upon output voltage and load current. See Applications Information. Note 6: VIN overvoltage lockout is defined as the voltage when exceeded halts converter operation. See Applications Information. 4 1.8 100 300 µA mV mV 9 40 13 55 17 70 mA mA 1.75 2.0 2.5 V Note 7: The TJ output voltage represents the temperature at the center of the die while dissipating quiescent power. Due to switch power dissipation and temperature gradients across the die, the TJ output voltage measurement does not guarantee that absolute maximum junction temperature will not be exceeded. Note 8: An internal power on reset (POR) latch is set on the positive transition of the SHDN1/2 pin through its threshold, thermal shutdown or overvoltage lockout. The output of the latch activates current sources on each SS pin which typically sink 400µA and discharge the SS capacitor. The latch is reset when both SS pins are driven below the soft-start POR threshold or the SHDN pin is taken below its threshold. Note 9: The threshold is expressed as a percentage of the feedback reference voltage for the channel. Note 10: To enhance dropout operation, the output switch will be turned off for the minimum off-time only when the voltage across the boost capacitor drops below the minimum boost for 100% duty cycle threshold. Note 11: The IND to VOUT maximum current is defined as the value of current flowing from the IND pin to the VOUT pin which resets the switch latch when the VC pin is at its high clamp. Note 12: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. 3692fa For more information www.linear.com/3692 LT3692 Typical Performance Characteristics 50 3.5 39.5 VIN = 15V VSHDN = 15V 40 2.5 2.0 SHUTDOWN THRESHOLD VOLTAGE 1.5 25 20 0 0 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 0 35.0 –50 –25 6000 10 9 5000 FB Voltage and CH1-CH2 FB Offset vs Temperature 820 VSHDN1 = VSHDN2 = 0V 2000 125°C FEEDBACK VOLTAGE (V) CURRENT (µA) –50°C IQ1 6 5 4 3 2 1000 0.2 0.4 1 0.6 0.8 VOLTAGE (V) 1.2 0 –50 –25 1.4 3692 G04 0.25 RTJ = 30k TO GND 0 RTJ = 30k TO –1V 0 3692 G07 –2 CH2 805 –4 CH1 0 –8 25 50 75 100 125 150 TEMPERATURE (°C) 3692 G06 Soft-Start-to-Feedback Offset vs Temperature 4 VSS = 0.4V 3 415 2 410 405 400 395 390 385 1 0 –1 –2 380 –3 375 25 50 75 100 125 150 TEMPERATURE (°C) 0 800 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) VOLTAGE (mV) TRANSCONDUCTANCE (µMho) 0.50 –0.50 –50 –25 0 420 1.25 –0.25 IQ2 425 0.75 810 Error Amplifier Transconductance vs Temperature 1.50 2 OFFSET 3692 G05 TJ Output Voltage vs Temperature 1.00 4 –6 1 0 815 OFFSET VOLTAGE (mV) 7 8 6 8 25°C 25 50 75 100 125 150 TEMPERATURE (°C) 3692 G03 Shutdown Quiescent Current vs Temperature 4000 0 3692 G02 VIN1 Quiescent Current vs SHDN1 Voltage 3000 37.0 35.5 25 50 75 100 125 150 TEMPERATURE (°C) 3692 G01 150°C 37.5 36.0 VIN = 15V VSHDN = 1.3V 5 0 –50 –25 38.0 36.5 10 0.5 IQ (µA) 38.5 30 15 1.0 VOLTAGE (V) 39.0 VOLTAGE (V) 35 CURRENT (µA) VOLTAGE (V) 40.0 45 MINIMUM INPUT VOLTAGE 3.0 0 VIN Overvoltage Threshold vs Temperature Shutdown Pin Input Current vs Temperature Shutdown Threshold and Minimum Input Voltage vs Temperature 370 –50 –30 –10 10 30 50 70 90 110 130 150 TEMPERATURE (°C) 3692 G08 –4 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3692 G09 3692fa For more information www.linear.com/3692 5 LT3692 Typical Performance Characteristics Comparator Sink Current vs Temperature Comparator Thresholds vs Temperature 750 400 740 RISING THRESHOLD CURRENT (µA) 700 690 680 0 200 150 1200 800 600 400 0 CLKOUT-to-SW1 Delay vs Temperature RT/SYNC-to-CLKOUT and SW1 Delay vs Temperature 400 191 140 350 189 130 187 120 DELAY (ns) 450 150 DELAY (ns) 160 193 110 100 200 150 179 80 100 177 70 50 60 –50 –25 0 MAXIMUM RT/SYNC DUTY CYCLE ÷4 1.0 0.8 ÷2 0.6 MINIMUM RT/SYNC DUTY CYCLE 0.4 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3692 G16 0 –50 –25 200 ISW = 1A 150 100 ISW = 500mA 50 0.2 10 6 1.2 VOLTAGE (mV) 40 ISW = 3A 250 1.4 50 20 300 ÷8 1.6 70 30 Switch Saturation Voltage vs Temperature 1.8 RT/SYNC FREQUENCY = 1MHz 60 25 50 75 100 125 150 TEMPERATURE (°C) 3695 G15 DIV Voltage Threshold vs Temperature VOLTAGE (V) DUTY CYCLE (%) 80 0 3692 G14 Synchronization Duty Cycles vs Temperature 90 0 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 3692 G13 100 CLKOUT 250 90 25 50 75 100 125 150 TEMPERATURE (°C) SW1 300 181 0 25 50 75 100 125 150 TEMPERATURE (°C) 3692 G12 195 175 –50 –25 0 3692 G11 Switching Phase vs Temperature 183 RRT/SYNC = 0k 0 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 3692 G10 185 RRT/SYNC = 13.0k 200 0 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) RRT/SYNC = 28.0k 1000 50 660 650 –50 –25 250 100 FALLING THRESHOLD 670 1400 300 710 RRT/SYNC = 44.2k 1600 FREQUENCY (kHz) 730 VOLTAGE (mV) 1800 SINK CURRENT AT VCMPO = 0.4V 350 720 PHASE (DEG) Switching Frequency vs Temperature 0 25 50 75 100 125 150 TEMPERATURE (°C) 3695 G17 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3692 G18 3692fa For more information www.linear.com/3692 LT3692 Typical Performance Characteristics Switch Peak Current vs Temperature 5.0 90 4.5 80 4.0 70 3.5 3A 50 40 30 10 0 –50 –25 0 2.50 3.0 VILIM = 0.5V 2.5 VILIM = 0V 1.5 0 –50 –25 0 90 2500 Efficiency, TJ vs Load Current 88 EFFICIENCY 84 20 82 TJ 80 30 40 50 60 RESISTANCE (kΩ) 70 80 90 78 VIN = 12V VOUT = 5V FREQ = 1MHz 0 0.5 1 1.5 2 2.5 3 LOAD CURRENT (A) Efficiency, TJ vs Load Current 3.5 30 72 20 VIN = 12V VOUT = 2.5V FREQ = 1MHz 1 1.5 2 2.5 3 LOAD CURRENT (A) 3.5 10 4 0 EFFICIENCY (%) TJ 0.5 TJ 40 30 76 10 72 0 70 20 VIN = 12V VOUT = 3.3V FREQ = 1MHz 0 0.5 1 1.5 2 2.5 3 LOAD CURRENT (A) 4 0 3692 G24 Efficiency, TJ vs Load Current 60 EFFICIENCY 50 74 40 72 TJ 70 30 68 20 66 64 VIN = 12V VOUT = 1.8V FREQ = 1MHz 62 60 3.5 10 TJ (°C) 40 TJ (°C) 76 0 50 78 74 76 50 70 4 60 EFFICIENCY 80 20 78 60 EFFICIENCY 78 68 80 70 74 82 70 3692 G23 82 80 60 30 76 70 84 40 3692 G22 EFFICIENCY (%) 10 70 50 74 0 Efficiency, TJ vs Load Current 86 TJ (°C) EFFICIENCY (%) 86 72 0 25 50 75 100 125 150 TEMPERATURE (°C) 3692 G21 80 TJ (°C) FREQUENCY (kHz) 2000 500 0 3692 G20 Switching Frequency vs RT/SYNC Resistance 1000 1.75 1.00 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 3692 G19 1500 2.00 1.25 0.5 25 50 75 100 125 150 TEMPERATURE (°C) 2.25 1.50 1.0 0.5A ISW = 3A 2.75 VILIM = 1.5V 2.0 1A 20 3.00 EFFICIENCY (%) 60 Minimum Boost Voltage vs Temperature VOLTAGE (V) 100 PEAK CURRENT (A) BOOST CURRENT (mA) Boost Current vs Temperature 0 0.5 3692 G25 1 1.5 2 2.5 3 LOAD CURRENT (A) 3.5 10 4 0 3692 G26 3692fa For more information www.linear.com/3692 7 LT3692 Pin Functions BST1/2: The BST pin provides a higher than VIN base drive to the power NPN to ensure a low switch drop. If the voltage between the BST pin and the VIN pin is less than the voltage required to fully turn on the power NPN, the power switch is turned off to recharge the BST capacitor. CMPI1/2: The CMPI pin is an input to a comparator with a threshold of 720mV and 60mv of hysteresis. Connecting the CMPI pin to the FB pin will generate a power good signal when the output is within 90% of its regulated value. CMPO1/2: The CMPO pin is an open-collector output that sinks current when the CMPI pin falls below its threshold. For a typical input voltage above 2.8V, its output state remains true, although during shutdown, VIN1 undervoltage lockout or thermal shutdown, its current sink capability is reduced. The COMPO pins can be left open circuit or tied together to form a single power good signal. DIV: The voltage present at the DIV pin determines the ratio of channel 1 frequency to the master clock frequency set by the RT/SYNC pin. The DIV pin is driven by an internal current source with a typical value of 12µA which allows a single resistor from the DIV pin to ground to set the DIV voltage and resulting channel 1 frequency divider. Ratios of 1, 2, 4 and 8 are available. See the Applications Information section for more information. DNC: Do Not Connect. GND: The exposed pad pin is the only ground connection for the device. The exposed pad should be soldered to a large copper area to reduce thermal resistance. The GND pin is common to both channels and also serves as small-signal ground. For ideal operation all small-signal ground paths should connect to the GND pin at a single point avoiding any high current ground returns. FB1/2: The FB pin is the negative input to the error amplifier. The output switches to regulate this pin to 806mV with respect to the exposed ground pad. Bias current flows out of the FB pin. 8 ILIM1/2: The voltage present at the ILIM pin determines the peak inductor current for the channel. The ILIM pin is driven by an internal current source with a typical value of 12µA. A resistor from the ILIM pin to ground sets the ILIM voltage. The maximum current limit range is 4.8A to 2A when the ILIM voltages are 1.5V and 0V respectively. IND1/2: The IND pin is the input to the internal sense resistor that measures current flowing in the inductor. When the current in the resistor exceeds the current dictated by the VC pin, the SW latch is held in reset, disabling the output switch. Bias current flows out of the IND pin. RT/SYNC: The voltage present at the RT/SYNC pin determines the constant switching frequency. The RT/SYNC pin is driven by an internal current source with a typical value of 12µA which allows a single resistor from the RT/ SYNC pin to ground to set the RT/SYNC voltage and resulting switching frequency. Minimum switching frequency is typically 110kHz when VRT/SYNC is 0V and maximum switching frequency is typically 2.5MHz when VRT/SYNC is above 950mV. Driving the RT/SYNC pin with an external clock signal will synchronize the switch to the applied frequency. Synchronization occurs on the rising edge of the clock signal after the clock signal is detected. Each rising clock edge initiates an oscillator ramp reset. A gain control loop servos the oscillator charging current to maintain constant oscillator amplitude. Hence, the slope compensation and channel phase relationship remain unchanged. If the clock signal is removed, the oscillator reverts to resistor mode after the synchronization detection circuitry times out. The clock source impedance should be set such that the current out of the RT/SYNC pin in resistor mode generates a frequency roughly equivalent to the synchronization frequency. See the Applications Information section for more information. 3692fa For more information www.linear.com/3692 LT3692 pin functions SHDN1/2: The shutdown pin is used to control each channel’s operation. In addition to controlling channel 1, the SHDN1 pin also activates control circuitry for both channels and must be present for channel 2 to operate. When SHDN1 is below its threshold, switching on both channels is halted. Further reducing the SHDN1 voltage to 0.6V reduces the quiescent current to a typical value of 6µA. If the shutdown features are not used, the SHDN pin can be tied to VIN. If SHDN pin is driven by a logic signal, a series resistor is required. See Applications Information. SS1/2: Current flowing out the SS pin into an external capacitor defines the rise time of the output voltage. When the SS pin is lower than the 0.8V reference, the feedback is regulated to the SS voltage. When the SS pin exceeds the reference voltage, the output will regulate the FB pin voltage to 0.8V and the SS pin will continue to rise until its clamp voltage. During an output overload, the VC pin is driven above the maximum switch current level activating its voltage clamp. When the VC clamp is activated, the SS pin is discharged until the output reaches a regulation point that the maximum output current can maintain. When the overload condition is removed, the output soft starts from that voltage. In the case of a SHDN or thermal shutdown event, a power on reset latch ensures the capacitors on both channels are fully discharged before either is released. Connecting both SS pins together ensures the outputs track together. CLKOUT: The CLKOUT pin generates a square wave of 0V to 2.5V which is synchronized to the internal oscillator. If the switching frequency is set by an external resistor the resultant clock duty cycle will be 50%. If the RT/SYNC pin is driven by an external clock source, the resultant CLKOUT duty cycle will mirror the external source. TJ: The TJ pin outputs a voltage proportional to junction temperature. The pin is 250mV for 25°C and has a slope of 10mV/°C. See the Applications Information section for more information. VC1/2: The VC pin is the output of the error amplifier and the input to the peak switch current comparator. It is normally used for frequency compensation, but can also be used as a current clamp or control loop override. If the error amplifier drives VC above the maximum switch current level, a voltage clamp activates. This indicates that the output is overloaded and current is pulled from the SS pin reducing the regulation point. VIN1: The VIN1 pin powers the internal control circuitry for both channels and is monitored by overvoltage/undervoltage lockout comparators. The VIN1 pin is also connected to the collector of channel 1’s on-chip power NPN switch. The VIN1 pin has high dI/dt edges and must be decoupled to ground close to the pin of the device. VIN2: The VIN2 pin powers the output stage for channel 2 and is monitored by overvoltage/undervoltage lockout comparators. VIN1 voltage must be greater than 2.8V for VIN2 operation. The VIN2 pin is also the collector of channel 2’s on-chip power NPN switch. The VIN2 pin has high dI/ dt edges and must be decoupled to ground close to the pin of the device. VOUT1/2: The VOUT pin is the output to the internal sense resistor that measures current flowing in the inductor. When the current in the resistor exceeds the current dictated by the VC pin, the SW latch is held in reset disabling the output switch. Bias current flows out of the VOUT pin. SW1/2: The SW pin is the emitter of the internal power NPN. At switch off, the inductor will drive this pin below ground with a high dV/dt. An external Schottky catch diode to ground, close to the SW pin and respective VIN decoupling capacitor’s ground, must be used to prevent this pin from excessive negative voltages. 3692fa For more information www.linear.com/3692 9 LT3692 Block Diagram VIN1 1.3V SHDN1 + – + – VIN1 38V CHANNEL 1 THERMAL SHUTDOWN 2.5V 12µA SS1 S – + 90mV – + S PRE PRE Q R DROPOUT ENHANCEMENT BST1 DRIVER CIRCUITRY SW1 + – Q R IND1 VOUT1 VC1 R1 FB1 2.5V ILIM1 RLIM CMPI1 12µA SLOPE COMPENSATION 2.5V 0.72V CMPO1 + – TJ CLK1 2.5V DIV 0.806V 12µA RT/SYNC R3 + + – R2 12µA OSCILLATOR AND AGC MASTER CLOCK VIN1 CLK2 TO CHANNEL 2 2.8V + – INTERNAL REGULATOR AND REFERENCES 2.5V CLKOUT GND RDIV 3692 F01 Figure 1. LT3692 Block Diagram Applications Information The LT3692 is a dual channel, constant frequency, current mode buck converter with internal 3.5A switches. Each channel can be independently controlled with the exception that VIN1 must be above the 2.8V undervoltage lockout threshold to power the common internal regulator, oscillator and thermometer circuitry. If the SHDN1 pin is taken below its 1.3V threshold switching on both channels will be disabled. Further reducing the SHDN1 below a typical value of 0.6V will place the LT3692 in a low quiescent current mode. In this mode the LT3692 typically draws 6µA from VIN1 and <1µA from VIN2. When the SHDN pin is driven above 1.3V, the internal bias circuits turn on generating an internal regulated voltage, 0.806VFB, 12µA RT/SYNC, DIV and ILIM current references, and a POR signal which sets the soft-start latch. 10 Once the internal reference reaches its regulation point, the internal oscillator will start generating a master clock signal for the two regulators at a frequency determined by the voltage present at the RT/SYNC pin. The channel 1 clock is then divided by 1, 2, 4 or 8 depending on the voltage present at the DIV pin. Channel 2’s clock runs at the master clock frequency with a 180° phase shift from channel 1. Alternatively, if a synchronization signal is detected by the LT3692 the RT/SYNC pin, the master clock will be generated at the incoming frequency on the rising edge of the synchronization pulse with channel 1 in phase with the synchronization signal. Frequency division and phase remains the same as the internally generated master clock. 3692fa For more information www.linear.com/3692 LT3692 Applications Information In addition, the internal slope compensation will be automatically adjusted to prevent subharmonic oscillation during synchronization. In either mode of oscillator operation, a square wave with the master clock frequency, synchronized to channel 1 is present at the CLKOUT pin. The two regulators are constant frequency, current mode step-down converters. Current mode regulators are controlled by an internal clock and two feedback loops that control the duty cycle of the power switch. In addition to the normal error amplifier, there is a current sense amplifier that monitors switch current on a cycle-by-cycle basis. This technique means that the error amplifier commands current to be delivered to the output rather than voltage. A voltage fed system will have low phase shift up to the resonant frequency of the inductor and output capacitor, then an abrupt 180° shift will occur. The current fed system will have 90° phase shift at a much lower frequency, but will not have the additional 90° shift until well beyond the LC resonant frequency. This makes it much easier to frequency compensate the feedback loop and also gives much quicker transient response. The Block Diagram in Figure 1 shows only one of the switching regulators whose operation will be discussed below. The additional regulator will operate in a similar manner with the exception that its clock will be 180° out of phase with the other regulator. When, during power-up, an internal POR signal sets the soft-start latch, both SS pins will be discharged to ground to ensure proper start-up operation. When the SS pin voltage drops below 90mV, the VC pin is driven low disabling switching and the soft-start latch is reset. Once the latch is reset the soft-start capacitor starts to charge with a typical value of 12µA. As the voltage rises above 115mV on the SS pin, the VC pin will be driven high by the error amplifier. When the voltage on the VC pin exceeds 0.8V, the clock set-pulse sets the driver flip-flop, which turns on the internal power NPN switch. This causes current from VIN, through the NPN switch, inductor and internal sense resistor to increase. When the voltage drop across the internal sense resistor exceeds a predetermined level set by the voltage on the VC pin, the flip-flop is reset and the internal NPN switch is turned off. Once the switch is turned off the inductor will drive the voltage at the SW pin low until the external Schottky diode starts to conduct, decreasing the current in the inductor. The cycle is repeated with the start of each clock cycle. However, if the internal sense resistor voltage exceeds the predetermined level at the start of a clock cycle, the flip-flop will not be set resulting in a further decrease in inductor current. Since the output current is controlled by the VC voltage, output regulation is achieved by the error amplifier continually adjusting the VC pin voltage. The error amplifier is a transconductance amplifier that compares the FB voltage to the lowest voltage present at either the SS pin or an internal 806mV reference. Compensation of the loop is easily achieved with a simple capacitor or series resistor/capacitor from the VC pin to ground. The regulators’ maximum output current occurs when the VC pin is driven to its maximum clamp value by the error amplifier. The value of the maximum switch current can be programmed from 4.8A to 2A by placing a resistor from the ILIM pin to ground. Since the SS pin is driven by a constant current source, a single capacitor on the soft-start pin will generate controlled linear ramp on the output voltage. If the current demanded by the output exceeds the maximum current dictated by the VC pin clamp, the SS pin will be discharged, lowering the regulation point until the output voltage can be supported by the maximum current. Once the overload condition is removed, the regulator will soft-start from the overload regulation point. Shutdown control, VIN overvoltage, or thermal shutdown will set the soft-start latch, resulting in a complete softstart sequence. The switch driver operates from either the VIN or BST voltage. An external diode and capacitor are used to generate a drive voltage higher than VIN to saturate the output NPN and maintain high efficiency. If the BST capacitor voltage is sufficient, the switch is allowed to operate to 100% duty cycle. If the boost capacitor discharges towards a level insufficient to drive the output NPN, a BST pin comparator forces a minimum cycle off time, allowing the boost capacitor to recharge. 3692fa For more information www.linear.com/3692 11 LT3692 Applications Information A comparator with a threshold of 720mV and 60mV of hysteresis is provided for detecting error conditions. The CMPO output is an open-collector NPN that is off when the CMPI pin is above the threshold allowing a resistor to pull the CMPO pin to a desired voltage. The voltage present at the TJ pin is proportional to the junction temperature of the LT3692. The TJ pin will be 250mV for a die temperature of 25°C and will have a slope of 10mV/°C. Choosing the Output Voltage The output voltage is programmed with a resistor divider between the output and the FB pin. Choose the 1% resistors according to: V R1= R2 • OUT – 1 0.806 the RT/SYNC pin which determines the master oscillator frequency as illustrated in Figure 2. A 0V to 2.5V square wave with the same frequency as the master oscillator and in phase with channel 1 is output via the CLKOUT pin. The CLKOUT signal can be used to synchronize multiple switching regulators. To alleviate duty cycle restrictions due to minimum switchon times, channel 1’s switching frequency can be divided from the master clock by 1, 2, 4 or 8 determined by resistor RDIV in Figure 1. Channel 2’s switching frequency is not affected by the DIV pin. The DIV pin is driven by a 12µA current source. Setting resistor RDIV sets the voltage present at the DIV pin which determines the divisor as shown in Table 1. The DIV pin doesn’t have any input hysteresis near the ratio thresholds. Table 1. Channel 1 Divisor vs VDIV R2 should be 10k or less to avoid bias current errors. Reference designators refer to the Block Diagram in Figure 1. 2500 FREQUENCY (kHz) 1500 1000 RDIV 1 0 0.5V < VDIV < 1.0V 2 62k 1.0V < VDIV < 1.5V 4 100k 1.5V < VDIV 8 150k The maximum recommended frequency can be approximated by the equation: 500 0 10 20 30 40 50 60 RESISTANCE (kΩ) 70 80 90 3692 F02 Figure 2. Switching Frequency vs RT/SYNC Resistance Choosing the Switching Frequency The LT3692 switching frequency is set by resistor R3 in Figure 1. The RT/SYNC pin is driven by a 12µA current source. Setting resistor R3 sets the voltage present at 12 FREQUENCY RATIO VDIV < 0.5V The switching frequency is typically set as high as possible to reduce overall solution size. The LT3692 employs techniques to enhance dropout at high frequencies but efficiency and maximum input voltage decrease due to switching losses and minimum switch on times. 2000 0 DIV VOLTAGE Frequency (Hz) = VOUT + VD 1 • VIN – VSW + VD tON(MIN) where VD is the forward voltage drop of the catch diode (D1 Figure 2), VSW is the voltage drop of the internal switch, and tON(MIN) in the minimum on-time of the switch. The following example along with the data in Table 2 illustrates the trade-offs of switch frequency selection for a single input voltage system. 3692fa For more information www.linear.com/3692 LT3692 Applications Information Table 2. Efficiency and Size Comparisons for Different RRT/SYNC Values, 3.3V Output FREQUENCY RT/SYNC EFFICIENCY VVIN1/2 = 12V VIN(MAX)† L* C* C + L (Area) 250kHz 5.90kΩ 77.8% 38V 12µH 120µF 59.8mm2 500kHz 13.0kΩ 81.2% 31V 6.8µH 60µF 54.6mm2 1000kHz 28.0kΩ 80.5% 16V 3.3µH 30µF 51.9mm2 1500kHz 44.2kΩ 79.3% 10V 1.5µH 22µF 46.9mm2 2250kHz 71.5kΩ 76.7% 6.5V 0.82µH 15µF 19.1mm2 †V IN(MAX) is defined as the highest input voltage that maintains constant output voltage ripple. *Inductor and capacitor values chosen for stability and constant ripple current. Example. VIN = 25V, VOUT = 3.3V, IOUT = 2.5A, tON(MIN) = 250ns, VD = 0.6V, VSW = 0.4V: Max Frequency = 3.3 + 0.6 1 • ~ 600kHz 25 – 0.4 + 0.6 250e-9 RT/SYNC ~ 15.8kΩ (Figure 2 ) has the same effect as lowering the clock frequency for a fixed off time, resulting in a higher duty cycle and lower minimum input voltage. The resultant duty cycle depends on the charging times of the boost capacitor and can be approximated by the following equation: DCMAX = Input Voltage Range Once the switching frequency has been determined, the input voltage range of the regulator can be determined. The minimum input voltage is determined by either the LT3692’s minimum operating voltage of ~2.8V, or by its maximum duty cycle. The duty cycle is the fraction of time that the internal switch is on during a clock cycle. Unlike most fixed frequency regulators, the LT3692 will not switch off at the end of each clock cycle if there is sufficient voltage across the boost capacitor (C3 in Figure 1) to fully saturate the output switch. Forcing switch off for a minimum time will only occur at the end of a clock cycle when the boost capacitor needs to be recharged. This operation 1 B This leads to a minimum input voltage of: VIN(MIN) = VOUT + VD – VD + VSW DCMAX where VSW is the voltage drop of the internal switch. Figure 4 shows a typical graph of minimum input voltage vs load current for Figure 19, the 3.3V and 1.8V application. 6 VOUT = 3.3V 5 START-UP VOLTAGE (V) SW1 tP SW2 tP/2 RUNNING 4 3 2 1 tP CLKOUT tDCLKOSW1 1+ where B is 3A divided by the typical boost current from the Electrical Characteristics table. tP tP/2 1 0 3692 F03 tDCLKOSW2 0 500 1000 1500 2000 2500 3000 3500 CURRENT (mA) 3692 F04 Figure 3. Timing Diagram RT/SYNC = 28.0k, tP = 1µs, VDIV = 0V Figure 4. Minimum Input Voltage vs Load Current 3692fa For more information www.linear.com/3692 13 LT3692 Applications Information The maximum input voltage is determined by the absolute maximum ratings of the VIN and BST pins and by the frequency and minimum duty cycle. The minimum duty cycle is defined as: DCMIN = tON(MIN) • Frequency Maximum input voltage as: VIN(MAX) = VOUT + VD – VD + VSW DCMIN Example: Note that the LT3692 will regulate if the input voltage is taken above the calculated maximum voltage as long as maximum ratings of the VIN and BST pins are not violated. However operation in this region of input voltage will exhibit pulse skipping behavior. Example: VOUT = 3.3V, IOUT = 1A, Frequency = 1MHz, Temperature = 25°C, VSW = 0.1V, B = 50 (from boost characteristics specification), VD = 0.4V, tON(MIN) = 225ns: DCMAX = 1 1+ VIN(MIN) = 1 50 DCMIN1 = tON(MIN1) • Frequency/2 = 0.1125 A good first choice for the LT3692 inductor value is: VOUT f If the maximum load for a single channel is lower than 2.5A, then you can decrease the value of the inductor and operate with higher ripple current, or you can adjust the maximum switch current for the channel via the ILIM pin. This allows you to use a physically smaller inductor, or one with a lower DCR resulting in higher efficiency. SW1 tP SW2 The peak inductor and switch current is: tP CLKOUT 3692 F05 tDCLKOSW2 Figure 5. Timing Diagram RT/SYNC = 28.0k, tP = 1µs, VDIV = 0.75V 14 L= With this value the maximum load current will be ~3.5A, independent of input voltage. The inductor’s RMS current rating must be greater than your maximum load current and its saturation current should be higher than the maximum peak switch current, and will reduce the output voltage ripple. 2 • tP tDCLKOSW1 3.3 + 0.4 – 0.4 + 0.1= 32.6V 0.1125 where f is frequency in MHz and L is in µH. 3.3 + 0.4 – 0.4 + 0.1= 16.1V 0.225 tP/2 VIN1(MAX) = Inductor Selection and Maximum Output Current 3.3 + 0.4 – 0.4 + 0.1= 3.48V 0.98 1/(2 • tP) VOUT = 3.3V, IOUT = 1A, Frequency = 1MHz, Temperature = 25°C, VSW = 0.1V, B = 50 (from boost characteristics specification), VD = 0.4V, tON(MIN) = 225ns. VDIV = 0.75V. = 98% DCMIN = tON(MIN) • Frequency = 0.225 VIN(MAX) = In cases where multiple input voltages are present, or the VIN/VOUT ratio for channel 1 is significantly different than channel 2, channel 1’s frequency can be divided by a factor of 2, 4 or 8 from the programmed value by setting the DIV pin resistor to the appropriate value. Dividing channel 1’s frequency will increase the maximum input voltage by the same ratio. Channel 1’s external components will have to be chosen according to the resulting frequency. ISW(PK) = IL(PK) = IOUT + ∆IL 2 To maintain output regulation, this peak current must be less than the LT3692’s switch current limit, ILIM. ILIM For more information www.linear.com/3692 3692fa LT3692 Applications Information can be set between 2A and 4.8A for each channel via a resistor from the ILIM pin to ground. The ILIM pin is driven by a 12µA current source. Setting resistor R LIM sets the voltage present at the ILIM pin which determines the maximum switch current as illustrated in Figure 6. A capacitor from the ILIM pin to ground, or a resistor divider from the output, can be used to limit the peak current during start-up. If a capacitor is used it must be discharged before power-up to ensure proper operation (see 3.3V and 1.8V 2-Stage Dual Step-Down Multi-Frequency Converter in Typical Applications). Referring to Figure 6, as the peak current limit is reduced, slope compensation further reduces the peak current with increasing duty cycle. When the ILIM pin is used to reduce the peak switch current, the equation for inductor choice becomes: L= 50 • VOUT f • RILIM where f is frequency in MHz, L in µH and R in kΩ. 4.5 When the LT3692’s input supplies are operated at different input voltages, an input capacitor sized for that channel should be placed as close as possible to the respective VIN pins. A caution regarding the use of ceramic capacitors at the input. A ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. If power is applied quickly (for example by plugging the circuit into a live power source) this tank can ring, doubling the input voltage and damaging the LT3692. The solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor. For details, see Application Note 88. Output Capacitor Selection Typically step-down regulators are easily compensated with an output crossover frequency that is 1/10 of the switching frequency. This means that the time that the output capacitor must supply the output load during a transient step is ~2 or 3 switching periods. With an allowable 1% drop in output voltage during the step, a good starting value for the output capacitor can be expressed by: PEAK SWITCH CURRENT (A) 4.0 CVOUT = Max Load Step Frequency • 0.01• VOUT 3.5 3.0 Example: 2.5 VOUT = 3.3V, Frequency = 1MHz, Max Load Step = 2A. 2.0 1.5 1.0 0 10 20 30 40 50 60 70 80 90 100 ILIM PIN RESISTOR (kΩ) 3692 F06 Figure 6. Peak Switch Current vs ILIM Resistor Input Capacitor Selection Bypass the inputs of the LT3692 circuit with a 4.7µF or higher ceramic capacitor of X7R or X5R type. A lower value or a less expensive Y5V type can be used if there is additional bypassing provided by bulk electrolytic or tantalum capacitors. CVOUT = 2 = 60µF 1E6 • 0.01• 3.3V The calculated value is only a suggested starting value. Increase the value if transient response needs improvement or reduce the capacitance if size is a priority. The output capacitor filters the inductor current to generate an output with low voltage ripple. It also stores energy in order to satisfy transient loads and to stabilize the LT3692’s control loop. The switching frequency of the LT3692 determines the value of output capacitance required. Also, the current mode control loop doesn’t require the presence of output capacitor series resistance (ESR). For these reasons, you are free to use ceramic capacitors to achieve very low output ripple and small circuit size. 3692fa For more information www.linear.com/3692 15 LT3692 Applications Information You can also use electrolytic capacitors. The ESRs of most aluminum electrolytics are too large to deliver low output ripple. Tantalum and newer, lower ESR organic electrolytic capacitors intended for power supply use, are suitable and the manufacturers will specify the ESR. The choice of capacitor value will be based on the ESR required for low ripple. Because the volume of the capacitor determines its ESR, both the size and the value will be larger than a ceramic capacitor that would give you similar ripple performance. One benefit is that the larger capacitance may give better transient response for large changes in load current. Table 3 lists several capacitor vendors. BST Pin Considerations Table 3 VENDOR TYPE Taiyo Yuden Ceramic X5R, X7R SERIES AVX Ceramic X5R, X7R Tantalum Kemet Tantalum TA Organic AL Organic T491, T494, T495 T520 A700 Sanyo TA/AL Orgainic POSCAP Panasonic AL Organic SP CAP TDK Ceramic X5R, X7R Catch Diode The diode D1 conducts current only during switch off time. Use a Schottky diode to limit forward voltage drop to increase efficiency. The Schottky diode must have a peak reverse voltage that is equal to regulator input voltage and sized for average forward current in normal operation. Average forward current can be calculated from: ID(AVG) = IOUT • ( VIN – VOUT ) VIN With a shorted condition, diode current will increase to the typical value determined by the peak switch current limit of the LT3692 set by the ILIM pin. This is safe for short periods of time, but it would be prudent to check with the diode manufacturer if continuous operation under these conditions can be tolerated. 16 The capacitor and diode tied to the BST pin generate a voltage that is higher than the input voltage. In most cases a 0.47µF capacitor and a small Schottky diode (such as the CMDSH-4E) will work well. To ensure optimal performance at duty cycles greater than 80%, use a 0.5A Schottky diode (such as a PMEG4005). Almost any type of film or ceramic capacitor is suitable, but the ESR should be <1Ω to ensure it can be fully recharged during the off time of the switch. The capacitor value can be approximated by: CBST = IOUT(MAX) • VOUT 5 • VIN ( VOUT – 2) • f where IOUT(MAX) is the maximum load current. Figure 7 shows four ways to arrange the boost circuit. The BST pin must be more than 3V above the SW pin for full efficiency. Generally, for outputs of 3.3V and higher the standard circuit (Figure 7a) is the best. For lower output voltages the boost diode can be tied to the input (Figure 7b). The circuit in Figure 7a is more efficient because the BST pin current comes from a lower voltage source. Figure 7c shows the boost voltage source from available DC sources that are greater than 3V. The highest efficiency is attained by choosing the lowest boost voltage above 3V. For example, if you are generating 3.3V and 1.8V and the 3.3V is on whenever the 1.8V is on, the 1.8V boost diode can be connected to the 3.3V output. In any case, you must also be sure that the maximum voltage at the BST pin is less than the maximum specified in the Absolute Maximum Ratings section. The boost circuit can also run directly from a DC voltage that is higher than the input voltage by more than 3V, as in Figure 7d. The diode is used to prevent damage to the LT3692 in case VX is held low while VIN is present. The circuit saves several components (both BST pins can be tied to D2). However, efficiency may be lower and dissipation in the LT3692 may be higher. Also, if VX is absent, the LT3692 will still attempt to regulate the output, but will do so with very low efficiency and high dissipation because 3692fa For more information www.linear.com/3692 LT3692 Applications Information D2 VIN VIN BST C3 D2 VIN SW VIN LT3692 GND (7b) D2 VX > VIN + 3V VIN BST C3 VIN SW LT3692 BST VIN SW LT3692 IND VOUT VBST – VSW = VX VBST(MAX) = VIN + VX VX(MIN) = 3V VOUT < 3V GND VBST – VSW = VIN VBST(MAX) = 2 • VIN D2 VIN SW IND VOUT VOUT (7a) VX = LOWEST VIN OR VOUT > 3V C3 LT3692 IND VOUT VBST – VSW = VOUT VBST(MAX) = VIN + VOUT BST IND VOUT VOUT < 3V GND (7c) VOUT < 3V GND VBST – VSW = VX VBST(MAX) = VX VX(MIN) = VIN + 3V 3692 F07 (7d) Figure 7. BST Pin Considerations the switch will not be able to saturate, dropping 1.5V to 2V in conduction. The minimum input voltage of an LT3692 application is limited by the minimum operating voltage (<3V) and by the maximum duty cycle as outlined above. For proper start-up, the minimum input voltage is also limited by the boost circuit. If the input voltage is ramped slowly, or the LT3692 is turned on with its SS pin when the output is already in regulation, then the boost capacitor may not be fully charged. Because the boost capacitor is charged with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. This minimum load will depend on input and output voltages, and on the arrangement of the boost circuit. The Typical Performance Characteristics section shows plots of the minimum load current to start and to run as a function of input voltage for 3.3V outputs. In many cases the discharged output capacitor will present a load to the switcher which will allow it to start. The plots show the worst-case situation where VIN is ramping very slowly. Use a Schottky diode for the lowest start-up voltage. Outputs Greater Than 6V For outputs greater than 6V, add a resistor of 1k to 2.5k across the inductor to damp the discontinuous ringing of the SW node, preventing unintended SW current. The 12V output circuit in the Typical Applications section shows the location of this resistor. Frequency Compensation The LT3692 uses current mode control to regulate the output. This simplifies loop compensation. In particular, the LT3692 does not require the ESR of the output capacitor for stability so you are free to use ceramic capacitors to achieve low output ripple and small circuit size. Frequency compensation is provided by the components tied to the VC pin. Generally a capacitor and a resistor in series to ground determine loop gain. In addition, there is a lower value capacitor in parallel. This capacitor is not part of the loop compensation but is used to filter noise at the switching frequency. 3692fa For more information www.linear.com/3692 17 LT3692 Applications Information Loop compensation determines the stability and transient performance. Designing the compensation network is a bit complicated and the best values depend on the application and in particular the type of output capacitor. A practical approach is to start with one of the circuits in this data sheet that is similar to your application and tune the compensation network to optimize the performance. Stability should then be checked across all operating conditions, including load current, input voltage and temperature. The LT1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability using a transient load. Figure 8 shows an equivalent circuit for the LT3692 control loop. The error amp is a transconductance amplifier with finite output impedance. The power section, consisting of the modulator, power switch and inductor, is modeled as a transconductance amplifier generating an output current proportional to the voltage at the VC pin. Note that the output capacitor integrates this current, and that the capacitor on the VC pin (CC) integrates the error amplifier output current, resulting in two poles in the loop. In most cases a zero is required and comes from either the output capacitor ESR or from a resistor in series with CC. This simple model works well as long as the value of the inductor is not too high and the loop crossover frequency is much lower than the switching frequency. A phase lead capacitor (CPL) across the feedback divider may improve the transient response. Synchronization The RT/SYNC pin can also be used to synchronize the regulators to an external clock source. Driving the RT/SYNC resistor with a clock source triggers the synchronization detection circuitry. Once synchronization is detected, the rising edge of SW1 will be synchronized to the rising edge of the RT/SYNC signal and the rising edge of SW2 synchronized to the falling edge of the RT/SYNC signal (see Figures 10 and 11). During synchronization, a 0V to 2.4V square wave with the same frequency and duty cycle as the synchronization signal is output via the CLKOUT pin with a typical propagation delay of 250ns. In addition, an internal AGC loop will adjust slope compensation to avoid subharmonic oscillation. If the synchronization signal is halted, the synchronization detection circuitry will timeout in typically 10µs at which time the LT3692 reverts to the free-running frequency based on the RT/SYNC pin voltage. The synchronizing clock signal input to the LT3692 must have a frequency between 200kHz and 2MHz, a duty cycle between 20% and 80%, a low state below 0.5V and a high state above 1.6V. Synchronization signals outside of these parameters will cause erratic switching behavior. If the RT/SYNC pin is held above 1.6V at any time, switching will be disabled. If the synchronization signal is not present during regulator start-up (for example, the synchronization circuitry is powered from the regulator output) the RT/SYNC pin must remain below 1V until the synchronization circuitry is active for proper start-up operation. LT3692 CURRENT MODE POWER STAGE gm = 4.8mho OUTPUT gm = 400µmho 3.6M RC CF CC + – VC ERROR AMP R1 CPL ESR FB C1 + 0.806V R2 C1 CERAMIC TANTALUM OR POLYMER 3692 F08 Figure 8. Model for Loop Response 18 3692fa For more information www.linear.com/3692 LT3692 Applications Information If the synchronization signal powers up in an undetermined state (VOL, VOH, Hi-Z), connect the synchronization clock to the LT3692 as shown in Figure 9. The circuit as shown will isolate the synchronization signal when the output voltage is below 90% of the regulated output. The LT3692 will start up with a switching frequency determined by the resistor from the RT/SYNC pin to ground. If the synchronization signal powers up in a low impedance state (VOL), connect a resistor between the RT/SYNC pin and the synchronizing clock. The equivalent resistance seen from the RT/SYNC pin to ground will set the startup frequency. If the synchronization signal powers up in a high impedance state (Hi-Z), connect a resistor from the RT/SYNC pin to ground. The equivalent resistance seen from the RT/SYNC pin to ground will set the start-up frequency. VOUT1 VCC LT3692 PG1 SYNCHRONIZATION CIRCUITRY RT/SYNC CLK 3692 F09 Figure 9. Synchronous Signal Powered from Regulator’s Output tP tP SW1 tP SW2 tPON tP CLKOUT tDCLKOSW1 tDCLKOSW2 tPON tP RT/SYNC 3692 F11 tDRTSYNCH tDRTSYNCH Figure 11. Timing Diagram RT/SYNC = 1MHz, Duty Cycle > 50% Reducing Input Ripple Voltage Synchronizing the switches to the rising and falling edges of the synchronization signal provides the unique ability to reduce input ripple currents in systems where VIN1 and VIN2 are connected to the same supply. Decreasing the input current ripple reduces the required input capacitance. For example, the input ripple voltage shown in Figure 12 for a typical antiphase dual 14.4V to 8.5V and 14.4V to 3.3V regulator is decreased from a peak of 472mV to 160mV as shown in Figure 13 by driving the LT3692 with a 71% duty cycle synchronization signal. SW1 SW1 SW2 tP/2 tP INPUT RIPPLE V SW2 tP tP/2 RT/SYNC 3692 F12 CLKOUT Figure 12. Dual 14.4V/8.5V, 14.4V/3.3V with 180° Phase tDCLKOSW1 tDCLKOSW2 tP/2 SW1 tP RT/SYNC SW2 3692 F10 tDRTSYNC Figure 10. Timing Diagram RT/SYNC = 1MHz, Duty Cycle = 50% INPUT RIPPLE V RT/SYNC 3692 F13 Figure 13. Dual 14.4V/8.5V, 14.4V/3.3V with 256° Phase 3692fa For more information www.linear.com/3692 19 LT3692 Applications Information Shutdown and Undervoltage/Overvoltage Lockout Typically, undervoltage lockout (UVLO) is used in situations where the input supply is current limited, or has a relatively high source resistance. A switching regulator draws constant power from the source, so source current increases as source voltage drops. This looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. UVLO prevents the regulator from operating at source voltages where these problems might occur. Overvoltage lockout (OVLO) is typically used to shut down the switching regulator during potentially harmful input voltage transients. Referring to Figure 14, if the SHDN pin is connected to VIN, then the overvoltage lockout threshold is set to the typical maximum value of 38V. There is no hysteresis on the SHDN pins. If the SHDN pins are not connected to VIN, then an internal clamp regulates the SHDN pin voltage to 2.5V. If the SHDN pin is driven by a logic signal greater than 2.5V, a series resistor is required to limit the current into the SHDN pin to no more than 10µA. Referring to Figure 15, a 249k resistor will suffice for a typical logic-level signal. If the logic signal is 5V or greater, choose a current limiting resistor equal to RSHDN = (VLOGIC – 2.5V)/10µA. Place a small Schottky diode (such as a BAT54) in parallel to the current-limiting resistor as shown in Figure 15. Keep the connections from any series resistors to the SHDN pins short and make sure that the interplane or surface capacitance to switching nodes is minimized. Additionally, an internal comparator will force both channels into shutdown below the minimum VIN1 of 2.8V. This feature can be used to prevent excessive discharge of battery-operated systems. In addition to the VIN1 undervoltage lockout, both channels will be disabled when SHDN1 is less than 1.3V. Programmable UVLO may be implemented using an input voltage divider and one of the internal comparators (see the Typical Applications section). When the SHDN pin is taken above 1.3V, its respective channel is allowed to operate. When the SHDN pin is driven below 1.3V, its channel is disabled. Taking SHDN1 below 0.6V will place the LT3692 in a low quiescent current mode. A graph of quiescent current vs SHDN1 voltage can be found in the Typical Performance Characteristics section. 1.3V SHDN1 + – + – 38V THERMAL SHUTDOWN LT3692 CHANNEL DISABLE 3692 F15 Figure 14. Connect SHDN to VIN to Select Default OVLO and UVLO RSHDN + – SHDN LT3692 SCHOTTKY OPTIONAL IF VLOGIC < 5V 3692 F15 Figure 15. External Control of the SHDN Pin Soft-Start The output of the LT3692 regulates to the lowest voltage present at either the SS pin or an internal 0.806V reference. A capacitor from the SS pin to ground is charged by an internal 12µA current source resulting in a linear output ramp from 0V to the regulated output whose duration is given by: VINX 20 VLOGIC tRAMP = CSS • 0.806V 12µA At power-up, a reset signal sets the soft-start latch and discharges both SS pins to approximately 0V to ensure proper start-up. When both SS pins are fully discharged the latch is reset and the internal 12µA current source starts to charge the SS pin. When the SS pin voltage is below 115mV, the VC pin is pulled low which disables switching. This allows the SS pin to be used as an individual shutdown for each channel. For more information www.linear.com/3692 3692fa LT3692 Applications Information As the SS pin voltage rises above 90mV, the VC pin is released and the output is regulated to the SS voltage. When the SS pin voltage exceeds the internal 0.806V reference, the output is regulated to the reference. The SS pin voltage will continue to rise until it is clamped at 2V. The comparators can be used to monitor input and output voltages as well as die temperature. See the Typical Applications circuit collection for examples. In the event of a VIN1 undervoltage lockout, the soft-start latch is set for both channels, triggering a full start-up sequence. If a channel’s SHDN pin is driven below 1.3V, its overvoltage lockout is enabled, or the internal die temperature for its power switch exceeds its maximum rating during normal operation, the soft-start latch is set for that channel. Complex output tracking and sequencing between channels can be implemented using the LT3692’s SS and CMPO pins. Figure 16 shows several configurations for output tracking/sequencing for a 3.3V and 1.8V application. In addition, if the load exceeds the maximum output switch current, the output will start to drop causing the VC pin clamp to be activated. As long as the VC pin is clamped, the SS pin will be discharged. As a result, the output will be regulated to the highest voltage that the maximum output current can support. For example, if a 6V output is loaded by 1Ω the SS pin will drop to 0.48V, regulating the output at 4.8V ( 4.8A • 1Ω ). Once the overload condition is removed, the output will soft start from the temporary voltage level to the normal regulation point. Ratiometric tracking is achieved in Figure 16b by connecting both SS pins together. In this configuration, the SS pin source current is doubled (24µA) which must be taken into account when calculating the output rise time. Since the SS pin is clamped at 2V and has to discharge to 0.806V before taking control of regulation, momentary overload conditions will be tolerated without a soft-start recovery. The typical time before the SS pin takes control is: C • 1.2V tSS(CONTROL) = SS 1.4mA Open-Collector Comparators The CMPO pin is the open-collector output of an internal comparator. The comparator compares the CMPI pin voltage to 90% of the reference voltage (0.72V) with 60mV of hysteresis. The CMPO pin has a typical sink capability of 300µA when the CMPI pin is below the threshold and can withstand 38V when the threshold is exceeded. The CMPO pin is active (sink capability is reduced in shutdown and undervoltage lockout mode) as long as the VIN1 pin voltage exceeds 2.8V. Output Tracking/Sequencing Independent soft-start for each channel is shown in Figure 16a. The output ramp time for each channel is set by the soft-start capacitor as described in the soft-start section. By connecting a feedback network from VOUT1 to the SS2 pin with the same ratio that sets VOUT2 voltage, absolute tracking shown in Figure 16c is implemented. The minimum value of the top feedback resistor (R1) should be set such that the SS pin can be driven all the way to ground with 1.4mA of sink current when VOUT1 is at its regulated voltage. In addition, a small VOUT2 voltage offset will be present due to the SS2 12µA source current. This offset can be corrected for by slightly reducing the value of R2. Figure 16d illustrates output sequencing. When VOUT1 is within 10% of its regulated voltage, CMPO1 releases the SS2 soft-start pin allowing VOUT2 to soft-start. In this case CMPO1 will be pulled up to 2V by the SS pin. If a greater voltage is needed for CMPO1 logic, a pull-up resistor to VOUT1 can be used. This will decrease the soft-start ramp time and increase tolerance to momentary shorts. If precise output ramp up and down is required, drive the SS pins as shown in Figure 16e. The minimum value of resistor (R3) should be set such that the SS pin can be driven all the way to ground with 1.4mA of sink current during power-up and fault conditions. 3692fa For more information www.linear.com/3692 21 LT3692 Applications Information Independent Start-Up Ratiometric Start-Up Absolute Start-Up VOUT1 0.5V/DIV VOUT1 0.5V/DIV PG1 VOUT2 0.5V/DIV VOUT2 0.5V/DIV 5ms/DIV LT3692 FB1 CMPI1 0.72V + – 0.1µF CMPO1 12µA 0.72V + – FB1 CMPI1 2.5V 12µA 0.72V SS1 R2 2.5V PG2 12µA 0.72V SS2 12µA PG1 0.72V + – R4 R5 FB2 CMPI2 2.5V PG2 12µA 0.72V SS2 R8 0.22µF (16a) PG1 VOUT2 R6 CMPO2 R3 R2 CMPO1 + – 0.1µF R4 FB2 CMPI2 FB1 CMPI1 2.5V VOUT2 R5 CMPO2 R1 SS1 R6 VOUT1 R3 CMPO1 + – 0.1µF FB2 CMPI2 SS2 R1 PG1 R4 LT3692 VOUT1 R3 R2 VOUT2 2.5V 10ms/DIV LT3692 R1 SS1 PG2 10ms/DIV VOUT1 2.5V VOUT2 0.5V/DIV PG2 PG2 12µA VOUT1 0.5V/DIV PG1 PG1 CMPO2 + – R6 R5 PG2 R7 (16b) (16c) Output Sequencing Controlled Power Up and Down VOUT1 0.5V/DIV VOUT1 0.5V/DIV PG1/PG2 VOUT2 0.5V/DIV VOUT2 0.5V/DIV PG1 SS1/2 PG2 10ms/DIV 10ms/DIV LT3692 LT3692 VOUT1 VOUT1 R1 FB1 CMPI1 2.5V 12µA 0.72V SS1 + – 0.1µF R1 R2 2.5V CMPO1 R4 12µA SS2 0.72V + – CMPO2 0.72V SS1 + – VOUT2 2.5V 12µA PG1 R5 FB2 CMPI2 FB1 CMPI1 + – R2 CMPO1 PG1 VOUT2 R4 R6 R5 FB2 CMPI2 2.5V PG2 R3 12µA SS2 0.72V + – 0.22µF R6 R5 CMPO2 PG2 3692 F16 (16d) (16e) Figure 16. SS Pin Configurations 22 3692fa For more information www.linear.com/3692 LT3692 Applications Information Single Step Down: Application Optimization In multiple channel applications requiring large VIN to VOUT ratios, the maximum frequency and resulting inductor size is determined by the channel with the largest ratio. The LT3692’s multi-frequency operation allows the user to minimize component size for each channel while maintaining constant frequency operation. The circuit in Figure 17 illustrates this approach. A 2-stage step-down approach coupled with multi-frequency operation will further reduce external component size by allowing an increase in frequency for the channel with the lower VIN to VOUT ratio. The drawback to this approach is that the output power capability for the first stage is determined by the output power drawn from the second stage. The dual step-down application in Figure 18 steps down the input voltage (VIN1) to the highest output voltage then uses that voltage to power the second output (VIN2). VOUT1 must be able to provide enough current for its output plus VOUT2 maximum load. Note that the VOUT1 voltage must be above VIN2’s minimum input voltage as specified in the Electrical Characteristics (2.8V) when the second channel starts to switch. Delaying channel 2 can be accomplished by either independent soft-start capacitors or sequencing with the CMP01 output. Frequency (Hz) = L1= (36V – 3.3) • 3.3 ≥ 12µH L2 = (36V – 1.8) • 1.8 ≥ 6.8µH Frequency (Hz) = L= VOUT + VD 1 • VIN – VSW + VD tON(MIN) ( VIN – VOUT ) • VOUT 36V • 250kHz 36V • 250kHz 2-Stage Step-Down: Frequency (Hz) = 3.3 + 0.6 1 • ≅ 400kHz 36V – 0.4 + 0.6 225ns L1= (36V – 3.3) • 3.3 ≥ 7.5µH L2 = (3.3 – 1.8) • 1.8 ≥ 2µH 36V • 400kHz 3.3 • 400kHz 2-Stage Step-Down Multi-Frequency: RDIV = 100k, FREQ1 = 400kHz, FREQ2 = 1600kHz. For example, assume a maximum input of 36V: VIN = 36V, VOUT1 = 3.3V at 1.5A and VOUT2 = 1.8V at 1.5A. 1.8 + 0.6 1 • ≅ 250kHz 36V – 0.4 + 0.6 225ns L1= (36V – 3.3) • 3.3 ≥ 7.5µH L2 = (3.3 – 1.8) • 1.8 ≥ 500nH 36V • 400kHz 3.3 • 2MHz In addition, RILIM2 = 40.2k reduces the peak current limit on channel to 2.5A, which reduces inductor size and catch diode requirements. VIN • f 3692fa For more information www.linear.com/3692 23 LT3692 Applications Information VIN 5V TO 36V 4.7µF 4.7µF VIN2 VIN1 SHDN1 BST1 8.2µH 0.47µF SHDN2 BST2 SW1 SW2 IND1 IND2 8.2µH 0.47µF LT3692 VOUT1 1.8V 3A 200kHz VOUT2 VOUT1 100µF ×3 8.06k 100pF 10k FB1 FB2 CMPI1 CMPI2 CMPO1 CMPO2 SS1 ILIM2 VC2 RT/SYNC 680pF DIV 10k 10.2k CLKOUT TJ GND 33pF 120k 100k 8.06k PG SS2 ILIM1 VC1 0.1µF 100µF 100pF 24.9k VOUT2 3.3V 3A 400kHz CLOCKOUT 400kHz 0.1µF 62k 470pF 0.1µF 33pF 49.9k 16.5k 120k 3692 F17 Figure 17. 3.3V and 1.8V Dual Step-Down Multi-Frequency Converter VIN 5V TO 36V 4.7µF SHDN1 BST1 8.2µH 0.47µF VOUT1 3.3V 2.5A 400kHz 100µF SHDN2 BST2 SW1 SW2 IND1 IND2 0.22µF 100pF 24.9k FB1 FB2 CMPI1 CMPI2 CMPO1 CMPO2 33pF 16.5k ILIM2 VC2 RT/SYNC DIV 47.5k 100k 10k 100pF 100k 8.06k PG SS2 ILIM1 VC1 470pF VOUT2 1.8V 1A 47µF 1600kHz VOUT2 VOUT1 SS1 120k 1µH LT3692 8.06k 0.1µF 1µF VIN2 VIN1 CLKOUT GND TJ 0.1µF CLOCKOUT 1600kHz 49.9k 0.1µF 330pF 33pF 36.5k 40.2k 3692 F18 Figure 18. 3.3V and 1.8V 2-Stage Dual Step-Down Multi-Frequency Converter 24 3692fa For more information www.linear.com/3692 LT3692 Applications Information Shorted and Reverse Input Protection PCB Layout If the inductor is chosen so that it won’t saturate excessively, an LT3692 step-down regulator will tolerate a shorted output. There is another situation to consider in systems where the output will be held high when the input to the LT3692 is absent. This may occur in battery charging applications or in battery back-up systems where a battery or some other supply is diode OR-ed with the LT3692’s output. If the VIN1/2 pin is allowed to float and the SHDN pin is held high (either by a logic signal or because it is tied to VIN), then the LT3692’s internal circuitry will pull its quiescent current through its SW pin. This is fine if your system can tolerate a few mA in this state. If you ground the SHDN pin, the SW pin current will drop to essentially zero. However, if the VIN pin is grounded while the output is held high, then parasitic diodes inside the LT3692 can pull large currents from the output through the SW pin and the VIN1/2 pin. Figure 19 shows a circuit that will run only when the input voltage is present and that protects against a shorted or reversed input. For proper operation and minimum EMI, care must be taken during printed circuit board (PCB) layout. Figure 20 shows the high di/dt paths in the buck regulator circuit. Note that large switched currents flow in the power switch, the catch diode and the input capacitor. The loop formed by these components should be as small as possible. PARASITIC DIODE D4 VIN VIN1/2 SW VOUT1/2 LT3692 3692 F19 Figure 19. Diode D4 Prevents a Shorted Input from Discharging a Backup Battery Tied to the Output These components, along with the inductor and output capacitor, should be placed on the same side of the circuit board and their connections should be made on that layer. Place a local, unbroken ground plane below these components, and tie this ground plane to system ground at one location, ideally at the ground terminal of the output capacitor C2. Additionally, the SW and BST traces should be kept as short as possible. Thermal Considerations The PCB must also provide heat sinking to keep the LT3692 cool. The exposed metal on the bottom of the package must be soldered to a ground plane. This ground should be tied to other copper layers below with thermal vias; these layers will spread the heat dissipated by the LT3692. Place additional vias near the catch diodes. Adding more copper to the top and bottom layers and tying this copper to the internal planes with vias can further reduce thermal resistance. With these steps, the thermal resistance from die (or junction) to ambient can be reduced to θJA = 35°C/W. VIN LT3692 SW VIN LT3692 SW VIN LT3692 SW GND GND GND 3692 F20 (20a) (20b) (20c) Figure 20. Subtracting the Current when the Switch is On (20a) from the Current when the Switch is Off (20b) Reveals the Path of the High Frequency Switching Current (20c). Keep this Loop Small. The Voltage on the SW and BST Traces will Also Be Switched; Keep These Traces as Short as Possible. Finally, Make Sure the Circuit is Shielded with a Local Ground Plane 3692fa For more information www.linear.com/3692 25 LT3692 Applications Information The power dissipation in the other power components such as catch diodes, boost diodes and inductors, cause additional copper heating and can further increase what the IC sees as ambient temperature. See the LT1767 data sheet’s Thermal Considerations section. Die Temperature and Thermal Shutdown The LT3692 TJ pin outputs a voltage proportional to the internal junction temperature. The TJ pin typically outputs 250mV for 25°C and has a slope of 10mV/°C. Without the aid of external circuitry, the TJ pin output is valid from 20°C to 150°C (200mV to 1.5V) with a maximum load of 100µA. Generating a Negative Regulated Voltage The simple charge pump circuit in Figure 22 uses the CLKOUT pin output to generate a negative voltage, eliminating the need for an external regulated supply. Surface mount capacitors and dual-package Schottky diodes minimize the board area needed to implement the negative voltage supply. LT3692 TJ R1 VNEG GND To extend the operating temperature range of the TJ output below 20°C, connect a resistor from the TJ pin to a negative supply as shown in Figure 21. The negative rail voltage and TJ pin resistor may be calculated using the following equations: + Full Temperature Range Measurement 3692 F23 Figure 21. Circuit to Extend the TJ Pin Operating Range 2 • TEMP(MIN)°C 100 |V | R1 ≤ NEG 33µA VNEG ≤ TJ LT3692 30k 330pF D4 CLKOUT GND where: D3, D4: ZETEX BAT54S TEMP(MIN)°C is the minimum temperature where a valid TJ pin output is required. 0.1µF D3 3692 F23 Figure 22. Circuit to Generate the Negative Voltage Rail to Extend the TJ Pin Operating Range VNEG = Regulated negative voltage supply. For example: TEMP(MIN)°C = –40°C VNEG ≤ –0.8V VNEG = –1, R1 ≤ |VNEG|/33µA = 30.2kΩ 26 3692fa For more information www.linear.com/3692 LT3692 Applications Information As a safeguard, the LT3692 has an additional thermal shutdown threshold set at a typical value of 163°C for each channel. Each time the threshold is exceeded, a power on sequence for that channel will be initiated. The sequence will then repeat until the thermal overload is removed. It should be noted that the TJ pin voltage represents a steady-state temperature and should not be used to guarantee that maximum junction temperatures are not exceeded. Instantaneous power along with thermal gradients and time constants may cause portions of the die to exceed maximum ratings and thermal shutdown thresholds. Be sure to calculate die temperature rise for steady state (>1Min) as well as impulse conditions. CLKOUT Capacitive Loading A minor drawback to generating a negative rail from the CLKOUT pin is that the charge pump adds capacitance to the CLKOUT pin, resulting in an output synchronization clock signal phase delay. Figures 23 and 24 show the impact of capacitive loading on the CLKOUT signal rise and fall times. Note that a typical 10:1 150MHz oscilloscope probe contributes significant capacitance to the CLKOUT node, necessitating a low capacitance probe for accurate measurements. Applications requiring CLKOUT to generate the negative supply voltage and provide the synchronization clock to other regulators may benefit from buffering CLKOUT prior to the charge pump circuitry. Other Linear Technology Publications Application notes AN19, AN35 and AN44 contain more detailed descriptions and design information for buck regulators and other switching regulators. The LT1376 data sheet has a more extensive discussion of output ripple, loop compensation and stability testing. Design Note DN100 shows how to generate a dual (+ and –) output supply using a buck regulator. SCOPE PROBE: 15pF 500mV/DIV CHARGE PUMP SCOPE PROBE: 15pF SYNCHRONIZED LT3692 RT/SYNC PIN FET PROBE: 2pF 40ns/DIV FREQUENCY: 1.000MHz 3692 F23 CHARGE PUMP SYNCHRONIZED LT3692 RT/SYNC PIN 500mV/DIV FET PROBE: 2pF 20ns/DIV FREQUENCY: 1.000MHz Figure 23. CLKOUT Rise Time 3692 F24 Figure 24. CLKOUT Fall Time 3692fa For more information www.linear.com/3692 27 VIN 7V TO 36V 28 VOUT1 5V 2A 500kHz 8.06k 100pF 0.47µF For more information www.linear.com/3692 120k 0.1µF 33pF 47µF ×2 4.7µF 36.5k 28.0k 330pF 42.2k 8.2µH VIN2 62k DIV GND 0.1µF TJ CLKOUT ILIM1 VC1 RT/SYNC SS2 ILIM2 VC2 SS1 CMPO2 CMPO1 FB2 VOUT2 CMPI2 LT3692 IND2 SW2 SHDN2 BST2 CMPI1 FB1 VOUT1 IND1 SW1 SHDN1 BST1 VIN1 49.9k 33pF 16.9k 2.2µH 25.5k 330pF 100pF 0.22µF 8.06k 4.7µF 49.9k PG 100k 8.06k 10k CLOCKOUT 1MHz 0.1µF 47µF VOUT2 2.5V 1A 1MHz 8.06k 4.02k VOUT3 1.2V 1A 1MHz 100µF 49.9k 33pF 8.06k 100pF 0.22µF 17.8k 470pF 4.02k 2.2µH 2.2µF DIV SW2 ILIM2 VC2 SS2 CMPO2 CMPI2 FB2 VOUT2 IND2 0.1µF TJ CLKOUT GND RT/SYNC ILIM1 VC1 SS1 VIN2 SHDN2 BST2 LT3692 CMPO1 CMPI1 FB1 VOUT1 IND1 SW1 SHDN1 BST1 VIN1 Quad Output 5V, 2.5V, 1.8V and 2V Multi-Frequency Synchronized, 2-Stage Converter with Output Sequencing, Absolute Tracking and Current Limiting 10k 2.2µH 8.06k 49.9k 33pF 3692 TA03 49.9k VOUT4 1.8V 1A 100µF 1MHz 330pF 25.5k 0.22µF 100pF 4.7µF LT3692 Typical Applications 3692fa LT3692 TYPICAL APPLICATIONS 3.3V and 1.8V 2-Stage Dual Step-Down Multi-Frequency Converter VIN 5V TO 36V 4.7µF SHDN1 BST1 8.2µH 0.47µF 1µF VIN2 VIN1 SHDN2 BST2 SW1 SW2 IND1 IND2 1µH 0.22µF LT3692 VOUT1 3.3V 2.5A 400kHz 100µF 100pF 24.9k 8.06k FB1 FB2 CMPI1 CMPI2 CMPO1 CMPO2 SS1 0.1µF 16.5k ILIM2 VC2 RT/SYNC DIV 47.5k CLKOUT TJ GND 33pF 120k 10k 100pF 100k 8.06k PG SS2 ILIM1 VC1 470pF VOUT2 1.8V 1A 47µF 1600kHz VOUT2 VOUT1 0.1µF CLOCKOUT 1600kHz 33pF 49.9k 100k 330pF 36.5k 0.1µF 40.2k 3692 TA02 12V to 3.3V and 2.5V Converter with Start-Up Current Limiting VIN 12V 4.7µF 4.7µF VIN2 VIN1 SHDN1 BST1 2.2µH 0.22µF SHDN2 BST2 SW1 SW2 IND1 IND2 0.22µF LT3692 VOUT1 2.5V 3A 1MHz VOUT2 VOUT1 47µF 8.06k 100pF 16.9k FB1 FB2 CMPI1 CMPI2 CMPO1 CMPO2 ILIM2 VC2 ILIM1 VC1 0.1µF RT/SYNC 330pF DIV 33pF 0.1µF 21.0k 28.0k 100pF 24.9k 8.06k VOUT2 3.3V 3A 47µF 1MHz SS2 SS1 120k 2.2µH CLKOUT GND TJ CLOCKOUT 1MHz 0.1µF 33pF 0.1µF 330pF 49.9k 24.9k 0.1µF 120k 3692 TA04 3692fa For more information www.linear.com/3692 29 LT3692 TYPICAL APPLICATIONS 3.3V/6A Single Output with UVLO and 100°C Temperature Warning VIN 6V TO 30V 4.7µF 4.7µF 80.6k VIN2 VIN1 6.5V UVLO RISING 6V UVLO FALLING SHDN1 BST1 10k 6.8µH 0.22µF SHDN2 BST2 SW1 SW2 IND1 IND2 6.8µH 0.22µF VOUT 3.3V 6A 800kHz EFFECTIVE RIPPLE LT3692 VOUT VOUT2 VOUT1 47µF 100pF 8.06k 24.9k FB1 FB2 CMPI1 CMPI2 CMPO1 SS1 CMPO2 SS2 ILIM2 VC2 ILIM1 VC1 0.1µF RT/SYNC 680pF DIV 10k 100°C TEMP FLAG SS1 ILIM1 VC1 CLOCKOUT 400kHz TJ GND 33pF 60.4k CLKOUT 47µF 100k FB1 28k R3 73.2k 0.1µF 10.2k 3692 TA05 Power Supply Dual Input Single 3.3V/4A Output Step-Down Converter VIN1 5V TO 36V 4.7µF SHDN1 BST1 5.6µH 0.22µF VOUT1 3.3V 4A 2.2µF VIN2 VIN1 VIN2 5V TO 36V 1A MAX SHDN2 BST2 SW1 SW2 IND1 IND2 6.8µH 0.22µF LT3692 100pF 8.06k 24.9k FB1 CMPI1 CMPI2 CMPO1 SS1 CMPO2 DIV 33pF 120k 24.9k 10.2k FB1 100k PG SS2 ILIM2 VC2 RT/SYNC 330pF 47µF FB2 ILIM1 VC1 0.1µF VOUT1 VOUT2 VOUT1 47µF CLKOUT GND VC1 CLOCKOUT 400kHz TJ 0.1µF 49.9k 0.1µF 3692 TA07 30 3692fa For more information www.linear.com/3692 LT3692 TYPICAL APPLICATIONS 5V and 1.8V Dual 2-Stage Converter VIN 6V TO 36V 1µF 4.7µF VIN2 VIN1 SHDN1 BST1 0.22µF VOUT1 5V 2A 500kHz 8.2µH SHDN2 BST2 SW1 SW2 IND1 IND2 1µH 0.22µF LT3692 VOUT2 VOUT1 47µF ×2 R9 100k 220pF 42.2k 8.06k PG FB1 CMPI2 CMPO1 CMPO2 SS1 0.1µF 47pF 120k 36.5k 61.9k 100k 100pF 47µF 8.06k ILIM2 VC2 RT/SYNC DIV FB1 SS2 ILIM1 VC1 330pF 10k FB2 CMPI1 VOUT2 1.8V 2A 2MHz CLKOUT GND 33pF TJ 0.1µF 0.1µF 330pF 49.9k 39.2k 120k 3692 TA10 3692fa For more information www.linear.com/3692 31 32 VOUT1 12V 1A 750kHz For more information www.linear.com/3692 120k 0.1µF 47µF 30.1k 33pF 330pF 8.06k 100pF 0.47µF VIN 15V TO 36V 120k 113k 1k 8.2µH 4.7µF DIV GND 0.1µF TJ CLKOUT ILIM1 VC1 RT/SYNC SS2 ILIM2 VC2 SS1 CMPO2 CMPO1 FB2 VOUT2 CMPI2 LT3692 IND2 SW2 SHDN2 BST2 VIN2 CMPI1 FB1 VOUT1 IND1 SW1 SHDN1 BST1 VIN1 24.9k 4.7µH 49.9k 33pF 2.2µF 8.06k 330pF 24.9k 100pF 0.22µF 133k 0.1µF 49.9k PG 47µF 100k VOUT2 3.3V 2A 750kHz OUT1 OUT2 MOD GND SET LTC6908-1 V+ 0.1µF VOUT3 1.2V 3A 375kHz 100µF ×2 120k 33pF 8.06k 220pF 0.22µF 20k 470pF 4.02k 3.3µH 1µF 62.0k DIV SS2 ILIM2 VC2 0.1µF TJ CLKOUT GND RT/SYNC ILIM1 VC1 SS1 CMPO2 CMPI2 FB2 VOUT2 IND2 SW2 SHDN2 BST2 VIN2 LT3692 CMPO1 CMPI1 FB1 VOUT1 IND1 SW1 SHDN1 BST1 VIN1 12V, 3.3V, 2.5V, 1.2V Quad Output with External Synchronization, Output Sequencing and Tracking Application 16.9k 4.7µH 30.1k 33pF 680pF 1µF 8.06k 100pF 100µF VOUT4 2.5V 2A 750kHz 3692 TA07 49.9k 0.22µF LT3692 TYPICAL APPLICATIONS 3692fa LT3692 TYPICAL APPLICATIONS 5V, 3.3V, 2.5V, 1.8V Synchronized Quad Output VOUT1 5V 2A 2.2µF SVIN PVIN2 PVIN DDR 4.7µF ×2 RUN LT3612 MODE RT VIN2 VIN1 SHDN1 BST1 6.8µH 0.22µF SW1 SW2 IND1 IND2 6.8µH 2.2µF 0.22µF 42.2k 8.06k FB1 FB2 CMPI1 CMPI2 CMPO1 SS1 CMPO2 SS2 ILIM2 VC2 ILIM1 VC1 0.1µF RT/SYNC 330pF DIV 33pF 60.4k 24.9k 16k FB 270k ITH TRACK/SS SGND PGND SVIN PVIN2 60.4k TJ 0.1µF RUN LT3612 100k SS1 ILIM1 VC1 MODE 100°C TEMP FLAG RT 3.3µH VOUT3 2.5V 100µF 2A SW PGOOD 47µF FB1 CLKOUT GND PVIN DDR VOUT2 VOUT1 100pF VOUT2 3.3V 100µF 2A SHDN2 BST2 LT3692 47µF 3.3µH SW PGOOD VIN1 7V TO 36V FB 191k ITH TRACK/SS SGND PGND SVIN PVIN2 60.4k CLOCKOUT 600kHz 2.2µF 28k 73.2k R14 49.9k PVIN DDR PGOOD RUN LT3612 MODE RT SGND 0.1µF 3.3µH VOUT4 1.8V 100µF 2A SW FB 121k ITH TRACK/SS PGND 60.4k 3692 TA08 3692fa For more information www.linear.com/3692 33 LT3692 Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693 Rev D) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.50 REF (4 SIDES) 3.45 ± 0.05 3.45 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.75 ± 0.05 R = 0.05 TYP 0.00 – 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 31 32 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.50 REF (4-SIDES) 3.45 ± 0.10 3.45 ± 0.10 (UH32) QFN 0406 REV D 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 34 0.25 ± 0.05 0.50 BSC 3692fa For more information www.linear.com/3692 LT3692 Revision History REV DATE DESCRIPTION A 3/13 Clarified Shutdown Quiescent Current vs Temperature Graph PAGE NUMBER 5 Clarified SHDN1/2 Pin Function description 9 Clarified SHDN pin operation in Applications Information operation in general description 10 Clarified SHDN pin operation description in Applications Information 20 3692fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection its circuits as described herein will not infringe on existing patent rights. Forofmore information www.linear.com/3692 35 LT3692 Typical Application 1.2MHz, 12V to 3.3V at 3A, 5V at 3A VIN 12V 4.7µF VIN1 SHDN1 BST1 2.2µH 0.22µF 4.7µF VIN2 SHDN2 BST2 SW1 SW2 IND1 IND2 2.2µH 0.22µF LT3692 VOUT1 3.3V 3A 1.2MHz 100pF 47µF 24.9k 100k 8.06k PG1 FB1 CMPI2 CMPO1 CMPO2 120k 24.9k ILIM2 VC2 RT/SYNC DIV 33pF 8.06k 22µF 100k PG SS2 ILIM1 VC1 330pF 100pF 42.2k FB2 CMPI1 SS1 0.1µF VOUT2 5V 3A 1.2MHz VOUT2 VOUT1 CLKOUT GND 42.2k TJ CLOCKOUT 1.2MHz 0.1µF 330pF 0.1µF 33pF 49.9k 30.1k 120k 3692 TA09 Related Parts PART DESCRIPTION COMMENTS LT3507 36V, Triple 2.4A, 1.4A and 1.4A (IOUT), 2.5MHz, High Efficiency Step-Down DC/DC Converter with LDO Controller VIN: 4V to 36V, VOUT(MIN) = 0.8V, IQ = 7mA, ISD = 1µA, (5mm × 7mm) QFN-38 LT3508 36V with Transient Protection to 40V, Dual 1.4A (IOUT), 3MHz, High Efficiency VIN: 3.7V to 37V, VOUT(MIN) = 0.8V, IQ = 4.6mA, ISD = 1µA, Step-Down DC/DC Converter (4mm × 4mm) QFN-24, TSSOP-16E LT3680 36V, 3A, 2.4MHz High Efficiency Micropower Step-Down DC/DC Converter VIN: 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 75µA, ISD < 1µA, (3mm × 3mm) DFN-10, MSOP-10E LT3693 36V, 3A, 2.4MHz High Efficiency Step-Down DC/DC Converter VIN: 3.6V to 36V, VOUT(MIN) = 0.8V, IQ = 1.3mA, ISD < 1µA, (3mm × 3mm) DFN-10, MSOP-10E LT3480 36V with Transient Protection to 60V, 2A (IOUT), 2.4MHz, High Efficiency Step-Down DC/DC Converter with Burst Mode® Operation VIN: 3.6V to 38V, Transients to 60V, VOUT(MIN) = 0.78V, IQ = 70µA, ISD < 1µA, (3mm × 3mm) DFN-10, MSOP-10E LT3980 58V with Transient Protection to 80V, 2A (IOUT), 2.4MHz, High Efficiency Step-Down DC/DC Converter with Burst Mode Operation VIN: 3.6V to 58V, Transients to 80V, VOUT(MIN) = 0.79V, IQ = 75µA, ISD < 1µA, (3mm × 4mm) DFN-16, MSOP-16E LT3971 38V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down DC/DC Converter with Only 2.8µA of Quiescent Current VIN: 4.2V to 38V, VOUT(MIN) = 1.2V, IQ = 2.8µA, ISD < 1µA, (3mm × 3mm) DFN-10, MSOP-10E LT3991 55V, 1.2A (IOUT), 2MHz, High Efficiency Step-Down DC/DC Converter with Only 2.8µA of Quiescent Current VIN: 4.2V to 55V, VOUT(MIN) = 1.2V, IQ = 2.8µA, ISD < 1µA, (3mm × 3mm) DFN-10, MSOP-10E 36 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/3692 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/3692 3692fa LT 0313 REV A • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2011